SMSC KBC1100 Keyboard / System Management Controller Overview

November 05,2004

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SMBus x4

SMSC KBC1100 PS/2 x4

8MByte Shared Flash Interface

16 bit Timers x4& WDT

MCU Debug Port

GPIO (92)

SPI x2

FanTachx3

Le

ga

cy I/O

768B Data RAM2KB Scratch RAM

8/10bitSigma Delta

ADCx8

PWMx6

PwrON Reset Gen

18x8 KeyScanAccurate12MHz RingOscillator

Host FlashRecovery

8bit0 ~ 2.5VDACx3SMSC

BudgetBusSensor

Interface

Enhanced8051 core

(Audio DJ) uP or EMA

LPC Bus

South Bridge

System BIOS+ KBBIOS

COM

LEDTrace FIFO

FIR

CIR

Battery Pack

5

4

1

2

3

Vdd

GND

KBC1100

176 TQFP

x2

SMSC SentinelAltert™ Shut Down

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KBC1100 Features

3.3V Operation with 5V Tolerant Buffers

ACPI Compliant LPC Interface 2 SPI ports Embedded 8051 Keyboard and

System Controller 512 Bytes Data RAM 2 KBytes Scratch ROM/RAM Up to 18x8 Keyboard Scan Matrix

(can be mux’d GPIO’s)

4 independent Hardware Driven PS/2 Ports

8MByte Shared Flash ROM Interface (SFI)

Host Flash Recovery • Redirection if Boot Block corrupt

Flash Recovery Mode

• On board ROM routine for Flash Reprogramming via Serial Port

2 8584-Style SMBus Ctlr’s 4 x 16bit Timers Battery Backed 1 Week timer

Wake capable

Up to 95 General Purpose I/O Pins

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KBC1100 Features

6 Pulse-Width Modulators Multiple clock source and

Independent Clock Rates 8 Bit Duty Cycle Granularity

3 Fan Tachometer Inputs 1 Serial Port

16550A-Compatible UART

2 Infrared Com. Controller Advanced IrCC 2.0

• IrDA V1.2 (4Mbps), HPSIR, ASKIR, Consumer IR Support

SMSC CIRCC2 • CIR supports popular CIR framing

in HW

2 Temp Sensor Inputs Single Pin Low Cost Sensor

Integrated Standby Power Reset Generator

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KBC1100 Features

DAC features 3 channels, 8 bit res. Sink and source 1mA Loads up to 50pF 0V to 2.5V w/ internal Vref 0V to Vcca w/ ext ref.

Voltage Resolution 9.76mV

SentinelAlert!® mode

Sigma Delta ADC 8 voltage channels Superb linearity

• Integral and Dynamic Non-Linearity = .5 LSB

• Monotonic by design 8 bit or 10 bit channels Programmable Activation MUX active channels

• Total conversion time dependant on the number of active channels

Conversion rate • 10ms per channel in 10bit mode

• 2.5ms per channel in 8bit mode

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8051 Features 4-clock instruction cycle in high-performance 8051 A set of External Memory/Mapped Control Registers provides the

80C51 core with the ability to directly control many functional blocks of the KBC1100

External 0.5M to 8M Flash ROM Through a Shared Flash Interface Programmed From Serial Flash Programming Interface, 8051, or

LPC Host 2K Bytes Internal Scratch RAM/ROM 256 Bytes Internal Data RAM 512 Bytes of External Data RAM 512 Byte External Memory Mapped Control Register Area 8042-style Keyboard Controller Host Interface Twelve Interrupt Sources Watch Dog Timer (WDT) 32Mhz Programmable Ring Oscillator with Fail Safe Control

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8051 functional blocks Shared Flash Interface (SFI) 8042 Style Keyboard Controller Interface Extended Interrupts Interrupt Accelerator Power Management Functions Direct Keyboard Scan Matrix (up to 18x8) Four channel PS/2 Interface Two I2C/SMBus Controllers LED controls 145 General Purpose I/O (GPIO) Pins Three ACPI Embedded Controller Interfaces PM1 Block Six Pulse Width Modulators Four 16 bit Counter/Timers Serial Peripheral Interface (SPI) Three Fan Tachometer Interface Consumer Infrared Communications Controller 8 channels Analog to Digital Converter 3 channels Digital to Analog Converter

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KBC1100 Power Planes VCC0

Real-time Clock Supply• 16 bits Week timer, 32.768kHz clock, Power Fail and Reset Status Register

VCC1 System Suspend Supply

• 8051, GPIO, SMBus, Key Scan, Share Flash Interface, Power management, Wake-up Functions, PWM, Counter/timer, CIR

VCC2 System Runtime Supply

• LPC Bus, SP, IR, PS/2 Ports

DAC_VCC System Suspend Supply

• DAC channel with SentinelAlert

ADC_VCC System Suspend Supply

• ADC channel, Output of Internal DBM General Purpose Input/Output

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8051 Clock Frequencies

External Clock Source (VCC2 On) Generated by 14.318M Clock Input Powered by VCC2 12, 16, 24 or 32MHz options Need to use proper Flash to match access timing

Internal 32Mhz Programmable Ring Oscillator (VCC1 On) Power by VCC1 Auto Start-up and Switch Over when Vcc2 power fail (Interrupt can be generated) Fixed frequency output in 16MHz Frequency can program between 1/8/16/32MHz Calibration with RTC 32.768KHz to determine exact frequency

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8051 System Power Management

Run Mode (VCC0, VCC1, Clock ON) Idle mode (VCC0, VCC1, Clock ON)

Initiated by an instruction that sets the PCON.0 bit In order to leave idle mode, the 8051 must receive an interrupt. Typically, a General

Purpose timer interrupt is used. Low Power

Sleep Mode (VCC0, VCC1 ON, Clock OFF) Sleep mode is initiated by a user defined 8051 command sequence CPU enters Sleep mode, all internal clocks, including the core clocks, are turned off RAM contents are preserved Exiting Sleep Mode

• Wake Up Events - RTC Alarm, Power Button, Ring Indicator

• The 8051 is now running in Idle mode and responds immediately to interrupt.

• 8051 leaves Idle mode, executes interrupt service routine and executes an IRET when done. Ultra low power

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8051 Memory Map External Program ROM

8051 has access to 64KB of program ROM through Shared Flash Interface. 2KB of Scratch ROM area can be enabled that overlays Flash ROM space

External Data RAM 512 bytes data RAM is available to the 8051 at external RAM addresses 7D00h

– 7EFFh. A 1024 bytes block of Memory Mapped Control Registers (MMCRs) are located at external RAM addresses 7F00h – 82FFh. 2KB of Scratch RAM area is accessible at external RAM addresses 0000h – 1FFFh when enabled.

Internal Data RAM Internal RAM space contains the internal 8051 generic register space and

Special Function Registers (SFRs). MMC Memory Map Control Bit

MMC=0, a 2KB ScratchRAM area at 0000h--07FFh in data space is available to the 8051. MMC=1, a 2KB ScratchROM area at 0000h--07FFh in code space is available to the 8051.

HF Host Flash HF=0, 8051 owns the Shared Flash Interface. HF=1, LPC Host owns the Shared Flash Interface.

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Default 8051 Memory Map (MMC = 0)

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8051 Scratch Memory The KBC1100 8051 has Scratch ROM space that allows 8051 to do useful work

while it does not have access to the Flash and may therefore be running during a system reset sequence.

Scratch Memory configured as RAM Scratch memory resides at 0000h to 07FFh in external data RAM space.

Scratch Memory configured as ROM scratch memory can reside at 0000h up to 07FFh in 8051 external program space.

When the MMC bit is cleared the entire 2KB scratch memory is accessible only as 8051 external data memory at address

0000h to 07FFh When the MMC bit is set

scratch memory can be configured as Scratch ROM. When the 8051 has access to the Shared Flash Interface and Scratch ROM is

enabled, the Scratch ROM area overlays the Flash. When executing the code from the Scratch ROM address range, the code is fetched from the Scratch ROM. Outside of the Scratch ROM address range the code is fetched from Flash.

The 8051 must use the Scratch ROM option to execute code when it does not have access to the Shared Flash Interface. In this case, the LPC Host has access to the SFI and the HOST FLASH bit is asserted.

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KBC1100 Memory Map MMC = 1, HF = 0

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KBC1100 Memory Map MMC = 1, HF = 1

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Shared Flash Interface (SFI)

KBC1100 Shared Flash Interface (SFI) supports 0.5 - 8MB of Flash memory

Memory devices on the SFI can be accessed by Firmware Hub (FWH) cycles or LPC memory cycles via the LPC interface

SFI Access Arbitration Normally 8051 is executing code from the Flash device and has ownership of the

SFI 8051 is notified of the LPC Host access request by the Host Access interrupt The KBC1100 provides hardware arbitration on the SFI so that the 8051 and the

LPC interface can read from Flash without software intervention

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Split 8051 Code Space Example

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Interrupt Interface 8051 core has twelve interrupts Interrupt priority level

Two programmable level • High and low

A third level for the Power Fail Interrupt• High priority over all other interrupts

Interrupts are same priority level• Interrupt events are prioritized according to the natural priority level

KBC1100 have 73 additional interrupt sources Interrupt Accelerator provide a unique vector for each interrupt source Interrupt Accelerator supports natural priority scheme

Interrupt accelerator KBC1100 interrupt accelerator provides a four bit vector bus to the 8051 that indicates

which of the sixteen interrupts associated with an external interrupt pin is being asserted Interrupt accelerator is disabled, the interrupt vector is the standard 8051 interrupt vector The default interrupt vector can be changed by Interrupt Vector Page register

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Interrupt Source Detection

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8051 Interrupts

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INT1 Interrupt Sources and Interrupt Accelerator Interrupt Vectors

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Wakeup Events

Wakeup Events can bring 8051 from Sleep mode to Run Mode Wake-up events can be internally or externally generated.

Total 73 Wake up Events Internal Events (18)

RTC Alarm Hibernation Timer Write to PM1 Status, Enable, Control Registers Thermal Event ADC Conversion Complete LPC Host Access to Share Flash Interface CIR Wake Event Specific Wake on Keyboard and Mouse

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External Wakeup Events

External Events (55) UART Ring Indicator SMBus 1 or 2 Start or other event IR and CIR detected Any Key Pressed on Key Scan Fan Tachometer 1 to 3 below programmed speed LPC Bus Reset (Falling Edge) PS2 Channel Activity 22 GPI or GPIO Pins (Programmable Edge or Either Edge)

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GPIO Interface

KBC1100 includes three general purpose I/O pin types 8051 Non-SFR GPIOs LPC/8051 Addressable GPIOs Bit-Wise Addressable 8051 SFR GPIOs

(67) 8051 non-SFR GPIO (Byte-wise Access) (16) 8051 SFR GPIO (SGPIO30-37, 40-47, Bit-wise Access) (19) LPC or 8051 addressable GPIO 4 Dedicate LED pins for power and battery

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I2C/SMBus Interface/Access Bus

KBC1100 implements two I2C/SMBus controllers Each controller through a multiplexer, can drive two independent

sets of Clock and Data pins SMBus logic is powered on the VCC1 and clocked by the 8051 clock

to provide the ability to wake-up the 8051 on an I2C/SMBus event SMBus interface is fully and directly controlled by the on-chip 8051

through a set of on-chip memory mapped control registers A single I2C/SMBus controller on a host can accommodate up to

125 peripheral devices Data Rate is Clock Source/240

Fixed 24MHz clock - 100KHz• Not available when Vcc2 is off

8051 Clock is 12/16/24/32MHz - 50/67/100/133KHz 8051 Clock is Ring Osc at 1-32 MHz - 4.2-133KHz

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Pulse Width Modulator (6) Independent PWM outputs

Fully Programmable From the 8051 Embedded Controller 8-bit Programmable Frequency

• Use 8 bits Prescaler Register 0 to 100% Duty Cycle in 1/255 Increments

• 8 bits PWM Duty Cycle Register Four Selectable Clock Sources

• CPU Clock, 14.318MHz, 32.768KHz, 16MHz Programmable Pre-divider

• divide by 1, 2 or 4 Selection Independent PWM Enable for Power Management

The frequency of the PWM pulse waveform fPWMx = fpc / ( CLK_PDIV * 255 * (PWM Prescaler + 1) ).

The duty cycle of the PWM pulse waveform % dc = PWM Duty Cycle / 255.

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PS/2 Device Interface

Four PS/2 ports implemented in hardware which are directly controlled by the on chip 8051

KBC1100 has logic to detect a keyboard make/break scan codescan autonomously and generate an 8051 wake event.

KBC1100 has logic to detect specific Mouse button clicks on a Mouse and generate an 8051 wake event.

Four independent ports to Support External Keyboard & Mouse, Internal Touch Pad & Pointing Stick

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16-Bit Counter/Timer Interface

The KBC1100 implements four 16-bit auto-reloading timer/counters General Purpose Timers

• General Purpose timers operate in all modes and may be used to generate interrupts after a specified amount of time.

Input-Only Timers• Input-Only timers also operate in all modes. Input-Only timers have an external input that

can be used to provide additional counting functionality. The external input can be used as a trigger in One-Shot mode, a clock source in Event mode or a gate in both Timer and Measurement modes.

Input/Output Timers• Input/Output timers provide the same functionality as Input-Only timers. It can generate an

external output signal in Timer mode.

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Counter/Timer Operating Modes Timer Mode

Generate periodic interrupts to the 8051 or to generate a periodic output pulse Timer always counts down The period between timer interrupts and the width of the output pulse is determined

by the speed of the clock source Event Mode

Event mode is used to count events that occur external to the timer. The timer can be programmed to count the overflow output from the previous timer or the TINx pin (Input-Only and Input/Output timers only)

One-Shot Mode One-Shot mode of the timer is used to generate a single interrupt to the 8051 after a

specified amount of time. The timer can be configured to start using the EN bit or an external event.

Measurement Mode Measurement mode measure the pulse width or period of an external signal. Generate 8051 interrupt

• Finish measurement• Timer overflows• No measurement occurred

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Watch-Dog Timer (WDT)

WDT consists of an 8-bit timer (WDT) with a 9-bit prescaler Prescaler is fed with 32KHz which always runs, even if the 8051 is in SLEEP

state. 8 bit WDT timer is decremented every (1/32KHz) *512 seconds or 16.0 ms.

Watchdog interval is programmable between 16ms and 4.08 seconds on 16ms intervals

8-bit timer (WDT) underflows, a VCC1 POR is generated. 8051 in Idle Mode

When the WDT timer underflows, the 8051 will be reset.

8051 in Sleep Mode WDT is enabled, the 8051 should never remain in the SLEEP state for more than

4 seconds.

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Hibernation Timer

Hibernation timer is clocked by the 32 KHz clock and is powered by VCC1.

8-bit binary count-down timer 0.5ms, 1.0ms and 30 second increments Period ranges are 0.5ms to 128ms, 1ms to 256ms and 30 seconds to 128 minutes

The Hibernation Timer asserts a wake-up interrupt when the count reaches zero.

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Mailbox Registers Interface

The Mailbox Registers Interface provides a standard run-time mechanism for the host to communicate with the 8051 and other logical components in the KBC1100.

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Serial Peripheral Interface (SPI) The KBC1100 SPI port is a configurable 3-wire serial interface for

communicating with various peripheral devices (EEPROMS, DACs, ADCs).

8-bit serial data is transmitted and received simultaneously over two data pins in Full Duplex mode with options to transmit and receive on one data pin in Bidirectional mode.

An internal programmable Baud Rate Generator and clock polarity and phase controls allow communication with various SPI peripherals with specific clocking requirements.

SPI cycle completion can be determined by status polling or interrupts.

The SPI port pins can be configured as GPIOs when SPI functionality is not needed.

The KBC1100 SPI is a master only device and does not support multiple-master SPI configurations.

The SPI is powered by VCC1 and can run on suspend power only.

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Fan Tachometer Interface KBC1100 has a three port fan tachometer interface for systems with

fans equipped with speed monitoring outputs. Fan Tachometer Operation Theory

Timebase for the fan tachometer interface is the 32.768kHz RTC oscillator A fan tachometer input gates the 32.768 kHz RTC oscillator for one period of the

input signal into an 8-bit counter. One fan revolution, TR, consists of two fan tachometer pulses

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Analog to Digital Converter (ADC) KBC1100 have eight channel sigma delta Analog to Digital

Converter Sigma delta ADC architecture features superb linearity and is capable of

converting analog signals to either 8 bit or 10 bit words. Conversion rate of the ADC using the 100 kHz clock is 10ms per channel in 10bit mode and 2.5ms per channel in 8bit mode.

Input range on the voltage channels spans from 0V to 1.5V which provides resolutions of 5.88mV in 8bit mode and 1.47mV in 10bit mode. The range can easily be extended with the aid of resistor dividers.

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Digital to Analog Converter (DAC)

DAC in the KBC1100 have 3 channels and 8 bit accuracy DAC output buffers are capable of sinking and sourcing 1mA of

current and can handle capacitive loads up to 50pF Low range mode, the DAC relies on an accurate internal reference

voltage Programmable and spans from 0V to 2.5V

High range mode, supply voltage AVDD serves as the reference Programmable and spans from 0V to AVDD

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SMSC BudgetBus Controller

KBC1100 SMSC BudgetBus Controller contain the control logic to support two SMSC BudgetBuses

BudgetBus Controller generates reset to the external temperature sensors Receives temperature data generated by the external temperature sensors Controller pushes acquired sensor data into internal FIFO that can store up to

eight sensor readings Generates a thermal event if the temperature exceeds the threshold value

Thermal Events Thermal event occurs when a temperature reading is greater than or equal to the

value programmed in one of the Thermal Threshold registers Temperature readings from BudgetBuses are compared against the Thermal

Threshold registers when they are pushed into the FIFO

One BudgetBus controller Two budgetBus interface

• One interface connect one budget sensor

• Measure 8 temperature points

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Thermal Event Routing Diagram

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SMSC SentinelAlert! Controls

SMSC SentinelAlert! Controls cause the KBC1100 DAC and SA_GPIO pins to transition to a known state when either of the following conditions occur

Watch-Dog timer expires• A programmable watchdog timer is used to monitor the 8051. The watchdog timer can be

set anywhere from 25 milliseconds to 6.4 seconds. The watchdog is restarted anytime the 8051 writes the WDRST bit in the SentinelAlert! Control Register.

External thermal diode sensors exceed critical temperature limits In SMSC SentinelAlert! Mode

• Temperatures are monitored by the BudgetBus Controller using the HWPRO Thermal Threshold

4 DAC outputs can be forced to minimum or maximum output voltage under program control and the SA_GPIO pins can be programmed as an input or as an output and forced High or Low.

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SMSC SentinelAlert

The Next Step in Thermal Protection

SMSCBudgetBus™

Sensor Interface

EMC1202Sensor

MemoryCPU

Chipset

BatteryPack

DC - DCConverters

Direct Charger

KBC1100

D/A

Con

tert

ers

GP

IO

Temp Limits

ProgrammedThermal

Response

Thermal Sensor Input

Watch DogTimer

SMSC SentinelAlert!™ LogicLPC

Interface

32MHz 8051micro-

controller

Shared FlashInterface

FanTach's

KeyScan +PS/2

A/DInterface

Serial+

IRDA

CIREngine

EMC1202Sensor

SystemThermal Alert

Closed Loop

Thermal

Protec

tion

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Advantages of Using SMSC KBC1100/1100L Cost Effective Total Solution

Advanced 0.35u process technology Shared Flash Architecture Build-in digital & analog chips

• Competitive total cost with flexible analog options for dumb charger/battery design• Very Competitive total cost with smart charger/battery design• Budget bus temp sensor can be placed near CPU

Simplify Designs Same EC/KBC code support KBC1100/1100L.

Flexible Power Management Unique Power Plan partition & GP I/O, Interrupt Architecture

Superior Debugging/Field Service Capability Debug code dumping to serial debug port or parallel port Interrupt Architecture Allows Single stepping operation Flash upgrade through parallel port

Technical training course for customer Important for engineer in EC hardware, software design

SMSC Budget Bus Temperature Sensors

October 28,2004

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EMC1201/2- BBUS Sensors from SMSC

Features

Only a SOT23 package is required for 2 sensors

Remote temp sensor accuracy 1°C max (40°C < Ta < 80°C)

Simple digital interface reduces the cost of the sensor

The host takes care of all interrupts

Host

SOT23 pkg

Budget Sensor Interface

The SMSC Budget Sensor Advantage

Special Interface AllowsFor Lower Cost and Small Sensors

Thermal Alert to System

5

4

1

2

3

Vdd

GND

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EMC1201/2- BBUS Sensors from SMSC

5

4

1

2

3

Vdd

GND

NC

NC

SMSC BBus

EMC1201

5

4

1

2

3

Vdd

GND

SMSC BBus

EMC1202

SMSC SolutionsTo Reduce Cost

Temperature Monitors Monitors One Remote Thermal Diode (EMC1202)

• +/-1°C accuracy 40°C<Td<80°C

• Extended temperature support

• Diode Fault Reporting

Internal Ambient Temperature sensor

• Max +/- 3°C over 0°C<Ta<85°C

11 bit resolution

SMSC BudgetBus™ one wire interface

Low digital overhead reduces size and cost

SMSC host takes care of all the interrupts

Two Operating Modes Active/Standby

< 3µA in Standby

SOT23-5 Package

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EMC1203- BBUS Sensors from SMSC

SMSC SolutionsTo Reduce Cost

8

5

1

2

3

DP1

DN2

VDD

GNDDN1

4

6

7

DP2SMSCBBus

EMC1203

Temperature Monitors Monitors Two Remote Thermal Diode (EMC1202)

• +/-1°C accuracy 40°C<Td<80°C

• Extended temperature support

• Diode Fault Reporting

Internal Ambient Temperature sensor

• Max +/- 3°C over 0°C<Ta<85°C

11 bit resolution

SMSC BudgetBus™ one wire interface

Low digital overhead reduces size and cost

SMSC host takes care of all the interrupts

Two Operating Modes Active/Standby

< 3µA in Standby

MSOP 8 Package