Date post: | 17-Jan-2015 |
Category: |
Technology |
Upload: | mahmoud-abd-el-latif |
View: | 366 times |
Download: | 1 times |
http://www.bized.co.uk
Copyright 2006 – Biz/ed
Prepared by Alaa Salah Shehata Mahmoud A. M. Abd El Latif Mohamed Mohamed Tala’t Mohamed Salah Mahmoud
Version 02 – October 2011
Start Group tutorial [2]
http://www.bized.co.uk
Copyright 2006 – Biz/ed
-Using Xilinx IP Cores
-ISIM Simulator
-Language Templates
B Outline
2
http://www.bized.co.uk
Copyright 2006 – Biz/ed
Using Xilinx IP Cores
http://www.bized.co.uk
Copyright 2006 – Biz/ed
tutorial
Why IP cores
4
An IP (intellectual property) core is a block of logic or data that is used in FPGAs or ASIC
for a product.
Features
1-Repeated use of previously designed components.
2-Portable that is able to easily be inserted into any design methodology.
http://www.bized.co.uk
Copyright 2006 – Biz/ed
First Step Generating IP Core
5
tutorial
http://www.bized.co.uk
Copyright 2006 – Biz/ed
6
tutorial
http://www.bized.co.uk
Copyright 2006 – Biz/ed
7
tutorial
In the IP selection window, find the IP to
customize.
http://www.bized.co.uk
Copyright 2006 – Biz/ed
8
tutorial
For information about the customization
options, click the Data Sheet button in the
core customization GUI. The data sheet that
appears explains all of the options.
http://www.bized.co.uk
Copyright 2006 – Biz/ed
9
Now, we generated an IP core and this core is on this
project, before generating this code you must read the
data sheet to deal with its GUI, know the timing diagram
and pins I/O interface of this core.
tutorial
http://www.bized.co.uk
Copyright 2006 – Biz/ed
10
tutorial
Data Sheet
http://www.bized.co.uk
Copyright 2006 – Biz/ed
Second Step Using IP Core
11
tutorial
http://www.bized.co.uk
Copyright 2006 – Biz/ed
12
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity add is
port (
in1 : IN std_logic_VECTOR(14 downto 0);
in2 : IN std_logic_VECTOR(14 downto 0);
clk : IN std_logic;
enable : IN std_logic;
result : OUT std_logic_VECTOR(15 downto 0));
end entity;
architecture Behavioral of add is
component adder_core
port (
a: IN std_logic_VECTOR(14 downto 0);
b: IN std_logic_VECTOR(14 downto 0);
clk: IN std_logic;
ce: IN std_logic;
s: OUT std_logic_VECTOR(15 downto 0));
end component;
Now, we will make a project that adds two
numbers using this IP core.
VHDL code
tutorial
http://www.bized.co.uk
Copyright 2006 – Biz/ed
13
Begin
your_instance_name : adder_core
port map (
a => in1,
b => in2,
clk => clk,
ce => enable,
s => result);
end Behavioral;
tutorial
http://www.bized.co.uk
Copyright 2006 – Biz/ed
Third Step Simulating IP Core
14
tutorial
Click the device icon ..in Design Utilities click
on compile HDL Simulation libraries.
For simulation on Modelsim you should
generate some libraries for the ip core.
http://www.bized.co.uk
Copyright 2006 – Biz/ed
[ISIM] ISE Simulator
http://www.bized.co.uk
Copyright 2006 – Biz/ed
ISIM Simulator
16
tutorial
http://www.bized.co.uk
Copyright 2006 – Biz/ed
ISIM Simulator
17
tutorial
http://www.bized.co.uk
Copyright 2006 – Biz/ed
ISIM Simulator
18
tutorial
http://www.bized.co.uk
Copyright 2006 – Biz/ed
ISIM Simulator
19
tutorial
http://www.bized.co.uk
Copyright 2006 – Biz/ed
ISIM Simulator
20
tutorial
http://www.bized.co.uk
Copyright 2006 – Biz/ed
Download ISIM tutorial from Xilinx
http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/ug682.pdf
tutorial
21
http://www.bized.co.uk
Copyright 2006 – Biz/ed
Language Templates
http://www.bized.co.uk
Copyright 2006 – Biz/ed
Language Templates
23
tutorial
The ISE Language Templates provide predefined pieces of code and code syntax for
use in your source files.
These templates enable easy insertion of pre-built text structures into your VHDL file.
Select Edit > Language Templates, or click the Language Templates toolbar button
shown .
http://www.bized.co.uk
Copyright 2006 – Biz/ed
Language Templates
24
tutorial
Click the plus (+) icon to expand the folders until you find the
template you want to use.
Select the template to display it in the right pane.
Insert the code in your source file.
http://www.bized.co.uk
Copyright 2006 – Biz/ed
Language Templates
25
tutorial
you can create your own custom templates
as follows.
1-Select the User Templates folder.
2-Right Click : New Folder
Type a name for your folder.
3-Right Click : New Template.
Type a name for your template.
http://www.bized.co.uk
Copyright 2006 – Biz/ed
Language Templates
26
tutorial
4-Add your code to the right pane of the
Language Templates window.
5-Right Click on the template name : Save
Template.
6-Note To remove a template, select the
template, and click the Delete toolbar
button .
http://www.bized.co.uk
Copyright 2006 – Biz/ed
See You Next Session
tutorial
27