Strained Silicon.pptx

7/28/2019 Strained Silicon.pptx

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Strained SiliconAbhishek Verma


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CMOS transistors performance is improved by geometricalscaling according to Moores law.

CMOS transistors performance is improved by geometricalscaling according to Moores law.

The physical dimensions of transistors enter in the Nano metric

regime.

Scaling becomes a severe target to be addressed due toproblems such as OFF-state draincurrent, gate leakage, andpower density.

Introduction


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So how can we further improve speed and

performance???

Solution is materials


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*m

e

Charge carrier mobility is defined as

e = charge

T = scattering time

m = effective mass

Increasing scattering time and decreasing effective massresults in higher mobility; higher device speed and

performance.

Strained Silicon is used to achieve higher mobility.


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Strained Silicon

Prof. Gene Fitzgerald developed strained silicon.

First used by Intel in the HT Prescott P4 processor.


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COMPARISON OF ITEM ONE

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United States 1254 1254 1254 1254

Europe and Asia 324 324 324 324

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TOTALS 1614 1614 1614 1614


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Quarter North America Asia Europe Australia

Q1 2009 123 34 45 10

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Q4 2010 250 62 70 20

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Strained Silicon.pptx

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