Beam Secondary Shower Acquisition System: Starting to implement GBT Protocol in Igloo2

and FATALIC as readout candidate

Student MeetingJose Luis Sirvent

PhD. Student17/02/2014

Igloo2 GBT-FPGA (STD) implementation statusSubstitute Xilinx IP’s by Microsemi IP’s (Others.. not)• Transceiver with EPCS @ 4.8GBPS:

- A lot of configuration registers- Big amount of documentation- Different implemented protocols (not needed)- Power-Up Initialization needed (HPMS)- Synchronization issues- Needed standalone testing and verification

Igloo2 SERDES Testing (Tx part)Different Speeds & Configurations

EPCS @ 1.25GbpsPre-Configured

EPCS @ 2.5GbpsPre-Configured

EPCS @ 4.8Gbps!!Custom Parameters

**EPCS : External Physical Coding Sublayer

Scope not for eye diagram determination BW 1Ghz, used just for reference 2* Signal Freq = Bit rateTransmission pattern “10101010101010101010”

Igloo2 SERDES Testing (EPCS-4.8Gbps) Looping the lines, TX & RX simulation and start-up sequence

Igloo2 SERDES Testing (EPCS-4.8Gbps) Looping the lines, TX & RX simulation and start-up sequence

• Next Step:- Continue validation or data TX/RX in simulations- Start validation with Igloo2 Dev. Kit (Lane1)- Study initialization sequence and look for optimization

- Gradual implementation of IP module on Igloo2 GBT-FPGA code- Frame Alignment- GBT encoding/decoding- …

Igloo2 SERDES Testing (TX & RX @ EPCS 4.8GBPS)Working with the Dev. Board and the means it provides

Parallel Input Data (20 bits):“1111 0000 1111 1111 XXXX”

Parallel Received Data (20 bits):“11110 00011 11111 1XXXX”

FramePos 3 2 1 0

Igloo2 SERDES Testing (TX & RX @ EPCS 4.8GBPS)Working with the Dev. Board and the means it provides

Parallel Input Data (20 bits):“1111 0000 1111 1111 XXXX”

Parallel Received Data (20 bits):“11110 00011 11111 1XXXX”

FramePos 3 2 1 0

FramePos 3 2 1 0

Recovered 11111 111XX XX111 10000

Rx Tx

SERDES

DataTx_0DataTx_1 …DataTx_19

DataRx_0DataRx_1 …DataRx_19