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Summer Internship Project Report

(Simulation model of Different types of adders using Verilog)

Submitted By:

Anumita Verma

Submitted To:

Dr. Aarti Noor

Mr. Ravi Payal

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Table of Contents

1. Introduction to Verilog HDL 3

2. Half Adder 4

- Diagram 4

- Theory 4

- Verilog Code 5

- Test Bench 5

- Simulation 5

3. Full Adder

- -Diagram 6

- Theory 6

- Verilog Code 6

- Test Bench 7

- Simulation 7

4. Ripple Carry Adder

- Diagram 8

- Theory 8

- Verilog Code 8

- Test Bench 9

- Simulation 9

5. Carry Look Ahead Adder

- Diagram 10

- Theory 10

- Verilog Code 11

- Test Bench 12

- Simulation 12

6. Carry Save Adder

- Diagram 13

- Theory 13

- Verilog Code 14

- Test Bench 15

- Simulation 15

7. References 16

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Verilog HDL

Verilog HDL is one of the two most common Hardware Description Languages (HDL)

used by integrated circuits designers. The other one is Very High Speed Hardware

Description Language (VHDL). HDL’s allows the design to be simulated earlier in the

design cycle in order to correct errors or experiment with different architectures in

order to reduce cost and time. Designs described in HDL are technology-independent,

easy to design and debug, and are usually more readable than schematics, particularly

for large circuits.

Verilog can be used to describe designs at four levels of abstraction:

(i) Gate Level Modelling: In terms of gates

(ii) Data Level Modelling: In terms of Boolean algebra

(iii) Behavior Modelling: In terms of the functionality or nature of desired circuit

(iv) Switch level (the switches are MOS transistors inside gates)

In this project report, Data Level Modelling has been implemented. This report discusses

three different types of adders: Ripple Carry Adder, Carry Look Ahead Adder and Carry

Save Adder. The three adders perform simple addition however each is a little different

from the other. There are minor variations in each type. Starting off with the simplest is

the Ripple Carry Adder. Carry Look Ahead Adder is similar with a little variation and

complexity and the rarest is the Carry Save Adder. The three adders are discussed below

in further detail.

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Half Adder

Diagram:

Theory:

The half adder in an example of a simple, functional digital circuit built from two logic

gates. The half adder adds to one-bit binary numbers (A and B). The output is the sum of

the two bits (S) and the carry (C). The same two inputs are directed to two different

gates. The inputs to the XOR gate are also the inputs to the AND gate. The input “wires”

to the XOR gate are tied to the input wires of the AND gate; thus, when voltage is

applied to the A input of the XOR gate, A input to the AND gate receives of the same

voltage.

Verilog Code:

5

Test Bench:

Simulation:

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Full Adder

Diagram:

Theory:

Full adders are implemented with the help of two sets of half adders along with an OR

gate. A full-adder circuit adds three one-bit binary numbers (A, B and Cin) and outputs

two one-bit binary numbers, a sum (S) and a carry (Cout). The full adder is usually a

component in a cascade of adders. The carry input for the full-adder circuit is from the

carry output from the circuit “above” itself in the cascade. The carry output from the full

add is fed to another full adder “below” itself in the cascade.

Verilog Code:

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Test Bench:

Simulation:

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Ripple Carry Adder

Diagram:

Theory:

Ripple Carry Adder, more commonly known as a four bit adder, adds two four bit

numbers. The Ripple Carry Adder is implemented with the help of four full adders where

the carry propagates through every full adder before the addition is complete. Each full

adder inputs a Cin, which is the Cout of the previous adder. This kind of adder is a

ripples carry adder, since each bit ripples to next full adder. Ripple Carry Adder is always

preferred in terms of power and area when it appears to be fast enough for its intended

purpose. Ripple Carry Adder requires least amount of hardware of all adders, but they

are the slowest. In a Ripple Carry Adder, the carry bit moves serially. Ripple Carry Adder

is most commonly used in the industry as a four bit adder; however it is not restricted to

just four bits. If needed, this adder can be modified into a five bit, six bit, etc. adder by

simply increasing the number of full adders in the circuit.

Verilog Code:

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Test Bench:

Simulation:

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Carry Look Ahead Adder

Diagram:

Theory:

In a busy era of ours, most other arithmetic operations, for example multiplication and

division are implemented using several adding and/or subtracting steps. Hence,

improving the speed of addition is very crucial. A Carry Look Ahead adder is faster way

of adding numbers. This method does not reuire the carry signal to propagate stage by

stage, causing a bottleneck. Instead it uses additional logic to expedite the propagation

and generation of carry information, allowing fast additional at the expense of more

hardware requirements. . It improves the speed by reducing the amount of time

required to determine carry bits. It can be contrasted with the simpler, but usually

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slower, ripple carry adder for which the carry bit is calculated alongside the sum bit, and

each bit must wait until the previous carry has been calculated to begin calculating its

own result and carry bits. The carry-look ahead adder calculates one or more carry bits

before the sum, which reduces the wait time to calculate the result of the larger value

bits. The CLA solves the problem of delay it takes to propagate, by calculating the carry

signal in advance based on the input signal. Carry look-ahead adder and the carry bit is

passed on in a parallel manner. The logic for the adder is as follows:

C1 = G0 + P0C0

C2 = G1 + P1C1

= G1 + P1 (G0 + P0C0)

C3 = G2 + P2C2

= G2 + P2 G1 + P1 (G0 + P0C0)

C4 = G3 + P3C3

= G3 + P3(G2 + P2 G1 + P1 (G0 + P0C0))

Verilog Code:

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Test Bench:

Simulation:

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Carry Save Adder

Diagram:

Theory:

Carry Save Adder is a kind of adder with low propagation delay, but instead of adding

two input numbers to a single sum output, it adds three input three input numbers to

an output pair of numbers. It’s two outputs are then summed by a traditional carry-

lookahead or ripple carry adder, we reeived the sum of all three inputs. In particular the

propagation delay of a Carry Save Adder is not affected by the width of vectors being

added. Each full adder’s output ‘S’ is connected to the corresponding output bit of one

output, and it’s output Cout is connected to the next higher output bit of the second

output; the lowest bit of the second output is fed directly from the Carry Save Adder’s

input. This adder, as seen from the above diagram has a very complex structure. Instead

of the sending the carry in a serial manner or parallel manner, the carry is sent

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diagonally, which are denoted by C[x] and D[x]. This is known as a Carry “Save” Adder

because during the last stage, it is seen from above that the C[3] and D[3] were “saved”

in order to be used during the last section of the circuit to generate the final carry. This

adder is used mostly in multipliers, specifically in a “Wallace Tree”.

Structures called in the Code:

While writing the Verilog Code, to avoid repetition of the same code over and over again, structures

were called in order to save redundancy. A full adder and half adder are the basic building blocks of a

carry save adder.

Verilog Code:

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Test Bench:

Simulation:

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References:

1. A verilog HDL By Samir Palnitkar 2. Digital Design By Morris Mano 3. http://isweb.redwoods.edu/INSTRUCT/CalderwoodD/diglogic/index.htm

4. http://www.cs.umd.edu/class/sum2003/cmsc311/Notes/Comb/adder.html

5. http://users.encs.concordia.ca/~asim/coen312/Lectures/RCA.pdf

6. http://www.circuitstoday.com/ripple-carry-adder