Abstract—Submicron CMOS technologies provide well- established solutions to the implementation of low-noise front- end electronics for a wide range of detector applications. Since commercial CMOS processes maintain a steady trend in device scaling, it is essential to monitor the impact of these technological advances on the noise parameters of the devices. In this paper we present the results of an extensive analysis carried out on CMOS transistors fabricated in 0.35, 0.25 and 0.18 µm technologies from different foundries. This allows to evaluate the behavior of 1/f and channel thermal noise parameters with different gate oxide thickness and minimum channel length and to give an estimate of their process-to- process spread. The experimental analysis is focused on actual device operating conditions in monolithic detector readout systems. This means that moderate or weak inversion are often the only relevant regions for front-end devices. To account for different detector requirements, the noise behavior of devices with different geometries and input capacitance was investigated. The large set of data gathered from the measurements provides a powerful tool to model noise parameters and establish front-end design criteria in deep submicron CMOS processes. I. INTRODUCTION HE advantages of deep submicron CMOS technologies in the design of low noise, mixed-signal front-end systems led in recent years to the fabrication of high performance integrated circuits in 0.35 µm and 0.25 µm CMOS processes [1]-[3]. Presently the IC designers’ effort is gradually shifting to 0.18 µm processes and beyond [4], [5], following the trend of commercial silicon foundries. The scaling acts also in reducing the thickness of the gate oxide to a few nm, which results in a remarkable improvement in radiation hardness features of the CMOS processes, such to make them fully adequate for rad-hard front-end design [6]. However, it is very important to monitor how process parameters are influenced by scaling, especially with respect to noise, which can be affected by gate oxide quality and short channel phenomena. In this paper, we have the opportunity to discuss a very large set of experimental results V. Re, M. Manghisoni and G. Traversi are with Dipartimento di Ingegneria Industriale, Università di Bergamo, Viale Marconi, 5, I-24044 Dalmine (BG), Italy (telephone: +39 0352052311, fax: +39 035562779, e- mail: [email protected]), and INFN, Pavia 27100, Italy. L. Ratti and V. Speziali are with INFN and Università di Pavia, Dipartimento di Elettronica, Via Ferrata 1, I-27100 Pavia, Italy. relevant to processes with different feature size and from different foundries. This comparative analysis was not previously possible [7], since for each CMOS generation only devices from a single foundry were available. The analysis of the experimental results includes the comparison of white and 1/f noise components of PMOS and NMOS inside the same process, an evaluation of the spread of noise parameters inside the same CMOS generation (considering devices from different foundries) and the study of scaling effects on noise in different CMOS generations from the same foundry. II. EXPERIMENTAL DETAILS A. Test devices The MOSFETs studied in this work belong to CMOS processes with minimum gate lengths of 0.35 µm (manufactured by ST and TSMC), 0.25 µm (IBM, TSMC) and 0.18 µm (TSMC, STMicroelectronics). The corresponding oxide thickness t OX is 7.2 nm, 5.5 nm and 4 nm. C OX , the gate capacitance per unit area, is about 4.8 fF/μm 2 , 6.4 fF/μm 2 , 8.8 fF/μm 2 respectively. NMOS in both IBM and TSMC 0.25 µm technologies are enclosed layout transistors [8] to prevent post-irradiation leakage currents, while in the 0.18 µm and 0.35 µm processes the transistors were laid out using a standard open structure configuration, without implementing any special radiation hard technique. B. Measurement setup We studied devices with a gate length L from 0.2 µm (in the 0.18 µm processes) to 1 µm and with a gate width W ranging from 100 µm to 2000 µm. The device parameters were characterized at drain currents I D below 1 mA, as dictated by power dissipation constraints in high density monolithic front-end systems. The gate-referred noise voltage spectrum was measured using instrumentation purposely developed at the Electronic Instrumentation Laboratory, University of Pavia. The noise of the DUT is amplified by a wideband interface circuit and detected by a Network/Spectrum Analyzer HP4195A [9]. Measurements of static and signal parameters were carried out with a Semiconductor Parameter Analyzer HP4145B. The value of the transconductance g m as a function of the drain current I D was extracted from I D - V GS curves. Survey of Noise Performances and Scaling Effects in Deep Submicron CMOS Devices from Different Foundries Valerio Re, Massimo Manghisoni, Lodovico Ratti, Valeria Speziali, Gianluca Traversi T 0-7803-8700-7/04/$20.00 (C) 2004 IEEE 1368
Transcript
Abstract—Submicron CMOS technologies provide well-
established solutions to the implementation of low-noise front-end electronics for a wide range of detector applications. Since commercial CMOS processes maintain a steady trend in device scaling, it is essential to monitor the impact of these technological advances on the noise parameters of the devices. In this paper we present the results of an extensive analysis carried out on CMOS transistors fabricated in 0.35, 0.25 and 0.18 µm technologies from different foundries. This allows to evaluate the behavior of 1/f and channel thermal noise parameters with different gate oxide thickness and minimum channel length and to give an estimate of their process-to-process spread. The experimental analysis is focused on actual device operating conditions in monolithic detector readout systems. This means that moderate or weak inversion are often the only relevant regions for front-end devices. To account for different detector requirements, the noise behavior of devices with different geometries and input capacitance was investigated. The large set of data gathered from the measurements provides a powerful tool to model noise parameters and establish front-end design criteria in deep submicron CMOS processes.
I. INTRODUCTION
HE advantages of deep submicron CMOS technologies in the design of low noise, mixed-signal front-end systems led in recent years to the fabrication of high
performance integrated circuits in 0.35 µm and 0.25 µm CMOS processes [1]-[3]. Presently the IC designers’ effort is gradually shifting to 0.18 µm processes and beyond [4], [5], following the trend of commercial silicon foundries. The scaling acts also in reducing the thickness of the gate oxide to a few nm, which results in a remarkable improvement in radiation hardness features of the CMOS processes, such to make them fully adequate for rad-hard front-end design [6]. However, it is very important to monitor how process parameters are influenced by scaling, especially with respect to noise, which can be affected by gate oxide quality and short channel phenomena. In this paper, we have the opportunity to discuss a very large set of experimental results
V. Re, M. Manghisoni and G. Traversi are with Dipartimento di
L. Ratti and V. Speziali are with INFN and Università di Pavia, Dipartimento di Elettronica, Via Ferrata 1, I-27100 Pavia, Italy.
relevant to processes with different feature size and from different foundries. This comparative analysis was not previously possible [7], since for each CMOS generation only devices from a single foundry were available. The analysis of the experimental results includes the comparison of white and 1/f noise components of PMOS and NMOS inside the same process, an evaluation of the spread of noise parameters inside the same CMOS generation (considering devices from different foundries) and the study of scaling effects on noise in different CMOS generations from the same foundry.
II. EXPERIMENTAL DETAILS
A. Test devices The MOSFETs studied in this work belong to CMOS processes with minimum gate lengths of 0.35 µm (manufactured by ST and TSMC), 0.25 µm (IBM, TSMC) and 0.18 µm (TSMC, STMicroelectronics). The corresponding oxide thickness tOX is 7.2 nm, 5.5 nm and 4 nm. COX, the gate capacitance per unit area, is about 4.8 fF/µm2, 6.4 fF/µm2, 8.8 fF/µm2 respectively. NMOS in both IBM and TSMC 0.25 µm technologies are enclosed layout transistors [8] to prevent post-irradiation leakage currents, while in the 0.18 µm and 0.35 µm processes the transistors were laid out using a standard open structure configuration, without implementing any special radiation hard technique.
B. Measurement setup We studied devices with a gate length L from 0.2 µm (in
the 0.18 µm processes) to 1 µm and with a gate width W ranging from 100 µm to 2000 µm. The device parameters were characterized at drain currents ID below 1 mA, as dictated by power dissipation constraints in high density monolithic front-end systems. The gate-referred noise voltage spectrum was measured using instrumentation purposely developed at the Electronic Instrumentation Laboratory, University of Pavia. The noise of the DUT is amplified by a wideband interface circuit and detected by a Network/Spectrum Analyzer HP4195A [9]. Measurements of static and signal parameters were carried out with a Semiconductor Parameter Analyzer HP4145B. The value of the transconductance gm as a function of the drain current ID was extracted from ID - VGS curves.
Survey of Noise Performances and Scaling Effects in Deep Submicron CMOS Devices
from Different Foundries Valerio Re, Massimo Manghisoni, Lodovico Ratti, Valeria Speziali, Gianluca Traversi
A. Transconductance A key parameter for the signal and noise performances of a
CMOS device is the transconductance gm. Its behavior depends on the inversion region where the device is operating. In strong inversion and in saturation, gm can be expressed as a function of the drain current ID by the following relationship [10]:
DOXm IL
Wn1C2g µ= (1)
In (1) µ is the channel mobility, W and L are the gate width and length. The coefficient n is proportional to the inverse of the subthreshold slope of ID as a function of the gate to source voltage VGS. The ratio gm/ID is inversely proportional to the square root of the normalized drain current IDL/W:
WLI
n1C2
I
g
D
OX
D
m µ= (2)
According to (2), gm/ID is proportional to the square root of the product µCOX. It is expected to be larger in NMOS (higher carrier mobility) as compared to PMOS, and larger in technologies with smaller feature size (larger COX).
In weak inversion the transconductance is:
T
Dm nV
Ig = (3)
In (3), VT = kT/q is the thermal voltage, k is the Boltzmann’s constant, T is the absolute temperature and q is the electron charge. The ratio gm/ID is independent of the drain current and of the device gate geometry (W and L):
TD
mnV
1Ig = (4)
In this region, a difference between NMOS and PMOS and between CMOS generations can only be given by a different value of the coefficient n, which is usually in the range between 1 and 1.2. The value 1/VT reached by the transconductance-to-current ratio for the bipolar transistor is therefore only approached by the MOSFET in weak inversion.
In the intermediate region (moderate inversion), general approximated expressions have been proposed to describe the transition between weak and strong inversion. It is possible to define a characteristic normalized drain current IZ* which sets the boundary between weak and strong inversion [10], [11]:
2
TOX*Z nVC2I µ= (5)
At IDL/W = IZ*, (2) and (4) predict the same value for the ratio gm/ID. In the region around IZ* the device is operating in moderate inversion. IZ* is expected to be larger in
NMOSFETs and in devices fabricated in processes with smaller feature size. This means that the weak and moderate inversion regions extend to higher normalized drain currents in the most advanced CMOS generations. This is supported by the experimental results on devices in the three CMOS generations studied in this paper.
Fig. 1 compares the ratio gm/ID for TSMC 0.18 µm NMOS and PMOS devices. For the NMOS, the plot shows also the behavior predicted by (2) and (4) and the extrapolated value of IZ* = 0.35 µA. The moderate inversion region is located at smaller drain currents for the PMOS, with IZ* = 0.12 µA.
1
10
100
0.0001 0.001 0.01 0.1 1 10
TSMC 0.18 µm process
NMOS
PMOS
g m/I D
(V
-1)
IDL/W (µA)
strong inversion lawweak inversion law
IZ*
Fig. 1. Transconductance-to-drain current ratio as a function of the normalized drain current for devices in the 0.18 µm process by TSMC measured at a drain-to-source voltage |VDS| = 0.8 V. For NMOS (white dots) and PMOS (black dots) W/L = 200/0.3.
Fig. 2. Transconductance gm as a function of the drain current ID for NMOSFETs and PMOSFETs in the 0.25 µm TSMC process.
Fig. 2 is an interesting example of the implications of this
behavior. The plot shows the transconductance as a function of the drain current for several NMOS and a PMOS with various gate geometries in the TSMC 0.25 µm process. The devices are biased in a normalized drain current region around 0.1 µA. Here the NMOS are very close to weak inversion, and gm approaches the linear behavior predicted by (3), with a small dependence on W and L. The PMOS is closer to strong inversion; its transconductance is sizably
smaller, and its behavior more similar to the square-root dependence predicted by (1).
1
10
100
0.0001 0.001 0.01 0.1 1 10
TSMC technology
0.180.250.35
g m/I D
(V
-1)
IDL/W (µA)
Fig. 3. Transconductance-to-drain current ratio as a function of the normalized drain current for NMOS in the 0.18 (W/L = 200/0.3), 0.25 (W/L = 1500/0.35), and 0.35 µm (W/L = 100/0.4) processes by TSMC measured at a drain to source voltage VDS = 0.8 V.
Fig. 3 compares the ratio gm/ID for TSMC devices in the three CMOS generations. In weak inversion the bipolar transistor limit (gm/ID = 38.5 V-1 at T = 300 K) is almost reached by 0.25 and 0.35 µm devices, while gm/ID is 20 % smaller in the 0.18 µm NMOS. This could be explained by a larger doping of the channel region in processes with smaller feature size, yielding a larger value of the coefficient n [10].
B. Noise The noise performances of NMOS and PMOS devices
were studied by measuring their noise voltage spectra Se(f), which can be modeled by means of the equation:
αf1
CKS)f(S
i
F2W
2e += (6)
The first term in (6) is determined by channel thermal noise. The second term is given by 1/f noise in the channel current. KF is an intrinsic process parameter for 1/f noise and Ci is the input capacitance, Ci = COXWL. The exponent α determines the slope of this low-frequency noise term, and its value is usually between 0.8 and 1.2.
Neglecting noise contributions from gate and substrate resistors, SW can be expressed by the relationship:
m
2W g
kT4S Γ= (7)
In (7), Γ is the coefficient of the channel thermal noise, and depends on the inversion region [2].
Fig. 4 shows the measured values of channel thermal noise voltage SW for PMOS and NMOS in the TSMC 0.25 µm process. Taking into account measurement errors, the results are consistent with (7) and with the behavior of the transconductance gm analyzed in Section III-A. In the investigated range of drain currents ID, the NMOS devices are
biased close to weak inversion, resulting in a very little dependence of SW on gate dimensions. The PMOS has instead a larger white noise, which can be explained by the fact that it is biased closer to strong inversion as compared to the NMOS, and, therefore, has a smaller transconductance.
The PMOS retains an advantage on the NMOS in terms of 1/f noise, as shown by Fig. 5, plotting noise voltage spectra of P and N-type devices with similar gate dimensions.
Fig. 4. White noise voltage spectra SW of PMOSFETs and NMOSFETs in the 0.25 µm process by TSMC measured at drain currents from 100 µA to 1 mA.
0.1
1
10
100
103 104 105 106 107
NMOS W/L = 1500/0.35
PMOS W/L = 1220/0.35
Noi
se v
olta
ge sp
ectr
um
[nV
/Hz1/
2 ]
f [Hz]
ID = 0.5 mA
Fig. 5. Noise voltage spectra of a PMOSFET with W/L = 1220/0.35 and an NMOSFET with W/L = 1500/0.35 in the 0.25 µm process by TSMC.
For other technologies, this is not immediately evident from Table I, which shows the averaged values of KF and α for the examined processes. NMOS devices feature a larger KF than the PMOS. However, this difference is not as large as usually reported (see also [7]), if the slope α of the 1/f noise term is taken into account. For all the examined processes, values of α ≥ 1 were found for the PMOS (except for TSMC 0.25 µm devices), while α ≤ 1 for the NMOS. This means that the 1/f noise contribution decays more quickly at increasing frequency in the case of the PMOS, as it is shown
for example by Fig. 6. Because of this effect, the difference between the noise spectra of PMOS and NMOS is more sizable at 100 kHz than at a lower frequency. This effect was discussed in [12], [13] and explained with a nonuniform distribution of the oxide traps responsible for generating 1/f noise. If the trap density increases towards the interface, tunnelling time of charge carriers is shorter, giving a larger noise at high frequency and, therefore, α < 1. The opposite (α > 1, larger noise at low frequency) is true if the trap density decreases towards the interface. The different behavior of PMOS and NMOS, pointed out by Table I for most of the examined deep submicron processes, could be related to a different profile of traps interacting with carriers of different polarity.
1
10
100
1000
103 104 105 106 107 108
PMOS
NMOS
Noi
se v
olta
ge sp
ectr
um
[nV
/Hz1/
2 ]
f [Hz]
Fig. 6. Noise voltage spectra of a PMOSFET (at ID = 700 µA) and an NMOSFET (at ID = 350 µA) with W/L = 200/0.3 in the 0.18 µm process by TSMC.
TABLE I 1/f NOISE PARAMETERS OF 0.18, 0.25 AND 0.35 µm CMOS TECHNOLOGIES
Generation Foundry KF
(10-25 J) α
NMOS PMOS NMOS PMOS TSMC 10 4 1 1.2
0.35
ST 10 9 0.9 1.1
TSMC 5 0.75 0.8 0.85
0.25
IBM 12 3.5 0.85 1.15
TSMC 10 5 0.9 1
0.18
ST 15 6 0.9 1.1
C. Effect of noise in charge measurements The study of the Equivalent Noise Charge allows to
compare the noise performances of NMOS and PMOS devices as input elements in a charge measuring system. In the case of CMOS readout processors, ENC is mostly
determined by the noise voltage spectrum of the preamplifier input device, and can be described as follows [14]:
( ) *D
1P2F
P
1i
2W
212 CtAK2tACSmmENC
++= −− απ (8)
In (8), CD* is the total external capacitance at the preamplifier input, including the detector capacitance, the preamplifier feedback capacitance and strays. m is the mismatch coefficient, m = (CD*/ Ci)1/2. tP is the signal peaking time, A1 and A2 are coefficients depending on the signal shaping. Equation (8) shows that 1/f noise gives an ENC contribution dependent on the peaking time, if α ≠ 1.
From (8), an effective evaluation of ENC when the gate width W is scaled to match the detector capacitance is provided by the normalized spectral density CiSe
2(f) [6]:
αfKCS)f(SC F
i2W
2ei += (9)
Fig. 7 compares the product CiSe2(f) of 0.18 µm NMOS
from two foundries. The comparison is done at the same current density ID/W, resulting in very similar properties at higher frequencies, where white noise is dominant. Considering that the NMOS devices are usually biased close to weak inversion, as discussed in Section III-A, the normalized white noise spectral density can be expressed as follows:
WI
LCqnV4
nVI
WLCkT4SCD
OX2T
T
DOX2
Wi ΓΓ == (10)
100
101
102
103
104
103 104 105 106 107
0.18 um ST, W/L = 2000/0.20.18 um TSMC, W/L = 200/0.2
Ci S
e2 (f)
[pF
(nV
)2 /Hz]
f [Hz] Fig. 7. Frequency dependence of the CiSe
2(f) product for two NMOSFETs in the 0.18 µm CMOS generation. The device with W/L = 200/0.2 is manufactured by TSMC and was biased at ID = 50 µA. The device with W/L = 2000/0.2 is manufactured by ST and was biased at ID = 500 µA.
Instead, at low frequency the behavior is determined by the
1/f noise parameter KF. It is an example of the different 1/f noise performances which devices from different foundries may exhibit, and which are expressed by the values in Table I.
Fig. 8 compares the product CiSe2(f) for NMOS in three
CMOS generations from the same foundry. The devices have a gate length larger than the minimum allowed by the technology to avoid possible excess noise. The value of the product COXL is very similar for the three devices. According to (10), this means that in the white noise region the relatively small differences may be explained by the different current density. Therefore, the three CMOS generations exhibit a similar thermal noise contribution to ENC, and no significant degradation or improvement can be expected by scaling to more advanced CMOS generations, at least down to the 0.18 µm process. Instead, at low frequency the contribution by 1/f noise appears to be larger for the devices in the 0.18 and 0.25 µm technologies. As shown by Table I, this is mostly due to the larger value of the slope for the 0.35 µm process, which results in an enhancement of the 1/f noise term for processes with smaller feature size in the investigated frequency range. This effect is related to different properties of the gate oxide, and appears to be process-dependent, since it is not found in ST devices. This points out, as expected, that it is difficult to reach a definite conclusion about the behavior of 1/f noise in different CMOS generations. This noise term has to be accurately characterized for every fabrication process, especially for the design of front-end systems operating at relatively large signal shaping times, where its impact on ENC is larger.
100
101
102
103
104
103 104 105 106 107
0.18 um NMOS, W/L = 200/0.30.25 um NMOS, W/L = 1500/0.450.35 um NMOS, W/L = 100/0.6
f [Hz]
Ci S
e2 (f)
[pF
(nV
)2 /Hz]
Fig. 8. Frequency dependence of the CiSe
2(f) product for three NMOSFETs in CMOS processes by TSMC. The device with W/L = 200/0.3 (0.18 µm process) was biased at ID = 35 µA. The device with W/L = 1500/0.45 (0.25 µm process) was biased at ID = 200 µA. The device with W/L =100/0.6 (0.35 µm process) was biased at ID = 40 µA.
IV. CONCLUSION The paper presented a noise characterization of CMOS
devices in three CMOS generations. The analysis of the experimental results shows that scaling brings the devices to operate closer to weak inversion. This is especially true for the NMOS, resulting in a smaller white noise contribution to the spectral density with respect to the PMOS. It was also shown that the white noise behavior is consistent with
equations valid in weak inversion. As expected from past experience on previous CMOS generations, 1/f noise is dependent on the fabrication technology. Low-noise design requires to keep it under control by an accurate experimental characterization. This will be important in the next future, when the design activity is expected to shift to 130 nm and 90 nm CMOS processes featuring very thin gate oxides.
ACKNOWLEDGMENT The authors are indebted to P.F. Manfredi for his help and
useful suggestions. They wish to thank G. De Geronimo, P. O’Connor and J.-F. Pratte (BNL) for providing the 0.18 and 0.35 µm TSMC devices studied in this paper. The authors also acknowledge R. Yarema, J. Hoff and A. Mekkaoui (Fermilab), who designed the chip with the TSMC 0.25 µm devices. IBM 0.25 µm devices were provided by P. Jarron and G. Anelli (CERN).
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