Swiss Federal Institute of Technology Computer Engineering and Networks Laboratory Modular...

Swiss FederalInstitute of Technology

Computer Engineeringand Networks Laboratory

Modular Performance Analysis

with Real-Time Calculus

Lothar Thiele, Simon Künzli, Alex Maxiaguine, Ernesto Wandeler, et al.

Computer Engineering and Networks Laboratory

ETH Zurich, Switzerland

23. November 2005

Workshop on Distributed Embedded Systems, Leiden, The Netherlands

2Swiss FederalInstitute of Technology


Real-Time Calculus

• Developed at ETH Zurich since 2000

• Based on:– Max-Plus/Min-Plus Algebra [Quadrat et al.,

1992]– Network Calculus [Le Boudec & Thiran, 2001]



Abstract Models for Performance Analysis

ProcessorTask

InputStream

ServiceModel

LoadModel

Concrete Instance

Abstract Representation

Task / ProcessingModel



Load Model

t [ms]

eventsEvent Stream

maximum / minimum arriving demand in anyinterval of length 2.5 ms

2.5

Arrival Curve & Delay ddemand

[ms] 2.5

number of events in in t=[0 .. 2.5] ms

deadline = d

ServiceModel

LoadModel

ProcessingModel

l

u



Load Model - Examples

periodic periodic w/ jitter

periodic w/ burst complex

ServiceModel

LoadModel

ProcessingModel



Service Model

t [ms]

availabilityResource Availability

maximum/minimum available service in anyinterval of length 2.5 ms

available service in t=[0 .. 2.5] ms

2.5

u

l

Service Curves [l, u]service

[ms] 2.5

ServiceModel

LoadModel

ProcessingModel



Service Model - Examples

full resource bounded delay

TDMA resource periodic resource

ServiceModel

LoadModel

ProcessingModel



d

Task / Processing Model

RTC

’

’

ServiceModel

LoadModel

ProcessingModel

Real-Time CalculusReal-Time Calculus



Scheduling / ArbitrationFP

GPS

EDF

TDMA



Analysis: Delay and Backlog

delay dmax

backlog bmax

l

u[l, u]

[l, u]

[l’, u’]

[l’, u’]

RTC

ServiceModel

LoadModel

ProcessingModel



Case Study

ECU1

BUS

CC1

ECU2CC2

ECU3CC3

S1

S2

S3

S4

S5

5 Real-Time Input Streams- with jitter- with bursts- deadline > period

3 ECU’s with own CC’s

12 Tasks & 7 Messages- with different WCED

2 Scheduling Policies- Earliest Deadline First (ECU’s)- Fixed Priority (ECU’s & CC’s)

Hierarchical Scheduling- Static & Dynamic Polling Servers

Bus with TDMA- 4 time slots with different lengths (#1,#3 for CC1, #2 for CC3, #4 for CC3)

Total Utilization:- ECU1 59 %- ECU2 87 %- ECU3 67 %- BUS 56 %



Specification Data



The Distributed Embedded System...

ECU1 BUS(TDMA)

C1.1

C1.2

C2.1

C3.1

C4.1

C5.1

C3.2

T1.1

T1.3T2.1

T3.1

T3.3

PS

FPFP

CC1

ECU2

T4.1

T5.1

FP

CC2

ECU3

T1.2

FP FP

CC3

T3.2

FP

EDF

T2.2

PS

T4.2

PS

T5.2

S1

S2

S3

S4

S5

S1

S3



... and its Real-Time Calculus Model

S5

S4

S1

S2

S3

T1.1

T1.3

C4.1

C5.1

TDMA

CPU

T2.1

T3.1

T3.3

CPU

T4.1

T5.1

CPU

PS

T1.2

EDF

PS

T3.2

C1.2

C3.2

C2.1

C3.1

C1.1

T5.2

T4.2

T2.2

PS

ECU1

ECU2

ECU3BUS

CC1

CC2

CC3



Input & Output of Stream 3

S5

S4

S1

S2

S3

T1.1

T1.3

C4.1

C5.1

TDMA

CPU

T2.1

T3.1

T3.3

CPU

T4.1

T5.1

CPU

PS

T1.2

EDF

PS

T3.2

C1.2

C3.2

C2.1

C3.1

C1.1

T5.2

T4.2

T2.2

PS

ECU1

ECU2

ECU3BUS

CC1

CC2

CC3



Service Demand & Supply for EDF Block

S5

S4

S1

S2

S3

T1.1

T1.3

C4.1

C5.1

TDMA

CPU

T2.1

T3.1

T3.3

CPU

T4.1

T5.1

CPU

PS

T1.2

EDF

PS

T3.2

C1.2

C3.2

C2.1

C3.1

C1.1

T5.2

T4.2

T2.2

PS

ECU1

ECU2

ECU3BUS

CC1

CC2

CC3




S5

S4

S1

S2

S3

T1.1

T1.3

C4.1

C5.1

TDMA

CPU

T2.1

T3.1

T3.3

CPU

T4.1

T5.1

CPU

PS

T1.2

EDF

PS

T3.2

C1.2

C3.2

C2.1

C3.1

C1.1

T5.2

T4.2

T2.2

PS

ECU1

ECU2

ECU3BUS

CC1

CC2

CC3




S5

S4

S1

S2

S3

T1.1

T1.3

C4.1

C5.1

TDMA

CPU

T2.1

T3.1

T3.3

CPU

T4.1

T5.1

CPU

PS

T1.2

EDF

PS

T3.2

C1.2

C3.2

C2.1

C3.1

C1.1

T5.2

T4.2

T2.2

PS

ECU1

ECU2

ECU3BUS

CC1

CC2

CC3



Buffer Requirements

S5

S4

S1

S2

S3

T1.1

T1.3

C4.1

C5.1

TDMA

CPU

T2.1

T3.1

T3.3

CPU

T4.1

T5.1

CPU

PS

T1.2

EDF

PS

T3.2

C1.2

C3.2

C2.1

C3.1

C1.1

T5.2

T4.2

T2.2

PS

ECU1

ECU2

ECU3BUS

CC1

CC2

CC3

3

3

1.81

5

2

2 5

4

6

5 4.1

1 5

1.3 4.5



Delay Guarantees

S5

S4

S1

S2

S3

T1.1

T1.3

C4.1

C5.1

TDMA

CPU

T2.1

T3.1

T3.3

CPU

T4.1

T5.1

CPU

PS

T1.2

EDF

PS

T3.2

C1.2

C3.2

C2.1

C3.1

C1.1

T5.2

T4.2

T2.2

PS

ECU1

ECU2

ECU3BUS

CC1

CC2

CC3

4910

4550

87

125

550

303

329

2140



System Analysis Time

• Pentium Mobile 1.6GHz

• Matlab 7

• RTC Kernel Prototype (Java 1.4)



Tool Support

• Matlab Toolbox for Real-Time Calculus– Version 1.0 to be released December 2005

• Simulink Frontend– Prototype under

development



Limitations of Real-Time Calculus

• High Level of Abstraction

• Time-Interval Domain

Swiss FederalInstitute of Technology


Thank you!

Ernesto Wandeler

[email protected]

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