SystemC Schuster

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SystemC

SystemC

Alexandra Schuster

Vienna University of Technology

4. Juni 2007


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SystemC

Table of contents

1 IntroductionSystemC Design FlowSynthese

2 Concepts and syntax of SystemCModulesPorts and SignalsProcess

ConfrontationAdvantages

3 Reference


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SystemC

Introduction

History

SystemC was first announced 1999 as a open source project

SystemC V1.0 was released on March 2000it provided modeling constructs similar to those used for RTL

SystemC V2.0 was released on Februar 2001

it enabled system level modeling and IP exchange

The actual Version of SystemC is 2.1Since December 2005: IEEE 1666 standard


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SystemC

Introduction

Purpose of SystemC

Today, problems arise from the use of different design

languages, incompatible tools and fragmented tool flowsSystemC is entirley based on C++

The creation of a system-level model is possible with SystemCand standard C++ development tools

SystemC provides hardware and software development teamwith an executable specification of the system


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SystemC

Introduction

SystemC Design Flow

Model types

System Architectural Model

executable specifications - describe software and hardware

System Performance Modelexecutable specifications with time response - describesoftware and hardware

Transaction Level Model (TLM)

executable specifications - only for hardware

Functional Modelone level higher than TLM and is used for runtime performance

Register Transfer Level Model (RTL)

S C


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SystemC

Introduction

SystemC Design Flow

SystemC Design Flow

S t C


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SystemC

Introduction

Synthese

Synthese

Take care, some data types, loops and so on are not

synthesizablefloat, double,loops with no constant boundary,pointer,I/O-Streams,

SC THREAD,...

SystemC


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SystemC

Concepts and syntax of SystemC

Library Overview

SystemC


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SystemC


Data Types

sc bit 2-valued single Bit (0,1)

sc logic 4-valued single Bit (0,1,X,Z)

sc int 1 to 64 Bit signed integer

sc uint 1 to 64 Bit unsigned integersc bigint arbitrary precision signed integer

sc biguint arbitrary precision unsigend integer

sc bv vector of sc bit

sc lv vector of sc logic

sc fixed templated signed fixed point typesc ufixed templated unsigend fixed point type

sc fix templated signed fixed point type

sc ufix templated unsigned fixed point type

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Fixed Point Types

Floating point operations are seldom used in hardwarebecause it consumes to many hardware resources.

Typical example for the use of fixed point type: DSPapplications

sc fixed and sc ufixed are setup at compile time and do notchange.

sc fix and sc ufix can use variables to determine word length,integer word length, ...

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Modules

Modules

Modules are the basic building blocks for partitioning a design

Modules allow designers to hide internal data representation

and algorithmsTherefore, designers are forced to use public interfaces toother modules

Modules can contain

portsprocessesinternal datahierarchically other modules

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Modules

Modules

Modules are declared with the SystemC keywordSC MODULE, e.g.: SC MODULE(nameOfModule);

The module is initiated by the constructor SC CTOR, e.g.:SC CTOR(nameOfModule);

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Ports and Signals

Ports and Signals

Ports of a module are the external interface that passinformation to and from a module, and trigger actions within

the module.Modes of operation:

Input (sc inporttype)Output (sc outporttype)In- and Output (sc inoutporttype)

Signals create connections between module ports allowingmodules to communicate.

A signal is declared with the keyword sc signal.

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Process

Processes

Processes provide the mechanism for simulating concurrentbehavior

A process is a member function of a module and called

whenever signals, this process is sensitive to, change value

Types of processes:method process (SC METHOD)

A SC METHOD process is triggered by events.These events must be declared in the sensitive list

thread process (SC THREAD)

A SC THREAD process can be suspended by the wait()function and reactivated by the occurence of an event. Theprocess continues to execute until the next wait().

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Process

Example of a process

1 SC MODULE( A d d e r ){2 s c i n a ;3 s c i n b ;4

s c o ut

c ;56 v o i d compute ( ){7 c = a + b ;8 }9 SC CTOR( A d d e r ){

10 SC METHOD( compute ) ;11 s e n s i t i v e


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Confrontation

VHDL vs. SystemC Example

1 l i b r a r y i e e e ; // c o u n t e r . h2 u s e i e e e . s t d l o g i c 1 1 6 4 . a l l ; #i n c l u d e s y s t e m c . h3 u s e i e e e . s t d l o g i c u n s i g n e d . a l l ;4 e n t i t y c o u n t e r i s SC MODULE( c o u n t e r ){5 p o r t ( s c i n c l oc k , l oa d , r e s e t ;6 c l o c k : i n s t d l o g i c ; s c i n d i n ;7 l o a d : i n s t d l o g i c ; s c o u t dout ;8 r e s e t : i n s t d l o g i c ;9 d i n : i n s t d l o g i c v e c t o r ( 7 downto 0 ) ; i n t c o u n t v a l ;

10 d ou t : i n o u t s t d l o g i c v e c t o r ( 7 downto 0 ) ; v oi d o n e tw o th r ee ( ) ;11 en d d f f ; SC CTOR( c o u n t e r ) {12 a r c h i t e c t u r e r t l o f c o u n t e r i s SC METHOD( o n e t w o t h r e e ) ;13 b e g i n s e n s i t i v e p o s ( c l o ck ) ;14 p r o c e s s ( r e s e t , l o ad , d in , d ou t ) }15 b e g i n } ;16 i f r e s e t = 1 then / / c o u n t e r . c c17 c o u n t v a l


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Advantages

Advantages

simulation performance

standardized modeling language: enable system level design

and IP exchange at multiple abstraction levelsprovide the hardware and software development team with anexecutable specification of the system

SystemC has a fixed-point numeric type

Open Source Licence - free development and simulationpackets

most designers familiar with C++???

SystemC


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Sources

Bibliography

Hannes Muhr.Einsatz von SystemC in Hardware/Software-CodesignDiplomarbeit: TU Wien, 2000

Thorsten Grotker.

System Design with SystemCKluwer Academic Publishers, New York. 2002

Frank Ghenassia

Transaction Level Modeling with SystemCSpringer, 2005

IEEE Computer SocietyIEEE Standard SystemC Language Reference ManualIEEE Std 1666, 2006

SystemC Users Guide

www.systemC.org, 2002

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