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TDM Pulse Amplitude Modulation/Demodulation Trainer ST2102

Learning Material Ver 1.2

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ST2102

Scientech Technologies Pvt. Ltd. 3

TDM Pulse Amplitude Modulation/De modulation Traîner ST2102

Table of Contents 1. Safety Instructions 4 2. Introduction 5

3. Features 7 4. Technical Specifications 8

5. Theory 9 I. Multiplexing 13

II. Synchronization 20 III. PLL 27 IV. TDM Synchronization 28 V. Receiver 32

6. Experiments

• Experiment 1 34 To understand, synchronization and control signals available on ST2102

• Experiment 2 36 To demonstrate the switching delay and its control on ST2102 with

Potentiometer

• Experiment 3 40 To show the importance of frame synchronization signal in Receiving the correct output at correct output channel.

• Experiment 4 42 To study the extraction of Sync Pulses from the TDM samples in operating mode 3

• Experiment 5 45 To demonstrate how the PLL locks a particular signal.

• Experiment 6 47 To interconnect the various functional blocks and to observe the overall effect of the individual parameter/ mode on the communication system. (Complete TDM PAM System)

• Experiment 7 49 To Observe output waveforms at receiver channels, CH1/ CH2/ CH3 on oscilloscope & observe preservation of dc level in output waveform compared to input signal.

7. Frequently Asked Questions 54

8. Warranty & List of Accessories 57

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Safety Instructions Read the following safety instructions carefully before operating the instrument. To avoid any personal injury or damage to the instrument or any product connected to it.

Do not operate the instrument if suspect any damage to it. The instrument should be serviced by qualified personnel only. For your safety: Use proper Mains cord : Use only the mains cord designed for this instrument.

Ensure that the mains cord is suitable for your country.

Ground the Instrument : This instrument is grounded through the protective earth conductor of the mains cord. To avoid electric shock the grounding conductor must be connected to the earth ground. Before making connections to the input terminals, ensure that the instrument is properly grounded.

Observe Terminal Ratings : To avoid fire or shock hazards, observe all ratings and marks on the instrument.

Use only the proper Fuse : Use the fuse type and rating specified for this instrument.

Use in proper Atmosphere : Please refer to operating conditions given in the manual.

1. Do not operate in wet / damp conditions. 2. Do not operate in an explosive atmosphere. 3. Keep the product dust free, clean and dry.

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Introduction Time Division Multiplexing Pulse Amplitude Modulation is communication system where the message signal modulates using Pulse Amplitude Modulation and multiple accesses is provided using Time Division Multiplexing. The message information is encoded in the amplitude of a series of signal pulses and transmitted using Time Division Multiplexing (i.e. in different time slots). ST2102 TDM-PAM Transmitter and Receiver Trainer demonstrates working of communication system in various modes of operation. There are following modes of operation.

Mode 1: In this mode of operation Clock signal and Synchronizing (Sync) signal are transmitted along with the modulated message signal.

Mode 2: In this mode of operation modulated message signal and Synchronizing (Sync) signal are transmitted, Clock and Synchronizing (Sync) signals recover at the receiver. Mode 3: In this mode of operation only modulated message signal is transmitted, Clock and Synchronizing (Sync) signals are recovered at the receiver. ST2152 TDM-PAM Transmitter and Receiver Trainer comprises of following major blocks: • Transmitter Section

a Signal Generator Unit. b Sampling Signal Generator and Duty Cycle Adjustment Logic. c Channel Selector Switch. d Four input channel.

• Receiver Section a Clock Recovery (PLL) and Delay Control Logic. b Channel Selector Switch. c Four output channel.

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Features • Crystal controlled clock

• On-board sine wave generator (synchronized)

• On-board pulse generator

• 4 Analog input channels sampled and time division multiplexed

• Pulse duty cycle selectable

• Internal/External sampling selectable

• 4 Channel De-multiplexer

• Generation of clock at receiver by PLL System

• 4th Order Butterworth Low. Pass. Filter

RoHS Compliance

Scientech Products are RoHS Complied. RoHS Directive concerns with the restrictive use of Hazardous substances (Pb, Cd, Cr, Hg, Br compounds) in electric and electronic equipments. Scientech products are “Lead Free” and “Environment Friendly”. It is mandatory that service engineers use lead free solder wire and use the soldering irons upto (25 W) that reach a temperature of 450°C at the tip as the melting temperature of the unleaded solder is higher than the leaded solder.

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Technical Specifications Crystal Frequency : 6.4 MHz Analog Input Channels : 4 in numbers

Multiplexing : Time Division Multiplexing Modulation : Pulse Amplitude Modulation

On Board Analog Signal : 250 Hz, 500 Hz, 1 KHz, 2 KHz (Sine wave synchronized to sampling pulse)

Adjustable amplitude and separate variable DC level).

Sampling Rate : 16 KHz / Channel Sampling Pulse : With duty cycle variable from 0-90% in decade

steps.

Clock Regeneration at : Using PLL Receiver Low Pass Filter Cut-Off : 3.4 KHz Frequency Test points : 52 in numbers

Interconnections : 2 mm Sockets Power Supply : 100-240VAC, 50,60Hz Dimensions (mm) : W420 x H 100 x D255 Weight : 2.5 Kg. (approximately)

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Theory Most digital modulation systems are based on pulse modulation. It involves variation of a pulse parameter in accordance with the instantaneous value of the information signal. This parameter can be amplitude, width, repetitive frequency etc. Depending upon the nature of parameter varied, various modulation systems are used. Pulse amplitude modulation, pulse width modulation, pulse code modulation are few modulation systems cropping up from the pulse modulation technique. In pulse amplitude modulation (PAM) the amplitude of the pulses are varied in accordance with the modulating signal.

In true sense, pulse amplitude modulation is analog in nature but it forms the basis of most digital communication and modulation systems. The pulse modulation systems require analog information to be sampled at predetermined intervals of time. Sampling is a process of taking the instantaneous value of the analog information at a predetermined time interval. A sampled signal consists of a train of pulses, where each pulse corresponds to the amplitude of the signal at the corresponding sampling time. The signal sent to line is modulated in amplitude and hence the name Pulse Amplitude Modulation (PAM).

Block diagram of Pulse Amplitude Modulation

Figure 1 Theory of sampling: The signals we use in the real world, such as our voice, are called "analog" signals. To process these signals for digital communication, we need to convert analog signals to "digital" form. While an analog signal is continuous in both time and amplitude, a digital signal is discrete in both time and amplitude. To convert continuous time signal to discrete time signal, a process is used called as sampling. The value of the signal is measured at certain intervals in time. Each measurement is referred to as a sample.

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Principle of sampling: Consider an analogue signal x(t) that can be viewed as a continuous function of time, as shown in figure1. We can represent this signal as a discrete time signal by using values of x(t) at intervals of nTs to form x(nTs) as shown in figure 1. We are "grabbing" points from the function x(t) at regular intervals of time, Ts, called the sampling period. The pulse amplitude modulation system can be simulated as shown in figure 2.

Basic Sampling Process

Figure 2 The receiver can reconstruct the signal from these samples, provided the sampling meets the Nyquist criteria. Nyquist criteria states that for a band limited signal with highest frequency component fm, the signal must be sampled at a rate greater then twice the highest frequency component in the signal for the sampled signal to be recovered exactly

i.e. fs > 2fm where fs = sampling frequency

Sampling of signal at sampling interval (period) Ts Figure 3

Figure 3 depicts the sampling of a signal at regular interval (period) t=nTs where n is an integer. The sampling signal is a regular sequence of narrow pulses δ (t) of amplitude 1.Figure 4 shows the sampled output at regular interval of time.

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Sampled Output of narrow pulses δ (t)

Figure 4 The control signal is totally electrically isolated from the information signal. Also the switch is considered ideal i.e.

• It should offer negligible resistance, when closed and should have infinite resistance when open.

• The opening and closing operations are delay free.

• The switch is free of contact bounce problem. The control signal closes the switch when it is at one level and opens it when it is at another. When the switch is closed the output voltage is equal to zero volts. The width of the sample depends upon the time duration for which the switch remained closed. In practice, the switch is operated electrically. The resulting PAM wave is as shown in figure 5.

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Use of PLL for TDM Synchronization

Figure 5 Because of its wide band and analog in nature, PAM has restricted of applications for direct transmission of signals. It is used, for example in instrumentation systems and in A/D Converters and for computer interfacing. It is also used as an intermediate stage in the generation of very popular digital modulation system viz. PCM (pulse code modulation.). Another advantage of PAM is that it allows for multiplexing of the signals.

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Multiplexing Multiplexing: A sampled signal consists of a train of pulses, where each pulse corresponds to the amplitude of the signal at the corresponding sampling time. The signal sent to line is modulated in amplitude and hence the name Pulse Amplitude Modulation (PAM).

Multiplexing is the process of combining signals from different information sources so that they can be transmitted over a common channel. Multiplexing is advantageous in cases where it is impracticable and uneconomical to provide separate links for the different information sources. The price that has to be paid to acquire this advantage is in the form of increased system complexity and bandwidth. The two most commonly used methods of multiplexing are:

1. Frequency division multiplexing (FDM)

2. Time division multiplexing (TDM)

Frequency Division Multiplexing: Frequency division multiplexing is the process of combining several information channels by shifting their signals to different frequency groups within the frequency spectrum so that they can all be transmitted over a common transmission channel.

The information signals are shifted in different frequency groups by making them modulate carrier signals at different frequencies e.g. Let us suppose two information signals occupy a frequency range of 300 - 3400Hz speech signal. Only lower side band is transmitted. The first signal modulates a 64 KHz carrier; the modulated signal occupies a frequencies band of 60.6 KHz to 63.7 KHz. The second signal modulates a 68 KHz carrier; the modulated signal occupies a frequency band of 64.6 KHz to 67.7 KHz. As it can be seen from above example, the modulated signals occupy different frequency ranges in the frequency spectrum. Hence they can be transmitted over the same channel. (See figure 6)

Frequency Division Multiplexing (FDM)

Figure 6

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At receiver, filters having different pass band frequency range are used to separate the various information signals. The pass band is chosen so as to extract the information from one channel. A separation between two modulated signals in frequency band reduces call interference and also allows for the gradual roll-off gradient of the filters.

Time Division Multiplexing: Time division multiplexing is the process of combining the samples from different information signals, in time domain so that they can be transmitted over the common channel. The fact utilized in TDM technique is that there are large intervals between the message samples. The samples from the other sources can be placed within these time intervals. Thus every sample is separated from other in time domain. The time division multiplexing system can be simulated by two rotating switches, one at transmitter and the other at receiver. (See figure 7) The two wipers rotate and establish electrical contact with one channel at a time.

Principle operation of TDM-PAM system

Figure 7 Each signal is sampled over one sampling interval and transmitted one after the other along a common channel. Thus part of message 1 is transmitted first followed by part of message 2, message 3 and then again message 1 so on.

The switches connect the transmitter and the receiver to each of the channels in turn for a specific interval of time. In effect each channel is sampled and the sample is transmitted

When the switches are in the channel 1 position, channel 1 forms a PAM channel with an LPF for reconstruction, and so on for channels 2 and 3. The result is that the amplitudes samples from each channel share the line sequentially, becoming interleaved to form a complex PAM wave, as shown above.

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A major problem in any TDM system is the synchronization of the transmitter and receiver timing circuits. The transmitter and receiver must switch at the same time and frequency. Also SW1 must be in the channel 1 position when SW2 is in the channel 1 position, so that the switches must be synchronized in position also.

In a system that uses analogue modulation (PAM) the time slots are separated by guard slots to prevent crosstalk between channels.

This figure 8 shows the waveforms produced during the operation of the PAM-TDM system.

Timing waveform of TDM-PAM system

Figure 8 It can be anticipated from above process that the receiver switch has to follow two constraints:

1. It must rotate at the same rate as the transmitter switch.

2. It must start at the same time as the transmitting switch and it must establish electrical contact with the same channel no. as that of the transmitter. If these two conditions are met, the receiver is said to be in synchronization with transmitter. If constraint one is not met, the samples of different sources would get mixed at the receiver. If constraint two is not met, the information from

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source 1 will be received by some other channel which is not intending to accept the information from that particular channel. To establish synchronization, the receiver needs to know:

a. Frequency/ rate of operation at transmitter.

b.Sample identification. This increases the transmitter and receiver complexity and cost.

Figure 9

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Practical Aspects of Time Division Multiplexing: In time division multiplexing the correct operation of transmitter switch which creates samples, is a must. The functioning of TDM switch is complex. But its understanding is easy, provided you are aware of the existence of circuit delays and setting times. Theoretically large number of samples can be multiplexed in time domain, but its practical implementation becomes harder and harder as the time interval between consecutive samples decreases. In ST2102, the operations of transmitter switch are controlled by the transmitter timing logic. (See figure 10)

Transmitter section

Figure 10 The opening and closing of particular switch depends upon the decoder output provided in transmitter timing logic. The decoder's output can be obtained at TP7, 8,9,10. Observe that the output at each of these test points is a train of pulses at frequency 16 KHz and with pulse duration set by the duty cycle selector switch.

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The decoder's output depends upon two quantities:

a. Divider output

b. Decoder Enable pulse train which is provided by the duty cycle control signal. The following table 1 summarizes the switch operation for various inputs to the decoder.

Table 1

Divider Output Transmitter Sampling Switches

MSB TP3

0

0

1 1

LSB TP2

0

1

0 1

CH0 TP7

Closed

Open

Open Open

CH0 TP8

Open

Closed

Open Open

CH2 TP9

Open

Open

Closed Open

CH3 TP10

Open

Open

Open Closed

The decoder output is decided by the divider output. But the operation takes places only when the decoder is enabled. The enable signal is active low and it is supplied from the duty cycle control switch (TP4) the switch is closed when a low signal is applied to it. The duration of a particular switch closing is decided by the duty cycle control switch whose output drives the enable input of the decoder. For different setting of the duty cycle switch, the output width driving the decoder's enable input varies. Hence the duration for which the switch remains closed also varies. The two control signals to the decoder create a problem. The problem arises when the decoder enable signal appears while divider output is changing. It causes sampling error, because the binary code at the divider output may initially correspond to a different switch. To overcome this problem, the duty cycle output is made to lag by 5% of one channel time slot. This allows the divider output to settle to a constant level before the enable signal arrives. Figure 11 illustrates the timing of the two signals when the duty cycle control is set to "9". The period allocated for transmitting one sample is called as a time slot. On ST2102 four channels are multiplexed. The groups of four time slots are termed as a frame.

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Time sequence for TDM-PAM system

Figure 11

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Synchronization The most vital requirement of a time division multiplexed system is synchronization. The Transmitter and Receiver are said to be synchronized when:

1. The rate of operation at transmitter is same as the rate of operation at receiver. 2. Samples can be identified with different channels i.e. time slot 0 samples must

go to channel 0 outputs, time slot 1 samples must go to channel 1 output and so on.

The circuitry that generates the timing signal for the system is called clock. Often the clock generates periodic rectangular pulses and hence is known as clock pulses. The question may arise "why is the clock so important?” As we know, the time division multiplexing and de-multiplexing requires a particular operation to occur on the precise time interval. Failure to meet this requirement leads to signal corruption, distortion and even complete system breakdown. The circuit which ensures precisely timed action is the clock circuit. All the time related processes derive the timing directly or indirectly from the system clock.

For correct operation of receiver, the switching rate should be same as that for transmitter. To do this the receiver clock must match with the transmitter clock. Besides clock signal, the receiver also requires information from the transmitter to identify one time slot per frame and so as to pass the time slot to correct output channel. If it is achieved for one time slot, then other time slots in the frame are passed to the correct channels. It is ensured by frame synchronization signal.

These two signals namely the clock signal and Frame synchronization signal should be transmitted by the transmitter along with the information signal. The TDM PAM trainer provides you the flexibility of using three different modes of these information transfers.

Mode 1: Three links between Transmitter & Receiver (figure 12) It gives rise to the most simple receiver circuitry. In this mode a separate transmission media are used to carry the information signal, the clock signal, and the frame synchronization signal.

Mode 2: Two links between transmitter & Receiver (figure 13) The number of links between transmitter and receiver can be reduced to two by embedding the frame synchronization information in the TDM waveform.

However, there is another way in which the number of links can be reduced to two. An easy solution to do this is to generate the clock locally at the receiver. This would remove the need of link for clock signal.

But the above solution is not error-free. The receiver and transmitter clock can at anytime slip out of synchronization. This may be due to temperature variation, environmental changes, aging of components etc. Hence this solution is not reliable. The alternate way, which is more reliable, is to extract the clock information from the frame synchronization signal.

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On TDM PAM trainer, the clock signal is multiple of frame synchronization signal. The clock frequency is four times that of the frame synchronization frequency. Also their rising edges occur simultaneously. We may add a circuitry, which can generate clock signal from the frame synchronization signal on receiver board.

By adding a further circuitry, we can compare the frame synchronization signal to every fourth receiver clock pulse and generate a control signal. This control signal can be used to adjust the receiver clock frequency. This will use the correct matching of transmitter and receiver clock.

Mode 3: One link between Transmitter & Receiver (figure 14) The number of links connecting transmitter and receiver can be reduced to one, thus achieving significant transmission media saving.

Note: The word 'link' refers to one set of dedicated connections and not necessarily one wire. Though TDM PAM trainer uses one 4mm Banana-Banana connector, because the receiver shares a common ground signal.

The reduction in number of links is achieved by using one time slot to transmit synchronization signal along with the information samples. Naturally, this synchronization signal must be different from the information samples for the receiver to distinguish it from the other samples. The distinction is achieved by fixing the amplitude of the synchronization level samples considerably greater than the maximum information signal amplitude.

Also, because the sync level pulse occurs in the same time slot in every frame, it refuses to establish synchronization and to generate the clock at the receiver.

The result is increased complexity. To implement this mode we require the de-multiplexer to be able to distinguish the synchronization signal from the information samples. Also, at the transmitter we require a circuitry to ensure that maximum amplitude of any information signal is limited to less than the synchronization signal detection level.

Model 1 Three Links Between Transmit Multiplexer and Receiver De-multiplexer

Figure 12

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Model 2

Two Links Between Transmit Multiplexer and Receiver De-multiplexer Figure 13

Model 3

One Link Between Transmit Multiplexer and Receiver De-multiplexer Figure 14

Phase Locked Loop : A PLL compares two input signals and produces an error signal which is proportional to their phase difference. The error signal is then low-pass filtered and used to drive a voltage-controlled oscillator (VCO) which creates an output frequency. The output frequency is fed through a frequency divider back to the input of the system, producing a negative feedback loop. If the output frequency drifts, the error signal will increase, driving the VCO frequency in the opposite direction so as to reduce the error. Thus the output is locked to the frequency at the other input. This input is called the reference and is often derived from a crystal oscillator, which is very stable in frequency.

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Block diagram of Phase lock Loop

Figure 15 Analog phase locked loops are generally built of a phase detector, low pass filter and voltage-controlled oscillator (VCO) placed in a negative feedback closed-loop configuration. There may be a frequency divider in the feedback path or in the reference path, or both, in order to make the PLL's output signal frequency an integer multiple of the reference. A non integer multiple of the reference frequency can be created by replacing the simple divide-by-N counter in the feedback path with a programmable pulse swallowing counter. This technique is usually referred to as a fractional-N synthesizer or fractional-N PLL. The oscillator generates a periodic output signal. Assume that initially the oscillator is at nearly the same frequency as the reference signal. Then, if the phase from the oscillator falls behind that of the reference, the phase detector changes the control voltage of the oscillator, so that it speeds up. Likewise, if the phase creeps ahead of the reference, the phase detector changes the control voltage to slow down the oscillator. Since initially the oscillator may be far from the reference frequency, practical phase detectors may also respond to frequency differences, so as to increase the lock-in range of allowable inputs. The block commonly called a low pass filter generally has two distinct functions.

The primary function is to determine loop dynamics, also called "stability". This is how the loop responds to disturbances, such as changes in the reference frequency, changes of the feedback divider, or at startup. Common considerations are the range over which the loop can achieve lock (pull-in range or lock range), how fast the loop achieves lock (lock time or lock-up time) and Overshoot (signal) (damping). Depending on the application, this may require one or more of the following: a simple proportion (gain or attenuation), an integral (low pass filter) and/or derivative (high pass filter). Loop parameters commonly examined for this are the loop's gain margin and phase margin. Common concepts in Control Theory are used to design this function and are covered in the Control system section.

The second common consideration is limiting the amount of reference frequency energy (ripple) appearing at the phase detector output that is then applied to the VCO control input. This frequency modulates the VCO and produces FM sidebands commonly called "reference spurious". The low pass characteristic of this block can be used to attenuate this energy, but at times a band reject "notch" may also be needed.

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The design of this block can be dominated by either of these considerations, or can be a complex process juggling the interactions of the two.

Depending on the application, either the output of the controlled oscillator, or the control signal to the oscillator, provides the useful output of the PLL system.

It should also be noted that the feedback is not limited to a frequency divider. This element can be other elements such as a frequency multiplier, or a mixer. The multiplier will make the VCO output a sub-multiple (rather than a multiple) of the reference frequency. A mixer can translate the VFO frequency by a fixed offset. It may also be a combination of these. An example being a divider following a mixer; this allows the divider to operate at a much lower frequency than the VCO without a loss in loop gain. The Phase Locked Loop serves as a synchronized clock generator in case when the transmitter clock is not transmitted. (As in connecting mode 2 & 3) Simple local oscillator serves the solution for simple defects like oscillator drift, component aging, and power fluctuations. All these variations cause the oscillator to step out of synchronization which is most vital for the TDM systems.

Phase Locked Loop (PLL) has very wide range of applications e.g. it is used in AM & FM demodulation, frequency multiplication, pulse regeneration and synchronization to name a few. The following lines describe the basic blocks and operations of the Phase Locked Loop (PLL) See figure 16.

The heart of PLL is the voltage controlled oscillator (VCO). The frequency of the signal generated by VCO is depends upon the DC voltage applied to its input. Higher the applied voltage higher is the frequency with suitable feedback; it is possible to generate the signal which is in synchronization with phase and frequency of a received input signal. The next important block of PLL circuit is the phase comparator / detector circuit. The function of this block is to compare the phase difference between the two applied input signals and generate an output proportional to their difference.

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Basic Operation of Phase Locked Loop Figure 16

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If the phase comparator input signals rising edge does not occur simultaneously with that of the input signal at other terminal, the phase comparator generates an error signal. This will be the case when the input signals are unmatched. i.e. either they have different frequency or having phase difference.

The error signals have either lead or lag phases which are passed to a low pass filter. This filter is generally referred as loop filter since it forms past of the PLL loop. The loop filter extracts the mean level information of the input error signals. This mean level depends upon the Phase/Frequency difference of the two inputs to the applied to the phase comparator. More the Phase/Frequency difference larger is the mean level. The loop filter's capacitor holds the mean level information which is applied to the VCO's control input. When the mean level is constant, the VCO output at constant frequency between error pulses. Error pulses either raise or lower this level to correct the VCO output frequency and therefore align the phase comparator input signals. If the input frequency is greater than the oscillator output frequency the error pulses generated increase the VCO output frequency by increasing the mean level.

If the input frequency is lesser than the oscillator output frequency the error pulses generated decreases the VCO output frequency by decreasing the mean level.

In this manner the PLL generates and synchronized clock signal. There are few terminologies related to PLL with which you should be familiar:

1. Hold in Range or Locked Range : When the frequency of PLL is synchronized to that of the signal is said to be locked. Once locked, the PLL output will be synchronized to the input signal over a limited frequency range. This frequency range is called as hold in range for locked range. If the frequency range of the input signal is very different from the natural frequency of the PLL, it may never be able to lock on to it.

2. Capture Range : It is defined as the range of frequencies over which the PLL can initially lock. In general Locked Range is large than the capture range. On TDM PAM trainer the locked range and the capture ranges are same. It is not necessary that the output of VCO can only be square wave. Although square wave output is generated by VCO on TDM PAM trainer, the output can be obtained as a sine wave, triangular wave or other wave forms by having a suitable PLL.

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PLL PLL as Frequency Multiplexer: One of the most important uses which the PLL can be put to is the frequency multiplier circuit. If on output frequency desired is N times the frequency applied to the input, it can simply be obtained by placing a module-N counter between the VCO output and the phase comparator input.

e.g. if the desired PLL output frequency is four times the applied input frequency, place a module 4 counter between VCO output and phase comparator input. See figure 17

Phase Locked Loop

Figure 17 The module-4 counter can be simulated by using the third bit output of a binary counter. The third bit output provides one output pulse for every four input pulses.

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TDM Synchronization As we have studied that receiver system requires both the synchronization signal and the clock signal for its accurate operation. Fortunately, the PLL can provide both information since on TDM-PAM trainer, the channels are sampled once per frame and the total number of channels is four. The clock frequency is four times the frame synchronization frequency. Because the frame synchronization signal and the clock signal are related, these two signals can be obtained from one PLL as shown in figure 18.

Use of PLL Circuit for TDM Synchronization

Figure 18 The timing of switch operation relative to the TDM waveform is also vital. To ensure the correct operation, one way is to use the leading edge of receiver switch control signal to operate the required channel switch. This is perfectly acceptable in ideal conditions. However, in practice many devices introduce delays between input and output signals and hence the closing of the switch may not be exactly aligned to the TDM sample. The result of a mismatch is as shown in figure 19.

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Figure 19

Also as the duty cycle decreases the adverse effect of delays become greater. A solution of this problem is to extract the samples by operating the switches mid way between the samples. See figure 20.

Figure 20

To cause the operation to start midway between the samples, we require advancing the receiver control pulse cycle relative to TDM samples. This is achieved by inserting delay element between the VCO an output and the binary counter input. The delay element may be a monostable. This causes the clock pulses to slightly advance in time.

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The input to the PLL is the frame synchronization signal. The frame synchronization signal can be obtained in two ways:

1. From Transmitter CH0 output (Mode 2). This requires a separate link. 2. By including the sync information within the sample (Mode 3).

This reduces the number of links to one. As it has been described, the sync pulses have amplitude greater than the highest possible amplitude of other channel's samples. At receiver system a voltage comparator is used to extract the sync information. The voltage comparator compares the incoming TDM samples with a reference level (or threshold level). The threshold level is set such that it is greater than the maximum amplitude of information signals but is lower as compared to the sync pulse amplitude. The voltage comparator provides an output pulse each time a sample goes above the threshold level. See figure 16.

CH 0 CH 2 CH 3 CH 0 CH 1 CH 2 CH 3 CH 0 CH 1 CH 2 CH 3

Figure 21 The output is a pulse per frame which is an indication of the Time slot 0 in the TDM signal. This pulse is utilized by the PLL to generate the clock and sync information.

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Complete PAM Receiver The receiver circuitry depends upon the choice of the method of Synchronization employed. Let us review the three modes of connecting the transmitter and receiver. They are: Mode 1: Three links:

Units at receiving End Transmission Link Receiver TDM samples

Receiver Timing Logic Frame Sync Clock

Features: 1. Simplest receiver Mode 2: Two links

Units at receiving End Transmission links Receiver TDM samples Receiver timing logic Frame Sync Phase locked timing Logic Features: 1. Receiver clock generated by local oscillator.

2. Synchronization obtained from frame synchronization signal. Mode 3: One Link Units at Received End Transmission link Receiver TDM samples Receiver Timing Logic Phase Locked Timing Logic Features: 1. Synchronization information interlinked with TDM samples. 2. Receiver clock regenerated locally.

Whichever the mode is chosen, the receiver and receiver timing logic are common to all. These blocks require the following three signals for their operation:

• TDM samples i.e. Information signal.

• Timing control signal at Receiver Clock input Socket.

• Synchronization signal at Receiver CH0 input Socket. Depending upon how we decide to provide these three signals dictates the use of three correcting modes?

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Receiver The receiver consists of a unity gain buffer, followed by switches and low pass filter. The input socket viz. Receiver Input receives the TDM samples. These samples are passed through the unity gain buffer to prevent its loading. The buffered signals are passed through the switches, which close at the correct instance of time. The operation of the switch is controlled by signals from the receiver timing logic circuitry. The particular switch closes when the sample corresponding to that particular channel is chosen. The result is PAM waveform at correct channel. The PAM signal is demodulated by passing it through the low pass filter. The low pass filter removes the higher frequency components present with the signal. The result is the reconstructed waveform at the corresponding channel.

Receiver Timing Logic: The accurate and error free reproduction of the signals requires pre-use timing controls of various operations. This function is carried on receiver system by, receiver timing logic.

The receiver timing logic accepts two input signals viz. Receiver Clock and Receiver CH0. These signals may come from the transmitter or receiver itself. The receiver timing logic operates the receiver switch in a manner similar to the transmitter switch operation.

The Receiver Clock signal ticks a two bit binary counter. The outputs of the two bit binary counter are passed to a decoder which identifies which particular switch is to be closed e.g. If the binary count is 01, the switch corresponding to channel1 will close.

To ensure that the count always starts at 0, the binary counter is reset by the frame synchronization signal at start of every frame. (Provided by Receiver CH0 input)

Thus the operation of switch in receiver system is similar to that of the transmitter system except for a fact that in receiver the switches are closed for the whole durations of the particular channel. It is unlike that in the transmitter system where the closing of switch depends upon the timing as well as the duty cycle selected.

As the switch is closed for its whole duration, the decoder does not require an enable signal.

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Testing Instruments Needed for Experiment 1. Oscilloscope 20 MHz, Dual Trace, ALT Trigger. 2. Oscilloscope probes X1 – X 10 etc.

3. Connect the power cord to the trainer. Keep the power switch in ‘Off’ position. 4. Connect 1 KHz Sine wave to signal Input.

5. Switch ‘On’ the trainer's power supply & Oscilloscope. 6. Connect BNC connector to the CRO and to the trainer’s output port.

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Experiment 1 Objective: To understand the synchronization and control signals available on ST2102.

Equipment Required: 1. ST2102 with power supply cord

2. Oscilloscope with connecting probe 3. Connecting cords

Connection Diagram:

Figure 1.1

Procedure: Initial Setup of Trainer: Function Generator pot direction : Anti clock wise

Duty cycle Position : 5 Delay control : Anti clockwise

Comparator Threshold level : Anti clockwise 1. Connect the power cord to the trainer. Keep the power switch in ‘Off’ position.

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2. Switch ‘On’ the trainer's power supply & Oscilloscope.

3. Connect BNC connector to the CRO and to the trainer’s output port.

4. Observe the clock signal (TP5) provided on Transmitter Timing Logic block on CRO. It will be a train of pulses having clock frequency of 64 KHz.

5. Display the clock signal (TP5) along with channel 0(TP6). Observe the relation between two signals.

6. Vary the Duty Cycle Selector switch and observe the variation in both signals (TP5 & TP6).

7. Observe the waveforms at TP7, 8, 9 & 10. Sketch the relative time graph between the waveforms observed at TP 5, 7, 8, 9 & 10.

8. With the same links, observe the waveform at Transmitter CH0 output (TP6) on channel 1 of the oscilloscope.

9. Observe the waveforms at TP7, 8, 9, & 10 on the other channel. 10. Plot the wave forms in time domain with reference to the Transmitter CH0

Signal.

Conclusion: 1. The ‘On’ and ‘Off” time of Sync signal is changed as we vary the Duty Cycle

Selector Switch. 2. The switching time is varying as we change duty cycle, so accordingly we can

change sampling period of input signals.

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Experiment 2 Objective: To demonstrate the switching delay and its control on ST2102 with potentiometer.

As it has been described the switch operation is not delay free. There is always a time delay between the switch closing and the moment when the control signal was applied to it.

Equipment Required: 1. ST2102 with power supply cord 2. Oscilloscope with connecting probe

3. Connecting cords Connection Diagram:

Figure 2.1

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Procedure: A. Initial Setup of Trainer: Function Generator pot direction : Anti clock wise Duty cycle Position : 5

Delay control : Anti clockwise Comparator Threshold level : Anti clockwise

1. Connect the power cord to the trainer. Keep the power switch in ‘Off’ position. 2. Switch ‘On’ the trainer's power supply & Oscilloscope. 3. Connect BNC connector to the CRO and to the trainer’s output port. 4. Connect the Sync Level to Transmitter's CH0 input socket with 4mm banana

Connector. Set voltage level to 5V with the aid of corresponding potentiometer by observing the signal at TP11 on oscilloscope.

5. Set the Duty Cycle Selector to position '4'. 6. On the dual channel oscilloscope observe the waveforms at TP7 & TP20. The

test point number 7 waveform controls the closing of the switch where as waveform at TP20 contain the samples of the input channels.

7. Plot these waveforms over one complete cycle of waveform at TP2. Estimate the delay between the application of control signal (available at TP7) and the sampling (available at TP20) to nearest 0.5µs. The delays inherent in operations are unavoidable but can cause errors if they are too large.

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B. Initial Setup of Trainer for delay control: Function Generator pot direction : Anti clock wise


Comparator Threshold level : Anti clockwise

Figure 2.2

1. Connect the power cord to the trainer. Keep the power switch in ‘Off’ position.


3. To observe the effect of 'Delay Control' in Receiver Timing Logic, make following connection with the help of cords : a. Sync Level of function generator to CH 0 of transmitter

b. Transmitter Clock to Receiver Clock c. Transmitter CH 0 to Receiver CH 0

d. Transmitter Output to Receiver Input.

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The variation of Delay Control potentiometer varies the time between switch operations with respect to TDM signal.

4. Switch ‘On’ the trainer's power supply & Oscilloscope. 5. Observe the sampled waveform (TP20) and the control signal to receiver's

channel 0 (TP35) on the oscilloscope. 6. Now set the Delay Control potentiometer fully clockwise. Again observe the

sampled waveform (TP20) and the control signal to receiver channel 0 (TP35) on the oscilloscope.

7. Note how the waveform at TP35 changes with respect to the sample waveform. Turn the Delay Control potentiometer fully anti-clockwise to give minimal delay. Display the waveforms at TP35 and TP41 on the oscilloscope simultaneously. These waveforms show the control signal and the extracted samples in time domain relatively. Measure width of the sample at TP41.

8. Turn the Delay Control Potentiometer fully clockwise. Observe the waveforms at TP35 & TP41 on oscilloscope simultaneously. Measure the width of the sample at TP41.

9. Plot the waveforms of TP20, 35 & 42 relatively in time domain in fully clockwise and anticlockwise in the case of Delay Control potentiometer.

Conclusion: 1. For proper signal recovery at receiver delay should be minimum.

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Experiment 3 Objective: To show the importance of frame synchronization signal in receiving the correct output at correct output channel.



Connection Diagram:

Figure 3.1

Procedure: Initial setup of Trainer: Function Generator pot direction : Anti clock wise


Comparator Threshold level : Anti clockwise

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1. Connect the power cord to the trainer. Keep the power switch in ‘Off’ position.


3. To observe the importance of Frame synchronization in Receiver, make Following connection with the help of cords :

a. Sync Level to CH 0 b. Transmitter Output to Receiver Input.

c. Transmitter Clock to Receiver Clock 4. Switch ‘On’ the trainer's power supply & Oscilloscope.

5. Set the sync levels to 5V with the aid of potentiometer. The sync level can be observed at TP11.

6. Observe the Transmitter Output signal on one channel of the oscilloscope. On other channel, check the wave from the inputs of all receivers’ low pass filters (TP41, 43, 45 & 47).

7. Find out receiver channel that contains the extracted samples.

8. Remove the Transmitter Clock and Receiver Clock link momentarily. Replace the link after a moment.

Now find out receiver channel that contains the extracted samples. 9. Repeat steps 7 & 8 several times. You will probably find the extracted samples

appearing at different output channel after each step.

Conclusion: 1. Synchronization must be in proper way otherwise actual signal can not be

received at receiver; some distortion may be presented in received signal.

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Experiment 4 Objective: To study the extraction of Sync Pulses from the TDM samples in operating mode 3.



Connection Diagram:

Figure 4.1

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Procedure: Initial setup of Trainer: Function Generator pot direction : Anti clock wise Duty cycle Position : 5


1. Connect the power cord to the trainer. Keep the power switch in ‘Off’ position. 2. Connect BNC connector to the CRO and to the trainer’s output port.

3. Make following connections with the help of cords between Function Generator block and the Transmitter block.

a. Sync Level to CH0 input b. ~500 Hz to CH1 input

c. ~1KHz to CH2 input d. ~2KHz to CH3 input

4. Switch ‘On’ the trainer's power supply & Oscilloscope. 5. Ensure following peak voltage levels at the described test-points by varying the

corresponding potentiometers in the Function Generator Block. a. Sync Level - 7V (at TP11)

b. ~500 Hz - 4V (at TP13) c. ~1KHz - 3V (at TP15)

d. ~2KHz - 2V (at TP17) This will help you to distinguish, the samples in multiplexed condition.

6. Observe the Transmitter Output (TP20) on oscilloscope. Use ~500Hz sine wave at TP13 for external triggering purpose to obtain the stable display. The sync pulses are ideally distinct in TDM signal by their highest amplitude.

7. Connect the Transmitter Output to Receiver Input socket. Also turn the Comparator Threshold Level potentiometer in Phase Locked Loop Timing Logic Block fully clockwise. This will ensure the highest comparator threshold level. The comparator generates a pulse whenever the voltage level of TDM signal exceeds the comparator's threshold level. Observe the comparator's output at TP22. It will be stream of pulses. Note the frequency of the output pulse train.

8. By varying the Sync Level potentiometer in the Function Generator block find out the comparator's threshold level to the nearest value.

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Keep the fact in mind, that for error free operation of the comparator block, the Sync Level amplitude must be well separated from the information signals amplitude.

9. Set the comparator threshold voltage to 3.5V by varying the Comparator Threshold Level potentiometer. Set the peak voltage level of the stated waveforms by verifying the corresponding potentiometer in the Function Generator block. a. Sync Level - 3.5V (at TP11)

b. ~500 Hz - 2V (at TP13) c. ~1KHz - 3V (at TP15)

d. ~2KHz- 4V (at TP17) 10. Observe the output of the comparator block at TP22 Explain why the frequency

and wave shape of the output is different in the case? This exercise demonstrates the importance of the level of sync signals in order to extract the sync, pulses correctly. Failure to do so causes large amplitude information signals to generate false pulses for PLL.

If the threshold level is very high the sync pulses or information signals would generate an output pulse from the comparator and the PLL output would be at lowest frequency.

Conclusion: 1. To get the actual signal at receiver, we must have sync signal in transmission for

mode 3, it must be made separable then other signals. 2. The comparator threshold level must be adjusted in such a way that we will get

pulse train in PLL’s output.

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Experiment 5 Objective: To demonstrate how the PLL locks a particular signal. As it has been described earlier, the Phase Locked Loop is used in connecting mode 2 & 3 to generate synchronization information and the clock signal. We will now investigate the control signals and the output of various sub-clocks of the PLL circuit. This will help to understand the process by which the PLL locks to the signals and generate the sync pulses and the clock signal.



Connection Diagram:

Figure 5.1

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Procedure: Initial setup of Trainer: Function Generator pot direction : Anti clock wise Duty cycle Position : 5



3. Switch ‘On’ the trainer's power supply & Oscilloscope. 4. Note the PLL's output frequency at TP28, without any input applied to it. It is

the lowest frequency generated by the PLL. Explain why this is so?

5. To see how the PLL output frequency changes when the PLL locks to an input signal make following changes in the system configuration.

Push the level of the toggle switch in Phase Locked Loop Timing Logic block in upward position. This connects the PLL blocks input to the PLL I/P socket.

6. Make the connection between Transmitter CH0 output socket in Transmitter Timing Logic block of the PLL input socket. This causes the PLL to lock the sync signal of 16 KHz.

7. Observe the input and output waveforms at TP23 and 28 respectively. The PLL output signal is the SYNC signal used for frame sync by the receiver.

8. Observe the waveforms at TP28 (Sync signal) and TP26 (Clock signal) on the oscilloscope. Notice that there is a delay between the two signals.

Measure this delay and observe the relation between Sync output frequency and the CLOCK output frequency.

Conclusion: 1. There should be minimum frequency available at output of PLL, without any

input, due to its internal oscillator. 2. Threshold level is so much significant as we need to adjust it otherwise we will

get problem in our synchronizations.

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Experiment 6 Objective: To interconnect the various functional blocks and to observe the overall effect of the individual parameter/ mode on the communication system (Complete TDM PAM System)

Equipment Required: 1. ST2102 with power supply cord 2. Oscilloscope with connecting probe

3. Connecting cords

Connection Diagram:

Figure 6.1

ST2102


Procedure: Initial setup of Trainer: Function Generator pot direction : clock wise Duty cycle Position : 5

Delay control : Anti clockwise Comparator Threshold level : clockwise


3. Make following connections with 4mm banana to banana connectors: a. 250 Hz to CH 0 input socket of Transmitter block.

b. 500 Hz to CH 1 input socket of Transmitter block. c. 1 KHz to CH 2 input socket of Transmitter block.

d. 2 KHz to CH 3 input socket of Transmitter block. 4. Switch ‘On’ the trainer's power supply & Oscilloscope.

5. Observe the Transmitter Output (TP20) along with CH0 input (TP11) for reference with the aid of oscilloscope. Use Transmitter's CH0 Input for external triggering of oscilloscope. This will help to achieve a stable waveform. The Transmitter Circuit samples all channels at different time intervals. The time division multiplexed samples appear at the Transmitter Output. (TP20). Vary the amplitude of the input sine-waves by varying the potentiometers in the Function Generator block. This will help in identifying which sample belongs to which input channel.

Ensure all the potentiometer in the Function Generator block is turned fully clockwise before continuing with the exercise.

Conclusion: 1. We can observe various signal to get sampled and multiplexed in a channel by

varying their amplitudes, it would be easy to observe every signal to get multiplexed on a channel.

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Experiment 7 Objective: To observe output waveforms at receiver channels, CH1/ CH2/ CH3 on oscilloscope & observe preservation of DC level in output waveform compared to input signal.

Procedure: Initial setup of Trainer: Function Generator pot direction : clock wise


Comparator Threshold level : clockwise 1. Connect the power cord to the trainer. Keep the power switch in ‘Off’ position. 2. Connect BNC connector to the CRO and to the trainer’s output port.

3. Make the following connections with banana connectors:

a. Transmitter Output to Receiver Input b. Transmitter Clock to Receiver Clock

c. Transmitter CH0 to Receiver CH 0 This ensures mode1 operation of the TDM PAM trainer (see diagram7.1) for interconnections. Transmitter Clock signal is used by the receiver to synchronizes its activity & Transmitter CH0 signal is used by the receiver to know which sample belongs to channel 0.

4. With the help of oscilloscope, observe the Transmitter Output signal (TP20) & the Receiver’s CH 0 Low Pass Filter's input (TP41)

The oscilloscope plots the extracted sample corresponding to channel 0 from the time division multiplexed samples.

5. Display the Receiver's Low Pass Filter's input (TP41) & output (TP42) simultaneously on the oscilloscope. The signal at TP42 shows the reconstructed ~250Hz sine wave which was transmitted at CH0.

Similarly view the outputs of all Receiver Low Pass Filters at TP44, 46, 48. Observe that each of the original sine waves has been correctly reconstructed.

6. The Duty Cycle Selector Switch can be varied from 0% to 90% in steps of 10%. Display Transmitter Output (TP20) and receiver CH0 output (TP42) on the oscilloscope

Now vary the Duty Cycle Selector switch. Notice the effect of variation duty cycle selector switches on Transmitter Output & amplitude of the Receiver's CH 0 Output.

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The Receiver's CH0 output increased with the increasing sampling duty cycle. This is due to the fact that the ST2102's Low Pass Filters are not preceded by the Sample/ Hold Circuitry.

7. Return the Duty Cycle Selector Switch to position '5'.

8. The three links required between transmitter & receiver in Mode 1 of operation can be reduced to two in Mode 2. To configure the trainer in mode 2 of operation, disconnect Transmitter CH0 & Receiver CH0 link & make following new links.

a. Transmitter CH0 to PLL Up b. Sync to Receiver CH0

c. PLL O/P to Receiver Clock

Also ensure that the level of toggle switch in Phase Locked Loop Timing Logic is in upward position. The configuration is given in Figure 7.2.

9. The Phase Locked Loop locks onto the Transmitter CH0 signal & produces two outputs. a. Sync: This serves the same purpose as Transmitter CH0, Receiver CH0 link

i.e. it tells the Receiver which of the transmitted signal belongs to channel 0. b. CLK: It is used to clock the receiver.

These signals can be examined on TP28 & 26 respectively. 10. Observe the receiver's CH0, CH1, CH2 & CH3 output on the oscilloscope

(TP42, 44, 46 & 48). Notice that the wave shapes are still preserved in mode 2. 11. The number of links can be further reduced to one link in mode 3. In this

operational mode, the sync pulse are transmitted along with the other samples in channel 0 time slot i.e. channel 0 is dedicated to carry sync pulses. To configure the trainer in mode 3 of operation, remove following links. a. ~250 Hz to Transmitter's CH0 Input

b. Transmitter CH0 to PLLIP Socket. Now establish the following connections,

a. Sync Level in Function Generator Block to Transmitter's CH0 Input. b. Ensure that the toggle level in Phase Locked Loop Timing Logic Block is

in upward position.

The configuration is as shown in diagram 7.3.

12. Observe Transmitter Output & Transmitter's CH1 input (TP13) on the oscilloscope. Use Transmitters CH1 Input for scope triggering (in External Trig mode). Vary the Sync Level preset & observe how the sync pulses change in amplitude. Return the Sync Level Pot to fully clockwise position. These sync pulses are fed to the voltage comparator which extracts the sync pulses. The threshold level of the comparator has been set such that it can easily distinguish

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between sync pulses & the other samples. These sync pulses are fed to the Phase Locked Loop circuitry which locks on to the sync pulse, and generates sync clock signal as in mode 2.

13. Observe the Receiver's CH1, CH2 & CH3 Outputs (TP44/46/48) on oscilloscope. Notice that the wave shapes still preserved in mode 3. Receiver CH0 output (TP42) is having DC level related to the amplitude of the transmitted sync pulses.

Conclusion: 1 We can observe here that its so convenient to use mode 3 for long distance

transmission because we don’t need to feed extra line for synchronization and clock signals, these signals are transmitted along with signal itself. But we require complex circuitry for this mode, which adds in cost for communication. Mode 1 & mode 2 are use for short distance transmission but we need to send clock or sync signal for effectively receive our signals.

Mode 1

Figure 7.1

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Mode 2

Figure 7.2

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Mode 3

Figure 7.3

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Frequently Asked Questions 1. What do you mean by PAM? Ans: A sampled signal consists of a train of pulses, where each pulse corresponds to

the amplitude of the signal at the corresponding sampling time. The signal sent to line is modulated in amplitude and hence the name Pulse Amplitude Modulation (PAM).

2. List the types of multiplexing? Ans : The two most commonly used methods of multiplexing are:

1. Frequency division multiplexing (FDM) 2. Time division multiplexing (TDM)

3. What is FDM? Ans : Frequency division multiplexing is the process of combining several

information channels by shifting their signals to different frequency groups within the frequency spectrum so that they can all be transmitted over a common transmission channel.

4. What is TDM? Ans: Time division multiplexing is the process of combining the samples from

different information signals, in time domain so that they can be transmitted over the common channel. The fact utilized in TDM technique is that there are large intervals between the message samples. The samples from the other sources can be placed within these time intervals. Thus every sample is separated from other in time domain.

5. What is the function of PLL? Ans : A PLL compares two input signals and produces an error signal which is

proportional to their phase difference. The error signal is then low-pass filtered and used to drive a voltage-controlled oscillator (VCO) which creates an output frequency.

6. Draw the block diagram of PLL?

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7. Which type of feedback is used in PLL? Ans: Negative feedback closed-loop configuration is used in PLL.

8. What are the primary functions of low pass filter in PLL? Ans: A low pass filter generally has two distinct functions which are as follows:

The primary function is to determine loop dynamics, also called "stability". This is how the loop responds to disturbances, such as changes in the reference frequency, changes of the feedback divider, or at startup. Common considerations are the range over which the loop can achieve lock (pull-in range or lock range), how fast the loop achieves lock (lock time or lock-up time) and Overshoot (signal) (damping). Depending on the application, this may require one or more of the following: a simple proportion (gain or attenuation), an integral (low pass filter) and/or derivative (high pass filter). Loop parameters commonly examined for this are the loop's gain margin and phase margin. Common concepts in Control Theory are used to design this function and are covered in the Control system section. The second common consideration is limiting the amount of reference frequency energy (ripple) appearing at the phase detector output that is then applied to the VCO control input. This frequency modulates the VCO and produces FM sidebands commonly called "reference spurious". The low pass characteristic of this block can be used to attenuate this energy, but at times a band reject "notch" may also be needed.

9. What are the applications of PLL? Ans: It is used in AM & FM demodulation, frequency multiplication, pulse

regeneration and synchronization.

10. What do you mean by sampling? Ans: To convert continuous time signal to discrete time signal, a process is used

called as sampling.

11. What is sampling theorem? Ans: The Sampling Theorem states that a signal can be exactly reproduced if it is

sampled at a frequency Fs, where Fs is greater than twice the maximum frequency Fmax in the signal.

Fs > 2· Fmax

12. What is Nyquist frequency?

Ans: The frequency 2· Fmax is called the Nyquist sampling rate. Half of this value, Fmax, is sometimes called the Nyquist frequency.

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13. List different sampling techniques? Ans: There are three types of sampling, which are as follows:

1. Ideal sampling or Instantaneous sampling or Impulse sampling 3. Natural sampling

4. Flat top sampling

14. What are active and passive filter? Ans: Filter is a network designed to pass signals having frequencies within certain

bands (called pass bands) with little attenuation, but greatly attenuates signals within other bands (called attenuation bands or stop bands). .A filter network containing no source of power is termed passive, and one containing one or more power sources is known as an active filter network.

ST2102


Warranty 1. We guarantee this product against all manufacturing defects for 24 months from

the date of sale by us or through our dealers. Consumables like dry cell etc. are not covered under warranty.

2. The guarantee will become void, if

a) The product is not operated as per the instruction given in the Learning Material

b) The agreed payment terms and other conditions of sale are not followed. c) The customer resells the instrument to another party.

d) Any attempt is made to service and modify the instrument. 3. The non-working of the product is to be communicated to us immediately giving

full details of the complaints and defects noticed specifically mentioning the type, serial number of the product and date of purchase etc.

4. The repair work will be carried out, provided the product is dispatched securely packed and insured. The transportation charges shall be borne by the customer.

List of Accessories

1. Patch Cord 16"........................................................................................8 Nos.

2. Patch Cord 20"........................................................................................1 No. 3. Mains Cord.............................................................................................1 No.

4. Learning Material ..................................................................................1 No.

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