TE design processes for successive-approximation A / D converter registers D.A. Pucknell, B.Sc, B.E., Ph.D., C.Eng., M.I.E.E. Indexing terms: Analogue-digital conversion, Mathematical techniques Abstract: Transition equations (TEs) and the associated design processes provide an interesting, and often rewarding, approach to sequential-logic circuit design. However, these processes are ignored in most of the text books and many engineers are thus unaware of them. The paper sets out the salient features of the technique by taking the design of a successive-approximation register as an example. It is hoped to show that TEs allow the designer to formulate device characteristics in a way not so readily possible with the more conventional design procedures. This in turn permits some extra degrees of freedom in design and can help to achieve very economical designs as a result. The register design arrived at by the TE design process is compared with the design achieved by more conventional methods and it will be seen that the TE design presents a quite significant saving in components or component area, as the case may be. Although the design process has been illustrated for a particular application, it will be realised that the TE approach to design has much wider applications. 1 Introduction The transition-equation (TE) design approach [1-3] to the design of logic circuitry is a convenient one which is, however, largely ignored in the text books. It is, therefore, a technique of which many designers are unaware and the paper sets out to demonstrate a TE approach to the design of successive- approximation registers as used in A/D convertors (Fig. 1). Several general arrangements of logic circuitry have emerged to meet the needs of the successive-approximation register which is used in these convertors. Designs have varied from the semi-intuitive approach using an (N+ l)-bit shift register with an TV-bit 'data' register to control the N bits of the D/A convertor, to more sophisticated designs which achieve better economy in components. The TE design approach achieves a very economical sol- ution and it is compared in the paper with the results achieved by a more conventional design process. 2 Transition-equation (TE) design processes The TE approach makes use of the A and V operators [4] which deal not with logic levels but with changes or transitions in binary levels. For example: AX is a change from 0 to 1 of variable X. Similarly VY is a change from 1 to_0 of variable Y. Also AX is coincident with VX... etc. There are_also conditons of no transition to be considered such as WX (no change from logical 1 of variable X) and AX (no change from logical 0 of variable X). Such considerations can be extended to characterise common sequential circuit elements [3] such as the JK flip-flop and, in contrast to the more accepted forms of characterisation, the TE approach includes all inputs namely, asynchronous inputs, clocked inputs and the clock input itself, within the characterisation. For example, the common type of JK flip-flop shown in Fig. 2 (and needing a change from logic 1 to logic 0 on its clock input T to activate it) can be characterised as follows: AQ = + AP} = 0) which reads in words: 'Output Q can be made to change from 0 to 1 if the clear input C is held at 0 and if either there is a ' 1 ' on / coinci- dent with the falling edge of the clock (V7) or if preset P changes from 0 to 1'. (Active 'Hi' levels for P and C. have been assumed for the actual flip-flop but the levels applied to the package may be active 'Lo' as indicated by the inverting symbols in Fig. 2.) Expr. 1 (etc.) may have the static terms expanded thus: AQ = ACC{J(yT) but in the author's opinion, the addition of C is unnecessary |c N-bit D/A convertor inputs digital £H outputs?— I I 2^-212* —t outputs (N*1)-bit successive- approximation register Vout comparator _ analogue voltage jr >EOC start error signal E "dock Fig. 1 A/D convertor arrangement Paper 1217E, first received 30th June and in revised form 28th October 1980 Dr. Pucknell is with the Department of Electrical Engineering, The University of Adelaide, Adelaide, South Australia 5000, Australia clocked, inputs (VT) clear C I j K preset P C1 P Q Q -output Fig. 2 Commonly used JK flip-flop C and P are asynchronous IEEPROC, Vol. 128, Pt. E, No. 2, MARCH 1981 0143-7062/81/01079+05 $01.50/0 79
Transcript
TE design processes for successive-approximationA/D converter registersD.A. Pucknell, B.Sc, B.E., Ph.D., C.Eng., M.I.E.E.
Abstract: Transition equations (TEs) and the associated design processes provide an interesting, and oftenrewarding, approach to sequential-logic circuit design. However, these processes are ignored in most of thetext books and many engineers are thus unaware of them. The paper sets out the salient features of thetechnique by taking the design of a successive-approximation register as an example. It is hoped to showthat TEs allow the designer to formulate device characteristics in a way not so readily possible with the moreconventional design procedures. This in turn permits some extra degrees of freedom in design and can help toachieve very economical designs as a result. The register design arrived at by the TE design process iscompared with the design achieved by more conventional methods and it will be seen that the TE designpresents a quite significant saving in components or component area, as the case may be. Although thedesign process has been illustrated for a particular application, it will be realised that the TE approach todesign has much wider applications.
1 Introduction
The transition-equation (TE) design approach [1-3] to thedesign of logic circuitry is a convenient one which is, however,largely ignored in the text books. It is, therefore, a techniqueof which many designers are unaware and the paper sets out todemonstrate a TE approach to the design of successive-approximation registers as used in A/D convertors (Fig. 1).
Several general arrangements of logic circuitry haveemerged to meet the needs of the successive-approximationregister which is used in these convertors. Designs have variedfrom the semi-intuitive approach using an (N+ l)-bit shiftregister with an TV-bit 'data' register to control the N bits ofthe D/A convertor, to more sophisticated designs whichachieve better economy in components.
The TE design approach achieves a very economical sol-ution and it is compared in the paper with the results achievedby a more conventional design process.
2 Transition-equation (TE) design processes
The TE approach makes use of the A and V operators [4]which deal not with logic levels but with changes or transitionsin binary levels.
For example:AX is a change from 0 to 1 of variable X. SimilarlyVY is a change from 1 to_0 of variable Y. AlsoAX is coincident with VX... etc.
There are_also conditons of no transition to be consideredsuch as WX (no change from logical 1 of variable X) and AX(no change from logical 0 of variable X). Such considerationscan be extended to characterise common sequential circuitelements [3] such as the JK flip-flop and, in contrast to themore accepted forms of characterisation, the TE approachincludes all inputs namely, asynchronous inputs, clockedinputs and the clock input itself, within the characterisation.
For example, the common type of JK flip-flop shown inFig. 2 (and needing a change from logic 1 to logic 0 on itsclock input T to activate it) can be characterised as follows:
AQ = + AP} = 0)which reads in words:
'Output Q can be made to change from 0 to 1 if the clearinput C is held at 0 and if either there is a ' 1 ' on / coinci-dent with the falling edge of the clock (V7) or if preset Pchanges from 0 to 1'. (Active 'Hi' levels for P and C. havebeen assumed for the actual flip-flop but the levels appliedto the package may be active 'Lo' as indicated by theinverting symbols in Fig. 2.)
Expr. 1 (etc.) may have the static terms expanded thus:
AQ = ACC{J(yT)
but in the author's opinion, the addition of C is unnecessary
|c
N-bit D/Aconvertor
inputs
digital £Houtputs?—
II
2^-212*
—t
outputs(N*1)-bitsuccessive-approximationregister
Vout
comparator
_ analogue voltage
j r
>EOC
start
errorsignalE
"dock
Fig. 1 A/D convertor arrangement
Paper 1217E, first received 30th June and in revised form 28th October1980Dr. Pucknell is with the Department of Electrical Engineering, TheUniversity of Adelaide, Adelaide, South Australia 5000, Australia
clocked,inputs
(VT)
clearC
I
j
K
presetPC1
P
Q
Q
-output
Fig. 2 Commonly used JK flip-flop
C and P are asynchronous
IEEPROC, Vol. 128, Pt. E, No. 2, MARCH 1981 0143-7062/81/01079+05 $01.50/0 79
since C remaining at 0 is implied in AC which is defined hereas no change from logical 0.
Similarly
VQ = AP{K(VT) + AC} = AQ
gives the conditions necessary to change Q from 1 to 0.Finally, no-change equations may also be written
AQ = AP{J(yT) + (Vr)' + AC} + VC
and
= AC{K(VT)
(2)
(3)
(4)
but these are not so often needed and can be infered fromeqns. 1 and 2.
It must be stressed that all inputs to the flip-flops appear inthe characterisation and this information can be made use ofin any design processes for sequential circuits.
3 Design of successive-approximation register for A/Dconvertor
A 3-bit convertor has been assumed to illustrate the designprocess without involving extensive and tedious work in thetext, but the design processes can be extended for any numberof bits.
It is first necessary to consider a specification for theregister and this is derived from the following requirements:
(i) number of bits = 3(ii) conversion to start on receipt of a logic 'Hi' or on
receipt of a short 'Hi' pulse on input line S(iii) an 'end of conversion' (EOC) 'Hi' output is to be
produced when data are ready to be read (EOC is to be 'lo'during conversion)
(iv) negative-going (1 to 0) edge-activated JK flip-flops areto be used — a suitable clock source is available on line T
(v) the comparator generates an error signal on line E (seeFig. 1) so that E is to change from 'Lo' to 'Hi' when Vout >
. Va + \AV and E is to change from 'Hi' to 'Lo' when Vout <Va~\ AV.From this information and a knowledge of successive-approxi-
9-16EOC.S-iQh
reset bystart signal (AS)
E=0_"CP3
6)0110 (7)1010 W 1 1 1 0E=0 E = 1 / A E = 0 E = 1 / \ E = O
Fig. 3 State diagram for 3-bit (+ 1) successive-approximation register
CP = clock pulse
mation techniques it is now possible to draw a state diagramfor the register as in Fig. 3.
3.1 Conventional design approachIt will be seen that 16 individual states are to be generatedand, thus, four variables are needed to represent the states.However, it will also be seen that the three output bits, A, Band C, and the EOC signal, can be used as the four variables toidentify the states. Thus the state diagram has appropriateentries for C, B, A and EOC against each state. Output statesand internal states are coincident and no freedom of stateassignment exists in this case.
It is now convenient to tabulate the state changes as inTable 1 which assumes that the change back from states
\2)~&) inclusive to state (T)is effected by start(S) with EOC.This may conveniently be achieved via the asynchronousclear (C) inputs of the JK flip-flops. A suitable connection isshown in Fig. 4. (The TE associated with Fig. 4 may be'read' as follows: 'The clear inputs of all four flip-flops willbe driven to their active state when S goes 'Hi' with EOC'Hi' or, when OEC goes 'Hi' with S held 'Hi' for continuousconversions with the NAND gate of Fig. 4 providing a shortdelay for output reading'.)
We now map each flip-flop, A, B and C, and (EOC) in turn.One such map, for FFC in this case, is included here as Table2. From the maps the required equations can be obtained asindicated.
FFC
JcKc
CB
A (EOC)
0001
^ \
0100
E
0
10
00
0
0000
0
00
00
1
0000
Table 2:
1
00
00
Map of J and
1
0000
1
00
00
K
0
0000
inputs for flip-flop C
E
1
00
00
0
0000
1
00
00
1
0000
0
00
00
1
0000
0
10
00
A (EOC)
0
0001
/
/
0011
/
/
CB
0110
80 IEEPROC, Vol. 128, Pt. E, No. 2, MARCH 1981
From the map of Table 2,
Jc = BA(EOC)
Kc = EBA(EOC)
Mapping for the other flip-flops gives the following completeset of equations for J and K inputs:
Kc = EBA{EOC)
KB EA(EOC)
KA = E(EOC)
Jc = BA{EOC)
JB = CA(EOC)
JA = B(EOC)
JEOC = A
Thus, for the most obvious realisation, the complete circuitis as shown in Fig. 5a.
3.2 TE design approachThe state diagram of Fig. 3 still applies but the state-transition
digital outputEOC
EOC
clock inT
digital output
EOC,
Fig. 5 Alternative designs for 3-bit successive-approximation register
a Circuit arrived at by 'conventional' designb Circuit arrived at by TE design approach
table, Table 3, now only needs to show the transitionsrequired of each variable since we are now using the TE,eqns. 1 and 2, to characterise the JK flip-flop elements. Forexample, row (2) shows the transitions of variables C and Bin taking up states (3) or (4).
The TE form of the JK flip-flop characteristics is now tobe used to approach the design of the register. For con-venience, eqns. 1 and 2 are reproduced for reference at thispoint in the text.
0)(2)
AQ = AC{J(yT)
VQ = AP{K(VT) + AC} = AQ
Inspection of eqns. 1—3 and consideration of transitionsrequired from statesfSu to 06) in Table 3 reveals that therequirements can be met by providing VCN inputs to the clearinputs of each of the four flip-flops A, B, C and (EOC). Thuswe may write:
VCC = VCB = = (E0C)AS + SA(E0C)
(5)
This is simply implemented as set out in Fig. 4 and now, if allPreset inputs are held permanently high and Gear inputs kepthigh at all times other than during the transition specified byeqn. 5 then the requirements will be met and exprs. 1 and 2reduce to:
AQ = J(VT)
VQ = K(VT)
(la)
(2a)
Thus the inputs to be used in the rest of the design are J or Kand the clock T.
Considering the clock input T first, and with regard toTable 3, we may see that no further action of flip-flop C isrequired after the second clock pulse CP2- Also, flip-flop Bneeds no clock after CP3 and similarly, flip-flop A and flip-flop (EOC) will be free of further disturbance if the clock isremoved after CP$.
Formalising this requirement (and with regard to Table 3)we may write
(EOC) = T(A) HEOC)
where T(EOC), T(A) = clock input to FF(EOC) and FFA,respectively and Tis the clock input to the whole register.Similarly,
Transitions here to be independent of E but initiated by AS [orA(EOC) if S already H i ] .The transitions are to (VC+ AC) (VB + AB) (VA + AA) V(EOC)
ASorA£0CIFS = 1
IEEPROC, Vol. 128, Pt. E, No. 2, MARCH 1981 81
whence
Tm = TiA)(A)
Finally,
TiC) = HEOC)(A)(B)
Thus, the clock circuit becomes the simple arrangement shownin Fig. 6.
Now, we may use 'don't care' states in mapping the J and Kinputs whenever the clock signal is not present for that flip-flop.
It remains to map l's for J wherever A transitions offlip-flop output Q is required and l's for K wherever V tran-sitions are needed.
Furthermore, the mapping can be greatly simplified bytaking account of two factors:
(i) When considering the mapping of inputs to any flip-flop, the state of the variable represented by that flip-flopneed not be mapped. For example, in mapping JA to achieveA/4 transitions of the variable A, the initial state of A is inthe operator A since a 0 to 1 transition cannot take placeunless the variable is presently 0. Therefore it is obvious thatvariable A does not have to be mapped, and, similarly, each ofthe other variables can be omitted in their turn.
(ii) The error signal E can also be omitted from the map-ping since A transitions (i.e. J = \ conditions) are independentof E and V transitions (i.e. K = 1 conditions) are alwayscoincided with E = 1 and never take place when E = 0. Thusthe state of E may be omitted provided that E = 1 issubsequently 'anded' with the equations for all K inputs.*(This simplification can be used with either of the designapproaches.)Two variables are thus removed from the mapping leaving onlythree variable maps to deal with. The transitions required areeasily read from Table 3.
Thus, for flip-flop C, the map is as shown in Table 4c, 1appearing for J or for K where AC or VC, respectively, isrequired and 'don't cares' appearing wherever the clock inputis not present.
From the map
Table 4A: Map of J and K inputs for flip-flop A
Jr. = 1 Kr = IE*
Simple maps for other variables are easily set out as in Tables4fl, 4b and 4d.
Thus, the circuit designed in this way needs no logiccircuitry associated with the J and K inputs, but needs three2-input AND gates for the clock line, and one 2-input NAND,or 2-input AND and inverter, for clear inputs as before.
The circuit for this realisation appears in Fig. 6b.
4 Conclusions
It will be seen that the savings in components or componentareas are significant even in the simple case chosen. Theaddition of further stages to the TE-designed circuit of Fig.5b can be made at a cost of one 2-input AND gate per JKflip-flop stage added, whereas the conventionally designed
EOC
T (clockinput)
Fig. 6 Clock-line circuitry for TE-designed register
Table 4D: Map of K and K inputs for flip-flop (EOC)
Table 4D: Map of K and K inputs for flip-flop (EOC)
J{EOC) K(EOC)
CB 0011
0110
A0
0000
0000
1
1111
0000
From the map, J(EOC) = A K{EOQ = 0
circuit has a requirement for 2 AND gates, each having anumber of inputs which grows by one per stage added. Thereare no real problems with clock skew due to the gated clockline since it is always adjacent stages which are being set andtested.
A similar register design was arrived at intuitively someyears ago [5] and was named the 'roll-up register' owing tothe gating of the clock line T which is successively removedfrom the stages of the register as the approximation progresses.
The TE design approach also lends itself to very simplemapping techniques as it makes it obvious that what is appar-ently a five-variable problem (C, B, A, (EOC) and E) can bereduced for mapping to a three-variable problem. Anyreduction in the number of variables is welcome, both fromthe point of view of reducing complexity and of allowinglarger numbers of variables to be handled by straightforwardtechniques. For example, up to eight variables could havebeen handled in this case using Karnaugh mapping techniques(e.g. a 6-bit A/D convertor design). Computerisation of thedesign technique should also be readily achieved but theauthor has not had occasion to do so and cannot substantiatethis attribute.
Although the successive approximation register has beenused as an example, it will be realised that the TE designapproach is not limited to this application alone [6, 7] butthat there will be other situations in which very economicaldesigns can be achieved, or in which this process simplifiesthe design procedures.
IEEPROC, Vol. 128, Pt. E, No. 2, MARCH 1981
References
PUCKNELL, D.A.: 'Transition equations' for the analysis andsynthesis of sequential circuits', Electron. Lett., 1970, 6, (23),-pp. 731-733SMITH, J.R., and ROTH, C.H.: 'Analysis and synthesis of asyn-chronous sequential networks using edge sensitive flip-flops', IEEETrans., 1971, C-20, pp. 847-855PUCKNELL, D.A.: 'Sequential-circuit characterisation and synthesisusing a 'transition-equation' approach', Proc. IEE, 1973, 120,(5), pp. 551-556
4 TALANTSEV, A.D.: 'On the analysis and synthesis of certainelectrical circuits by means of special logical operators', Avtom &Telemekh, 1959, 20, pp. 895-907
5 BARTLETT, J.P., and PUCKNELL, D.A.: 'The roll-up register andits application to A/D conversions', Proc. IREE, 1973, 34, pp. 92-94
6 PUCKNELL, D.A.: 'Application equations, transition equations andthe realisation of sequential networks of JK flip-flops', Monitor,1976, 37, pp. 339-342
7 SOSNOWSKI, J.: 'An algebraic approach toward transient analysisof asynchronous circuits', Digital Processes, 1978, 4, pp. 45-66
Book reviewVisual display terminals: A manual covering ergonomics,workplace design, health and safety, task organisation.A. Cakir, D.J. Hart and T.F.M. StewartWiley, 1980, 266pp., £17.50ISBN 0-471-27793-2
With the widespread expansion of computer visual displayterminals (VDTs) numerous demands have come from usergroups, planners and designers for more information on howto design, install, and use these devices so that they will beacceptable to those who operate them. This manual has beenproduced to meet this need, and it provides a comprehensivesource book suitable for a wide range of technical and non-technical readership.
The work brings together the expertise of authors fromseveral different backgrounds: T.F.M. Stewart, formally ofthe HUSAT Research Group at Loughborough University,A. Cakir of the Technical University of Berlin, and D.J. Hartof the Inca-Fiej Research Association for newspaper tech-nology, which sponsored the work.
The manual covers an impressive range of topics. In theopening chapters there are simple descriptions of the varioustechnology components of the VDT: cathode ray tube,keyboard, control logic, character generation, systemcommunication, etc. Here the intent is to show how thedesign must pay due regard to the ergonomic needs of thehuman user. To this end sections are included on thecharacteristics of human vision and the properties of light.Also considered are the potential hazards of radiation andimplosion, which have been the subject of much publicattention. Z-radiation in particular receives extensive treat-ment, although it is difficult to see why, since there is noevidence that this represents any hazard at all for VDT users.
Later chapters deal with the ergonomic needs of VDT
workplaces, and stress that the success or failure of a VDTinstallation depends not only on the design of the VDTitself, but also on adherence to good ergonomic practice inthe design of the work place. Thus recommendations forseating, worktops, lighting, etc., are given in detail and arerelated to the type of task the VDT operator is expectedto do.
The final chapter considers certain health, safety, andorganisational problems which might arise with VDT usage,and recommends many environmental, job design, andmanagement practices which, if implemented, would avoidthese problems.
An Appendix contains ergonomic checklists for VDTs andworkplaces. Although very thorough, these checklists shouldbe used with some caution, and not in isolation from the maintext. Each 'check' question is answered by a simple YES/NO,and users may be tempted to total up a simple score from theanswers - ignoring their relative importance, and how thatdepends very much on the circumstances in which the VDTis to be used.
The book is very hardware oriented and readers will notfind much on those aspects of VDT use determined by thecentral computer system, such as good practice in application-program design, or responsetime requirements.
Anyone who is involved with the installation of VDTs —planners, designers, user groups — will find this manual veryvaluable. Although some level of technical appreciation isnecessary to understand some sections, it is a work not justfor the technically initiated in its subject area, and isparticularly recommended for those new to VDTs, who needa comprehensive understanding of how they work and shouldbe used.
