Integrated Circuit Technology Overview

Hazırlayan : Yrd. Doç. Dr. Burcu ERKMEN

Typical VLSI SystemsCell Phones

Biomedical

Automotive

Hearing aidsDigital Cameras

Computers

Why ICsIntegration improves

Size (Submicron)SpeedPowerComplexity

Smaller size of IC components yields higher speed and lower power consumption.

Integration reduce manufacturing costs (almost) no manual assembly

Discrete vs Integrated Circuit Design

Active devices, capacitors, and resistorAll possibleComponents

Schematic Capture, Simulation, extraction, LVS,

layout and routing

Schematic Capture, Simulation, PC Board LayoutCAD

Must be considered before design

Generally complete testing is possibleTesting

Model parameters vary widelyModel parameters well knownSimulation

Must be included in the designNot ImportantParasitics

Layout, Verification and ExtractionPC layoutPhysical Implementation

Very dependentIndependentFabrication

No (kit parts)YesBreadboarding

Poor absolute accuraciesWell knownComponent Accuracy

IntegratedDiscreteActivity / Item

HistoryThe First Computer

The BabbageDifference Engine(1832)25,000 partscost: £17,470

Mechanical computing devices

Used decimal number system

Could perform basic arithmetic operations

Even store and execute

Problem: Too complex and expensive!

ENIAC ENIAC -- The first electronic computer (1946)The first electronic computer (1946)

17,468 vacuum tubes7,200 crystal diodes1,500 relays70,000 resistors10,000 capacitors30 tons63 m²150 kW 5,000 simple addition or subtraction operations

Problem: Reliability issues and excessive power consumption!

Invention of the Transistor

Vacuum tubes invented in 1904 by FlemingLarge, expensive, power-hungry, unreliable

Invention of the bipolar transistor (BJT) 1947Shockley, Bardeen, Brattain – Bell Labs

First Integrated Circuitintegrated circuit 1958 Jack Kilby – Texas InstrumentsA device having multiple electrical components and their interconnects manufactured on a single substrate.

Intel 4004 MicroIntel 4004 Micro--ProcessorProcessor

19712300 transistors108 KHz operationPMOS only (10 um process)

Intel Intel Pentium 4 Pentium 4 MicroMicro--ProcessorProcessor

200042 million transistors2 GHz operation0.18 um

Intel Core 2 Quad

2008820 million transistors2.83 GHz operation45 nm

VLSI technological growth based on:

• Feature size

• Gate count of a chip

• Transistor count of a chip

• Operating frequency of a chip

• Power consumption of a chip

• Power density in a chip

• Size of a device used in chip

Moore’s Law

Gordon MooreIntel Co-Founder

In 1965, Gordon Moore noted that the number of transistors on a chipdoubled every 18 to 24 months.

820 millionCore 2 Quad2008410 millionCore 2 Duo2007

1328 millionQuad Core2006376 millionDual Core2006230 millionPentium D200577 millionPentium M2003220 millionItanium II200242 millionPentium 42000

18.9 millionCeleron19999.5 millionPentium III19997.5 millionPentium II19975,5 millionPentium Pro19953,1 millionPentium19931,2 million804861989

2750008038619851340008028619822900080861978600080801974350080081972230040041971

Transistor CountModelYear

http://www.intel.com/pressroom/kits/quickreffam.htm

Intel Processor Transistor Count Trends

Intel Processor Transistor Size Trends

45nmCore 2 Quad200865nmCore 2 Duo200765nmDual Core200690nmPentium D2005

0,13umPentium M20030,18umItanium 220020,18umPentium 420000,25umCeleron19990,25umPentium III19990,35umPentium II19970,6umPentium Pro19950,8umPentium19931um804861989

1,5um8038619851,5um8028619823um808619786um80801974

10um8008197210um40041971

Transistor SizeModelYear

http://www.intel.com/pressroom/kits/quickreffam.htm

EXACTLY HOW SMALL (AND POWERFUL) IS 45 NANOMETERS

45nm Size Comparison

o A nail = 20 million nm

o A human hair = 90,000nm

o Ragweed pollen = 20,000nm

o Bacteria = 2,000nm

o Intel 45nm transistor = 45nm

o Rhinovirus = 20nm

o Silicon atom = 0.24nm

1.000.000.000nm = 1m

Expected CMOS Downsizing from History to Future

100nmIn early 1990500nmIn early 1980

1micro-meterIn late 1970

ExpectedDownsizing

LimitEra

5nm gate lenght p-channel MOSFET has been reported in the research level

Today

Intel plans to introduce processors built on 32nm technology in 2009

(H. Wakabayashi, S. Yamagami, N. Ikezawa, A. Ogura, M Narihiro, K. Arai, Y. Ochiai, K. Takeuchi, T. Yamamoto, and T. Mogami, “Sub-10- nm Planar-Bulk-CMOS Devices using Lateral Junction Control”, IEDM Tech., Dig., pp.989-991, Washington DC, December, 2003)

Future

The ultimate limit of downsizing is the distance of atoms in silicon crystals.(about 0.3nm )

History

http://www.intel.com/pressroom/kits/quickreffam.htm

Intel Processor Operating Frequency Trends

2.83GHzCore 2 Quad20082.33GHzCore 2 Duo20072.66GHzQuad Core20063.2GHzPentium D20051.7GHzPentium M20031GHzItanium 220022GHzPentium 42000

333MHzCeleron1999600MHzPentium III1999300MHzPentium II1997200MHzPentium Pro199566MHzPentium199350MHz80486198933MHz80386198512MHz80286198210MHz808619782MHz80801974

200KHz80081972108KHz40041971

Clock Speed(s)ModelYear

Power Density

Power density too high to keep junctions at low tempPower density too high to keep junctions at low temp

-4.4273,911100.0261,900Total

-1.6147,58655.4145,180Others

5.35,5932.25,889NEC Electronics1210

-29.79,1002.46,400Hynix Semiconductor79

15.05,6192.56,463Qualcomm118

-1.98,0013.07,849Renesas Technology87

-20.810,1943.18,078Infineon Technologies (incl. Qimonda)

56

-3.29,9663.79,652STMicroelectronics65

-16.811,7683.79,792Texas Instruments44

-11.111,8204.010,510Toshiba33

-12.520,4646.817,900Samsung Electronics22

1.133,80013.134,187Intel11

2007-2008 Growth (%)

2007 Revenue

2008 Market Share (%)

2008 Revenue Company

2007 Rank

2008 Rank

Source: Gartner (December 2008)

Top 10 Preliminary Worldwide Semiconductor Vendors by Revenue Estimates (Millions of U.S. Dollars)

Worldwide IC Foundry Centers

6Europe & Israel

25Other Asian Countries

(China, Taiwan, Singapore, Korea)

12Japan

16USA

The total number of IC Foundry Center Country

ITRS - International Technology Roadmap for Semiconductors

60005500450040002500MAXIMUM NUMBER OF I/O PINS

180W175W170W160W130WMAXIMUM POWER DISSIPATION

0.6V0.6V0.9V1.2V1.5VMINIMUM SUPPLY VOLTAGE

3.5GHz3GHz2.5GHz2GHz1.6GHzMAXIMUM CLOCK FREQUENCY

200GBits70GBits25GBits10GBits2GBitsDRAM CAPACITY

16 Billion6 Billion3 Billion 1 Billion400MNUMBER OF TRANSISTOR (LOGIC)

900mm2800mm2750mm2600mm2400mm2CHIP SIZE

35nm50nm70nm100nm130nmTECHNOLOGY

20142011200820052002YEAR

Predictions of the worldwide semiconductor / ICindustry about its own future prospects..

ASIC Design Strategies

Design is a continuous tradeoff to achieve performance specs with adequate results in all the other parameters.Performance Specs - function, timing, speed, powerSize of Die - manufacturing costTime to Design - engineering cost and scheduleEase of Test Generation & Testability -engineering cost, manufacturing cost, schedule

Design Abstraction Levels

n+n+S

GD

+

DEVICE

CIRCUIT

GATE

MODULE

SYSTEM

From Sand to IC

2-inch to 12-inch wafersWhen Intel first began making chips, the company printed circuits on 2-inch wafers. Now the company uses both 300-millimeter (12-inch) and 200-millimeter (8-inch) wafers, resulting in larger chip yields and decreased costs.

The larger wafers can yield more than twice as many chips, achieving an economy of scale that Intel says will save 30% inmanufacturing costs for each wafer.

Scaling & Integration Analogy

12 inch wafer:300 mm diameter23 billion components

Earth:13000 km diameter7 billion people

IC Classification

Circuit technology (BJT, BiCMOS, NMOS, CMOS)

Design style (Standard cell, Gate Array, Full Custom, FPGA)

Design Type (Analog, Digital, or Mixed-Signal)

Circuit Size (SSI, MSI, LSI, VLSI, ULSI, GSI)

IC Classification

Circuit technology (BJT, BiCMOS, NMOS, CMOS)

Design style (Standard cell, Gate Array, Full Custom, FPGA)

Design Type (Analog, Digital, or Mixed-Signal)

Circuit Size (SSI, MSI, LSI, VLSI, ULSI, GSI)

Classification of IC Technologies

(for RF) (for High Speed)

IC Technology Market

Signal Bandwidths versus Technology

Signal Bandwiths versus Application

Why CMOSPower dissipation only during switching

(circuitry dissipates less power when static)

Higher packing density – lower manufacturing cost per device

MOS devices could be scaled down more easily

Bipolar transistors can operate at higher frequencies than CMOS(usefull for microwave applications )

Bipolar vs. MOS Transistor

FasterSlowerTechnology Improvement

GoodPoorSwitch Implementation

Smaller for short channelSlightly largerSmall Signal Output Resistance

PoorGood Noise (1/f)

50 GHz (0.25µm)100 GHzCutoff Frequency(fT)

43Number of Terminals

0.4mS (W=10L)4mSgm at 100MicroAmper

FastFasterSpeed

Low but can be largeModerate to HighPower Dissipation

CMOSBJTCATEGORY

IC Classification

Circuit technology (BJT, BiCMOS, NMOS, CMOS)

Design style (Standard cell, Gate Array, Full Custom, FPGA)

Design Type (Analog, Digital, or Mixed-Signal)

Circuit Size (SSI, MSI, LSI, VLSI, ULSI, GSI)

Classification of ASIC Design Styles

Full Custom DesignCustom design involves the entire design of the IC, down to the smallest detail of

the layout.No restriction on the placement of functional blocks and their interconnectionsHighly optimized, but labor intensive..Designer must be an expert in VLSI design Design time can be very long (multiple months)Involves the creation of a a completely new chipFabrication costs are high

Full Custom Design Style

Full Custom LayoutFull Custom Layout of Square Root Circuit

Standart Cell DesignDesigner uses a library of standard cells; an automatic place and route

tool does the layout.Each standard cell contains a single gate of AND, OR, NOT etc.Standard cells can be placed in rows and connected with wiresRouting done on “channels” between the rows.All cells are the same height but vary in width.All cells have inputs and outputs on top or bottom

of cell.Design time can be much faster than full custom because layout is

automatically generated.

Standart Cell Design Style

Standart Cell Layout

Gate Array Design

Pre-fabricated array of gates (could be NAND). (Gates already created on a wafer; only need to add the interconnections.)

Entire chip contains identical gatesnormally 3- or 4-input NAND or NOR gates.10,000 – 1,000,000 gates can be fabricated within a single IC depending

on the technology used. A routing tool creates the masks for the routing layers and "customizes" the

pre-created gate array for the user's designManufacture of interconnections requires only metal depositionFabrication costs are cheaper than standard cell or full custom because the

gate array wafers are mass producedThe density of gate arrays is lower than that of custom IC’sThis style is often a suitable approach for low production volumes.

Gate Array Design Style

FPGA DesignPre-fabricated array of programmable logic and interconnections.Programmable interconnects between the combinational logic, flip-flops

and chip Inputs and OutputsField Programmable devices are arrays of logic components whose

connectivity can be established simply by loading appropriate configuration data into device’s internal memory.

No fabrication step required, avoid fabrication cost and timeVery good for prototype design because many FPGAs are

re-usable.

FPGA Design Style

Design Style Comparisons

LargeModerateCompact to Moderate

CompactArea

LowModerateHigh to Moderate

HighPerformance

NoneRoutingAll LayersAll LayersFabricate

Prog.VariableVariableVariableInterconnections

LowMediumMediumHighDesign cost

FixedFixedIn rowVariableCell placementProg.FixedVariableVariableCell type

FixedFixedFixed heightVariableCell size

FPGAGate ArrayStandard CellFull Custom

IC Classification

Circuit technology (BJT, BiCMOS, NMOS, CMOS)

Design style (Standard cell, Gate Array, Full Custom, FPGA)

Design Type (Analog, Digital, or Mixed-Signal)

Circuit Size (SSI, MSI, LSI, VLSI, ULSI, GSI)

Design TypeAnalog, Digital, or Mixed-Signal VLSI

DIGITALRegular, hierarchical and modularDesigned at the system levelStandardizedComponents must have fixed valuesSimplified device modelsAvailable synthesis EDA toolsDesigned at the system level (top-down)Short design timeFirst time successful prototyping

Irregular /hardly hierarchicalDesigned at the circuit level CustomizedComponents must have a continuum valuesRequired precision modelingHard to find synthesis toolsMixed bottom-up top-downLonger design timeMore spins for prototypingDifficult to testLess power consumption

ANALOG

Mixed Mode

IC Classification

Circuit technology (BJT, BiCMOS, NMOS, CMOS)

Design style (Standard cell, Gate Array, Full Custom, FPGA)

Design Type (Analog, Digital, or Mixed-Signal)

Circuit Size (SSI, MSI, LSI, VLSI, ULSI, GSI)

2010>1billionGSIGiga Scale Integration

1990>1millionULSIUltra-Large Scale Integration

198030000 - 1millionVLSIVery Large-Scale Integration

1975300 - 30000LSILarge-Scale Integration

1970100-300MSIMedium-Scale Integration

1963<100SSISmall-Scale Integration

System-on-a-Chip (SoC)

Three Dimensional Integrated Circuit (3D-IC)

Classification of Circuit Size

System-on-a-Chip (SoC)Integrating all or most of the components of a hybrid system on a single substrate

(silicon or MCM), rather than building a conventional printed circuit board.

More compact system realizationHigher speed Better reliabilityLess expensive

Three Dimensional Integrated Circuit (3D-IC)

Advatages of 3D-ICs

Improved packing densityNoise immunityImproved total power due to reduced wire length/lower capacitanceSuperior performanceThe ability to implement added functionality

http://www.research.ibm.com/journal/rd/504/topol.html

Traditional VLSI Design Flow

Traditional VLSI Design Flow (Cont'd)

Future of CMOS Technology

Future Lithography Techniques (electron-beam lithography, X-ray lithography, Excimer laser)

Novel transistor structures (SOI, double-gate MOSFETs , High-k (dielectric constant) gate insulatoror technology)

Wiring and interconnections (aluminium-based inter-connects are being replaced by lower-resistance copper ; low-k (dielectric constant) interlayer for interconnects)

Control of Power and heat generation (New cooling technologies, Changeable clock frequency and supply voltage )