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© April 27, 2014 Dr. Lynn Fuller
Testing – Device Problem Analysis
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ROCHESTER INSTITUTE OF TECHNOLOGY
MICROELECTRONIC ENGINEERING
Testing – Device Problem Analysis
Dr. Lynn FullerWebpage: http://people.rit.edu/lffeee
Electrical and Microelectronic EngineeringRochester Institute of Technology
82 Lomb Memorial DriveRochester, NY 14623-5604
Tel (585) 475-2035Email: [email protected]
MicroE webpage: http://www.microe.rit.edu
4-27-2014 Device_Test.ppt
© April 27, 2014 Dr. Lynn Fuller
Testing – Device Problem Analysis
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OUTLINE
IntroductionGood Device CharacteristicsVarious Not So Good Device CharacteristicsDiscussion of CharacteristicsDesign Errors Fabrication Problems
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INTRODUCTION
This document is a collection of test results showing problems with various semiconductor devices made in the microelectronics fabrication laboratory. The objective is to provide useful information for identification of the source of problems and to enhance the education of our students.
© April 27, 2014 Dr. Lynn Fuller
Testing – Device Problem Analysis
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GOOD NMOS DEVICE CHARACTERISTICS
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GOOD PMOS DEVICE CHARACTERISTICS
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Testing – Device Problem Analysis
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NON OHMIC CONTACT TO NMOS DRAIN/SOURCE IN
SUB-CMOS PROCESS
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NON OHMIC CONTACT TO NMOS DRAIN/SOURCE IN
SUB-CMOS PROCESS
N-N+
Over etched contact cuts makes a non-ohmic (rectifying or Schottky) contact with the lighter doped n-type area of the drain/source. P-type devices have ohmic contacts.
< 1um
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Testing – Device Problem Analysis
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CONTACTS TO SILICON
Ideal OhmicAl/p-silicon
Tunneling OhmicAl/n+-silicon
RectifyingAl/n-silicon
V
I
V
I
V
I
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NON OHMIC CONTACT TO NMOS DRAIN/SOURCE IN
ADV-CMOS PROCESS
0
20
40
60
80
100
120
140
0 1 2 3 4
VD (volts)
ID (
µA
/um
)VG=3.5V
VG=2.92V
VG=2.33V
VG=1.75V
VG=1.17V
VG=0.58V
Lmask drawn = 0.6 µm
Leffective = 0.4 µm
*This is RIT’s first sub-0.5 µm Transistor*
Gate
Source Drain
ID-VD for NMOS Transistor
Mike Aquilino May 2004
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Testing – Device Problem Analysis
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SILICIDE FORMATION CONSUMES SILICON
N+< 1um
IMEC MeetingDecember 1999
Too much silicide formation makes a non-ohmic (rectifying or Schottky) contact with the lighter doped n-type area of the drain/source.
TiSi2
N-
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Testing – Device Problem Analysis
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EFFECT OF SINTER ON IV CHARACTERISTICS
Native Oxide
Before Sinter After Sinter
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Testing – Device Problem Analysis
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DIFFERENT LOOKING FAMILY OF CURVES AT
DIFFERENT LOCATIONS ON THE WAFER
2µm/32µm L/W NMOS AND PMOS
Family of curves for L=2µm MOSFETs
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Testing – Device Problem Analysis
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NON UNIFORMITY IN PLASMA ETCH OF POLY
2µm/32µm L/W NMOS AND PMOS
Family of curves for L=2µm MOSFETs
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GOOD DEVICE SUB THRESHOLD CHARACTERISTICS
Occasionally our 1um Devices WorkWhy does the sub-threshold plot not flatten out at the bottom?
Answer: Vt is ~0.5 volt and swing is ~100mV/decade so at zero voltsthe device can be down 5 decades of current which is 10-10 it should flatten out at ~ 10-11 or 10-12 …… need higher Vt or smaller swing
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Testing – Device Problem Analysis
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SHORT CHANNEL – BAD SUB THESHOLD
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Testing – Device Problem Analysis
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REALLY SHORT CHANNEL
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Testing – Device Problem Analysis
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DRAIN INDUCED BARRIER LOWERING
DIBL = change in VG /change in VDat ID=1E-9 amps/µmor 1.6E-8 amps for thissize transistor
= ~ (1.1957-1.1463)/(5-0.1)= ~ 10mV/V
L/W=2/16
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PUNCH THROUGH
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MOBILITY DEGRADATION
32/16
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Testing – Device Problem Analysis
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VELOCITY SATURATION
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RIT’s FIRST SUB MICRON TRANSISTOR
Mark Klare 7/22/94 Electron beam direct write on wafer, n-well process 5E12 dose, P+ Poly Gate PMOS, shallow BF2 D/S implant, no Vt adjust implant.
L=0.75 umXox=300 ÅD/S Xj = 0.25 µmP+ polyNd well ~3E16
Vt = -0.15Sub Vt Slope=130 mV/dec
-3.0-2.5-2.0-1.5-1.0-0.5
0 3.0Vds VoltsId
s (m
A)
0
-8
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Testing – Device Problem Analysis
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WHAT IS WRONG?
NO CONNECTION
Switch Matrix Programmed WrongSwitch Matrix Not CopiedIncomplete Contact Cut EtchAluminum Oxide Between M1 and M2
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Testing – Device Problem Analysis
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GOOD RESISTOR CHARACTERISTICS
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Testing – Device Problem Analysis
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IS THIS GOOD?
NO
Open Circuit, both electrical and visual evidence
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IS THIS GOOD?
NO
R = 1/ slope = 1/.03357m = 29,788 ohmswhich is 58 ohms/contact512 Vias
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Testing – Device Problem Analysis
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IS THIS GOOD?
F081201
YESM1-M2 Via chain with 512 Vias and total resistance of 118 ohms or 0.231 ohms per contact
512 Vias
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WHAT IS WRONG?
Testing PMOS with NMOS-1 Setup Testing PMOS with PMOS-1 Setup
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Testing – Device Problem Analysis
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WHAT IS WRONG?
Leff is almost zero
Poly over etched making L too smallPMOS works at L/W = 2/4 but not at 1/4
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NON UNIFORMITY IN PLASMA ETCH OF POLY
2µm/32µm L/W NMOS AND PMOS
Family of curves for L=2µm MOSFETs
Lot Number = F050118 Wafer Number = D3
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Testing – Device Problem Analysis
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WHAT IS WRONG WITH THIS DIGITAL CIRCUIT
Design Errors – Missing Contact Cuts
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Testing – Device Problem Analysis
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MASK DEFECTS
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Testing – Device Problem Analysis
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JOHN GALT CMOS TESTCHIP
2010
Defect
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MASK DEFECT
160 um
100 um
Defect
This defect will cause a short through the pn junction of our solar cell.
Chrome Side of
N-well Mask
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LARGE 5mm X 5mm PHOTODIODE
Isc = 0.15mA (short circuit current)or 9.09 A/m2
5mmx
3.33mm
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73 STAGE RING OSCILLATOR
73 Stage4X Buffer
L=2µm5Volt Supply
Frequency = 4.37MHzPeriod = T = 2 N td = 230ns
td = 1.58ns
Design Photo
Electrical Test Results
The Ring Oscillator WorksIs It Working Correctly?
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RING OSCILLATOR LAYOUTS
17 Stage Un-buffered Output
L/W 8/16 4/16 2/16
L/W=2/30 Buffered Output
73 Stage 37 Stage
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MOSFETS IN THE INVERTER OF 73 RING OSCILLATOR
nmosfet pmosfet
73 Stage Ring Oscillator
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FIND DIMENSIONS OF THE TRANSISTORS
NMOS PMOS
L 2u 2u
W 12u 30u
AD 12ux12u=144p 12ux30u=360p
AS 12ux12u=144p 12ux30u=360p
PD 2x(12u+12u)=48u 2x(12u+30u)=84u
PS 2x(12u+12u)=48u 2x(12u+30u)=84u
NRS 1 0.3
NRD 1 0.3
Use Ctrl Click on all NMOS on OrCad SchematicUse Ctrl Click on all PMOS on OrCad SchematicThen Enter Dimensions
73 Stage
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SIMULATED OUTPUT AT 5 VOLTS
Three Stage Ring Oscillator with Transistor Parameters for 73 Stage Ring Oscillator and Supply of 5 volts td = T / 2N = 5.5nsec / 2 / 3
td = 0.92 nsecMeasured td = 1.580 nsec @ 5 V
360p
360p
144p
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REFERENCES
1. Dr Fuller’s webpage on CMOS testing, http://people.rit.edu/lffeee/CMOS.htm
2. other
