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TMS320TCI6488 W-CDMA DSP SoC
Introduction This white paper will highlight the Digital
Signal Processor (DSP) based System-on-
Chip (SoC) approach for high-performance
wireless Base Stations. TIs
TMS320TCI6488 device will be used as an
example to highlight the benefits of a flex-
ible DSP SoC approach for W-CDMA base-
band processing. A DSP SoC can provide asingle-chip solution, lower power usage,
better performance, more frugal use of
board real estate, simpler integration, and
lower part counts. Compared to multi-chip
solutions, the DSP SoC has several advan-
tages that will be discussed in this paper.
Introduction to TMS320TCI6488 The TMS320TCI6488, as shown in Figure 1, is a very high-performance base
DSP SoC designed specifically for W-CDMA base stations.
This three-core DSP, running at 1GHz per core, supports all of the necessar
band functions required for a macro base station on a single chip. Designed
ically to solve problems at a system level, this baseband on a chip eliminate
need for Field Programmable Gate Arrays (FPGA) and Application-Specific
Circuits (ASIC) and other bridging devices, reducing the total bill of material
Original Equipment Manufacturers (OEMs) by up to a factor of five, resulting
ered equipment costs for service providers.
The TCI6488 is built on the latest cutting edge technology, the new 65-nm
node, allowing an unprecedented level of functional integration leading to a v
high-performance, high-density modem solution. This allows the device to pe
a level that is an order of magnitude higher than the previous process node at
tion of the power consumption.
W H I T E P A P E R
By Sandeep Kumar
Strategic Marketing Manager,Communications Infrastructure;
Alan Gatherer Chief Technical Officer,Communications Infrastructure
(Continued next column)
Enhanced
DM
A
Controller
L2
Cache
Memory
512
K Bytes
Enhanced
DM
A
Controller
L2
Cache
Memory
512
K Bytes
GPIO PLL I C2
Timers Others BootROM
McBSP AntennaInterface
EDMA 3.0 with Switch Fabric
DDR-2I/F
C64x+Core
C64x+Core
C64x+Core
L1 Data L1 Data L1 DataL1 Prog L1 Prog L1 Prog
L2 Memory L2 Memory L2 Memory
RSA RSA RSA
10/100/1GEthernet
SerialRapidIO
VCP2
TCP2
RAC
Figure 1: TMS320TCI6488 Block Diagram
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With a high level of functional integration and a high channel density supported on a
single device, this DSP offers a modular and scalable design with a small footprint.TCI6488 is a software programmable solution that is upward code-compatible with prev
ous devices belonging to the C6000 DSP family, and allows for the reuse of existing DS
software.
Time-to-Market
The time-to-market benefits of using a standard DSP SoC are clear. Eliminating ASIC
design from scratch can lead to significant time savings. In addition, not having to re-sp
one or multiple of the various functional devices in a legacy system can be the differencbetween an OEM getting a majority of the market share and missing the market window
As illustrated in Figure 2 above, being slightly late to market, ensures missing a signific
portion of the revenue and virtually ensures not capturing the entire market when the
product is finally released.
The total revenue lost in this scenario can be calculated as the difference in area
between the two triangles the red shaded area.
Assuming a constant market ramp, on-time revenue is half (base) (height)
= 0.5 Product Lifetime (L) Maximum Revenue (R) = 0.5 L R
And delayed revenue is half (base) (height)
= 0.5 Delayed Product lifetime (LLD) Delayed Maximum Revenue (RD)
= 0.5 (LLD) RD
Total Revenue Loss is = 0.5 L R 0.5 (LLD) RD =0.5 [L R(LLD) RD]
Texas Instruments
TMS320TCI6488 W-CDMA DSP SoC White Paper May 2007
0.5L L
On-Time SlopeMarketRamp
Late to MarketSlope
Loss Due to
Late to Market
R
RD
LDFigure 2: Revenue Lost Due to Delayed Market Entry
General Benefits of
DSP SoC
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Example of Late to Market Revenue Loss
For example, if the total product lifecycle (L) is 48 months, the Max Revenue is $10M p
month, the project delay (LD) = 6 months and the delayed maximum revenue is $7M,
The Total Lost Revenue = 0.5 (1048 (42)7) =$93M!!(Almost40%of potential
total revenue from the project)As can be seen, the revenue lost due to delayed market entry has components of both
delayed market start and inability to hit 100% market share as components of the lost re
enue. This does not yet comprehend the additional development expense for the duratio
of the delay as well as the lost margin in having to compete for market share when com-
ing from a late-to-market position.
Total Cost of Ownership
Lower Development and Fixed Cost
As can be seen in Figure 3 below, the SoC approach considerably lowers the cost of
development.
The NRE costs associated with developing IP blocks, generating and re-spinning ASI
well as testing and qualifying various devices can run in the 10s of millions of dollars.
There is also another component of the initial investment the additional cost of havi
to develop custom prototyping boards for ASIC, as off-the-shelf solutions are not availa
with the custom pin-out. DSP SoCs, on the other hand, have a variety of off-the-shelf st
dardized board solutions available. These are generally also lower in cost as they are so
across multiple OEMs and application areas.
Total$Am
ount
NRE & Fixed Cost Custom
NRE & Fixed Cost DSP SoC
Total Cost DSP SoC
Volume
Total Cost Custom
Total Revenue
Variable Cost Custom
Breakeven Custom
Variable Cost DSP SoC
Breakeven DSP SoC
Figure 3: Standardized DSP SoCs Lower NRE and Fixed Cost
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Texas Instruments
TMS320TCI6488 W-CDMA DSP SoC White Paper May 2007
Lower Bill of Materials
In W-CDMA applications, the TCI6488 DSP eliminates the need for ASIC or FPGAs fo
chip-rate processing. This results in significant unit cost savings. In addition, through th
integration of standardized system-level interfaces such as Serial RapidIO and OBSAI, it
also eliminates the need for bridges or glue logic, allowing the device to seamlessly com
municate with the backplane and a host of other devices. As such, the TCI6488 can lowthe total Bill of Materials (BOM) for a system by up to one-fifth of legacy systems as se
in Figure 4.
Compared to an all ASIC approach, the DSP SoC approach provides a good balance o
flexibility and cost efficiency. DSP SoCs are used across multiple air-interface standards
due to their support of multiple standards, and across multiple generations of systems,
due their ability to support emerging features and requirements. Typically, this leads to
DSP SoCs shipping in volumes that exceed what any single custom device would be abl
to achieve in isolation. These volumes are leveraged to lower silicon costs and are used
offer a very attractive price point to help OEMs meet their BOM targets for established
markets, as well as niche and emerging applications.
There are several scenarios where the TCI6488 DSP SoC further demonstrates its abil
to fit into various partitions and resource allocation approaches. In one such example, as
shown previously in Figure 4, the device can be used to construct a 192-user 3GPP
Release 99 system quite easily using four devices. The same device can also be used to
Rx SRDSP
Rx SRDSP
Rx CRDSP
Rx CRDSP
Rx CRDSP
Rx CRDSP
Traditional Rx Card
10
Rx CR
192 DL & UL User Card based on Faraday
EthernetSwitch
(Optional)Traditional Rx CardTraditional Rx Card 64 Users
Tx SRDSP
Traditional Tx Card 192 Users
4 5 Devices
HostProcessor
HostProcessor
FPGAs/ Bridges?
FPGAs/ Bridges?
Serial RIO
192 DL & UL User Card Based on Faraday
Backplane to Radio
OBSAI / CPRI
OBSAI / CPRI
TxASIC
Rx SRDSP
10 18 Devices Total
Rx CRDSP Rx CR
ASIC
OBSAI / CPRI
RapidIOSwitch
(Optional)
Backplane to Network
HostProcessor
TCI6488
DSP
TCI6488
DSP
DSP
TCI6488TCI6488
DSP
Figure 4: TCI6488 Can Reduce BOM Cost by a Factor of 5
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create a High-Speed Downlink Packet Access (HSDPA) system. A virtually complete ba
band system with 192-User, 3-Sector RACH, HSDPA / HSUPA (additional small device
needed for transmit chip rate functionality) can be implemented using just four devices a
seen in Figure 5. This simple example demonstrates how, through software modification
the same architecture (if not the same channel card) can be used for voice-only users,
HSDPA/HSUPA users, dedicated data users or various combinations of three.
Software Programmable Solution
The move from modems dominated by lots of low data rate voice calls to modems with
few large data rate data channels that are time multiplexed has actually decreased the
front end signal processing complexity. This is seen conceptually in Figure 6 on the foll
ing page.
As the data portion of the processing mix on the modem increases, there has been a
steady increase in modem complexity because this processing is correlated with the data
bit rate. On the other hand, the signal processing complexity actually decreased as we
moved away from voice dominated standards and towards time-multiplexed, shared cha
nels, as used in HSDPA. The addition of antenna arrays and more complicated receiver
structures with HSUPA has increased the complexity of the signal processing. But never
theless, the role of data processing has increased significantly and this type of processin
has always been done in software. Hence, modems are becoming increasingly soft.
TCI6488
DSP1
TCI6488
DSP2
TCI6488
DSP3
TCI6488
DSP4
GigabitEthernet toNetwork
Backplane
Ethernet
Switch
SRIO
SRIO
SRIO
DSP SoC 1, 2, 3:64 UL DCH +
1 cell RACH PD +8 RACH m +64 R.99 SR
DSP SoC 4:3 cell Mac-HS +
3 cell HSDPA SR +192 R.99 SR
AIF to AntennaBackplane
AIF
AIF
AIF
Figure 5: 192-User, 3-Sector RACH, HSDPA/HSUPA on TCI6488
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Texas Instruments
Software programmability on the baseband, such as that available on the TCI6488, isbecoming more desirable.
By using the TCI6488, OEMs can accelerate their channel card development since it
offers a software-programmable solution and allows for the reuse of existing DSP soft-
ware developed for previous generations of TI infrastructure DSPs. TCI6488 is upward
code-compatible from previous devices that are part of the TMS320C6000 DSP platfo
Customers can re-use their existing software code base and evolve their system architec
tures ensuring they get to market more quickly.
Easier Higher Layer Software Provisioning
The main benefit of a system allowing easily provisioned software is quick time to mark
A system using the TCI6488 can provide this benefit in three ways:
Single-Chip Physical Layer Functionality
From the higher layer software perspective, each DSP SoC looks identical and operates
a user level. This is because a complete user can reside on a single SoC. Therefore the
board-level resource manager does not have to be cognisant of the resource mapping on
the hardware, simplifying resource management. The resource manager on the SoC is in
charge of load balancing the users it is given.
Aggregated MAC Functionality
Traditionally, higher-layer software also has to deal with the task of partitioning physica
control and signalling as well as MAC layer functionality across separate devices.
SignalProcessing
Dedicated ChannelsMany Fingers
C o m p l e x
i t y
Standards evolution
Scarce SpectrumSingle, Shared chanelHSDPA, OFDM
HSUPA, OFDMAAntenna Arrays, MIMO
Higher DL Data RateMAC Functionality
Higher ULData Rate
DataProcessing
Figure 6: Signal Processing Complexity vs. Standards Evolution
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Typically, the software layers of the modem protocol were separated onto different CPU
with the Layer 2 protocol and the board control being implemented on a control proce
sor, usually a PowerPC. One reason for this split was that the control processor devices
had a more suitable peripheral set for communicating with upstream components and ha
better software development tools for this type of code.However, over the last few years, the software development support for Texas
Instruments DSPs has improved significantly with industry competitive C, C++ and mi
Linux support. The TMS320C64x+ CPU used on the TCI6488 also supports memory
agement and a user/supervisor mode. TCI6488 supports both Ethernet and Serial RapidI
and therefore does not suffer from being interface poor for board level and Layer 2
processing.
Greater DSP Horse Power Allows System Homogeneity
With 1-GHz performance per DSP core, the TCI6488 has sufficient processing power o
the three CPUs to absorb the L2 processing and the board control functions on to the D
SoC. This gives system designers greater flexibility as to how the software is partitioned
This has the dual-purpose benefit of simplifying upper-layer software provisioning as w
as reducing the modem board BOM.
Easier Software Replication and System Testing
A direct consequence of the system homogeneity discussed above is that the same physi
cal layer (and potentially L2) software would be written once and then replicated across
multiple TCI6488 devices making the software development easier and enabling shorter
time-to-market.
Also, since every SoC is self contained, when designing a higher-performance system
adding more SoCs, the channel card would require little or no testing at the SoC level.
This would mean minimal additional testing at a system level when scaling a system.
Investment Protection via Flexibility
Feature additions and standards evolution are now routinely expected in the wirelessdevelopment world. For example, the difference between GPRS and W-CDMA maturity
deployment is shown in Figure 7 on the following page. A non-editorial change request
(CR) is essentially an engineering bug in the standard. Increasingly, standards are
launched early and equipment is deployed with bugs and other uncertainties still present
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Texas Instruments
TMS320TCI6488 W-CDMA DSP SoC White Paper May 2007
in the standards. Wireless operators demand that this early equipment be fixed in thefield after deployment. Replacement of equipment is considered an ugly (and expensive
fix for the problem and is only available as a last resort option.
Add to this every carriers requirement to differentiate themselves via a slightly differ
ent twist on the standards specification and it is the recipe for frequent changes to sys-
tem designs that OEMs must make, sometimes mid-stream in a design. Also, in the early
stages of any system development project, it is often not clear which functions should be
implemented with hardware and which in software. Consequently, the ability to make
changes during development without being too disruptive can be valuable. Given the
recent history of tighter development budgets, its no wonder that more of the OEMs are
looking at flexible implementations such as DSP SoC. Also, the cost of ASIC developm
is rising and becoming harder to justify with typical infrastructure volumes. This is more
clearly seen with emerging wireless markets where the uncertainty of gaining critical
market share is even greater.
The DSP SoC, like the TCI6488, allows OEMs to have the flexibility to deal with feat
creep. Often they can begin development without nailing down the complete architectur
of the system knowing that, through software, the TCI6488 is able to support a variety o
system partitions and configurations.
Improved Power Efficiency
The increased processing demands of todays advanced wireless networks have also
increased power consumption. The ever-growing demand for high-capacity, high-data-ra
signal processing in base stations raises a chronic technology challenge. The challenge i
to squeeze higher functionality and performance within increasingly tighter power and
System-Level Benefits of
DSP SoC
0
200
400
600
800
1000
1200
Source:
Non-Editorial CRs
J u n 9
7
J u n 9
8
J u n 9
9
J u n 0
0
J u n 0
1
J u n 0
2
J u n 0
3
J u n 0
4
D e c 9
7
D e c 9
8
D e c 9
9
D e c 0
0
D e c 0
1
D e c 0
2
D e c 0
3
D e c 0
4
ETSI CR Database 11 Jan 2005
W-CDMA Total
GPRS Total
W-CDMA Test
Source: Agilent Technologies
Early GPRSDeployment
Global GPRS
GPRS SubscriberGrowth
Early R99 W-CDMADeployment
Figure 7: Open Change Requests Comparison Between GSM/GPRS and W-CDMA
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space constraints. As a result, power-performance metrics are now a central concern in
infrastructure system design. New methods have been devised enabling designers toaddress the two main areas of power consumptionnamely leakage power and dynamic
powerto significantly improve performance compared to conventional techniques.
To solve this problem, the TCI6488 DSP SoC sports a new power and performance m
agement technology called SmartReflex. Texas Instruments SmartReflex technology
used to decrease both static and dynamic power consumption while maintaining the spe
ified device performance.
This technology takes advantage of the fact that a devices leakage and associated
power can vary significantly across a process distribution as shown in Figure 8.SmartReflex technology make use of this phenomenon by adjusting the core voltage of
devices to suit the process type of the material.
Another element of SmartReflex technology is enhancing device performance and opt
mizing power efficiency by considering thermal parameters. To achieve improved powe
efficiency, the device implements temperature-dependent dynamic voltage scaling.
The final solution allows full performance utilization of highly integrated silicon desig
such as TCI6488, with optimized power consumption. A comparison of the 65-nm node
(with and without SmartReflex technology) with the 90-nm node is shown in Figure 9 o
the following page. This allows designers the ability to add multiple TCI6488 devices o
single card, while still meeting the board power budget.
Another primary component of dynamic power is the chip-to-chip interface between
multiple devices on legacy systems. Through system integration, the DSP SoC approach
ensures that device-to-device communication is kept at a minimum, reducing the overal
system power consumption.
Distributionof Devices
Power
1 GHz
Weaker StrongerProcessStrength
Performance
Figure 8: Device Leakage and Power Can Vary Significantly Across Process Distribution
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0 Texas Instruments
TMS320TCI6488 W-CDMA DSP SoC White Paper May 2007
Smaller Form Factor
The efficient integration of the various system-level components on the DSP SoC also
allows for a smaller number of input and output signals (I/Os) and package ball count,which in turn reduces the size of the device. This has the dual benefit of reducing packa
ing cost as well as allowing a greater device density on a single board, thus allowing sy
tem designers to pack more functionality on their board with every generation. The
TCI6488 fits into a small 23 mm 23 mm flip chip BGA package.
With fewer signals leaving the device, DSP SoCs such as the TCI6488 also have the
added benefit of simplifying board layout and reducing board complexity associated boa
cost.
Greater Scalability
According to some analysts, the market for small form factor base stations is on the rise
(see Figure 10).
Relative Power per Function Relative Power per Unit Area
90 nm 90 nm65 nm 65 nm
Process Node Process Node
65 nm withSmartReflex
65 nm withSmartReflex
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
3.0
2.5
2.0
1.5
1.0
0.5
0.0
Relative Dynamic Power
Relative Leakage (Static) Power
Relative Dynamic Power
Relative Leakage (Static) Power
Figure 9: 65-nm Node (With and Without SmartReflex) Compared with 90-nm Node
Percentage of BTS Shipments
12%
W-CDMA
GSM/GPRS/EDGE
CDMA
9%
6%
3%
0%
2 0 0 1
2 0 0 2
2 0 0 3
2 0 0 4
2 0 0 5
2 0 0 6
2 0 0 7
2 0 0 8
2 0 0 9
2 0 1 0
Figure 10: Forecast of Pico Base Station as a Percentage of Total Base Stations Shipped
Source: Dell OroMobility ForecastReport 3Q06
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However, the uncertainty around the timing and slope of the pico base station market
ramp make this a questionable market for a custom chip development from the very beg
ning. As such, a phased approach starting with a standard DSP SoC moving to a custom
SoC is recommended for such markets.
The beauty of a DSP SoC approach is that it allows designers to pick an appropriate
granularity of system performance and then replicate that to match the end system as
shown in Figure 11.
A single TCI6488 can support a complete HSPA pico base station. Thus, software can
be, written, verified and qualified once for such a single DSP SoC to support a pico imp
mentation and then replicated on top of multiple devices to create larger system configu
ration, such as micro or macro, in the future. In addition, the availability of high band-
width, peer-to-peer interconnect like Serial RapidIO, enables OEMs to reduce overall
R&D by allowing it be re-used across form-factor product lines ranging from small ente
prise class pico base station, all the way to a super macro covering over a 100-Km cell.
Conversely, if the modem designer wishes to dedicate a chip to only one function, sucas Random Access Channel (RACH) messaging, this is also possible with the TCI6488.
designer can therefore trade off the advantages of code that is repeatable across multiple
devices with the efficiency that might come from concentrating a single function in one
device.
TCI6488
DSP
TCI6488
DSP
TCI6488
DSPMicro
Macro &Super Macro
TCI6488 to TCI6488 data transport via: Serial RapidIOAntennae data transport via: AIF with daisy chain aggregation
Network data transport via: Integrated Ethernet
PicoTCI6488
DSP
TCI6488
DSP
TCI6488
DSP
TCI6488
DSP
TCI6488
DSP
TCI6488
DSP
TCI6488
DSP
Figure 11: Standard DSP SoCs Allow for Easy System Scalability
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TMS320TCI6488 W-CDMA DSP SoC White Paper May 2007
Simpler Redundancy and Load Balancing
Inherent in DSP SoC architecture is the built-in multi-function redundancy. Since all the
baseband functions are performed on the TCI6488, system redundancy can be implemen
ed by just adding an additional TCI6488 to the system.
With proper system design, it may be possible to have system redundancy withoutadding an additional device. In such cases, the system software would sense if a function
al unit or logical block on the DSP SoC was not performing and simply switch the task t
another DSP SoC via the Serial RapidIO subsystem. However, this approach will likely
require the system to drop to a fewer number of supported users.
Via the same approach, the presence of a Serial RapidIO-connected DSP subsystem al
makes it easy for the system to balance the processing load between various DSP SoCs
the system.
Multi-Standard SupportBack almost a decade ago at the start of the 3G standards development, industry pundits
predicted that the world would converge to one wireless air interface. The mess of stan-
dards that had been 1G had given way to a slightly better situation, at least in Europe,
with 2G, and the hope was that 3G would finish the job. Now, a decade later, this utopia
ideal has been replaced by a fragmented world where multiple standards not only surviv
but are being pushed to compete and inter-operate at the same time.
The explosion in the number of wireless air interfaces compounded by a simultaneous
cut back in capital expenditure is forcing OEMs to consider ways to address multiple maket opportunities while getting the most out of their architecture investments.
This is where TCI6488 comes to the rescue with its ability to support UMTS, GSM, T
SCDMA, WiMAX and cdma2000 applications as seen in Figure 12. The three 1-GHZ D
Figure 12: TCI6488 Enables Multiple Wireless Modem Standards
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cores go a long way in enabling this device to support multiple standards, while the acce
eration of the mature, compute intensive W-CDMA functionalities makes sure it is able
meet the aggressive W-CDMA cost efficiency targets. This flexibility in a small form fa
tor, scaleable solution provides OEMs a unique solution to support established markets
and extend these into new and emerging infrastructure applications.
Primary W-CDMA Functional Processing
Symbol Rate and MAC-hs Processing
Uplink and downlink symbol rate processing, as well as MAC-hs processing, is perform
on one or more of the three TMS320C64x+ 1-GHz DSP cores available on the TCI64
TCI6488 is upward code-compatible from previous devices that are part of the
TMS320C6000 DSP platform, with the TCI6488 allowing system designers to re-use
existing software code base.
In addition, twenty eight (28) new instructions have been added to this DSP core with
large number of these targeted at improving performance in wireless infrastructure appli
cations. As such, designers can improve their code performance on a per cycle basis sim
ply by taking advantage of these new instructions.
FEC Decoding for Voice and Data
The device has two high-performance embedded coprocessors [enhanced Viterbi Decod
Coprocessor (VCP2) and enhanced Turbo Decoder Coprocessor (TCP2)] that significan
speed up channel-decoding operations on chip. The VCP2 can decode over 763 12.2-Kbadaptive multi-rate (AMR) [K=9, R=1/3] voice channels. The TCP2 can decode up to 4
384-Kbps or 8 2-Mbps turbo encoded channels [assuming 6 iterations].
Both TCP2 and VCP2 are loosely coupled into a DSP subsystem and are fully parame
ized to flexibly support various options within the 3GPP specifications. The presence of
VCP2 and TCP2 frees up DSP resources for other processing and enables basebands wi
much higher voice and data density than would have been possible with a DSP-only
approach.
Chip-Rate Processing
Transmit Chip-Rate Acceleration Using RSA
Transmit chip-rate processing on the TCI6488 is implemented by a DSP subsystem and
associated Rake Search/Spread Accelerator (RSA) extensions. These RSA extensions
accelerate CDMA transmit processing by performing the spreading and scrambling func
tions. The RSA extensions are also capable of carrying out the stream aggregation
W-CDMA-Specific Benefits of a
DSP SoC Approach
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functionality Also, in conjunction with the DSP cores, they can also perform search func
tionality that can be used to augment the Preamble Detect (PD) and Path Monitoring (PM
functions typically performed on the Receive Accelerator.
The RSA extensions allow the TCI6488 to truly shine in supporting very high user de
ty, multiple antennas, variety of data formats as well as an array of system configuration
Thus a base station using the TCI6488 can flexibly support multiple voice and data user
as well as cell sizes over 100 miles in size. All of this is accomplished without sacrificin
cost or power efficiency, in large part due to the RAC.
Figure 13 shows the functional split of transmit chip-rate processing between the DSP
subsystem and the RSA extensions. The DSP core generates both OVSF and PN codes a
provides the multiplied result of these two codes as input to the RSA. The modulated us
symbols are also provided as input to the RSA. The RSA applies the code values to themodulated symbols to achieve spreading and scrambling.
Receive Chip-Rate Acceleration Using RAC
Receive chip-rate processing on the TCI6488 is implemented via the Receive DSP core
the Receive Accelerator (RAC). The RAC is comprised of highly flexible and programm
correlation engines, as shown in Figure 14. These can be configured to carry out various
receive chip-rate functions, including Rake finger de-spreading (FD), EOL finger tracki
(FT), search or path monitoring (PM) operations and RACH preamble detection (PD) options. These blocks receive 2 over sampled chip-rate antenna streams and provide the R
accelerator DSP with either de-spread symbols or correlation energies. These blocks sup
port a very large amount of correlation resources and can support up to 6,144 32-chip co
relations per 32-chip period. The DSP associated with the RAC serves to control and co
figure the two correlation engines.
DSPSystem
OVSF and PNCode Generation
384 channels24 antennastreamsMIMO and
beamformingenabled
1-Bit I,1-Bit Q
EFI
EFI 32-Bit I,32-Bit Q
L2 Memory(User Symbols)
RSAMultiply
and
Accumulate
ModulationApply Closed-Loop Gain
Apply Power-Control Gain
Figure 13: Functional DSP and RSA Split for Transmit Chip-Rate Processing
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Advanced and Emerging Features Support
The TCI6488 has support for various Multiple Input Multiple Output (MIMO) antenna cfigurations. Fixed and adaptive beam forming can be enabled on both uplink and downl
via the RSA and RAC. Parallel Interference Cancellation (PIC) is enabled with re-sprea
possible via the RSA. Thus, as the market demand for advanced features materializes,
OEMs using TCI6488 will be able to quickly support advanced features without having
redesign their existing baseband platforms. The soft nature of the DSP SoC also makes
an ideal candidate for OEMs to support emerging features and capabilities on their curre
platforms.
W-CDMA Software Library Elements
The TCI6488 platform is supported by a hardware adaptation software layer, which
abstracts the hardware implementation details and provides a well-defined API to the
upper software layers. A comprehensive set of optimized hardware-dependent functions
are provided as apart of this hardware adaptation layer. In addition, a robust set of
W-CDMA software library elements are also provided to give system designers a head
start in developing a complete physical layer. Alternately, OEMs can build their own pro
cessing elements on top of the hardware adaptation software to complement or replace
the ones provided along with the TCI6488. An API layer on top of the hardware adapta
software and the W-CDMA software library elements allows OEMs the freedom to choo
the level at which they want to develop their differentiated software component.
CorrelationEngines
Receive Accelerator (RAC)
CorrelationEngines
Host InterfaceAntennaInterface
Receive Chip-Rate Processing Using RAC
Flexible support ofFinger De-Spread (FD),Path Monitoring (PM)& Preamble Detect (PD)
48 Antenna Streams
Continuous SearchSupport
Large Cell Size Support(160 km)
Beamforming Enabled
HostInterruptInterface
System (VBUS)Bridge
Figure 14: Receive Chip-Rate Processing Using RAC
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W-CDMA on DSP SoC Architecture Considerations
Introduction
A base station modem is a real-time system with multiple users, all with their own real-
time constraints, being supported simultaneously. Recent modems that support data tran
fer have the added complexity of having to support many different users with different
data rates and QoS requirements leading to differing I/O, MIPS, and memory require-ments. In order to understand the benefits of the DSP SoC approach for W-CDMA base
stations, it is pertinent to consider the trade-offs made by designers when designing a
multi-user modem.
For the purposes of this discussion, a simplified receiver (demodulation) modem data
flow is considered, as shown in Figure 15, which includes both a low latency control pat
and a higher latency data path.
Additionally, every system is assumed to have at least a basic Real-Time Operating
System (RTOS) to schedule tasks and users.
Task Division
One of the basic decisions concerning whether a basic software task can be performed
relates to a user or a function, as seen in Figure 16. This decision impacts the way
filter
demod FEC unpack
demod FEC unpack
data
control
Figure 15: Simplified Receiver Modem Data Flow
Filt1
D_slow1
Filt2
F_slow1
F_slow2
U_slow1
U_slow2
D_fast1 D_fast1
D_fast2 D_fast2
U_fast1
U_fast2 U_fast2
F_fast1
F_fast2 F_fast2
Tasks Split by User Tasks Split by Function
D_slow2 F_slow2 U_slow2D_slow2
Filt1
Filt2
D_slow1 U_slow1F_slow1
U_fast1F_fast1
Figure 16: Processing Tasks Split by User and Function
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interrupts are generated and how often tasks switch. It also affects the way software
interacts with any peripherals and hardware acceleration on the DSP SoC.
Dividing Tasks by Users
If the tasks are divided by users, the RTOS will not know how many tasks will be presen
at any given time. The main issue with dividing the tasks by user is that the number of
tasks grows with the number of users. For instance, on a macro base station, there may b
up to 64 users running on a TCI6488 and these users may require multiple tasks each.
Also, as the number of tasks grows, so generally will the number of task switches per se
ond. Not only is there a crushing number of task structures to manage, but also more tim
will be spent in interrupt routines and in the kernel, and less time doing useful work.
Typically, this can lead to an unmanageable system above a few tens of users.
Dividing Tasks by Functions
If the tasks are divided by functions, the RTOS does not have to know how many users
present in the system. It only has to know how many unique functions are to be per-
formed. As the number of users increases, the time it takes a task to complete will
increase as that task will run for each user that needs that task at that point in time. If the
task is called immediately, when there is data available for each task, then each task will
be called for each user and the number of task switches will increase with the number of
users. This can again lead to a crushing number of task switches.
A Hybrid Approach
A better way to manage this is to assign each task to a linked list. When a task runs to
completion, for each user, it will add an item to the linked list of the task associated with
the next function to be performed on that user. This will not cause an interrupt to be gen
erated and the users will accumulate on the linked list. At some point the task will be
activated and it will process its linked list to completion, or until it is pre-empted.This
method of task definition and processing is generally preferred on the TCI6488.
Key Take-Away From the User and Task Grouping Analysis
In order to keep the number of tasks, and the task pre-emption overhead, to a manageab
level, they must not scale with the number of users. Tasks should be associated with fun
tions and not users. This can be done by setting up a number of queues. Tasks are
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associated with a queue (usually several tasks per queue) and requests for operation of a
task on a particular user are linked to these queues. The kernel will manage the draining
of these queues and can do this in several ways, using periodic or data-driven interrupts
to achieve real-time operation. As mentioned earlier, this is the recommended approach
when using the TCI6488 for W-CDMA applications.
Scheduling on a Multi-Core DSP SoC with Acceleration
Having considered how to group tasks and users on the TCI6488, the question naturally
arises of how to map users and task on a DSP SoC. The TCI6488 is a multi-CPU DSP S
and composed of independent IP blocks that interoperate and synchronize to achieve a s
gle complete modem function. As such, mapping the priority queue into a multi-CPU en
ronment is an important consideration when designing W-CDMA systems using it.
Mapping Users Across DSP SoC CPUs
One simple way to do this is to divide the users amongst the CPUs, so that each CPU
maintains its own queues. However, some functions, such as filtering and demodulation
may be shared amongst all users. Also, some functions may be required to share
coprocessors or peripherals, and are therefore interdependent.
In this case, the interaction between the sets of priority queues can get quite complicat
ed and it gets difficult to ensure real-time performance. Also, the complexity of the
coprocessors and peripherals increases because they have to support multiple CPUs. Thi
involves making decisions about priority of tasks from different CPUs. All this adds com
plexity to hardware and also to software drivers. It also makes testing of the final system
more complex.
Mapping Tasks across DSP SoC CPUs
Another approach is one of assigning a functional task to a single CPU so that each CPU
in charge of a unique group of functions. Each coprocessor, which generally accelerates
specific type of function, is associated with a single CPU and control of the order of task
performed on that coprocessor is significantly simplified. In many cases peripherals will
only communicate with a single CPU as well. This reduces the testing required to verify
that tasks will not be starved of data.
Synchronization between CPUs can be achieved by system-wide synchronization sig
that align the CPUs to frame, slot and symbol boundaries. Communication between CPU
is in the form of blocks of data generated by one task and destined for another via Direc
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Memory Access (DMA) approach between L2 memories. This is the recommended
approach when using the TCI6488.
Recommended Resource Mapping with TCI6488
The architecture of the TCI6488 has been kept as symmetrical as possible so that it may
be used with a variety of functional splits and system partitions. All DSP cores have
access to the Receive accelerator, for instance. It is therefore possible to run the same
functions on all CPUs, and have all CPUs access all coprocessor and peripheral resource
Yet, it is noted that simplicity of software architecture, along with the nature of many
modem algorithms, leads the smart system designer to partition the tasks so that the soft
ware is not symmetric across CPUs. This is why despite the symmetric architecture, the
is still a recommended usage model, the outcome of extensive study of code cycle esti-
mates, spreadsheet analysis and transactional level models.Based on this analysis, software partition recommended for W-CDMA allows the sim
plicity of having only one CPU controlling the RAC, one CPU controlling the TCP and
and one CPU performing transmit chip-rate function as well as communication with the
antenna array interface for output. Each CPU is also equipped with its own L2 memory
is appropriate in an implementation where each CPU has a unique function. This simpli
the operation of the device and allows the system designer to extract maximum applica-
tion level efficiency from the device.
For other standards, such as those based on OFDM, the natural inclination may be to
use a symmetrical software architecture. But even in this case, it is recommended to
divide the problem so that certain functions, such as FFT/IFFT and some modulation an
demodulation is performed by one CPU and the results communicated to another CPU f
symbol-rate processing. In fact, in the case of OFDMA, the modulation is jointly perfor
for all users and users cannot be completely separated onto different CPUs. This certain
simplifies communication between the antenna interface (or Serial RapidIO if this is
used for antenna data) and the CPU processing the front end. This also has the added be
efit of simplifying the back-end symbol-rate processing and its communication with the
network interface.
Balancing Resources on a Multi-DSP SoC System
As it was recommended in the previous section that each CPU perform different tasks
from each other, it is worthwhile considering if the same approach can be extended to
each DSP SoC having a different task in a multi-DSP system. For instance, a scenario c
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be imagined in which there would be one DSP SoC performing nothing but symbol-rate
decode and one DSP SoC performing nothing but chip-rate modulation.
In a purely soft implementation, this makes sense. However, in such a scenario, any co
processing elements present on chip will not be used efficiently. For instance on a
TCI6488, performing only symbol-rate processing needs a powerful set of VCP2 and TCengines, as present. However, on another DSP SoC performing only chip-rate tasks, the
VCP2 and TCP2 engines would be unused.
Thus, dedicating DSP SoCs to a particular subset of functions also does not make for
scalable system. Clearly, if one wishes to increase the channel density on a board, with
each SoC performing the same complete set of functions, one can simply add more SoC
to the board. The TCI6488 is designed to allow this to happen with the minimal extra h
ware. The Antenna Interface (AIF) and Serial RapidIO both can be connected in a daisy
chain configuration to enable multi-device systems. The gigabit Ethernet and Serial Rapi
interfaces can also be attached to a switch to create a scaleable fabric-based system.
Handling of W-CDMA Tighter Latency on DSP SoC
Compared to a design where each device performs a different task, DSP SoC has the
advantage of latency in transferring data from task to task, while executing the data path
of one user is smaller because the data is kept contained on chip.
System Architecture Conclusion
For a system design using DSP SoCs, such as TCI6488, the system architecture that is thmost scalable at the board level and leads to the simplest, most easily tested software is
one in which each CPU in the DSP SoC performs a unique subset of tasks, but each SoC
the system performs the same set of tasks as the other SoCs. TCI6488 has been optimize
for this scenario for W-CDMA/HSPA, but is flexible enough to also efficiently support
other modem standards and partitions.
The goal for any SoC is to have the perfect balance of on-chip resources. Therefore, pro
erly sizing memory, IO, CPU and other resources from the outset is critical. Comprehen
and balancing resource requirements on a DSP SoC requires a good grasp of the end sy
tem as well as a clear understanding of the real-time constraints. Failure to understand
real-time requirements can be disastrous and lead to resource underutilization, insufficie
capacity, bandwidth, memory or a combination of these. Sharing hardware resources and
multiple threads or services allocated to multiple processor cores increases complexity
and risk. Up-front understanding and avoidance of known resource sharing pitfalls is
Challenges to the DSP SoC
Approach
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strongly suggested. When multiple resources must be shared, interaction should be well
synchronized, brief and well tested.
How TCI6488 Guards Against Typical SoC Pitfalls
Though the TCI6488 was designed from the ground-up to be a very effective real timeW-CDMA baseband processor, it still incorporates features to help the system designer,
should one of the typical problems listed above occur.
Insufficient memory In addition to the hefty on-chip memory already included, the
TCI6488 also allows for a variety of external memory devices supported through its
DDR-2 memory interface.
Inadequate acceleration The presence of Serial RapidIO allows for a very-high band-
width, low-latency option for connectivity to external accelerators, including those
implemented on FPGAs.
Insufficient performance Multiple copies of the TCI6488 can be instantiated. Given th
re-use of the software and the ease of connectivity via Serial RapidIO, getting to the
right performance is easier than ever.
The value in a DSP SoC approach lies in its ability to provide time-to-market advantage
without sacrificing BOM savings. The ease of software provisioning and testing eases th
burden on system software. The software programmable nature of TCI6488 helps insula
OEMs and carriers against unanticipated changes, while allowing them to leverage their
existing code base. The ease of software replication and the enhanced device features,along with power efficiency and small form factor, allow system designers to easily scal
their designs to meet application requirements. DSP SoCs are also particularly well suit
to allow implementation of redundancy and load balancing. Via hardware and software
mechanisms, well-designed DSP SoCs, like the TCI6488, also avoid the typical pitfalls
can plague SoCs.
TCI6488 DSP offers a high-performance, power-efficient and cost-effective baseband
platform capable of supporting physical layer processing, including symbol-rate and chi
rate processing. Designed specifically for the W-CDMA base station, the TCI6488 help
designers achieve unprecedented system density and performance.
Summary and Conclusion
SPRAAM8 2007 Texas Instruments IncorporatedPrinted in the U.S.A.
Important Notice: The products and services of Texas Instruments Incorporated and its subsidiaries described herein are sold subject to TIs standard terms andconditions of sale. Customers are advised to obtain the most current and complete information about TI products and services before placing orders. TI assumeliability for applications assistance, customers applications or product designs, software performance, or infringement of patents. The publication of informatioregarding any other companys products or services does not constitute TIs approval, warranty or endorsement thereof.
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I M P O R T A N T N O T I C E
T e x a s I n s t r u m e n t s I n c o r p o r a t e d a n d i t s s u b s i d i a r i e s ( T I ) r e s e r v e t h e r i g h t t o m a k e c o r r e c t i o n s , m o d i f i c a t i o n s , e n h a n c e m i m p r o v e m e n t s , a n d o t h e r c h a n g e s t o i t s p r o d u c t s a n d s e r v i c e s a t a n y t i m e a n d t o d i s c o n t i n u e a n y p r o d u c t C u s t o m e r s s h o u l d o b t a i n t h e l a t e s t r e l e v a n t i n f o r m a t i o n b e f o r e p l a c i n g o r d e r s a n d s h o u l d v e r c o m p l e t e . A l l p r o d u c t s a r e s o l d s u b j e c t t o T I s t e r m s a n d c o n d i t i o n s o f s a
T I w a r r a n t s p e r f o r m a n c e o f i t s h a r d w a r e p r o d u c t s t o t h e s p e c i f i c a t i o n s a t h T I s s t a n d a r d w a r r a n t y . T e s t i n g a n d o t h e r q u a l i t y c o n t r o l t e c h n i q u e s a r e u s e dx t e n t T I d e e m s n e c e s s a r y t o s u p p o r t t h iw a r r a n t y . E x c e p t w h e r e m a n d a t e d b y g o v e r n m e n t r e q u i r e m e n t s , t e s t i n g o f a l l p a r a m e t e r s o f e a c h p p e r f o r m e d .
T I a s s u m e s n o l i a b i l i t y f o r a p p l i c a t i o n s a s s i s t a n c e o r c u s t o m e r p r o d u c t d e s i g n . C u s t o m e r s a r e r e s p o n s i b l e f o r t h e i r p r o d u a p p l i c a t i o n s u s i n g T I c o m p o n e n t s . T o m i n i m i z e t h e r i s k s a s s o c i a t e d w i t h c u s t o m e r p r o d u c t s a n d a p p l i cp r o v i d e a d e q u a t e d e s i g n a n d o p e r a t i n g s a f e g u a r d s .
T I d o e s n o t w a r r a n t o r r e p r e s e n t t h a t a n y l i c e n s e , e i t h e r e x p r e s s o r i m p l i e d , i s g r a n t e d u n d e r a n y T I p a t e n t r i g h t , c o p y r i g h t , w o r k r i g h t , o r o t h e r T I i n t e l l e c t u a l p r o p e r t y r i g h t r e l a t i n g t o a n y c o m b i n a t i o n , m a c h i n e , o r p r o c e s s i n w h i c h T I p r o d u c t s o r sa r e u s e d . I n f o r m a t i o n p u b l i s h e d b y T I r e g a r d i n g t h i r d - p a r t y p r o d u c t s o r st u t e a l i c e n s e f r o m T I tp r o d u c t s o r s e r v i c e s o r a w a r r a n t y o r e n d o r s e m e n t t h e r e o f . U s e o f s u c h i n f o r m a t i o n m a y r e q u i r e a l i c e n s e f r o m a t h i r d p a r t t h e p a t e n t s o r o t h e r i n t e l l e c t u a l p r o p e r t y o f t h e t h i r d p a r t y , o r a l i c e n s e f r o m T I u n d e r t h e p a t e n t s o r o t h e r i n t e l l e c t u a l p r o p e
R e p r o d u c t i o n o f i n f o r m a t i o n i n T I d a t a b o o k s o r d a t a s h e e t s i s p e r m i s s i b l e o n l y i f r e p r o d u c t i o n i s w i t h o u t a l t e r a t i o n a n d i s a c c o m p a n i e d b y a l l a s s o c i a t e d w a r r a n t i e s , c o n d i t i o n s , l i m i t a t i o n s , a n d n o t i c e s . R e p r o d u c t i o n o f t h i s i n f o r m a t e r a t i o n i s a n u n f a i r a n d d e c e p t i v e b u s i n e s s p r a c t i c e . T I i s n o t r e s p o n s i b l e o r l i a b l e f o r s u c h a l t e r e d d o c u m e n t a t i o n .
R e s a l e o f T I p r o d u c t s o r s e r v i c e s w i t h s t a t e m e n t s d i f f e r e n t f r o m o r b e y o nv o i d s a l l e x p r e s s a n d a n y i m p l i e d w a r r a n t i e s f o r t h e a s s o c i a t e d T I p r o d u cn e s s p r a c t i c e . T I i s n o t r e s p o n s i b l e o r l i a b l e f o r a n y s u c h s t a t e m e n t s .
T I p r o d u c t s a r e n o t a u t h o r i z e d f o r u s e i n s a f e t y - c r i t i c a l a p p l i c a t i o n s ( s u c r e a s o n a b l y b e e x p e c t e d t o c a u s e s e v e r e p e r s o n a l i n j u r y o r d e a t h , u n l e s s s p e c i f i c a l l y g o v e r n i n g s u c h u s e . B u y e r s r e p r e s e n t t h a t t h e y h a v e a l l n e c e s s a r y e x po f t h e i r a p p l i c a t i o n s , a n d a c k n o w l e d g e a n d a g r e e t h a t t h e y a r e s o l e l y r e s p o n s i b l e f o r a l l l e g a l , r e g u l a t o r y a n d s a f e t y - r e l ar e q u i r e m e n t s c o n c e r n i n g t h e i r p r o d u c t s a n d a n y u s e o f T I p r o d u c t s i n s u c h sa p p l i c a t i o n s - r e l a t e d i n f o r m a t i o n o r s u p p o r t t h a t m a y b e p r o v i d e d b y T I . Fy i n d e m n i f y T I a n d i t s r e p r e s e n t a t i v e s a g a i n s t a n y d a m a g e s a r i s i n g o u t o f t h e u s e o f T I p r o d u c t t i c a l a p p l i c a t i o n s .
T I p r o d u c t s a r e n e i t h e r d e s i g n e d n o r i n t e n d e d f o r u s e i n m i l i t a r y / a e r o s p as p e c i f i c a l l y d e s i g n a t e d b y T I a s m i l i t a r y - g r a d e o r " e n h a n c e d p l a s t i c . " O n l y p r o d u c t s d e s i g n a t e d b y T I a s m i l i t a r y - g rs p e c i f i c a t i o n s . B u y e r s a c k n o w l e d g e a n d a g r e e t h a t a n y s u c h u s e o f T I p r o d u c t s w h i c h T Is o l e l y a t t h e B u y e r ' s r i s k , a n d t h a t t h e y a r e s o l e l y r e s p o n s i b l e f o r c o m p l i a n c e w i t h a l l l e g a l a n d r e g u l a t o r y r e q u i r e m e n t s i n c o n n e c t i o n w i t h s u c h u s e .
T I p r o d u c t s a r e n e i t h e r d e s i g n e d n o r i n t e n d e d f o r u s e i n a u t o m o t i v e a p p lf i c T I p r o d u ca r e d e s i g n a t e d b y T I a s c o m p l i a n t w i t h I S O / T S 1 6 9 4 9 r e q u i r e m e n t s . B u y e r s a c k n o w l e d g e a n d a g r e e n o n - d e s i g n a t e d p r o d u c t s i n a u t o m o t i v e a p p l i c a t i o n s , T I w i l l n o t b e r e s p ob l e f o r a n y f a i l u r e t o m e e t s u c h r e
F o l l o w i n g a r e U R L s w h e r e y o u c a n o b t a i n i n f o r m a t i o n o n o t h e r T e x a s I n s t r u m e n t s p r o d u c t so n s o l u t i o n s :
P r o d u c t s A p p l i c a t i o n s
A m p l i f i e r s a m p l i f i e r . t i . c o m A u d i o w w w . t i . c o m / a u d i o
D a t a C o n v e r t e r s d a t a c o n v e r t e r . t i . c o m A u t o m o t i v e w w w . t i . c o m / a u t o m o t i v e
D S P d s p . t i . c o m B r o a d b a n d w w w . t i . c o m / b r o a d b a n d
I n t e r f a c e i n t e r f a c e . t i . c o m D i g i t a l C o n t r o l w w w . t i . c o m / d i g i t a l c o n t r o l
L o g i c l o g i c . t i . c o m M i l i t a r y w w w . t i . c o m / m i l i t a r y
P o w e r M g m t p o w e r . t i . c o m O p t i c a l N e t w o r k i n g w w w . t i . c o m / o p t i c a l n e t w o r k
M i c r o c o n t r o l l e r s m i c r o c o n t r o l l e r . t i . c o m S e c u r i t y w w w . t i . c o m / s e c u r i t y
R F I D w w w . t i - r f i d . c o m T e l e p h o n y w w w . t i . c o m / t e l e p h o n y
L o w P o w e r w w w . t i . c o m / l p w V i d e o & I m a g i n g w w w . t i . c o m / v i d e o W i r e l e s s
W i r e l e s s w w w . t i . c o m / w i r e l e s s
M a i l i n g A d d r e s s : T e x a s I n s t r u m e n t s , P o s t O f f i c e B o x 6 5 5 3 a s , T e x a s 7 5 2 6 5 C o p y r i g h t 2 0 0 7 , T e x a s I n s t r u m e n t s I n c o r p o r a t e d
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