The WIRE Modelingjcf/ensino/disciplinas/mieec/... · Wire Model- The Lumped-C Model WIRE Modeling...

The WIRE Modeling

Ahmed Saeed

Future University in Egypt

Faculty of Engineering and Technology

Project

Contents

• Introduction• Geometry and Electrical Properties:

– Resistance– Capacitance

• Wire Model– Lumped-C Model– Lumped-RC Model– Elmore Delay– Distributed-RC Model

• Inductance• Signal Integrity

– Definitions– Signal Aberrations– System Model

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Contents






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Introduction

A timing example

• Pin to Pin Combinational Delay (A to Y) =

U7Tpd + U5Tpd + U6Tpd = 1 + 9 + 6 = 16 ns

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The Wire

• A line connecting two components in a circuit diagram

– To distribute power and clock.

– communicate signals from one place to another

• Stripguides on (and in) PCB, layered over & sandwiched between groundplanes

• Stripguides on ICs, layered atop each other

• Conductors in cables and cable assemblies

• Connectors

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The Wire

• We tend to think of this line representing an ideal wire.– no resistance,

– no inductance, and

– no capacitance to any other circuit element.

– no delay

– A voltage change at one end of the ideal wire is immediately visible at the other.

This can be an expensive mistake.

Clearly such an ideal wire is not physically realizable.

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The Wire

• Superconductors

– reduce the resistivity to zero → €

– inductance and capacitance cannot be eliminated → delay

• The ideal wire is a useful approximation

– appropriate when the effect of the parasitic elements is small

– lets us concentrate on the circuit properties of the components being connected.

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The Wire - Reality

• Real wires are not ideal: have parasitic capacitance, resistance, and inductance which have multiple effects on the circuit behavior.– increase propagation delay → drop in

performance.– impact the energy dissipation and the power

distribution.– introduce extra noise sources, which affects the

reliability of the circuit.

• Wires dominate a modern digital system in terms of speed, power, and cost.

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The Wire - Reality

X The time required to drive wires and for signals to propagate over wires is often the largest factor in determining cycle time.

X The bulk of the power in many systems is dissipated driving wires, on-chip and off.

X The amount of wiring, not the number of transistors or gates, usually determines the amount of area required by a function on a chip.

X The number of terminals required is a major factor in the area and cost of chips, packages, and circuit boards.

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Contents






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Geometry And Electrical Properties-Resistance• The resistance of wire is defined by its geometry:

𝑅 =

𝜌𝑙ℎ𝑤

𝜌𝑙𝜋𝑟2

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Rectangular Wire: on-chip wires & vias, PCB traces

Circular Wire: off-chip wires, off-PCBs

Geometry And Electrical Properties-Resistance

• The resistivity of commonly used materials (@ 20C):

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Material 𝝆 [x10-8 Ω-m]

Silver (Ag) 1.6 Seldom used in electronic packaging because of its high cost.

Copper (Cu) 1.7 Most used material for electrical conductors: cabling,ground planes, and stripguides in circuit boards and bus bars.

Gold (Au) 2.2

Aluminum (Al) 2.7 Offers higher 𝝆/$ It is widely used for wiring on integrated circuits, low-cost power cables, and bus bars

Tungsten (W) 5.5 Used for vias (suitable high-temperature processingafter deposition)


• Since h is a constant for a given technology,

𝑅 = 𝑅∎𝑙𝑤

with

𝑅∎ =𝜌ℎ

• 𝑅∎the sheet resistance of the material in Ω/∎

• To obtain the resistance of a wire, simply multiply the sheet resistance by its ratio (l/w).

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Geometry And Electrical Properties-Resistance• Sheet resistance values for a 0.25 μm CMOS process

• Aluminum (or copper) is the preferred material for the wiring of long wires. • Polysilicon should only be used for local interconnect. • The sheet resistance of the diffusion layer (n+, p+) is comparable to that of

polysilicon, the use of diffusion wires should be avoided due to its large capacitance and the associated RC delay.

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Material 𝐒𝐡𝐞𝐞𝐭 𝐑𝐞𝐬𝐢𝐬𝐭𝐚𝐧𝐜𝐞 [Ω/∎]

n- or p-well diffusion 1000 - 1500

n+, p+ diffusion 50 - 150

n+, p+ diffusion with silicide 3 - 5

n+, p+ Polysilicon 150 - 200

n+, p+ polysilicon with silicide 4 -5

Aluminum 0.05 – 0.1


• Example: Consider a wire of which is 10 cm long and 1 μm wide, and is routed on the first layer. Calculate the total resistance of this wire.

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1- Aluminum (𝑅∎=0.075 Ω/∎): the total resistance of the wire Rwire = 0.075 Ω/∎ x (0.1x106 μ m) / (1 μm)= 7.5 kΩ

2- polysilicon (𝑅∎=175 Ω/∎):Rwire = 175 Ω/∎ x (0.1x106 μm) / (1 μm)= 17.5 MΩ !

3- Silicided polysilicon (𝑅∎=4 Ω/∎):Rwire = 4 Ω/∎ x (0.1x106 μm) / (1 μm)= 400 kΩ

better alternative!

Contents






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Geometry And Electrical Properties-Capacitance

• The capacitance of such a wire is a function of:

– its shape,

– its environment,

– its distance to the substrate, and

– the distance to surrounding wires.

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• If the width of the wire is larger than the thickness of the insulating material -> the electrical-field lines are orthogonal to the capacitor plates.

• Parallel-plate Model

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Geometry And Electrical Properties-Capacitance• SiO2 is the dielectric material of choice.

• lower permittivity → lower capacitance.

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Material ϵr

Free space 1

Aerogels 1.5

Polymides 3 - 4

SiO2 3.9

Glass Epoxy (PCB) 5

Silicon Nitride 7.5

Silicon 11.7

- It is advantageous to use a material with the lowest possible permittivity, for it gives not only lower capacitance, but also a higher propagation velocity.


• common wire cross sections

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Geometry And Electrical Properties-Capacitance• To minimize the resistance of the wires, cross-section of the

wire (W/H) as large as possible.

• On the other hand, over the years witnessed a steady reduction in the W/H-ratio, such that it has even dropped below unity → the parallel-plate model assumed becomes inaccurate.– The capacitance between the side-walls of the wires and the substrate

can no longer be ignored and contributes to the overall capacitance.

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Fringing Capacitance: The capacitance between the side-walls of the wires and the substrate.


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We will approximate it by a parallel plate capacitor of width, w, to account for the field

under the conductor, in parallel with a wire over a ground plane of thickness H, to account

for the fringing field from the two edges.

Geometry And Electrical Properties-Capacitance– For larger values of (W/H) the

total capacitance approaches the parallel-plate model.

– For (W/H) smaller than 1.5, the fringing component actually becomes the dominant component.

– The fringing capacitance can increase the overall capacitance by a factor of more than 10 for small line widths.

– The total capacitance levels off to a constant value of approximately 1 pF/cm for line widths smaller than the insulator thickness. In other words, the capacitance is no longer a function of the width.

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• The case of a single rectangular conductor placed over a ground plane (microstripline), used to be a good model for interconnections when the number of interconnect layers was restricted to 1 or 2.

• Today’s processes offer many more layers of interconnect.

• Each wire is not only coupled to the grounded substrate, but also to the neighboring wires on the same layer and on adjacent layers.


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The case of a single rectangular conductor placed over a ground plane (microstripline), used to be a good model for interconnections when the number of interconnect layers was restricted to 1 or 2.


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Contents






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Wire Model- The Lumped-C Model

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• Reality: The circuit parasitics of a wire are distributed along its length: not lumped.

• It is often useful to lump the different fractions into a single circuit element:– when only a single parasitic component is dominant– when looking at only one aspect of the circuit

behavior.

• The advantage of this approach is that the effects of the parasitic then can be described by single ordinary differential equation.


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• Lumped Capacitor Model: lump the distributed capacitance into a single capacitor

– the resistive component of the wire is small

– the switching frequencies are up to medium range.

- The wire still represents an equipotential region, and that the wire does not introduce delay.

- The only impact on performance is introduced by the loading effect of the capacitor on the

driving gate.


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• Example: For the circuit shown, assume that a driver with a source resistance of 10 kΩ is used to drive a 10 cm long, 1 μm wide Al1 wire with total lumped capacitance of 11 pF.

The operation of this RC network is

described by:

For Vin step input (from 0 to V), the transient response of this circuit is known to be


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• Example: For the circuit shown, assume that a driver with a source resistance of 10 kΩ is used to drive a 10 cm long, 1 μm wide Al1 wire with total lumped capacitance of 11 pF.

The time to reach 50% point is

And

Which is not acceptable -> solution is to reduce Rdriver

Contents






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Wire Model- The Lumped-RC Model

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• Lumped RC Model: lump the distributed capacitance and resistance into a single capacitor and resistor, respectively.

– On-chip wires have a significant resistance.

– The equipotential is no longer adequate.

- lumped RC model is pessimistic and inaccurate for long interconnect


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• Consider the RC tree:

– It has a single input node (called s)

– all capacitors are between a node and the ground

– the network does not contain any resistive loops (tree)


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- Path resistance Rii = total resistance along the path to

node i

- Shared path resistance Rik, = the resistance shared among the

paths from node s to nodes k and i

Example

Contents






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Wire Model- Elmore Delay

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• The Elmore delay (for N nodes tree) at node i is then given by:

The Elmore delay for node i

Example


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• Special Case: non-branched RC chain (ladder)

- The Elmore delay for node 2 equals to

Example

- The Elmore delay for node i equals to


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• Example wire of length L is partitioned into N identical segments, each of L/N. The resistance and capacitance of each segment are given by rL/N and cL/N, respectively. Using Elmore formula, the time-constant of the wire:

For very large value of N

Conclusion:

- The delay of a wire is a quadratic function of its length! Doubling the length of wire

quadruples its delay.

- The delay of the distributed rc-line is one half of the delay of lumped RC model.

Contents






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Wire Model- The Distributed-rc Model

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The voltage at node i of this network can be determined by solving:

reducing ΔL to 0 yields V is the voltage at a particular point in the wire,

and x is the distance between this point and the

signal source.

No closed-form solution exists for this equation

Wire Model- The Distributed-rc Model

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Driving these rc lines and minimizing the delay and signal degradation is one of the trickiest problems in modern digital integrated circuit.

r: distributed resistance per unit of distancec: distributed capacitance per unit of distance

Simulated step response of resistive-capacitive wire as a function of time and place

Wire Model- Distributed vs Lumped

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Step response of lumped and distributed RC networks—points of Interest

Contents






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Inductance

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• High speed interconnects are considered as distributed RLC transmission lines

• Zo of the interconnect equals both the output impedance of the driver and the input impedance of the receiver, there are no signal reflections.

• Any impedance difference introduces reflections, which limit the energy transmitted to the receiver.

• Consequences: – ringing and overshoot effects– reflections of signals due to impedance mismatch– inductive coupling between lines– switching noise due to L (di/dt) voltage drops.

Inductance

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• To model the ringing, at least a second-order approximation is required to characterize this non-monotone, underdamped, response.

• So, the inductance should be taken into account.

• A simpler approach to find the inductance of wire relies on:

cl =ϵμ

Contents






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What is Signal Integrity ?

• At low clock frequencies, system interconnects assumed to have no effect on the signals: transparent.

• In High-speed regime, the frequency-dependent behavior of interconnects starts to impact the signal propagation.


• Speed is dominated by the interconnect between Tx and Rx.

Tx RxInterconnect

Tx• Transistors• Passives• Chip• Etc.

Rx• Transistors• Passives• Chip• Etc.

Example


Example


Tx RxInterconnect


• Problems:

– Timing Noise

– Voltage Noise

– EMI

Delay ReflectionsRinging

Ground bounceCrosstalk

Critical net TerminationsInductance

Parasitic IR dropOvershoot, UndershootRail-Collapse

Non-monotonic edges

These problems play a role in all interconnects: • Smallest on-chip wire• Cables connecting racks of boards• everywhere in-between.

Contents






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What are signal aberrations?

Settling timeFor RingingOvershoot

Overshoot

Undershoot

Rise time

Nonlinearity

We wouldlike to have

The real life

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Signal Integrity

• “All the problems that arise in high-speed systems due to the interconnects".

• Good integrity, signal has:– clean shape– valid logic levels– timing accuracy– glitches-free.

Good Integrity

Cleanshape

Validlogic levels

Timing accuracy

Glitches-free

Fasttransitions

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• Effective SI is Pre-Product Release.

• It must be designed and not discovered.

Post-Release

Validation

Pre-Prototype

Cost of failure (M$)

When Signal Integrity ?

It costs less hereTime = €

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Signal Integrity- Discontinuity

• How the system performance can be affected by the interconnects properties : electrical and mechanical ?

• The signal see the interconnect as an electrical impedance.

– If the impedance stays the same --> undistorted signal.

– If the impedance changes --> reflections --> distorted signal.

• Discontinuity

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• Discontinuity : any feature that changes the impedance the signal sees.

• Socket or Connector

• Branch, tee, or stub

• line-width change

• A layer change: Via

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Keep the impedance constant:

– Use a board with constant, or "controlled," impedance traces (uniform).

– Use routing rules that allow the topology to maintain a constant impedance down the trace.

– Use strategically placed resistors to manipulate the reflections and keep the received signals looking clean.

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Signal Integrity- Solutions

Noise Category Design Principle

Signal Quality → Signals should see the same impedance through all interconnects

X-Talk → Keep spacing of traces greater than a minimum value, minimize mutual inductance with non-ideal returns

Rail Collapse → Minimize the impedance of the power/ground path.

EMI → Minimize bandwidth, minimize ground impedance, and shielding

Even if these guidelines are followed, it is still essential to model and simulate the system to evaluate whether the design will meet the performance requirements.

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Motivation

• Typical analysis of SI problems:– How ?

• Circuit-level

• Transient-analysis tools, such as ELDO and SPICE

• Entirely in time domain.

– Cons• it can not accurately account for the system interconnects,

elements of frequency-dependent behaviors and the elements have non-ideal- frequency response.

• model the system interconnects by simplified lumped models with no dispersion and constant loss, which is not accurate in the high-speed regime.

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Contents






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System Model

• Point-to-point connection.

Model is properly configured and terminated,the signal integrity excellent

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System Model

• Point-to-point connection.Stub resistor; to improve signal quality by dampening ringing, overshoots, and undershoots

DDR-3 SDRAM IBIS

ClockGenerator

Stratix III FPGA IBIS

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System Model

• Point-to-point connection.Interconnect may include PCB traces and vias, sockets, and cables.

DDR-3 SDRAM IBIS

Stratix III FPGA IBIS

ClockGenerator

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Problems

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References

• Rabaey, Jan, A. Chandrakasan, and B. Nikolic. Digital Integrated Circuits: A Design Perspective. 2nd ed. Upper Saddle River, NJ: Prentice Hall, 2002. ISBN: 0130909963.

• Dally, William, and J. Poulton. Digital System Engineering. 1st ed. Cambridge University Press, 2008. ISBN: 978-0521061759.

• Hubert Kaeslin. Digital Integrated Circuit Design From VLSI Architectures to CMOS Fabrication. Cambridge University Press, 2008. ISBN: 0521882672

• Eric Bogatin. Signal and Power Integrity. 2nd ed. Prentice Hall, 2009. ISBN: 9780132349796.

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