Thermal-Driven 3D Floorplanning using Localized TSV Placement

Puskar Budhathoki, Andreas Henschel and Ibrahim (Abe) M. Elfadely

IC Design & Technology (ICICDT), 2014

I. INTRODUCTION II. MOTIVATION III. PROBLEM FORMULATION IV. METHODOLOGY V. RESULT AND DISCUSSION VI. CONCLUSIONS

INTRODUCTION The complexity of physical design increases

with the exponential growth of circuit. 3D integration technology is a promising

technique to boost performance and reduce wirelength.

However, the critical challenge in 3D IC is thermal management.

MOTIVATION Goplen et al [6] indicates that thermal TSVs

constitute an important path for vertical heat flow.

Lee et al [7] studies arrangement of thermal TSVs in multichip modules packaging and found that heat removal is directly proportional to the size of thermal via islands

PROBLEM FORMULATION

multi-objective optimization problem, minimizing the occupied area of the floorplan (A), total wirelength (w) and number of signal TSVs ()

METHODOLOGY Placement of thermal TSVs considers both

thermal effect as well as area impact of thermal TSVs.

design flow

A. Floorplanning A very recent CBL based floorplanning tool

(Corblivar [9]) is employed as floorplanning module which accounts for optimization of chip area, wirelength, and interconnects as well.

B. Floorplanning/Thermal Management Interface This module converts CBL tuples and global

alignment sequence into Cartesian coordinates and generates an output format readable by the thermal simulation module.

C. Thermal Simulation The HotSpot extension tool presented in [10]

allows modeling of thermal TSVs with related thermal resistivity and specific heat capacity values in specified (delimited) regions.

D. Thermal Constraint Assessment and TSV Placement An iterative greedy approach is used in a grid

cell having maximum temperature and thermal TSVs are placed in passive substrate and bonding layer until the maximum temperature of each grid cell is below the predefined target temperature.

is the previous conductivity of the grid cell, is the current temperature and is the target maximum temperature of the whole package chip.

is the maximum allowable TSV density in each grid cell, c is a user specified constant and is the thermal conductivity of TSVs.

RESULT AND DISCUSSION

RESULT AND DISCUSSION

CONCLUSIONS Experimental results show that our approach

can optimize interconnect wirelength, chip area, number of TSV and hotspot temperatures simultaneously.