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Laurent Leyssenne – November 27th 2009 – Bordeaux – Part 2
PA discretized reconfigurability
Integrated Passive Device design on glass substrate
ConclusionIntro. Gate Bias Envelope Tracking
S-parameters measurement
(5W diff. to 50W single)
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Laurent Leyssenne – November 27th 2009 – Bordeaux – Part 2
PA discretized reconfigurability
Envelope Tracking Principle
ConclusionIntro. Gate Bias Envelope Tracking
Goal: making DC consumption follow envelope
variations
Adaptive control of power supply (VDD) or
Adaptive control of Current consumption (IDD)
Issues/requirements:
Reduced die area / complexity / Bill-Of-Material
Immunity on linearity and noise performances
Wide channel bandwidth to address 3G/4G and latest RF
standards.
Accurate reconfiguration of envelope tracking behavior to
optimize simultaneously linearity/ and efficiency.
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Laurent Leyssenne – November 27th 2009 – Bordeaux – Part 2
PA discretized reconfigurability
Envelope Tracking general synoptic
ConclusionIntro. Gate Bias Envelope Tracking
General envelope tracking architecture (gate et drain control)
Efficient but based on DC/DC converter:
• Difficult to integrate
• Increased Bill-Of-Material
(at least 1 ext. Choke required)
Dynamic gate bias:
• Low complexity
• Low BOM
• Low silicon Option considered
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Laurent Leyssenne – November 27th 2009 – Bordeaux – Part 2
PA discretized reconfigurability
Reconfigurable-Depth adaptive Bias technique
IDD adaptive bias modifies PA properties
Impact on AM/AM and AM/PM
1st-order base-band current law in classic IDD adaptive bias systems:
where h is fixed-valued and presents minor frequency dependence
.
Proposed reconfigurable-depth adaptive bias law:
where hDEPTH is frequency-controlled and voltage-controlled by VDEPTH
If VDEPTH is power dependent 2nd-order system with respect to power
h 2
,RFgDDQDD VII
ConclusionIntro. IDD Bias Envelope Tracking
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,Δω RFgDDQDD VηII ,VDEPTHDEPTH
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Laurent Leyssenne – November 27th 2009 – Bordeaux – Part 2
PA discretized reconfigurability
Reconfigurable-Depth adaptive Bias technique
Dual adaptive bias system (patent pending)
Coarse adaptive bias: Diode-connected LDMOS linearizer VSWR mismatch sensitive (PA protection purpose)
Inserted in a closed-loop for increased channel bandwidth and betterrobustness
Fine tuning adjustable bias (for reconfiguration depth) Includes a power detector featuring an negative to positive Voltage-
Controlled Gain
Includes a reconfigurable base-band filter to:
control the phase of the injected envelope harmonics
cancel / magnify memory effects
balance / unbalance lower and upper spectral regrowth
The control of PA response in base-band domain is of crucialimportance in the prospect of linearity immunity.
ConclusionIntro. IDD Bias Envelope Tracking
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Laurent Leyssenne – November 27th 2009 – Bordeaux – Part 2
PA discretized reconfigurability
Reconfigurable-Depth Adaptive Bias LDMOS PA schematic
ConclusionIntro. Gate Bias Envelope Tracking
LDMOS linearizerEnvelope probe node
Zero for wider
bandwidth
LDMOS linearizer
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Laurent Leyssenne – November 27th 2009 – Bordeaux – Part 2
PA discretized reconfigurability
Base-band building blocks: Variable-Gain Mixer
ConclusionIntro. IDD Bias Envelope Tracking
t
ADJ
t
IN
t
IN2
BIASOUTOUT2U
Vtanh
2U
Vcosh
2U
Vsinh
III
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Laurent Leyssenne – November 27th 2009 – Bordeaux – Part 2
PA discretized reconfigurability
Dual-tone illustration of linearity improvement via
reconfigurable-depth adaptive Bias (a)
3rd degree non-linearities (red harmonics) tend to compress the
magnitude of the output power (gm3<0).
ConclusionIntro. IDD Bias Envelope Tracking
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Laurent Leyssenne – November 27th 2009 – Bordeaux – Part 2
PA discretized reconfigurability
Dual-tone illustration of linearity improvement via
reconfigurable-depth adaptive Bias (b)
The power detector generates an envelope signal that modulates
the base-band gate voltage (green harmonics) with an adjustable
conversion gain.
ConclusionIntro. IDD Bias Envelope Tracking
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Laurent Leyssenne – November 27th 2009 – Bordeaux – Part 2
PA discretized reconfigurability
Dual-tone illustration of linearity improvement via
reconfigurable-depth adaptive Bias (c)
Base-band gate voltage harmonics combine with RF harmonics
via power transistor 2nd–order non-linearities (blue harmonics) and
combat 3rd degree non-linearities (gm3<0<gm2)
ConclusionIntro. IDD Bias Envelope Tracking
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Laurent Leyssenne – November 27th 2009 – Bordeaux – Part 2
PA discretized reconfigurability
Dual-tone illustration of linearity improvement via
reconfigurable-depth adaptive Bias (d)
When the injected envelope magnitude exceeds a threshold level,
over-compensation is observed linearity is degraded.
ConclusionIntro. IDD Bias Envelope Tracking
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Laurent Leyssenne – November 27th 2009 – Bordeaux – Part 2
PA discretized reconfigurability
Dual-tone illustration of linearity degradation /
improvement due to slow rate memory effects (a)
Importance of memory effects:
Phase shifts in envelope injection
Spectral regrowth unbalance
Vectorial illustration on IMD3
ConclusionIntro. IDD Bias Envelope Tracking
Lower and upper IMD3 balance
No memory effect
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Laurent Leyssenne – November 27th 2009 – Bordeaux – Part 2
PA discretized reconfigurability
Dual-tone illustration of linearity degradation /
improvement due to slow rate memory effects (b)
Importance of memory effects:
Phase shifts in envelope injection
Spectral regrowth unbalance
Vectorial illustration on IMD3
ConclusionIntro. IDD Bias Envelope Tracking
Lower and upper IMD3 unbalanced
With memory effects
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Laurent Leyssenne – November 27th 2009 – Bordeaux – Part 2
PA discretized reconfigurability
Effect of reconfigurable depth adaptive bias
on 2-tone PA response
ConclusionIntro. IDD Bias Envelope Tracking
Locuses of G3/G1 ratio for:
• various power levels
• various VDEPTH values
Minimum G3/G1 ratio locus in green
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Laurent Leyssenne – November 27th 2009 – Bordeaux – Part 2
PA discretized reconfigurability
Effect of reconfigurable depth adaptive bias
on ACLR and EVM
ConclusionIntro. IDD Bias Envelope Tracking
ACLR peaks can be shifted with
respect to power
EVM notches can be shifted with
respect to power
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Laurent Leyssenne – November 27th 2009 – Bordeaux – Part 2
PA discretized reconfigurability
BiCMOS Silicon Power Amplifier
ConclusionIntro. Gate Bias Envelope Tracking
A 32dBm differential 2ndG LDMOS PA (100W diff. to 5W diff.)
Power stage: (320x20µm)x2 overall gate width
Driver stage: (48x20µm)x2 overall gate width
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Laurent Leyssenne – November 27th 2009 – Bordeaux – Part 2
PA discretized reconfigurability
Continuous wave PA performances @1.75GHz (DCS/EDGE)
ConclusionIntro. Gate Bias Envelope Tracking
On-wafer singled-ended load-pull
PA characterization was
performed.
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Laurent Leyssenne – November 27th 2009 – Bordeaux – Part 2
PA discretized reconfigurability
Continuous wave PA performances @1.75GHz (DCS/EDGE)
ConclusionIntro. Gate Bias Envelope Tracking
On-wafer singled-ended load-pull PA characterization was
performed.
OCP1=27.5dBm
Max. PAE=47%
PAE @ OCP1=40%
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Laurent Leyssenne – November 27th 2009 – Bordeaux – Part 2
PA discretized reconfigurability
Continuous wave PA performances @1.95GHz (WCDMA)
ConclusionIntro. Gate Bias Envelope Tracking
OCP1=27.5dBm
Max. PAE=57%
PAE @OCP1=51%
PAE @OCP1-10dBm=12%
Min. IDD=120mA
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Laurent Leyssenne – November 27th 2009 – Bordeaux – Part 2
PA discretized reconfigurability
Dynamic PA performances @1.75GHz (DCS/EDGE)
ConclusionIntro. Gate Bias Envelope Tracking
200kHz 2tone
spacing
50dBm OIP3
Max. EDGE PAE
=17%
Max. EDGE output
power =21dBm
Non symetric phase shift
(memory effect)
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Laurent Leyssenne – November 27th 2009 – Bordeaux – Part 2
PA discretized reconfigurability
Dynamic PA performances @1.95GHz (WCDMA)
ConclusionIntro. Gate Bias Envelope Tracking
35dBm OIP3
Max. PAE for WCDMA
=22%
Max. linear power for WCDMA
=21dBm @ACLR=33dBc
Max. linear power for slow rate HPSK
=26.5dBm @ACLR=33dBc
Max. PAE for slow rate HPSK=43%
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Laurent Leyssenne – November 27th 2009 – Bordeaux – Part 2
PA discretized reconfigurability
Effect of reconfigurable depth adaptive bias on linearity
ConclusionIntro. Gate Bias Envelope Tracking
Probed HPSK
envelope
IMD3 can be optimized by a few dB
up to 10dB
VDEPTH polarity reversal (,,)
required for linearity optimization
over wide power range
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Laurent Leyssenne – November 27th 2009 – Bordeaux – Part 2
Gate Bias Envelope TrackingPA discretized reconfigurability ConclusionIntro.
IV. Conclusion & Prospects (a)
Many issues are to be considered for PA design:
Quantization noise
Memory effects …
Some were overcome, some others not.
Demonstrators have proven to be efficient with some linearity degradation however.
1 national publication:
JNM2005
6 international publications:
DCIS2004, IMOC2005, BCTM2006, IEEE Topical Workshop on Power Amplifiers for Wireless Communications 2008, RWS2009, SBCCI2009
1 book contribution In Microwave Filters and Amplifiers (2005)
1 patent pending
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Laurent Leyssenne – November 27th 2009 – Bordeaux – Part 2
Gate Bias Envelope TrackingPA discretized reconfigurability ConclusionIntro.
IV. Conclusion & Prospects (b)
Increasing S modulator bandwidth
Investigating decimator filter impact, and complexity
Taking into account phase noise
Combined reconfigurable/cartesian dual-loop
Better correction of memory effects
Accurate characterizing thermal effect
Integration of a fast temperature sensor
Integration of base-band filter
Reconfiguration of phase advance/delay
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Laurent Leyssenne – November 27th 2009 – Bordeaux – Part 2
Gate Bias Envelope TrackingPA discretized reconfigurability ConclusionIntro.
Thank you for your attention