Timers

Chapter 10

9S12DP256

Timers

• The 9S12DP256 Programmable Timer

• Output Compares

• Pulse Train Using Interrupts

• Input Capture

• Measuring the Period of a Pulse Train Using Interrupts

PIM_9DP256

Block Diagram

Table 10.1 Timer Registers in the 9S12DP256 Name Register Addr Description TIOS 0040 Timer Input Capture/Output Compare Select CFORC 0041 Timer Compare Force Register OC7M 0042 Output Compare 7 Mask Register OC7D 0043 Output Compare 7 Data Register TCNT 0044 Timer Count Register TSCR1 0046 Timer System Control Register 1 TCTL1 0048 Timer Control Register 1 TCTL2 0049 Timer Control Register 2 TCTL3 004A Timer Control Register 3 TCTL4 004B Timer Control Register 4 TIE 004C Timer Interrupt Enable Register

TSCR2 004D Timer System Control Register 2 TFLG1 004E Timer Interrupt Flag Register 1 TFLG2 004F Timer Interrupt Flag Register 2 TC0 0050 Timer Input Capture /Output Compare Register 0 TC1 0052 Timer Input Capture /Output Compare Register 1 TC2 0054 Timer Input Capture /Output Compare Register 2 TC3 0056 Timer Input Capture /Output Compare Register 3 TC4 0058 Timer Input Capture /Output Compare Register 4 TC5 005A Timer Input Capture /Output Compare Register 5 TC6 005C Timer Input Capture /Output Compare Register 6 TC7 005E Timer Input Capture /Output Compare Register 7

Timer Counter

$0044 Bit 15 14 13 12 11 10 9 Bit 8 TCNT (High) $0045 Bit 7 6 5 4 3 2 1 Bit 0 TCNT (Low)

Free running 16-bit counter Clock input is MCLK (8 MHz) pre-scaled by 1, 2, 4, 8, 16, 32, 64, or 128 according to bits PR2:PR0 in TSCR2

Timer System Control Register 1 7 6 5 4 3 2 1 0

$0046 TEN TSWAI TSFRZ TFFCA 0 0 0 0 TSCR1

TEN: Timer Enable 0 – Timer disabled, including the counter 1 – Timer enabled, counter free running

TSWAI: Timer Stops While in Wait 0 – Timer continues to run during wait 1 – Timer disabled when MCU is in the wait mode

TSFRZ: Timer Stops While in Freeze Mode 0 – Timer continues to run while in background mode 1 – Timer disabled when MCU is in freeze mode

TFFCA: Timer Fast Flag Clear All 0 – Normal timer flag clearing 1 – Fast timer flag clearing (see technical data sheet)

Setting the timer count time

7 6 5 4 3 2 1 0 $004D TOI 0 0 0 TCRE PR2 PR1 PR0 TSCR2

PR[2:0]: Timer Prescaler Select

PR[1:0] Prescaler 1 count time (MCLK = 8 MHz)

overflow time (MCLK = 8 MHz)

00 0 1 0.125 µs 8.192 ms 00 1 2 0.25 µs 16.384 ms 01 0 4 0.5 µs 32.768 ms 01 1 8 1.0 µs 65.536 ms 10 0 16 2.0 µs 131.07 ms 10 1 32 4.0 µs 262.14 ms 11 0 64 8.0 µs 524.28 ms 11 1 128 16.0 µs 1048.56 ms

PR[2:0] can be read or written anytime.

7 6 5 4 3 2 1 0 $004F TOF 0 0 0 0 0 0 0 TFLG2

TOF: Timer Overflow Interrupt Flag 0 – Cleared by writing a 1 to bit position 7 1 – Set to 1 when counter rolls over from $FFFF to $0000

Figure 10.4 The timer overflow interrupt flag is bit 7 of TFLG2

PORT T IOC7 IOC6 IOC5 IOC4 IOC3 IOC2 IOC1 IOC0

Pin PT7 PT6 PT5 PT4 PT3 PT2 PT1 PT0

7 6 5 4 3 2 1 0

$0040 IOS7 IOS6 IOS5 IOS4 IOS3 IOS2 IOS1 IOS0 TIOS

IOS[7:0]: Input Capture or Output Compare Channel Designator 0 – The corresponding channel is an input capture 1 – The corresponding channel is an output compare

Figure 10.5 Selecting pins of Port T to be either an input capture or an output compare

Timers

• The 9S12DP256 Programmable Timer

• Output Compares

• Pulse Train Using Interrupts

• Input Capture

• Measuring the Period of a Pulse Train Using Interrupts

$005y Bit 15 14 13 12 11 10 9 Bit 8 TCx (High) $005y+1 Bit 7 6 5 4 3 2 1 Bit 0 TCx (Low)

Figure 10.8 Timer input capture/output compare register x (y = 2x)

7 6 5 4 3 2 1 0

$004E C7F C6F C5F C4F C3F C2F C1F C0F TFLG1

C0F–C7F: Channel x Flag 0 – Cleared by writing a 1 to corresponding bit position 1 – Set to 1 when counter matches output compare x value

Figure 10.9 The output compare channel flags

\ Delay using 9S12DP256 output compare timer functions. File: OC_DELAY.WHP  HEX 0040 CONSTANT TIOS \ Timer Input Cap.\Output Comp. Select 0044 CONSTANT TCNT \ Timer Counter Register 0046 CONSTANT TSCR1 \ Timer System Control Register 1004D CONSTANT TSCR2 \ Timer System Control Register 2 004E CONSTANT TFLG1 \ Timer Interrupt Flag Register 1 005C CONSTANT TC6 \ Timer Output Compare Register 6 \ Use output compare 6 for a 25 msec delay : TIMER.INIT ( -- ) \ Initialize timer 40 TIOS C! \ select output compare 6 32 TSCR2 C! \ div by 4: 2 MHz timer clock 80 TSCR1 C! ; \ enable timer : C6F.CLR ( -- ) \ Clear C6F - bit 6 - in TFLG1 ) 40 TFLG1 C! ;

 DECIMAL : 25.MSEC ( cnt -- cnt' ) \ wait 25 msec. 50000 + \ add 50000 to prev cnt DUP TC6 ! \ store in output compare 6 reg C6F.CLR \ clear output compare 6 flag BEGIN \ wait for timeout 6 TFLG1 ?HI UNTIL ; : S.DELAY ( n -- ) \ delay n seconds TIMER.INIT 40 * \ no. of 25.msec delays TCNT @ SWAP \ cnt # FOR 25.MSEC NEXT DROP ; 

Pulse Train Example

TC6 match

TC7 match

PERIOD P_WIDTH

7 6 5 4 3 2 1 0

$0042 OC7M7 OC7M6 OC7M5 OC7M4 OC7M3 OC7M2 OC7M1 OC7M0 OC7M

OC7M7–OC7M0: Output Compare 7 Masks 0 – TC7 is disabled for the corresponding port T pin 1 – TC7 is enabled to control the corresponding port T pin

7 6 5 4 3 2 1 0

$0043 OC7D7 OC7D6 OC7D5 OC7D4 OC7D3 OC7D2 OC7D1 OC7D0 OC7D

If OC7Mx is set, data in OC7Dx is output to port T, bit x on successful TC7 compares.

7 6 5 4 3 2 1 0

$0048 OM7 OL7 OM6 OL6 OM5 OL5 OM4 OL4 TCTL1

7 6 5 4 3 2 1 0 $0049 OM3 OL3 OM2 OL2 OM1 OL1 OM0 OL0 TCTL2

OM[0:7]: Output Mode OL[0:7]: Output Level

OMx OLx Action taken on successful TCx compare 0 0 Timer disconnected from output pin logic 0 1 Toggle OCx output line 1 0 Clear OCx output line to 0 1 1 Set OCx output line to 1

Figure 10.10 Additional registers used for output compares

\ Pulse train using output compares 7 and 6. File: PULSE.WHPHEX 0040 CONSTANT TIOS \ Timer Input Cap.\Output Comp. Select 0042 CONSTANT OC7M \ Output Compare 7 Mask Register 0043 CONSTANT OC7D \ Output Compare 7 Data Register 0044 CONSTANT TCNT \ Timer Counter Register 0046 CONSTANT TSCR1 \ Timer System Control Register 10048 CONSTANT TCTL1 \ Timer Control Register 1 004D CONSTANT TSCR2 \ Timer System Control Register 2 004E CONSTANT TFLG1 \ Timer Interrupt Flag Register 1 005C CONSTANT TC6 \ Timer Output Compare Register 6005E CONSTANT TC7 \ Timer Output Compare Register 7 DECIMALVARIABLE P_WIDTH 6625 P_WIDTH !VARIABLE PERIOD 17500 PERIOD !HEX : TINIT ( -- ) C0 TIOS C! \ select output compares 6 & 7 02 TSCR2 C! \ div by 4: 2 MHz timer clock 80 TSCR1 C! \ enable timer TCNT @ DUP TC6 ! TC7 ! \ init cnt in TC6 & TC7 6 OC7M HI \ pulse train out PT6 6 OC7D LO \ PT6 goes low on TC7 match 4 TCTL1 HI 5 TCTL1 HI ; \ set PT6 high on TC6 match

 : CLR.C76 ( -- ) \ clear both C7F and C6F C0 TFLG1 C! ; : PULSE ( -- ) TINIT BEGIN TC7 @ CLR.C76 PERIOD @ + DUP TC7 ! \ TC7new = TC7old + PERIOD P_WIDTH @ + TC6 ! \ TC6 = TC7new + P_WIDTH BEGIN \ wait for PT6 to go low on 6 TFLG1 ?HI \ TC7 match and the high on UNTIL \ TC6 match AGAIN ; DECIMAL 

Timers

• The 9S12DP256 Programmable Timer

• Output Compares

• Pulse Train Using Interrupts

• Input Capture

• Measuring the Period of a Pulse Train Using Interrupts

Pulse Train

TC6 match

TC7 match

PERIOD P_WIDTH

7 6 5 4 3 2 1 0 $004C C7I C6I C5I C4I C3I C2I C1I C0I TIE

CxI: Input Capture/Output Compare "x" Interrupt enable 0 – Interrupt disabled 1 – Interrupt enabled

7 6 5 4 3 2 1 0

$004D TOI 0 0 0 TCRE PR2 PR1 PR0 TSCR2

TOI: Timer Overflow Interrupt Enable 0 – Timer overflow interrupt disabled 1 – Timer overflow interrupt enabled

Figure 10.22 Enabling timer interrupts

\ Pulse train using output compares 7 and 6. File: PULSEI.WHPHEX 0040 CONSTANT TIOS \ Timer Input Cap.\Output Comp. Select 0042 CONSTANT OC7M \ Output Compare 7 Mask Register 0043 CONSTANT OC7D \ Output Compare 7 Data Register 0044 CONSTANT TCNT \ Timer Counter Register 0046 CONSTANT TSCR1 \ Timer System Control Register 1 0048 CONSTANT TCTL1 \ Timer Control Register 1 004C CONSTANT TIE \ Timer Interrupt Enable Register 1 004D CONSTANT TSCR2 \ Timer System Control Register 2 004E CONSTANT TFLG1 \ Timer Interrupt Flag Register 1 005C CONSTANT TC6 \ Timer Output Compare Register 6005E CONSTANT TC7 \ Timer Output Compare Register 73FE2 CONSTANT TC6.IVEC \ Timer Channel 6 interrupt vector DECIMALVARIABLE P_WIDTH 6625 P_WIDTH !VARIABLE PERIOD 17500 PERIOD !HEX : TINIT ( -- ) C0 TIOS C! \ select output compares 6 & 7 00 TSCR2 C! \ div by 1: 8 MHz timer clock 80 TSCR1 C! \ enable timer TCNT @ DUP TC6 ! TC7 ! \ init cnt in TC6 & TC7 6 OC7M HI \ pulse train out PT6 6 OC7D LO \ PT6 goes low on TC7 match 4 TCTL1 HI 5 TCTL1 HI \ set PT6 high on TC6 match 40 TIE C! ; \ enable TC6 interrupts

 : CLR.C76 ( -- ) \ clear both C7F and C6F C0 TFLG1 C! ; INT: TC6.INTSER ( -- ) TC7 @ PERIOD @ + DUP TC7 ! \ TC7new = TC7old + PERIOD P_WIDTH @ + TC6 ! \ TC6new = TC7new + P_WIDTH CLR.C76RTI; : SET.TC6.INTVEC ( -- ) [ ' TC6.INTSER ] LITERAL TC6.IVEC ! ; : PULSEI ( -- ) SEI TINIT SET.TC6.INTVEC CLI ; DECIMAL

Timers

• The 9S12DP256 Programmable Timer

• Output Compares

• Pulse Train Using Interrupts

• Input Capture

• Measuring the Period of a Pulse Train Using Interrupts

Input Capture 7 6 5 4 3 2 1 0

$004E C7F C6F C5F C4F C3F C2F C1F C0F TFLG1

C0F–C7F: Channel x Flag 0 – Cleared by writing a 1 to corresponding bit position 1 – Set each time a selected active edge is detected on the ICx input line

7 6 5 4 3 2 1 0

$004A EDG7B EDG7A EDG6B EDG6A EDG5B EDG5A EDG4B EDG4A TCTL3

7 6 5 4 3 2 1 0 $004B EDG3B EDG3A EDG2B EDG2A EDG1B EDG1A EDG0B EDG0A TCTL4

EDGxB, EDGxA: Input Capture Edge Control

EDGxB EDGxA Configuration 0 0 Capture disabled 0 1 Capture on rising edges only 1 0 Capture on falling edges only 1 1 Capture on any edge (rising or falling)

Figure 10.13 Registers used for input capture

\ Use input capture to measure width of single pulse. File: PWIDTH.WHP\ Polling mode -- no interrupts\ Use TC2 -- signal on PT2HEX 0040 CONSTANT TIOS \ Timer Input Cap.\Output Comp. Select 0044 CONSTANT TCNT \ Timer Counter Register 0046 CONSTANT TSCR1 \ Timer System Control Register 1004B CONSTANT TCTL4 \ Timer Control Register 4 004D CONSTANT TSCR2 \ Timer System Control Register 2 004E CONSTANT TFLG1 \ Timer Interrupt Flag Register 1 0054 CONSTANT TC2 \ Timer Input Capture Register 2  : TIC.INIT ( -- ) 0 TIOS C! \ select all input captures 0 TSCR2 C! \ div by 1: 8 MHz timer clock 80 TSCR1 C! ; \ enable timer

 : PULSE.WIDTH ( -- n ) \ Measure width n of pulse TIC.INIT \ initialize timer input capture 5 TCTL4 LO \ capture on rising edge 4 TCTL4 HI 04 TFLG1 C! \ clear C2F flag BEGIN 2 TFLG1 ?HI \ wait for rising edge UNTIL TC2 @ \ t1 04 TFLG1 C! \ clear C2F flag 5 TCTL4 HI \ capture on falling edge 4 TCTL4 LO BEGIN 2 TFLG1 ?HI \ wait for falling edge UNTIL TC2 @ \ t1 t2 04 TFLG1 C! \ clear C2F flag SWAP - ; \ width = (t2 - t1) DECIMAL 

Timers

• The 9S12DP256 Programmable Timer

• Output Compares

• Pulse Train Using Interrupts

• Input Capture

• Measuring the Period of a Pulse Train Using Interrupts

\ Measuring the period of a pulse train. File: PERIOD.WHPHEX0040 CONSTANT TIOS \ Timer Input Cap.\Output Comp. Select 0044 CONSTANT TCNT \ Timer Counter Register 0046 CONSTANT TSCR1 \ Timer System Control Register 1 004B CONSTANT TCTL4 \ Timer Control Register 4 004C CONSTANT TIE \ Timer Interrupt Enable Register004D CONSTANT TSCR2 \ Timer System Control Register 2 004E CONSTANT TFLG1 \ Timer Interrupt Flag Register 1 004F CONSTANT TFLG2 \ Timer Interrupt Flag Register 2 0052 CONSTANT TC1 \ Timer Input Capture Register 13FEC CONSTANT TC1.IVEC \ Timer Channel 1 interrupt vector3FDE CONSTANT TOF.IVEC \ Timer overflow flag interrupt vector VARIABLE OVCNT \ timer overflow countVARIABLE OVCNT.OLD \ old timer overflow countVARIABLE TC1.OLD \ old TC1VARIABLE DPERIOD 2 VALLOT \ double word period dH dL : INIT.IC ( -- )

C0 TIOS C! \ select input capture 100 TSCR2 C! \ div by 1: 8 MHz timer clock80 TSCR1 C! \ enable timer3 TCTL4 LO 2 TCTL4 HI \ rising edge of TC102 TFLG1 C! \ clear any old flags80 TFLG2 C! \ clear TOI flag7 TSCR2 HI \ enable TOI interrupt1 TIE HI ; \ enable TC1 interrupt

\ Timer overflow interrupt routineINT: TOF.INTSER ( -- )

1 OVCNT +! \ inc OVCNT80 TFLG2 C! \ clear TOF

RTI;

\ Input capture 1 interrupt routineINT: TC1.INTSER ( -- )

TC1.OLD @ OVCNT.OLD @ \ ic.o ov.oTC1 @ DUP TC1.OLD ! \ ic.o ov.o icOVCNT @ DUP OVCNT.OLD ! \ ic.o ov.o ic ov2SWAP D- \ spL spHDPERIOD 2! \ store period in DPERIOD02 TFLG1 C! \ clear C1F

RTI; \ Set interrupt vectors: SET.TOF.INTVEC ( -- )

[ ' TOF.INTSER ] LITERAL TOF.IVEC ! ;  : SET.TC1.INTVEC ( -- )

[ ' TC1.INTSER ] LITERAL TC1.IVEC ! ; 

 \ Main program: MAIN ( -- )

SEI \ set interrupt flagSET.TOF.INTVEC \ set interrupt vectorsSET.TC1.INTVECINIT.IC \ init input captureCLI ; \ clear interrupt flag

 DECIMAL