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Stephanie Allison/John Dusatko EPICS Collaboration Meeting [email protected] May 1, 2009 1 Timing and Event System for the LCLS Electron Accelerator
Stephanie Allison/John Dusatko EPICS Collaboration Meeting [email protected] 1, 2009 1
Timing and Event System for the LCLS Electron Accelerator
Stephanie Allison/John Dusatko EPICS Collaboration Meeting [email protected] 1, 2009 2
Outline Introduction Architecture and Pictures Issues and Tasks
Stephanie Allison/John Dusatko EPICS Collaboration Meeting [email protected] 1, 2009 3
LCLS IntroductionThe Linac Coherent Light Source is an X-ray FEL based on the SLAC Linac:
1.0nC, 14GeV e- are passed thru an undulator, a Self Amplifying Stimulated Emission process produces 1.5 Angstrom X-Rays.
LCLS is an addition to the existing SLAC Linac: it uses the last 1/3 of the machine►This is important to note because we have to integrate
the New LCLS Timing System with the Existing Linac (SLC) Timing System.
Stephanie Allison/John Dusatko EPICS Collaboration Meeting [email protected] 1, 2009 4
(pre-LCLS) SLAC Accelerator Complex(Lots of Pieces)
Stephanie Allison/John Dusatko EPICS Collaboration Meeting [email protected] 1, 2009 5
Existing SLAC Timing SystemThe Linac is a Pulsed Machine (get a packet of beam per pulse) runs at a max of 360Hz (120Hz)Three Main Timing Signals:
476MHz Master Accelerator Clock (runs down 2mile Heliax Main Drive Line cable)360Hz Fiducial Trigger (used to ‘tell’ devices when the beam bunch is present) / encoded onto the 476MHz master clock128-Bit PNET (Pattern Network) Digital Broadcast (contains trigger setup, beam type & rate information)
Stephanie Allison/John Dusatko EPICS Collaboration Meeting [email protected] 1, 2009 6
New LCLS Timing SystemOld CAMAC System is no longer viable for new Systems (performance limited, obsolete)Seek to implement a new Timing System that has similar functionality, better performance, and can be laid atop the old system, working alongside itIn addition, LCLS has its own master oscillator (PLL sync’d with Linac MO) and local phase reference distribution system at S20
►LCLS Electron Accelerator is VME based (most CPUs are MVME6100), using High-Speed digital serial links to send Clock, Trigger and Data all on one optical Fiber to timing clients. Uses commercial hardware (MicroResearch Finland)
►So far for the electron side, there are >80 EVRs (mostly PMC) and >10 fanout modules.
DEV
LCLS Timing/Event System Architecture~ Linac main drive line
Sync/Div
SLCMPG
PNET
119 MHz 360 Hz
SLCevents
LCLSevents
PNET
P
PDU
EVR
OC
TTL-NIMconvert.
DigitizerLLRFBPMsToroidsCamerasWire ScannerSLC klystrons
TTL
SLC Trigs
FAN
OC
Low Level RF
EPICS Network
Precision<10 ps
fiber distribution
LCLS Timing System components are in RED
*MicroResearch
*
*
EVG
LCLS MasterOscillator
476MHzLinac
Master Osc
System is based around the EVent Generator and EVent
Receiver
FIDO PDURaw 360 Hz LCLS Timeslot Trigger
Stephanie Allison/John Dusatko EPICS Collaboration Meeting [email protected] 1, 2009 8
LCLS Systems – Master Timing Rack
119MHz Synchronizer Chassis
Contains:
• VME CPU
• VME PNET Rx
• EVG
• Master Fanouts
Master Timing Crate
Master FODUConnects fibers to Long-Haul
Trunks for entire machine
Stephanie Allison/John Dusatko EPICS Collaboration Meeting [email protected] 1, 2009 9
LCLS Timing System – BPM Client
Rx FODU & Fanout Crate
BPM Crate w/VME-EVR
Rear of BPM Crate / Showing Trigger Rear Transition Module
Stephanie Allison/John Dusatko EPICS Collaboration Meeting [email protected] 1, 2009 10
LCLS Timing System – Other ClientsToroid Crate w/PMC-EVR
Rear of Toroid Crate / Showing Trigger Rear Transition Module
Profile Monitor Crate w/ (4) CPUs & PMC-EVRs
MCOR Magnet Crate
Stephanie Allison/John Dusatko EPICS Collaboration Meeting [email protected] 1, 2009 11
Event System RequirementsEvent Generator IOC:
Send out proper event codes at 360Hz based on:PNET pattern input (beam code and bits that define beam path and other conditions)Add LCLS conditions such as BPM calibration on off-beam pulses , diagnostic pulse etc.
Future – event codes also based on new MPS and user inputSend out timing pattern, including EPICS timestamp with encoded pulse in nsec. part on timing fiberManage user-defined beam-synchronous acquisition measurement definitions
Stephanie Allison/John Dusatko EPICS Collaboration Meeting [email protected] 1, 2009 12
Trigger Generation ProcessHow an LCLS trigger is generated:1) PNET message broadcast from old timing system (following a Fiducial)2) VME PNET receiver in LCLS Master Timing Crate rx's the PNET broadcast and
gen's IRQ to VME CPU3) The Master Timing VME CPU takes the PNET data and uses it to assign the
proper event codes (MPG xmits pipelined pattern data 3 fids ahead)4) Event Codes setup in EVG one cycle ahead5) Next Fiducial is Sent 360Hz Fiducial signal rx'd by EVG6) The EVG begins to send out the event codes in its Sequence RAM7) The event codes get sent across the serial fiber links to the EVRs8) Inside the EVR, its mapping RAM (assoc memory) is set to map a specific HW
trigger to an event code.9) When the Event Code matches the same value in the mapping RAM, a hit is
generated and after a programmed delay, a HW trigger is output from the EVR to the device.
Stephanie Allison/John Dusatko EPICS Collaboration Meeting [email protected] 1, 2009 13
Event System Requirements, contEvent Receiver IOC:
Set trigger delays, pulse widths, and enable/disable via user requests (not yet done on a pulse-by-pulse basis)Set event code per trigger (triggering done in HW when event code received)Receive timing pattern 8.3 msec before corresponding pulse. Provide EPICS timestamp to record processing.Perform beam-synchronous acquisition based on tags set by EVG in the timing pattern.Process pre-defined records when specific event codes are received – not used much yet.
Stephanie Allison/John Dusatko EPICS Collaboration Meeting [email protected] 1, 2009 14
EVR IOC Time Line – 1 Beam Pulse (B0)
F00
Fiducial
Time (usec)
B0
Acq Trigger
1023
Beam Kly Standby
Record processing (event, interrupt)
Fiducial Event Received
Event Timestamp, pattern records, and BSA ready
Receive pattern for 3 pulses ahead
Hardware Triggers
~5000.3
~40100
Triggering Event Codes
Kly Accel
F1
Fiducial
…2778
110
Start End
Stephanie Allison/John Dusatko EPICS Collaboration Meeting [email protected] 1, 2009 15
Issues and TasksModifications to EVG HW and firmware for 119MHz clock input and AC line input.Changing an event code for a specific trigger requires a change in the delay to trigger at the same time – need database to automate the changeNeed to get status of RF clock into the control system“Trigger Storms”: Due to LCLS Master Osc unlocking / Fix: New MO / De-Couple LCLS Timing Sys from it (connect direct to MDL)Need interface to MPS over private UDP at 360hzNeed global kicker control (single-shot, burst) done by EVG instead of locally.Record processing at beam rate (up to 120hz) – some processing delays seen:
Too many records in one lockset.Some records pick up wrong timestamp when delayed too long and data cannot be correlated with other data on other IOCs.Some records need to have TSE field properly set.Too many CA clients monitoring PVs at beam rate instead of snapshot PVs provided at a slower rate.
Not an issue but interesting - some beam diagnostic (ie, BPM) IOC engineers choosing to trigger at max possible rate and then use the timing data to decide if record processing required or to set record severity.
Stephanie Allison/John Dusatko EPICS Collaboration Meeting [email protected] 1, 2009 16
Linac Upgrade ListWhen 2 event codes trigger a device on the same pulse, the second event restarts the delay. The second event must be ignored instead.Interrupt from the EVG on fiducial trigger (AC line trigger).Diagnostics from the fanout modules.Upgrade front end timing hardware.Move functions from the old timing system master pattern generator to the EVG IOC.
Stephanie Allison/John Dusatko EPICS Collaboration Meeting [email protected] 1, 2009 17
End of Talk – Thank you!
Stephanie Allison/John Dusatko EPICS Collaboration Meeting [email protected] 1, 2009 18
Timing RequirementsMaximum trigger rate 360 Hz Clock frequency 119 MHzClock precision 20 psCoarse step size 8.4 ns ± 20 psDelay range >1 secFine step size 20 psMax timing jitter w.r.t. clock 2 ps rmsDifferential error, location to location 8 nsLong term stability 20 ps
