IEEE TRANSACTIONS O N CIRCUITS AND SYSTEMS, VOL. 35, NO. 8, AUGUST 1988 947

Timing- Con trolled Fully Programmable Analog Signal Processors Using Switched

Continuous-Time Filters

Abstract -Analog signal processors based on continuous-time emulation of sampled-data networks are presented. In these processors, continuous- time signal delay is realized using the phase shift of fixed-frequency, fixed-Q, continuous-time low-pass filters, (LPF's), and analog multiplica- tion is sccomplisbed through signal switching using digitally programmable duty cycles. Each coefficient of the processor transfer function is indepen- dently programmable, without requiring selectable capacitor (or resistor) arrays. Experiments verify that this methad can be used to construct analog signal processors with arbitrarily programmable frequency re- sponses. - results presented here are complementary to other results presented earlier by the authors, using sampledata delays.

I. INTRODUCTION IGITAL TECHNIQUES have found increasing use D in programmable signal processing. For some appli-

cations, however, such techniques represent unnecessarily large or expensive solutions, due to the amount of circuitry (A/D, D/A converters, microprocessors, and so forth) required. Analog approaches, which may be more efficient alternatives in these cases, have in the past suffered from limited programming versatility in order to maintain com- pact implementation. This is because frequency response programming is usually achieved in analog filters by selec- tive connection of circuit elements (such as capacitors) from arrays containing many such elements of different values. The variability of transfer function shape then depends on the specific network topology used and on the number and range of element values in the arrays. As greater accuracy and/or greater freedom in specifying the filter characteristics is required, selectable element arrays can become prohibitively large and impractical.

Analog signal processing with full digital programmabil- ity of each transfer function coefficient (and thus arbitrary selection of transfer function shape) is possible without sacrificing compactness, using timing-controlled analog multipliers [l], [2]. A discrete-time timing-controlled signal processing chip using sample/hold delay elements has

Manuscript received June 30, 1987; revised October 10, 1987. This work was supported by the National Science Foundation under Grant MIP-86-1639 and by the American Electronics Association with funds provided by Analog Devices Inc. Portions of this paper were presented at the IEEE International Symposium on Circuits and Systems, Phila- delphia, PA. This paper was recommended by Associate Editor T. R. Viswanathan.

The authors are with the Department of Electrical Engineering and Center of Telecommunications Research, Columbia University, New York, NY 10027.

IEEE Log Number 8821671.

been described [2]. In this paper, we concentrate instead on schemes using no sample/hold elements, relying in- stead on the delays inherent in continuous-time filters. The resulting signal processors are composed of switches, fixed continuous-time low-pass filters (LPF's), and in some in- stances continuous-time summers. Using only these ele- ments, it is possible to program arbitrary frequency re- sponse characteristics over a specified frequency range. This is in contrast to previously reported switched filters [3], in which flexibility is limited to frequency scaling or, at most, to changing the quality factor for a given frequency response shape.

11. PRINCIPLES OF OPERATION 2. I . Timing-Controlled Multiplication

The timing-controlled analog multiplication technique is illustrated in Fig. l(a)-(c). In Fig. l(a), a continuous-time signal x ( t ) is chopped by an analog transmission gate, then reconstructed by a low-pass filter (LPF). The chopped signal w ( t ) applied to the LPF can be written as w ( t ) =

+ ( t ) x ( t ) , where the input signal x ( t ) is assumed to be bandlimited to half the chopping frequency (that is, X ( w ) is bandlimited to o < rfR = r / T R rad/s). The dc compo- nent of the gating signal + ( t ) is 7/TR, i.e., the duty cycle of the transmission gate, and represents the desired multi- plication factor produced by the chopping as described. The other terms in the Fourier series expansion of + ( t ) cause extra frequency components which are usually not useful. These components, which occur around multiples of f R are, therefore, to be removed by the LPF. If an ideal LPF (characterized as having unity gain and zero phase shift in the frequency range up to fR/2 Hz and zero gain elsewhere) is used to remove the extra frequency compo- nents, then the continuous output signal y ( t ) is simply given by

y ( t ) = L ( t ) . (1) TR

This method has been proposed [l] for use in implement- ing programmable analog signal processors. Since a single digitally controlled transmission gate can be timed to produce many different coefficients when the above multi- plication method is used in a signal processor, selectable capacitor (or resistor) arrays commonly used for gain programming in previous analog filters are avoided.

0098-4094/88/0800-0947$01.00 01988 IEEE

948 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, VOL. 35, NO. 8 , AUGUST 1988

LPF is used to reconstruct the chopped signal, the ampli- tude and phase response of the LPF distort the desired baseband signal. An LPF can be designed to have negligi- ble attenuation over much of its passband, but phase shift cannot be ignored. Rather than having to take it into

do . %

.nnMN account as a parasitic effect [l], it will be shown that this phase shift can in fact be used to advantage.

(4 2.2. Continuous-Time Delay

(b) Fig. 1. (a) Analog multiplier using switches and low-pass filter. (b) A

continuous multiplier equivalent to (a).

Consider the “discrete-time” network shown in Fig. 3(a), consisting of the well-known “coupled-form” poles section, and “direct-form’’ zeros section. (This network is used for illustrative purposes, and is not necessarily opti- mal.) In this network, the elements denoted by blocks marked “ z --’” represent time delay of one sampling period, equal to TO seconds. An extra z - l block appears at the output; this does not alter the magnitude response of the network, and its presence will be appreciated shortly. The difference equation relating the output sample values to input sample values for the network is

y ( n ) = -2dy( n - 1) + (c’ + d’) y ( n - 2 ) + ca ox ( n - 3) + calx ( n - 4) + c a ’x ( n - 5 ) . ( 2 )

Taking the z transform of both sides and using H ( z ) =

Y( z)/X( z) yields

J

+-----TI---.(

Fig. 2. Continuous-time signal summation using time-interleaving.

Typically, the digital control will consist of a simple RAM or ROM from which the signal + ( t ) is just clocked out. From Fig. l(b), it is seen that the coefficient reso- lution depends on the ratio of the repetition interval TR( = nT,) to the system clock period (Tc). As VLSI scaling permits higher system clock frequencies, T, de- creases, so more periods of T, fit into a given repetition interval: the resolution n thus increases.

Timing-controlled multiplication can be extended [ 11 to perform weighted summation without reliance on resistor or capacitor ratios, as illustrated in Fig. 2. In the figure, if the gating pulses (pl(t), +’(t), and & ( t ) for the switches connecting the three signals x l ( t ) , x 2 ( t ) , and x g ( r ) to the LPF are constrained to be non-overlapping, then the smoothing action of the LPF not only completes the timing-controlled multiplication process for each chopped signal, but also, simultaneously, sums them together, eliminating the need for a separate summing element.

When realistic LPF‘s are used in the multiplier, the chopping frequency f R must be set high enough to allow sufficient suppression of extra frequency components. (However, note that the actual value of the chopping frequency is immaterial; only the duty cycle matters, as long as spurious frequencies are rejected.) When such an

a 0 + a 1 z - ’ + a , z - 2 H ( z ) =cz-3 (3) 1 -2dz - 1 + ( c’ + d 2 ) z - 2 .

For a forcing function consisting of samples of a sinusoid of frequency a, evaluation of (3) using the substitution z + exp[ joT,] gives the magnitude and phase of the re- sulting output signal, a sampled sinusoid of the same frequency. For analysis purposes this substitution can be made into the network block diagram itself. The resulting network may be viewed as a new, continuous-time network consisting of amplifiers, summers, and continuous-time delay lines of T, seconds each, as shown in Fig. 3(b). The continuous difference equation describing the behavior of this network in the time domain is

y ( t ) = - 2dy ( t - T,) + ( c2 + d ’) y ( t - 2T,)

+ caox( t - 32’’) 4- Calx( t -47”) 4- ca ,x ( t - 5TD).

( 4 ) Note that (4) is valid for all values of the time variable. Taking the Laplace transform of both sides of (4) and using H ( s ) = Y ( s ) / X ( s ) yields

For s + jo, (5) gives the frequency response of the con- tinuousTtime network. The resulting equation has the same form as (3) evaluated at z=exp[jaT,], so the two net- works (Fig. 3(a), (b)) have homologous frequency char- acteristics.

The continuous delay lines in Fig. 3(b) can be viewed as

949 VALLANCOURT AND TSIVIDIS: ANALOG SIGNAL PROCESSORS

D D

C - s a

I I

C

L-DJ ( 4 (e)

Fig. 3. (a) A discrete-time network. (b) Continuous-time version of (a). (c) Idealized rogrammable version of (b). (d) Prac- tical programmable ASP. (e) Fully continuous filter equivakk to (d).

ideal all-pass filters, characterized as having unity gain at all frequencies, and linear phase shift with phase delay equal to TD seconds. (For linear phase filters, the phase delay is equal to the group delay.)

2.3. Combining Timing-Controlled Multiplication and Continuous Delay

The network in Fig. 3(b) can be made programmable by replacing the amplifiers with switches and ideal low-pass filters (LPF's) as described in Section 2.1 (if a coefficient is negative, the signal must be inverted before feeding it to the corresponding switch). The resulting network is shown in Fig. 3(c). (Here, ideal LPF's have also been placed in front of two delay lines which do not contain switched paths; this does not alter the transfer function, and the reason for doing this will become apparent below.) If the duty cycles of the switches in Fig. 3(c) are made equal to the corresponding gains of the amplifiers in Fig. 3(b), then the frequency responses of the networks in Fig. 3(a)-(c) are identical over the passband of the ideal LPF's.

The network of Fig. 3(c) is unrealizable, as it contains ideal delay lines and ideal LPF's; however, these elements only appear together. The salient properties of the combi- nation of an ideal delay and ideal LPF as shown in Fig. 4(a). This frequency selective phase shifting characteristic over some band of interest 1 0 1 < w, can be approximated using a suitable realistic LPF, as shown in Fig. 4(b). We may then replace each ideal delay/ideal LPF combination in Fig. 3(c) with a single real LPF, leading to the realizable final version of the programmable analog signal processor

MAGNlTUDEQPHASE

'-\". \

REAL

LPF

Fig. 4. (a) Ideal low-pass filter and ideal continuous-time delay line in cascade. (b) A real low-pass filter which is approximately equivalent to ( 4 .

(ASP) shown in Fig. 3(d). The frequency response of this network over the band of interest ( I w l < on) will be the same as that of Fig. 3(c) (and thus Fig. 3(b)) if (i) the LPF passband gain is constant, equal to unity; (ii) the LPF passband phase delay is constant, equal to T,; (iii)

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, VOL. 35, NO. 8, AUGUST 1988 950

the LPF stopband rejection is sufficient to surpass all spurious switching-produced frequencies. Thus, if switch C gates with duty cycle= c, switch D with duty cycle=d, etc., then the frequency response of the network in Fig. 3(d) is approximately

Note that the LPF‘s used each have fixed critical frequency and fixed Q, so all programming is done only by variation of the switch duty cycles. Also, since all LPF‘s in the network are identical, all “time delays” in the network are equal.

In practice, the conditions on the LPF stopband rejec- tion are not difficult to satisfy, but the conditions on the LPF‘s gain and phase can be easily met only over a portion of the LPF passband. The frequency response of the network in Fig. 3(d) will then deviate from that in Fig. 3(c) at higher frequencies; if such frequencies are of inter- est, a more detailed network model and transfer function are required. This is considered in Section IV.

The network topology of Fig. 3(d) was chosen as an example because it allows demonstration of some interest- ing features.’ We first reiterate a general property of this method, that each LPF simultaneously performs two func- tions: (1) reconstruction of the chopped signals applied to it, that is, completion of the timing-controlled multiplica- tion procedure; (2) continuous time delay. If the switches feeding a given LPF are operated in non-overlapping fash- ion, as in Fig. 2, then that LPF also performs: (3) weighted summation.

For the network shown in Fig. 3(d), the input path is not chopped before being applied to the first LPF. Thus in addition to performing the functions above, this first LPF also acts as the anti-aliasing filter for the ASP in which it is embedded. The ASP thereby exhibits self-anti-aliasing inherently. Similarly, the last LPF in the ASP can act as the final output smoothing filter.

The circuit in Fig. 3(d) employs timing control to achieve programmability [l], [2]. However, this circuit uses only LPF’s and switches (and possibly summers), and is thus different from other proposed systems that use separate continuous delay lines [ l ] or sampled-data delay lines and integrators [l], [2].

An accurate design procedure will rely on precise knowledge of the LPF parameters. Automatically tuned MOSFET-C techmques [6] may be used to obtain LPF’s with the necessary predictability and stability of character- istics for this purpose.

‘The poles section of Fig. 3(d) is closely related to the “Follow the Leader Feedback” (FLF) topolo y [4], common in continuous-time active filter design. In FLF design, kst-order LPF’s are used, and then a low-pass to bandpass transformation is applied to yield an overall band- pass response. In the specific FLF implementation known as “Primary Resonator Block” (PRB) [5 ] , each LPF is identical, just as in Fig. 3(d).

111. EXAMPLE AND EXPERIMENTAL. VERIFICATION In this section, we assume that the input to the ASP is

band limited such that the approximations leading from Fig. 3(a)-(d) are valid; we then design a programmable biquad using the topology of Fig. 3(d) and (3).

The steps involved in synthesis are:

a) set the desired ASP frequency range; b) select the reconstruction LPF‘s; c) set the chopping frequency; d) determine the LPF “delay”, T D ;

e) perform standard z-domain design using TD and (3); f) implement using the network of Fig. 3(d), with switch

duty cycles equal to coefficients determined from part (e).

We now present an example. The frequency range will be the voiceband region, 0-4 kHz. (This means that the LPF’s chosen should exhibit linear phase and unity gain over this range.) Next the LPF‘s are selected; for simplic- ity, these will be second-order, with no zeros. The general form of the transfer function for a second-order all-pole LPF with unity 0-frequency gain is

(7)

where wo is the LPF angular critical frequency and Q is the pole quality factor. This can also be expressed as

G( w ) = A ( U ) e (8) where the magnitude response is

A ( w ) = [ 1-(2-Q-’ ) ( - + (Y;i’]-’” - (9)

and the phase response is

r 1

The phase delay of the LPF‘s is 8 ( w ) / w . We will choose a Butterworth LPF response for this design, due to its maxi- mum flat passband gain and good phase characteristics. Recall that exact phase linearity is required in order for the phase delay (“time delay”) through the LPF to be constant; since we do not have exact linearity, we will define the time delay through the LPF as the phase delay near w = O . (This definition makes sense, as the phase characteristic of the Butterworth LPF used is very nearly linear at low frequencies. We could have defined the “time delay differently; this will be commented on later.) At w = 0, the phase delay is obtained using L‘Hospital‘s rule, yielding the “time delay”

TD (w,Q)-’. (11) In choosing Butterworth LPF‘s, we have set Q = 0.7071;

we must now select wo. We will allow the maximum LPF deviation from unity passband gain to be 1 percent for a

VALLANCOURT AND TSIVIDIS: ANALOG SIGNAL PROCESSORS 951

(e) 1 mmIv Fig. 5. Selected test results obtained from a single ASP at a single output node; all are obtained by programming switch

timing only. (a) Low-pass responses. (b) Bandpass responses. (c) Notch responses. (d) High-pass responses. (e) Change from bandpass to lowpass by variation of a single control pulsewidth.

4-kHz operating range, the minimum oo for which this specification is met is found from (9) to be 66.6 krad/sec or 10.6 kHz. Since this design was used to construct an experimental breadboard, oo was selected so as to yield convenient values for the LPF resistors and capacitors, while still satisfying the operating frequency range require- ments above. This lead to oo = 70.7 krad/s or 11.3 kHz; from dc to 4 kHz, the magnitude response for this choice is flat within - 0.07 dB, and the deviation from phase linear- ity is within 4 percent (it will be seen in a later section that phase nonlinearity is less difficult to compensate for than gain variation).

The chopping frequency may now be determined, given the above choice of LPF and a specification on the mini- mum acceptable rejection of the spurious frequencies pro- duced by timing-controlled multiplication. We will set this level at - 40 dB; using (9), the minimum acceptable chop- ping frequency is found to be 117 kHz, assuming that frequencies only up to 4 kHz are of interest. (If the LPF's in the ASP are relied upon to perform inherent anti-alias- ing as mentioned in Section 2.3, then signals up to the LPF comer frequency 11.3 kHz will be present at baseband; the minimum chopping frequency must then be increased to 124.3 kHz.)

952 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, VOL. 35, NO. 8, AUGUST 1988

Using (ll), the “time-delay” for the chosen LPF is TD = 20 pS. We have now established all the ASP parame- ters, and may proceed to program transfer functions using T,, (3), and standard z-domain design methods.

A breadboard was constructed based on the above parameters, and using the network of Fig. 3(d). (Timed- interleaved summation as discussed in Section 2.1 was used in the zeros section, eliminating the final summer in Fig. 3(d).) For the breadboard, Sallen-Key LPF‘s were used, guaranteeing unity gain at dc, independent of resis- tor or capacitor values. The circuit was constructed using LF356 opamps, CD4066 CMOS switches, 10-percent toler- ance resistors and capacitors in the LPF‘s, and 1-percent tolerance resistors in the summers. The transmission gate duty cycles were set by eye, and were accurate to about 1-4 percent. (In an integrated version, the transmission gate control signals would of course be developed using digital means.)

Fig. 5 shows a selection of measured programmed frequency responses obtained from the ASP breadboard. All responses shown were produced by one circuit, at the same output node, with fixed switching frequency, and with the switch duty cycles being programmed to obtain the uari- OUT results. In some cases, inverters were inserted (by programming the appropriate switches) into signal paths in order to produce negative coefficients. For an integrated implementation in which the LPF’s are realized using fully balanced techniques, negative coefficients are produced by exchanging balanced signal lines, so no inverters are re- quired.

Fig. 5(a) is a demonstration of pole-Q programming for a fixed comer frequency low-pass response; Fig. 5(b) shows center frequency programming for a fixed-bandwidth bandpass characteristic. In Fig. 5(c), notch responses with fixed Q and varying notch frequency are shown. (The notch depth is sensitive to small inaccuracies in control pulsewidth matching; the responses shown were obtained by adjustment of the pulsewidths to an accuracy greater than that used for the other responses shown in Fig. 5.) Fig. 5(d) is a demonstration of corner frequency program- ming for a fixed-Q high-pass response. In Fig. 5(e), a bandpass response is converted in steps to a low-pass response, accomplished by varying a single switch control pulsewidth in the ASP.

The responses obtained were in close agreement with predictions based on (3) (or, equivalently, (6)), over the specified 4-kHz range. Small errors in the observed frequency responses are caused by approximations made in the design process (to be discussed shortly) and non- idealities in the physical implementation. The latter group includes pulsewidth mismatches (as mentioned above) and general nonideal switching waveforms, resistor mismatches in the summers and inverters, finite opamp gain/band- width effects, and inaccuracies in the element values of the LPF’s.

Time-domain waveforms are presented in Fig. 6. Fig. 6(a) shows a music signal input waveform with corre- sponding output waveform of the ASP programmed to

0.5 mS/DIV ( 4

0.1 mS/DIV (b)

Fig. 6 . Selected waveforms from the ASP. (a) Music signal input time waveform (top) and band-pass filtered time waveform (bottom); (b) Output of timing-controlled oscillator produced by programming poles on the unit circle in the z-plane.

produce a bandpass response. Fig. 6(b) shows the ASP output produced when poles are deliberately programmed onto the unit circle in the z-plane, thus producing a timing-controlled oscillator. (Note that the frequency of oscillation is related only to the switch duty cycles, not the switching frequency itself.)

In another experiment, the switches were replaced with resistor dividers measured to produce the same coefficients as the switch duty cycles; the resulting completely non- switched system produced nearly the same results as the switched system. This network us shown in Fig. 3(e).

The self-anti-aliasing and output smoothing was tested by applying all test signals directly to the ASP input and performing measurements immediately at the ASP output; alias components were found to be attenuated by at least 40 dB. The ASP performance was also tested subjectively, by applying recorded music to the breadboard ASP input, and connecting an amplifier and loudspeaker to the out- put. The programmable filtering action was clearly audi- ble, and no unexpected effects were observed.

As stated earlier, deviation of the ASP frequency re- sponse from that predicted by (3) or (6) will occur as the evaluation frequency exceeds the region in which the LPF

VALLANCOURT AND TSIVIDIS: ANALOG SIGNAL PROCESSORS 953

phase is approximately linear and gain is approximately actual LPF characteristics. If the LPF magnitude variation unity. However, if the actual LPF gain and phase are is large enough, the simple design method of Section I11 known, the response deviates predictably from the ideal- will not work, and more accurate (and complicated) ized model, and so is useful nevertheless. Therefore, for synthesis techniques must be used. (Increasing the LPF maximum transfer function accuracy, the amplitude and order allows an increasingly good approximation to unity phase characteristics of the LPF's should be taken into gain throughout the passband (if done properly), so that account; this is discussed next. (6) holds over a larger range of frequency.)

Iv. ASP MODEL FOR REALISTIC LOW-PASS DELAY ELEMENTS

In the following, we will assume that the gain of the LPF's approaches zero at high frequencies; if this is the case, then the extra frequency components created by timing-controlled analog multiplication can be neglected for chopping frequencies sufficiently high.' Using this assumption, the network of Fig. 3(d) can be modelled for our purposes as shown in Fig. 3(e). (Recall that the net- work of Fig. 3(e) also describes a filter obtained when all gains are realized by continuous amplifiers rather than switches.) For LPF's characterized by the frequency re- sponse G ( o) = A( w ) exp [ - j e ( U ) ] , the frequency re- sponse of the network of Fig. 3(e) is

H ( U ) = C A ~ ( U )

a , + a ,A(w)e - j e (o )+ a2~ ' (w)e - j2 ' (" )

1- A(w)2de- je (")+ A 2 ( w ) ( c 2 + d2)e-j2'(")'

(12) The expression above becomes identical to (6) for LPF's with unity gain and linear phase (of slope -To) in the passband and frequencies restricted to this region; outside of this range, (12) remains valid, and may be used in accurate designs where frequencies higher than those for which (6) holds are of interest.

Consider now an LPF with exactly linear phase, but varying magnitude response; its frequency response can be written as G(u) = A(w)exp( - ~uTD). Using such LPF's in the network of Fig. 3(e), (12) becomes

H ( U ) = C A ~ ( U )

a , + a,A(w)e-'"TD+ a , ~ ' ( w ) e - j ~ ' ~ ~

1- A ( w ) 2 d e - i u T ~ + A ' ( w ) ( c 2 + d2)e-jo2TD *

(13) Comparing (13) and (6) reveals that LPF passband magni- tude variation causes the coefficients of the complex ex- ponentials in (13) to become frequency dependent with respect to those in (6). This behavior, while unusual, is not altogether unexpected, as we are insisting on modeling the network starting from the continuous difference equation (4) instead of differential equations which account for the

The leading term in (13) introduces a droop in the response as the frequency increases. This droop is similar in magnitude (but not in origin) to the zeroth-order hold effect that accompanies sampled-data filters. It should be emphasized that the ASP's described in this paper do not suffer from the zeroth-order hold effect because no sam- ple/hold elements are used; the high-frequency droop present in these ASP's is due only to the attenuation introduced by the LPF delay elements. It may be possible to compensate for such droop in a manner similar to that used to compensate for zeroth-order hold, by a small perturbation of the main part of the transfer function.

The effects of LPF phase may be seen by assuming LPF's with unity gain in the passband, zero gain elsewhere, and phase factor exp[ - j e ( w ) ] . Equation (12) can then be written as

(14)

Comparing (14) and (6), it is evident that LPF phase nonlinearity causes the "time delay" (the quantity multi- plying - jo in the exponent of e, i.e., the phase delay e( w ) / w ) to become frequency-dependent. This does not invalidate the simple design method of Section 111, as the coefficients of the transfer function in (14) are not frequency dependent. Nonlinear phase (nonuniform delay) can be shown [7] to have a "warping" effect on the frequency response of a network as compared with the response of the same network using uniform delay lines. Thus, for "brick wall" responses, nonlinear phase shift can be accounted for by a suitable "prewarping" procedure similar to that used in bilinear transformation; such a technique has been considered in [7].

In Section 111, the time delay was taken for simplicity as a fixed constant T,, equal to the phase delay near w = 0; this was justified on the basis of near phase-linearity of Butterworth LPF's at low frequencies. In this or other instances involving weak nonlinearity of phase, alternative definitions of a fixed time delay may be used. For exam- ple, we may wish to program the ASP to produce some transfer function with critical frequency wc; in order to ensure maximum accuracy of behavior near this frequency, we could define the time delay To as the phase delay at wc,

'If the input signal to the ASP is externally bandlimited to the desired frequency range of interest, then higher frequency components created by switching within the ASP will not lead to spurious frequencies appearing in the baseband, even if the LPF's inside the ASP do not suppress the higher freauencies comDletelv: the onlv effect of such oDeration will be a

i.e., 8 ( w c ) / U c * If a generally good approximation Over the entire LPF passband is important, we could define TD as the slope of the best-fit straight line through the entire

Gdictabl; change in h e b&eband c6m onent, caused by the fact that Lgh frequencies will be aliased back to tI!e signal frequincies from which they arose. The uses of this effect are currently under investigation.

passband phase characteristic. Other definitions are also possible-

954 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, VOL. 35, NO. 8, AUGUST 1988

The total amount of phase shift produced by the LPPs over their passbands determines the periodicity of the ASP

sponses of discrete-time networks). Depending on the LPF type and order, the LPF‘s may produce more or less total phase shift than w radians over their passbands; if they have more, the frequency response of the ASP repeats

I51 G. Hurtig, 111, “The primary resonator block technique of filter synthesis ” in Proc. Int. Filter Symp. p. 84 1972.

[6] y . Tsividis, M. B ~ ~ , and J. aoury, “Co&uous-time MOSFET-c

125-140, Feb. 1986. [7] A. G. J. Hoit and c. Pule, “Continuous filters using digital tech-

niques and incorporating variable frequency delay lines,” Int. J. Electron., vol. 29, no. 4, pp. 349-354, 1970.

frequency response (similar to the periodic frequency re- filters in VLSI,” IEEE Trans. Circuits S Y S ~ . , vol. CAS-33, pp.

within the useful operating range, leading to the possibility of implementing bandpass or bandstop filters, etc. The actual phase response of the LPF’s may be tailored by selection of LPF order and type, or by cascading all-pass filters with each LPF.

V. CONCLUSION Analog signal processors based on continuous-time emu-

lation of sampled-data networks have been described. These processors are constructed of fixed continuous-time low-pass filters and switches, and may be digitally pro- grammed through the switch duty cycles to produce arbi- trary frequency responses over a specified range. Each coefficient of the processor transfer function is indepen- dently programmable, without requiring selectable capaci- tor (or resistor) arrays. In some cases, application of the methods given here yield signal processors that can per- form their own anti-aliasing without the addition of any extra circuits. Theoretical results have been verified experi- mentally using a breadboard ASP.

[31

141

REFERENCES Y. P. Tsividis, “Signal processors with transfer function coefficients determined by timmg,” IEEE Trans. Circuits Syst. vol. CAS-29, pp. 807-817, Dec. 1982. D. Vallancourt and Y. P. Tsividis, “A fully programmable sampled- data analoe CMOS filter with transfer function coefficients de- termined b: timing,” IEEE J. Solid-State Circuits, vol. SC-22, pp. 1022-1030, Dec. 1987. W. Heinlein and H. Holmes, Active Filters for Integrated Circuits, London, Endand: Prentice-Hall Int., 1974, ch. 11 and references therein. K. R. Laker and M. S. Ghausi, “Synthesis of a low-sensitivity multiloop feedback active RC filter, IEEE Trans. Circuits Syst., vol. CAS-21, pp. 252-259, Mar. 1974.

David Vallancourt (S’84-M87) received the B.S., M.S., and Ph.D. degrees in electrical engineering from Columbia University, New York, in 1981, 1984, and 1987, respectively.

He worked for Hewlett-Packard from 1981 to 1984 as an R&D engineer, and spent the summer of 1984 at Motorola Inc., Austin TX, designing a discrete-time analog signal processing chip for use in his Ph.D. research. He is currently an Assistant Professor in the Department of Electri- cal Eneineerine and Center for Telecommunica-

0

tions Research of Columbia University. His research interests include discrete- and continuous-time signal processors, mixed analog/digital VLSI systems, and analog artificial intelligence networks.

m

Yannis P. Tsividis (S’71-M74-SM’81-F’86) re- ceived the Ph.D. degree from the University of California, Berkeley, in 1976.

He is a Professor at Columbia University, New York, and is the author of Operation and Modeling of the MOS Transistor (McGraw-Hill, 1987). He has been a member of the Administra- tive Committee of the IEEE Circuits and Sys- tems Society and of the United Nations Ad- visory Committee on Science and Technology for DeveloDment. He is the recinient of the 1984

IEEE W. R. G. Baker Best Paper Award and the 19i6 European Solid State Circuits Conference Best Paper Award, and co-recipient of the 1987 IEEE Circuits and Systems Society Darlington Best Paper Award.