TLC4501, TLC4501A, TLC4502, TLC4502A FAMILY OF SELF ... · tlc4501, tlc4501a, tlc4502, tlc4502a...

TLC4501, TLC4501A, TLC4502, TLC4502AFAMILY OF SELF-CALIBRATING (Self-Cal )

PRECISION CMOS RAIL-TO-RAIL OUTPUT OPERATIONAL AMPLIFIERSSLOS221A – MAY 1998 – REVISED JULY 1999

1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Self-Calibrates Input Offset Voltage to40 µV Max

Low Input Offset Voltage Drift . . . 1 µV/°C Input Bias Current . . . 1 pA

Open Loop Gain . . . 120 dB

Rail-To-Rail Output Voltage Swing

Stable Driving 1000 pF Capacitive Loads

Gain Bandwidth Product . . . 4.7 MHz

Slew Rate . . . 2.5 V/µs

High Output Drive Capability . . . ±50 mA

Calibration Time . . . 300 ms

Characterized From –55 °C to 125°C Available in Q-Temp Automotive

HighRel Automotive ApplicationsConfiguration Control / Print SupportQualification to Automotive Standards

description

The TLC4501 and TLC4502 are the highest precision CMOS single supply rail-to-rail operational amplifiersavailable today. The input offset voltage is 10 µV typical and 40 µV maximum. This exceptional precision,combined with a 4.7-MHz bandwidth, 2.5-V/µs slew rate, and 50-mA output drive, is ideal for multipleapplications including: data acquisition systems, measurement equipment, industrial control applications, andportable digital scales.

These amplifiers feature self-calibrating circuitry which digitally trims the input offset voltage to less than 40 µVwithin the first 300 ms of operation. The offset is then digitally stored in an integrated successive approximationregister (SAR). Immediately after the data is stored, the calibration circuitry effectively drops out of the signalpath, shuts down, and the device functions as a standard operational amplifier.

Power-OnReset

IN+

OUT

A/D

–

+

ControlLogic Oscillator

D/A

SAR

GND

IN–

VDD5 V

Calibration Circuitry

Offset Control3

2

8

1

4

Figure 1. Channel One of the TLC4502

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Copyright 1999, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily includetesting of all parameters.

LinEPIC and Self-Cal are trademarks of Texas Instruments Incorporated.

On products compliant to MIL-PRF-38535, all parameters are testedunless otherwise noted. On all other products, productionprocessing does not necessarily include testing of all parameters.

TLC4501, TLC4501A, TLC4502, TLC4502AFAMILY OF SELF-CALIBRATING (Self-Cal )PRECISION CMOS RAIL-TO-RAIL OUTPUT OPERATIONAL AMPLIFIERSSLOS221A – MAY 1998 – REVISED JULY 1999

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

description (continued)

Using this technology eliminates the need for noisy and expensive chopper techniques, laser trimming, andpower hungry, split supply bipolar operational amplifiers.

NCVDD +2OUT2IN –2IN +

NC1OUT1IN –1IN +

VDD–/GND

1

2

3

4

5

10

9

8

7

6

3 2 1 20 19

9 10 11 12 13

4

5

6

7

8

18

17

16

15

14

NC2OUTNC2IN–NC

NC1IN–

NC1IN+

NC

NC

1OU

TN

C2I

N+

NC

NC

NC

NC

VD

D+

VD

D–

/GN

D

TLC4502FK PACKAGE(TOP VIEW)

NC – No internal connection

1

2

3

4

8

7

6

5

1OUT1IN –1IN +

VDD –/GND

VDD+2OUT2IN–2IN+

TLC4502D OR JG PACKAGE

(TOP VIEW)

1

2

3

4

8

7

6

5

NC1IN –1IN +

VDD –/GND

NCVDD+OUTNC

TLC4501D PACKAGE(TOP VIEW)

TLC4502U PACKAGE(TOP VIEW)

AVAILABLE OPTIONS

PACKAGED DEVICES

TA VIOmax AT 25 °C SMALLOUTLINE†

(D)

CHIP CARRIER(FK)

CERAMIC DIP(JG)

CERAMIC FLATPACK

(U)

40 µV TLC4501ACD — — —

0°C to 70°C50 µV TLC4502ACD — — —

0°C to 70°C80 µV TLC4501CD — — —

100 µV TLC4502CD — — —

40 µV TLC4501AID — — —

40°C to 125°C50 µV TLC4502AID — — —

–40°C to 125°C80 µV TLC4501ID — — —

100 µV TLC4502ID — — —

40°C to 125°C50 µV TLC4502AQD — — —

–40°C to 125°C100 µV TLC4502QD — — —

55°C to 125°C50 µV TLC4502AMD TLC4502AMFKB TLC4502AMJGB TLC4502AMUB

–55°C to 125°C100 µV TLC4502MD TLC4502MFKB TLC4502MJGB TLC4502MUB

† The D package is also available taped and reeled.




absolute maximum ratings over operating free-air temperature range (unless otherwise noted) †

Supply voltage, VDD+ (see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Differential input voltage, VID (see Note 2) ±7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input voltage range, VI (any input, see Note 1) –0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input current, II (each input) ±5 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output current, IO (each output) ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Total current into VDD+ ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Total current out of VDD–/GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrostatic discharge (ESD) > 2 kV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Duration of short-circuit current at (or below) 25°C (see Note 3) unlimited. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating free-air temperature range, TA: TLC4502C 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TLC4502I –40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TLC4502Q –40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TLC4502M –55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Case temperature for 60 seconds, TC: FK package 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, andfunctional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is notimplied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. All voltage values, except differential voltages, are with respect to VDD –/GND.2. Differential voltages are at IN+ with respect to IN–. Excessive current flows when an input is brought below VDD– – 0.3 V.3. The output may be shorted to either supply. Temperature and/or supply voltages must be limited to ensure that the maximum

dissipation rating is not exceeded.

DISSIPATION RATING TABLE

PACKAGETA ≤ 25°C DERATING FACTOR TA = 70°C TA = 85°C TA = 125°C

PACKAGE APOWER RATING ABOVE TA = 25°C

APOWER RATING

APOWER RATING

APOWER RATING

DFK

725 mW1375 W

5.8 mW/°C11 0 W/°C

464 mW880 W

377 mW715 W

145 mW275 WFK

JG1375 mW1050 mW

11.0 mW/°C8.4 mW/°C

880 mW672 mW

715 mW546 mW

275 mW210 mWJG

U1050 mW675 mW

8.4 mW/ C5.4 mW/°C

672 mW432 mW

546 mW350 mW

210 mW135 mW

recommended operating conditions

TLC4502C TLC4502I TLC4502Q TLC4502MUNIT

MIN MAX MIN MAX MIN MAX MIN MAXUNIT

Supply voltage, VDD 4 6 4 6 4 6 4 6 V

Input voltage range, VI VDD– VDD+ – 2.3 VDD– VDD+ – 2.3 VDD– VDD+ – 2.3 VDD– VDD+ – 2.3 V

Common-mode input voltage, VIC VDD– VDD+ – 2.3 VDD– VDD+ – 2.3 VDD– VDD+ – 2.3 VDD– VDD+ – 2.3 V

Operating free-air temperature, TA 0 70 –40 125 –40 125 –55 125 °C



electrical characteristics at specified free-air temperature, V DD = 5 V, GND = 0 (unless otherwisenoted)

PARAMETER TEST CONDITIONS TA†TLC450xC

UNITPARAMETER TEST CONDITIONS TA†MIN TYP MAX

UNIT

TLC4501 –80 10 80

VIO Input offset voltageVDD = ±2.5 V, VO = 0, TLC4501A

Full range–40 10 40

µVVIO Input offset voltage DD ,VIC = 0,

O ,RS = 50 Ω TLC4502


µV

TLC4502A –50 10 50

αVIOTemperature coefficient of input

Full range 1 µV/°CαVIO offset voltageFull range 1 µV/°C

IIO Input offset current VDD = ±2.5 V, VO = 0, 25°C 1pAIIO Input offset current VDD ±2.5 V,

VIC = 0,VO 0,RS = 50 Ω Full range 500

pA

IIB Input bias current25°C 1

pAIIB Input bias currentFull range 500

pA

IOH = – 500 µA 25°C 4.99

VOH High-level output voltageIOH = 5 mA

25°C 4.9 VIOH = – 5 mA

Full range 4.7

VIC = 2.5 V, IOL = 500 µA 25°C 0.01

VOL Low-level output voltageVIC = 2 5 V IOL = 5 mA

25°C 0.1 VVIC = 2.5 V, IOL = 5 mA

Full range 0.3

AVDLarge-signal differential voltage VIC = 2.5 V, VO = 1 V to 4 V, 25°C 200 1000

V/mVAVDg g g

amplificationIC ,

RL = 1 kΩ,O ,

See Note 4 Full range 200V/mV

RI(D) Differential input resistance 25°C 10 kΩ

RL Input resistance See Note 4 25°C 1012 Ω

CL Common-mode input capacitance f = 10 kHz, P package 25°C 8 pF

zO Closed-loop output impedance AV = 10, f = 100 kHz 25°C 1 Ω

CMRR Common mode rejection ratioVIC = 0 to 2.7 V, VO = 2.5 V, 25°C 90 100

dBCMRR Common-mode rejection ratio IC , O ,RS = 1 kΩ Full range 85

dB

kSVRSupply-voltage rejection ratio

VDD = 4 V to 6 V VIC = 0 No load25°C 90 100

dBkSVRy g j

(∆VDD ± /∆VIO)VDD = 4 V to 6 V, VIC = 0, No load

Full range 90dB

TLC4501/A25°C 1 1.5

IDD Supply current VO = 2 5 V No load

TLC4501/AFull range 2

mAIDD Supply current VO = 2.5 V, No load

TLC4502/A25°C 2.5 3.5

mA


VIT(CAL) Calibration input threshold voltage Full range 4 VVIT(CAL) Calibration input threshold voltage Full range 4 V

† Full range is 0°C to 70°C.NOTE 4: RL and CL values are referenced to 2.5 V.




operating characteristics, V DD = 5 V

PARAMETER TEST CONDITIONS TA†TLC450xC, TLC450xAC


UNIT

SR Slew rate at unity gain VO = 0 5 V to 2 5 V CL = 100 pF25°C 1.5 2.5 V/µs

SR Slew rate at unity gain VO = 0.5 V to 2.5 V, CL = 100 pFFull range 1 V/µs

V Equivalent input noise voltagef = 10 Hz 25°C 70

nV/√HzVn Equivalent input noise voltagef = 1 kHz 25°C 12

nV/√Hz

VN(PP)Peak-to-peak equivalent input noise f = 0.1 to 1 Hz 25°C 1

µVVN(PP)q

voltage f = 0.1 to 10 Hz 25°C 1.5µV

In Equivalent input noise current 25°C 0.6 fA/√Hz

VO = 0.5 V to 2.5 V,f 10 kH

AV = 1 25°C 0.02%

THD + N Total harmonic distortion plus noisef = 10 kHz,RL = 1 kΩ, AV = 10 25°C 0.08%RL 1 kΩ,CL = 100 pF AV = 100 25°C 0.55%

Gain-bandwidth productf = 10 kHz,CL = 100 pF

RL = 1 kΩ,25°C 4.7 MHz

BOM Maximum output swing bandwidthVO(PP) = 2 V,RL = 1 kΩ,

AV = 1,CL = 100 pF

25°C 1 MHz

t Settling time

AV = –1,Step = 0.5 V to 2.5 V,

to 0.1% 25°C 1.6µsts Settling time RL = 1 kΩ,

CL = 100 pF to 0.01% 25°C 2.2

µs

φm Phase margin at unity gain RL = 1 kΩ, CL = 100 pF 25°C 74

Calibration time 25°C 300 ms

† Full range is 0°C to 70°C.NOTE 4: RL and CL values are referenced to 2.5 V.




PARAMETER TEST CONDITIONS TA†TLC450xI


UNIT

TLC4501 –80 10 80

VIO Input offset voltageVDD = ±2.5 V, VO = 0, TLC4501A



O ,RS = 50 Ω TLC4502


µV

TLC4502A –50 10 50



VDD = ±2.5 V, VO = 0, 25°C 1

IIO Input offset current

DDVIC = 0,

ORS = 50 Ω –40°C to

85°C 500pA

Full range 5 nA

25°C 1

IIB Input bias currentVDD = ±2.5 V,VIC = 0,

VO = 0,RS = 50 Ω

–40°C to85°C 500

pA

Full range 10 nA

IOH = – 500 µA 25°C 4.99


25°C 4.9 VIOH = – 5 mA

Full range 4.7

VIC = 2.5 V, IOL = 500 µA 25°C 0.01


25°C 0.1 VVIC = 2.5 V, IOL = 5 mA

Full range 0.3


V/mVAVDg g g

amplificationIC ,

RL = 1 kΩ,O ,








dB

kSVRSupply-voltage rejection ratio

VDD = 4 V to 6 V VIC = 0 No load25°C 90 100

dBkSVRy g j

(∆VDD ± /∆VIO)VDD = 4 V to 6 V, VIC = 0, No load

Full range 90dB

TLC4501/A25°C 1 1.5

IDD Supply current VO = 2 5 V No load


mAIDD Supply current VO = 2.5 V, No load

TLC4502/A25°C 2.5 3.5

mA



† Full range is –40°C to 125°C.NOTE 4: RL and CL values are referenced to 2.5 V.





PARAMETER TEST CONDITIONS T †TLC450xI, TLC450xAI


UNIT

SR Slew rate at unity gain VO = 0 5 V to 2 5 V CL = 100 pF25°C 1.5 2.5 V/µs

SR Slew rate at unity gain VO = 0.5 V to 2.5 V, CL = 100 pFFull range 1 V/µs



nV/√Hz


µVVN(PP)q



VO = 0.5 V to 2.5 V,f 10 kH

AV = 1 25°C 0.02%



RL = 1 kΩ,25°C 4.7 MHz


AV = 1,CL = 100 pF

25°C 1 MHz

t Settling time

AV = –1,Step = 0.5 V to 2.5 V,


CL = 100 pF to 0.01% 25°C 2.2

µs



† Full range is –40°C to 125°C.NOTE 4: RL and CL values are referenced to 2.5 V.




PARAMETER TEST CONDITIONS TA†TLC4502Q,TLC4502M UNITA

MIN TYP MAX

VIO Input offset voltageVDD = ±2.5 V, VO = 0, TLC4502



O ,RS = 50 Ω TLC4502A


µV



IIO Input offset current VDD = ±2.5 V, VO = 0, 25°C 1nAIIO Input offset current VDD ±2.5 V,

VIC = 0,VO 0,RS = 50 Ω 125°C 5

nA

IIB Input bias current25°C 1

nAIIB Input bias current125°C 10

nA

IOH = – 500 µA 25°C 4.99


25°C 4.9 VIOH = – 5 mA

Full range 4.7

VIC = 2.5 V, IOL = 500 µA 25°C 0.01


25°C 0.1 VVIC = 2.5 V, IOL = 5 mA

Full range 0.3


V/mVAVDg g g

amplificationIC ,

RL = 1 kΩ,O ,








dB

kSVRSupply-voltage rejection ratio VDD = 4 V to 6 V, VIC = VDD /2, 25°C 90 100

dBkSVRy g j

(∆VDD ± /∆VIO)DD , IC DD ,

No load Full range 90dB

IDD Supply current VO = 2 5 V No load25°C 2.5 3.5

mAIDD Supply current VO = 2.5 V, No loadFull range 4

mA


† Full range is –40°C to 125°C for Q suffix, –55°C to 125°C for M suffix.NOTE 4: RL and CL values are referenced to 2.5 V.





PARAMETER TEST CONDITIONS TA†

TLC4502Q, TLC4502M,TLC4502AQ,TLC4502AM UNIT

MIN TYP MAX

SR Slew rate at unity gainVO = 0.5 V to 2.5 V, CL = 100 pF 25°C 1.5 2.5 V/µs

SR Slew rate at unity gain O ,See Note 4

LFull range 1 V/µs



nV/√Hz


µVVN(PP)q



VO = 0.5 V to 2.5 V,f 10 kH

AV = 1 25°C 0.02%



RL = 1 kΩ,25°C 4.7 MHz


AV = 1,CL = 100 pF

25°C 1 MHz

t Settling time

AV = –1,Step = 0.5 V to 2.5 V,


CL = 100 pF to 0.01% 25°C 2.2

µs



† Full range is –40°C to 125°C for Q suffix, –55°C to 125°C for M suffix.NOTE 4: RL and CL values are referenced to 2.5 V.



TYPICAL CHARACTERISTICS

Table of GraphsFIGURE

VIO Input offset voltageDistribution 2, 3, 4

VIO Input offset voltagevs Common-mode input voltage 5

αVIO Input offset voltage temperature coefficient Distribution 6, 7

VOH High-level output voltage vs High-level output current 8

VOL Low-level output voltage vs Low-level output current 9

VO(PP) Maximum peak-to-peak output voltage vs Frequency 10

IOS Short-circuit output current vs Free-air temperature 11

VO Output voltage vs Differential input voltage 12

AVD Large signal differential voltage amplificationvs Free-air temperature 13

AVD Large-signal differential voltage amplificationvs Frequency 14

zo Output impedance vs Frequency 15

CMRR Common mode rejection ratiovs Frequency 16

CMRR Common-mode rejection ratioq y

vs Free-air temperature 17

SR Slew ratevs Load capacitance 18

SR Slew ratevs Free-air temperature 19

Inverting large-signal pulse response 20

Voltage-follower large-signal pulse response 21

Inverting small-signal pulse response 22

Voltage-follower small-signal pulse response 23

Vn Equivalent input noise voltage vs Frequency 24

Input noise voltage Over a 10-second period 25

THD + N Total harmonic distortion plus noise vs Frequency 26

Gain-bandwidth product vs Free-air temperature 27

φ Phase marginvs Load capacitance 28

φm Phase marginvs Frequency 14

Gain margin vs Load capacitance 29

PSRR Power-supply rejection ratio vs Free-air temperature 30

Calibration time at –40°C 31

Calibration time at 25°C 32







10

8

2

0

12

16

DISTRIBUTION OF TLC4502 INPUTOFFSET VOLTAGE

18

14

6

4

–40

–30

–20

–10 0 10 20 30 40

Per

cent

age

Of A

mpl

ifica

tion

– %

VIO – Input Offset Voltage – µV

339 Amplifier From 2 Wafer LotVDD = ± 2.5 VTA = 40°C

Figure 2–6

0

6

4

2

0

10

12

14

–50

–40

–30

–20

–10 0 10 20 30 40 50 60



Per

cent

age

of A

mpl

ifier

s –

%


8

Figure 3

8

6

2

0

Per

cent

age

Of A

mpl

ifica

tion

– %

10

12


16

14

4

–50

–40

–30

–20

–10 0 10 20 30 40 50



Figure 4 Figure 5

0

–50

–150

–200–3 –2 –1 0

– In

put O

ffset

Vol

tage

–

50

150

INPUT OFFSET VOLTAGEvs

COMMON-MODE INPUT VOLTAGE200

1 2 3

100

–100

VIC – Common-Mode Input Voltage – v

VIO

Vµ

VDD = ±2.5 VRS = 50 ΩTA = 25°C




Figure 6

αVIO – Temperature Coefficient – µV/°C

30 Amplifiers From 1 Wafer LotVDD = ± 2.5 VTA = 25°C To –40°C

10

5

0–3 –2 0 1

Per

cent

age

Of A

mpl

ifier

s –

%

15

20

DISTRIBUTION OF TLC4502 INPUT OFFSETVOLTAGE TEMPERATURE COEFFICIENT

25

2 3–1

Figure 7

30 Amplifiers From1 Wafer LotVDD = ± 2.5 VTA = 25°C To 85°C

10

8

2

0

Per

cent

age

Of A

mpl

ifier

s –

%

14

16

DISTRIBUTION OF TLC4502 INPUT OFFSETVOLTAGE TEMPERATURE COEFFICIENT

20

18

12

6

4

–3.5 –3

–2.5 –2

–1.5 –1

–0.5 0

0.5 1

1.5 2

2.5 3

3.5

αVIO – Temperature Coefficient – µV/°C

Figure 8

IOH – High-Level Output Current – mA

3

2

0.5

00 10 20 30 40

3.5

4.5

HIGH-LEVEL OUTPUT VOLTAGEvs

HIGH-LEVEL OUTPUT CURRENT5

50 60 70 80

4

2.5

VDD = 5 VVIC = 2.5 V

1.5

1

TA = –40°C

TA = 25°C

VO

H –

Hig

h-Le

vel O

utpu

t Vol

tage

– V

ÁÁÁÁ

V OH

TA = 125°C

TA = 85°C

Figure 9

IOL – Low-Level Output Current – mA

1

0.75

0.25

00 10 20 30 40 50

– Lo

w-L

evel

Out

put V

olta

ge –

V

1.5

1.75

LOW-LEVEL OUTPUT VOLTAGEvs

LOW-LEVEL OUTPUT CURRENT2

60 70 80

0.5

1.25

VO

L

VDD = 5 VVIC = 2.5 V

TA = –40°C

TA = 25°C

TA = 85°C

TA = 125°C





Figure 10

8

4

2

0

10

6

100

– M

axim

um P

eak-

To-P

eak

Out

put V

olta

ge –

V

f – Frequency – Hz

MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGEvs

FREQUENCY

1 k 10 k 100 k 1 M 10 M

VO

(PP

)

VDD = 5 V

Figure 11

IOS+

IOS–

61

59

57

55–50 –25 0 25

– S

hort

-Circ

uit O

utpu

t Cur

rent

– m

A

65

67

SHORT-CIRCUIT OUTPUT CURRENTvs

FREE-AIR TEMPERATURE69

50 75 100

63

TA – Free-Air Temperature – °C

I OS

Figure 12

1

0

–2

–3–0.2 –0.15 –0.1 –0.05

2

0.15

OUTPUT VOLTAGEvs

DIFFERENTIAL INPUT VOLTAGE

0.20

3

–1

0.05 0.1VID – Differential Input Voltage – mV

– O

utpu

t Vol

tage

– V

VO

VDD = 5 VVIC = 2.5 VRL = 1 kΩTA = 25°C

Figure 13

800

600

200

0–55 –30 –5 20 45

– La

rge-

Sig

nal D

iffer

entia

l

1000

1400

LARGE-SIGNAL DIFFERENTIALVOLTAGE AMPLIFICATION

vsFREE-AIR TEMPERATURE

1600

70 95 120

1200

400

AV

DV

olta

ge A

mpl

ifica

tion

– V

/mV


RL = 1 kΩ




VDD = 5 VRL = 1 kΩCL = 100 pFTA = 25°C

20

0

–20

–401 k

40

60


LARGE-SIGNAL DIFFERENTIAL VOLTAGEAMPLIFICATION AND PHASE MARGIN

vsFREQUENCY

80

10 k 100 k 1 M 10 M 100 M

Pha

se M

argi

n

180°

135°

90°

45°

0°

–45°

–90°

– La

rge-

Sig

nal D

iffer

entia

lA

VD Vol

tage

Am

plifi

catio

n –

dB

Figure 14

10

1

0.1

0.001

1000

100

– O

utpu

t Im

peda

nce

–

100


OUTPUT IMPEDANCEvs

FREQUENCY

0.01

1 k 10 k 100 k 1 M

zO

Ω

AV = 1

AV = 100

AV = 10

Figure 15





Figure 16

90

80

60

40

10

110

70

100

CM

RR

– C

omm

on-M

ode

Rej

ectio

n R

atio

– d

B 100


COMMON-MODE REJECTION RATIOvs

FREQUENCY

50

30

20

1 k 10 k 100 k 1 M 10 M

VDD = 5 VVIC = 2.5 VTA = 25°C

Figure 17


110

105

95

90–50 –25 0 25 50

CM

RR

– C

omm

on-M

ode

Rej

ectio

n R

atio

– d

B

120

125

COMMON-MODE REJECTION RATIOvs


75 100 125

115

100

VDD = 5 V

Figure 18

CL – Load Capacitance – pF

SR+

SR–

4

3

2

0

6

1

10

SR

– S

lew

Rat

e –

V/

5

SLEW RATEvs

LOAD CAPACITANCE

100 1 k 10 k 100 k

sµ

Figure 19


4

2

0–50 –25 0 25 50

SR

– S

lew

Rat

e –

6

SLEW RATEvs


75 100 125

sµ

V/

SR–

SR+

VDD = 5 VRL = 1 kΩCL = 100 pFAV = 1




Figure 20

t – Time – µs

2.5

2

1

0.50 25 50 75 100 125

3

4

INVERTING LARGE-SIGNAL PULSE RESPONSE

4.5

150 175 200

3.5

1.5VDD = 5 VRL = 1 kΩCL = 100 pFAV = –1TA = 25°C

– O

utpu

t Vol

tage

– V

VO

Figure 21

t – Time – µs

2.5

2

1

0.50 25 50 75 100 125

3.5

4

VOLTAGE-FOLLOWER LARGE-SIGNALPULSE RESPONSE

4.5

150 175 200

3

1.5 VDD = 5 VRL = 1 kΩCL = 100 pFAV = 1TA = 25°C

– O

utpu

t Vol

tage

– V

VO

Figure 22

t – Time – µs

2.5

2.49

2.48

2.470 20 40 60 80 100 120

2.505

2.515

INVERTING SMALL-SIGNAL PULSE RESPONSE

2.525

140 160 180 200

2.52

2.51

2.495

2.485

2.475

VDD = 5 VRL = 1 kΩCL = 100 pFAV = –1TA 25°C

– O

utpu

t Vol

tage

– V

VO

Figure 23

t – Time – µs

2.5

2.49

2.48

2.470 50 100 150

2.51

2.52

VOLTAGE-FOLLOWER SMALL-SIGNALPULSE RESPONSE

2.53

200 250

VDD = 5 VRL = 1 kΩCL = 100 pFAV = 1TA = 25°C

– O

utpu

t Vol

tage

– V

VO





Figure 24

50

30

20

010 100 1 k

70

90


EQUIVALENT INPUT NOISE VOLTAGEvs

FREQUENCY100

10 k 100 k

80

60

40

10

VDD = 5 VRS = 20 ΩTA = 25°C

VN

– E

quiv

alen

t Inp

ut N

oise

Vol

tage

– n

v//H

znV

/H

zV

n

Figure 25

–400

–12000 1 2 3 4 5 6

Inpu

t Noi

se V

olta

ge –

nV

400

t – Time – s

INPUT NOISE VOLTAGE OVERA 10-SECOND PERIOD

1200

7 8 9 10

VDD = 5 Vf = 0.1 Hz To 10 HzTA = 25°C

Figure 26

0.1

0.01

1

100 1 k 10 k 100 k

TH

D+N

– T

otal

Har

mon

ic D

isto

rtio

n P

lus

Noi

se –

%


TOTAL HARMONIC DISTORTION PLUS NOISEvs

FREQUENCY

VDD = 5 VRL = 1 kΩ TIED 2.5 V

AV = 1

AV = 100

AV = 10

Figure 27

VDD = 5 VF = 10 kHzRL = 1 kΩCL = 100 pF

5

4.5

4–40 –25 0 25

Gai

n-B

andw

idth

Pro

duct

– M

Hz 5.5

GAIN-BANDWIDTH PRODUCTvs


50 75 85





Figure 28

Rnull = 50 Ω

Rnull = 20 Ω

Rnull = 0

45

30

15

010

Pha

se M

argi

n

60

75

PHASE MARGINvs

LOAD CAPACITANCE90

100 1 k 10 k 100 k

CL – Load Capacitance – pF

50 kΩ

50 kΩ

VDD –

VDD +Rnull

CLVI

+–

Figure 29

Rnull = 50 ΩRnull = 20 Ω

Rnull = 0

TA 25°C

15

10

5

010

Gai

n M

argi

n –

dB

20

25

GAIN MARGINvs

LOAD CAPACITANCE30

100 1 k 10 k 100 kCL – Load Capacitance – pF

Figure 30


115

110

105

100–50 –25 0 25 50

PS

RR

– P

ower

Sup

ply

Rej

ectio

n R

atio

– d

B

120

125

POWER SUPPLY REJECTION RATIOvs


75 100 125

VDD = 4 V To 6 VVIC = VO = VDD/2

Figure 31

–1

–1.5

–2

–30 100 200 300 400 500 600

–0.5

0

t – Time – ms

CALIBRATION TIME AT –40 °C0.5

700 800 900 1000

–2.5

– O

utpu

t Vol

tage

– V

VO VDD = 2.5 V

GND = –2.5 VRL = 1 kΩ to GNDAV = –1VI = 0





Figure 32

–1

–1.5

–2

–30 100 200 300 400 500 600

–0.5

0

t – Time – ms

CALIBRATION TIME AT 25 °C0.5

700 800 900 1000

– O

utpu

t Vol

tage

– V

VO

–2.5

VDD = 2.5 VGND = –2.5 VRL = 1 kΩ to GNDAV = –1VI = 0

Figure 33


–1

–1.5

–2

–30 100 200 300 400 500 600

–0.5

0

t – Time – ms


700 800 900 1000

–2.5

– O

utpu

t Vol

tage

– V

VO


–1

–1.5

–2

–30 100 200 300 400 500 600

–0.5

0

t – Time – ms


700 800 900 1000

–2.5

– O

utpu

t Vol

tage

– V

VO

Figure 34



APPLICATION INFORMATION

The TLC4502 is designed to operate with only a single 5-V power supply, have true differential inputs, andremain in the linear mode with an input common-mode voltage of 0.

The TLC4502 has a standard dual-amplifier pinout, allowing for easy design upgrades.

Large differential input voltages can be easily accommodated and, as input differential-voltage protectiondiodes are not needed, no large input currents result from large differential input voltage. Protection shouldbe provided to prevent the input voltages from going negative more than –0.3 V at 25°C. An input clampdiode with a resistor to the device input terminal can be used for this purpose.

For ac applications, where the load is capacitively coupled to the output of the amplifier, a resistor can beused from the output of the amplifier to ground. This increases the class-A bias current and preventscrossover distortion. Where the load is directly coupled, for example in dc applications, there is no crossoverdistortion.

Capacitive loads, which are applied directly to the output of the amplifier, reduce the loop stability margin.Values of 500 pF can be accommodated using the worst-case noninverting unity-gain connection. Resistiveisolation should be considered when larger load capacitance must be driven by the amplifier.

The following typical application circuits emphasize operation on only a single power supply. Whencomplementary power supplies are available, the TLC4502 can be used in all of the standard operationalamplifier circuits. In general, introducing a pseudo-ground (a bias voltage of VI/2 like that generated by theTLE2426) allows operation above and below this value in a single-supply system. Many application circuitsshown take advantage of the wide common-mode input-voltage range of the TLC4502, which includes ground.In most cases, input biasing is not required and input voltages that range to ground can easily beaccommodated.

description of calibration procedure

To achieve high dc gain, large bandwidth, high CMRR and PSRR, as well as good output drive capability, theTLC4502 is built around a 3-stage topology: two gain stages, one rail-to-rail, and a class-AB output stage. Anested Miller topology is used for frequency compensation.

During the calibration procedure, the operational amplifier is removed from the signal path and both inputs aretied to GND. Figure 35 shows a block diagram of the amplifier during cabilbration mode.




POWER-ON RESET S

R

Q

Q

ENABLE

RCOSCILLATOR

COUNTER

RCO

CLOCK CAL

RESETSAR

RCO

DAC

LPF

VDD

COREAMPLIFIER

+

–

Figure 35. Block Diagram During Calibration Mode

The class AB output stage features rail-to-rail voltage swing and incorporates additional switches to put theoutput node into a high-impedance mode during the calibration cycle. Small-replica output transistors (matchedto the main output transistors) provide the amplifier output signal for the calibration circuit. The TLC4502 alsofeatures built-in output short-circuit protection. The output current flowing through the main output transistorsis continuously being sensed. If the current through either of these transistors exceeds the preset limit (60 mA– 70 mA) for more than about 1 µs, the output transistors are shut down to approximately their quiescentoperating point for approximately 5 ms. The device is then returned to normal operation. If the short circuit isstill in place, it is detected in less than 1 µs and the device is shut down for another 5 ms.

The offset cancellation uses a current-mode digital-to-analog converter (DAC), whose full-scale current allowsfor an adjustment of approximately ±5 mV to the input offset voltage. The digital code producing the cancellationcurrent is stored in the successive-approximation register (SAR).

During power up, when the offset cancellation procedure is initiated, an on-chip RC oscillator is activated toprovide the timing of the successive-approximation algorithm. To prevent wide-band noise from interfering withthe calibration procedure, an analog low-pass filter followed by a Schmidt trigger is used in the decision chainto implement an averaging process. Once the calibration procedure is complete, the RC oscillator is deactivatedto reduce supply current and the associated noise.




The key operational-amplifier parameters CMRR, PSRR, and offset drift were optimized to achieve superioroffset performance. The TLC4502 calibration DAC is implemented by a binary-weighted current array using apseudo-R-2R MOSFET ladder architecture, which minimizes the silicon area required for the calibrationcircuitry, and thereby reduces the cost of the TLC4502.

Due to the performance (precision, PSRR, CMRR, gain, output drive, and ac performance) of the TLC4502, itis ideal for applications like:

Data acquisition systems Medical equipment Portable digital scales Strain gauges Automotive sensors Digital audio circuits Industrial control applications

It is also ideal in circuits like:

A precision buffer for current-to-voltage converters, a/d buffers, or bridge applications High-impedance buffers or preamplifiers Long term integration Sample-and-hold circuits Peak detectors

The TLC4502 self-calibrating operational amplifier is manufactured using Texas instruments LinEPIC processtechnology and is available in an 8-pin SOIC (D) Package. The C-suffix devices are characterized for operationfrom 0°C to 70°C. The I-suffix devices are characterized for operation from –40°C to 125°C.The M-suffix devicesare characterized for operation from –55°C to 125°C.





1/2TLC4502

+

–

R1

90 kΩ

R2

9 kΩ

R3

1 kΩ

R4

1 kΩ

R5

9 kΩ

R6

90 kΩ

1/2TLC4502

+

–

VDD

80.1 pF

VO+VO–RP

1 kΩ

VDD

RP

1 kΩ

VI2

VI1

Gain = 10Gain = 10 Gain = 100Gain = 100

V(REF)+

V(REF)–

2

3 5

6

4

71

(Gain 10) VO VI1 VI21 R6

R4 R5 V(REF) Where R1 R6, R2 R5, and R3 R4

(Gain 100) VO VI1 VI21 R5 R6

R4 V(REF) Where R1 R6, R2 R5, and R3 R4

Figure 36. Single-Supply Programmable Instrumentation Amplifier Circuit

1/2TLC4502

–

+

R1

1/2TLC4502

–

+ VO

RP1 < 1 kΩ

VI

V(REF)

3

2

6

5

4

7

1

VO VI1 R4R32R4

RG V(REF)

RP2 < 1 kΩ

R3

R2

RG

R4

Where : R1 R4 and R2 R3

Figure 37. Two Operational-Amplifier Instrumentation Amplifier Circuit




VI

V(REF)

VO VIR5R32R1

RG 1 V(REF)

RG

Where : R1 R2, R3 R4, and R5 R6

1/2TLC4502

–

+3

21

1/2TLC4502

+

–2

31

1/2TLC4502

+

–

5

6

7

R1

R2

R3

R4

R5

VO

R6

Figure 38. Three Operational-Amplifier Instrumentation Amplifier Circuit

1/2TLC4502

+

–2

3

1

I1

R1

R2R5

R4

R3

I2

VI

Figure 39. Fixed Current-Source Circuit





1/2TLC4502

+

–2

3

1

VI

VO

VI VO

Figure 40. Voltage-Follower Circuit

1/2TLC4502

+

–2

31

600 mA

VI

100 Ω

β ≥ 2030 mA

Figure 41. Lamp-Driver Circuit

1/2TLC4502

+

–2

3

1

RL240 Ω

Figure 42. TTL-Driver Circuit




1/2TLC4502

–

+3

2

1

IO

VI

REIO

VIRE

Figure 43. High-Compliance Current-Sink Circuit

1/2TLC4502

+

–2

3

1VOR1

10 kΩ

R210 MΩ

V(REF)

VI

Figure 44. Comparator With Hysteresis Circuit

1/2TLC4502

+

–

1/2TLC4502

+

– VO

VI

2

3

5

6

7

1

C11 µF

ZO

ZI

IB

IB

Figure 45. Low-Drift Detector Circuit




APPLICATION INFORMATIONmacromodel information

Macromodel information provided was derived using Microsim Parts Release 8, the model generationsoftware used with Microsim PSpice . The Boyle macromodel (see Note 4) and subcircuit in Figure 46 aregenerated using the TLC4501 typical electrical and operating characteristics at TA = 25°C. Using thisinformation, output simulations of the following key parameters can be generated to a tolerance of 20% (in mostcases):

Maximum positive output voltage swing Maximum negative output voltage swing Slew rate Quiescent power dissipation Input bias current Open-loop voltage amplification

Unity-gain frequency Common-mode rejection ratio Phase margin DC output resistance AC output resistance Short-circuit output current limit

NOTE 4: G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Intergrated Circuit Operational Amplifiers”, IEEEJournal of Solid-State Circuits, SC-9, 353 (1974).

+

–

+

–

+

–

+

– +

–

.subckt TLC4501 1 2 3 4 5*

c1 11 12 1.4559E–12 c2 6 7 8.0000E–12 css 10 99 1.0000E–30 dc 5 53 dy de 54 5 dy dlp 90 91 dx dln 92 90 dx dp 4 3 dx egnd 99 0 poly(2) (3,0) (4,0) 0 .5 .5 fb 7 99 poly(5) vb vc ve vlp vln 0

+ 84.657E9 –1E3 1E3 85E9 –85E9 ga 6 0 11 12 236.25E–6 gcm 0 6 10 99 2.3625E–9 iss 10 4 dc 20.000E–6 hlim 90 0 vlim 1K j1 11 2 10 jx1 j2 12 1 10 jx2

r2 6 9 100.00E3 rd1 3 11 4.2328E3 rd2 3 12 4.2328E3 ro1 8 5 5.0000E–3 ro2 7 99 5.0000E–3 rp 3 4 5.0000E3 rss 10 99 10.000E6 vb 9 0 dc 0 vc 3 53 dc .92918 ve 54 4 dc .82918 vlim 7 8 dc 0 vlp 91 0 dc 67 vln 0 92 dc 67

.model dx D(Is=800.00E–18)

.model dy D(Is=800.00E–18 Rs=1m Cjo=10p)

.model jx1 NJF(Is=500.00E–15 Beta=2.7907E–3 Vto=–1)

.model jx2 NJF(Is=500.00E–15 Beta=2.7907E–3 Vto=–1)

.ends

VDD+

RP

IN –2

IN+1

VDD–

RD1

11

J1 J2

10

RSSISS

3

12

RD2DP

VD

DC

4

C1

53

EGNDFB

HLIM

90

DLP

91

DLN

92

VLNVLP

99

CSS

+

–VE

DE

54

OUT

+

–+

–

R2 6

9

VB

C2

GA

VLIM

8

5

RO1

RO2

7

GCM

Figure 46. Boyle Macromodel and Subcircuit

PSpice and Parts are trademarks of MicroSim Corporation.



MECHANICAL INFORMATIOND (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE14 PIN SHOWN

4040047/D 10/96

0.228 (5,80)0.244 (6,20)

0.069 (1,75) MAX0.010 (0,25)0.004 (0,10)

1

14

0.014 (0,35)0.020 (0,51)

A

0.157 (4,00)0.150 (3,81)

7

8

0.044 (1,12)0.016 (0,40)

Seating Plane

0.010 (0,25)

PINS **

0.008 (0,20) NOM

A MIN

A MAX

DIM

Gage Plane

0.189(4,80)

(5,00)0.197

8

(8,55)

(8,75)

0.337

14

0.344

(9,80)

16

0.394(10,00)

0.386

0.004 (0,10)

M0.010 (0,25)

0.050 (1,27)

0°–8°

NOTES: A. All linear dimensions are in inches (millimeters).B. This drawing is subject to change without notice.C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).D. Falls within JEDEC MS-012




MECHANICAL INFORMATIONFK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER

4040140/D 10/96

28 TERMINAL SHOWN

B

0.358(9,09)

MAX

(11,63)

0.560(14,22)

0.560

0.458

0.858(21,8)

1.063(27,0)

(14,22)

ANO. OF

MINMAX

0.358

0.660

0.761

0.458

0.342(8,69)

MIN

(11,23)

(16,26)0.640

0.739

0.442

(9,09)

(11,63)

(16,76)

0.962

1.165

(23,83)0.938

(28,99)1.141

(24,43)

(29,59)

(19,32)(18,78)

**

20

28

52

44

68

84

0.020 (0,51)

TERMINALS

0.080 (2,03)0.064 (1,63)

(7,80)0.307

(10,31)0.406

(12,58)0.495

(12,58)0.495

(21,6)0.850

(26,6)1.047

0.045 (1,14)

0.045 (1,14)0.035 (0,89)

0.035 (0,89)

0.010 (0,25)

121314151618 17

11

10

8

9

7

5

432

0.020 (0,51)0.010 (0,25)

6

12826 27

19

21B SQ

A SQ22

23

24

25

20

0.055 (1,40)0.045 (1,14)

0.028 (0,71)0.022 (0,54)

0.050 (1,27)

NOTES: A. All linear dimensions are in inches (millimeters).B. This drawing is subject to change without notice.C. This package can be hermetically sealed with a metal lid.D. The terminals are gold plated.E. Falls within JEDEC MS-004



MECHANICAL INFORMATIONJG (R-GDIP-T8) CERAMIC DUAL-IN-LINE PACKAGE

0.310 (7,87)0.290 (7,37)

0.014 (0,36)0.008 (0,20)

Seating Plane

4040107/C 08/96

5

40.065 (1,65)0.045 (1,14)

8

1

0.020 (0,51) MIN

0.400 (10,20)0.355 (9,00)

0.015 (0,38)0.023 (0,58)

0.063 (1,60)0.015 (0,38)

0.200 (5,08) MAX

0.130 (3,30) MIN

0.245 (6,22)0.280 (7,11)

0.100 (2,54)

0°–15°

NOTES: A. All linear dimensions are in inches (millimeters).B. This drawing is subject to change without notice.C. This package can be hermetically sealed with a ceramic lid using glass frit.D. Index point is provided on cap for terminal identification only on press ceramic glass frit seal only.E. Falls within MIL-STD-1835 GDIP1-T8




MECHANICAL INFORMATIONU (S-GDFP-F10) CERAMIC DUAL FLATPACK

4040179/B 03/95

1.000 (25,40)

0.080 (2,03)

0.250 (6,35)

0.250 (6,35)

0.019 (0,48)

0.025 (0,64)

0.300 (7,62)

0.045 (1,14)

0.006 (0,15)

0.050 (1,27)

0.015 (0,38)

0.005 (0,13)

0.026 (0,66)

0.004 (0,10)

0.246 (6,10)

0.750 (19,05)

1 10

5 6

0.250 (6,35)0.350 (8,89)0.350 (8,89)

0.250 (6,35)

0.050 (1,27)

NOTES: A. All linear dimensions are in inches (millimeters).B. This drawing is subject to change without notice.C. This package can be hermetically sealed with a ceramic lid using glass frit.D. Index point is provided on cap for terminal identification only.E. Falls within MIL STD 1835 GDFP1-F10 and JEDEC MO-092AA

IMPORTANT NOTICE

Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinueany product or service without notice, and advise customers to obtain the latest version of relevant informationto verify, before placing orders, that information being relied on is current and complete. All products are soldsubject to the terms and conditions of sale supplied at the time of order acknowledgement, including thosepertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale inaccordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extentTI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarilyperformed, except those mandated by government requirements.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OFDEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICALAPPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, ORWARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHERCRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TOBE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operatingsafeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or representthat any license, either express or implied, is granted under any patent right, copyright, mask work right, or otherintellectual property right of TI covering or relating to any combination, machine, or process in which suchsemiconductor products or services might be or are used. TI’s publication of information regarding any thirdparty’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

Copyright 1999, Texas Instruments Incorporated

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