TM1100 Data Book Foreword Table of Contents 1 Pin List 2 Overview 3 DSPCPU Architecture 4 Custom Operations for Multimedia 5 Cache Architecture 6 Video In 7 Enhanced Video Out for TM1100 8 Audio In 9 Audio Out 10 PCI Interface 11 SDRAM Memory System 12 System Boot 13 Image Co Processor 14 Variable Length Decoder 15 I 2 C Interface 16 Synchronous Serial Interface 17 JTAG Functional Specification 18 On-Chip Semaphore Assist Device 19 Arbiter 20 Power Management 21 PCI-XIO Bus Functional Specification A DSPCPU Operations for TM1000 B MMIO Register Summary C Endian-ness Index PRELIMINARY INFORMATION Title Page 1999 Philips Electronics North America Corporation All rights reserved. See Terms and Conditions on the next page. July 1999 Third Draft
Transcript
TM1100 Data Book
Foreword
Table of Contents
1 Pin List
2 Overview
3 DSPCPU Architecture
4 Custom Operations for Multimedia
5 Cache Architecture
6 Video In
7 Enhanced Video Out for TM1100
8 Audio In
9 Audio Out
10 PCI Interface
11 SDRAM Memory System
12 System Boot
13 Image Co Processor
14 Variable Length Decoder
15 I
2
C Interface
16 Synchronous Serial Interface
17 JTAG Functional Specification
18 On-Chip Semaphore Assist Device
19 Arbiter
20 Power Management
21 PCI-XIO Bus Functional Specification
A DSPCPU Operations for TM1000
B MMIO Register Summary
C Endian-ness
Index
PRELIMINARY INFORMATION
Title Page
1999 Philips Electronics North America CorporationAll rights reserved.
See Terms and Conditions on the next page.
July 1999 Third Draft
TERMS AND CONDITIONS
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes,without notice, in the products, including circuits, standard cells, and/or software, described or containedherein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility orliability for the use of any of these products, conveys no license or title under any patent, copyright, or mostwork right to these products, and makes no representations or warranties that these products are free frompatent, copyright, or most work right infringement, unless otherwise specified. Applications that are describedherein for any of these products are for illustrative purposes only. Philips Semiconductors makes norepresentation or warranty that such applications will be suitable for the specified use without further testingor modification.
LIFE SUPPORT APPLICATIONS
Philips Semiconductors and Philips Electronics North America Corporation products are not designed for usein life support appliances, devices, or systems where malfunction of a Philips Semiconductors and PhilipsElectronics North America Corporation product can reasonably be expected to result in a personal injury.Philips Semiconductors and Philips Electronics North America Corporation customers using or selling PhilipsSemiconductors and Philips Electronics North America Corporation products for use in such applications doso at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North AmericaCorporation for any damages resulting from improper use or sale.
Philips Semiconductors and Philips Electronics North America Corporation register eligible circuits under theSemiconductor Chips Protection Act.
1999 Philips Electronics North America Corporation, 1999
All rights reserved.
Printed in U.S.A.
TriMedia Product Group, 811 E. Arques Avenue, Sunnyvale, CA 94088
DEFINITIONS
Data Sheet Identification Product Status Definition
Objective Specification
Formative or in Design
This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice.
Preliminary Specification
Preproduction Product
This data sheet contains preliminary data, and supplementary data will be pub-lished at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Product Specification
Full Production
This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve the design and supply the best possible product.
Terms and Conditions
Foreword
The TriMedia TM1100 is a higher speed, functionallyenhanced version of the TM1000 media processor.
TM1100 contains an ultra-high performance Very LongInstruction Word processor, as well as a complete intelli-gent video and audio input/output subsystem. The pro-cessor has an instruction set that is optimized for pro-cessing audio, video and graphics. It includes powerfulSIMD multimedia operators for eight- and 16-bit signaldatatypes as well as a full complement of 32-bit IEEEcompatible floating point operations.
TM1100 is intended as a multi-standard programmablevideo, audio and graphics processor. It can either beused standalone, or as an accelerator to a general pur-pose processor.
The architecture of the TriMedia family came about asthe result of many years of effort of many dedicated indi-viduals. Going back in history, the origin of TriMedia waslaid by the LIFE-1 VLIW processor, designed by JunienLabrousse and myself in 1987. Work continued after-wards in Philips Research Labs, Palo Alto. My specialthanks go to the entire Palo Alto research team: MikeAng, Uzi Bar-Gadda, Peter Donovan, Martin Freeman,Eino Jacobs, Beomsup Kim, Bob Law, Yen Lee, VijayMehra, Pieter van der Meulen, Ross Morley, MarietteParekh, Bill Sommer, Artur Sorkin and Pierre Uszynski.
The Palo Alto period matured the architecture—we port-ed all video and audio algorithms that we could find to thecompiler/simulator and refined the operation set. In addi-tion, we learned how to give the architecture a market di-rection. In May 1994, Philips management—in particularCees-Jan Koomen, Eddy Odijk, Theo Claasen and DougDunn—decided to develop TriMedia into a major PhilipsSemiconductors product line.
Under the guidance of Keith Flagler, the TriMedia teamwas built. All of them contributed to take this from a setof interesting ideas to a reliable and competitive productin a short period of time. The initial TriMedia team includ-ed Fuad Abu Nofal, Karel Allen, Mike Ang, Robert Aqui-no, Manju Asthana, Patrick de Bakker, Shiv Balakrish-nan, Jai Bannur, Marc Berger, Sunil Bhandari, RustyBiesele, Ahmet Bindal, David Blakely, Hans Bouw-meester, Steve Bowden, Robert Bradfield, NancyBreede, Shawn Brown, Sujay Chari, Catherine Chen,
Howen Chen, Yan-ming Chen, Yong Cho, Scott Clapper,Matthew Clayson, Paul Coelho, Richard Dodds, MarcDuranton, Darcia Eding, Aaron Emigh, Li Chi Feng, KeithFlagler, Jean Gobert, Sergio Golombek, Mike Grim-wood, Yudi Halim, Hari Hampapuram, Carl Hartshorn,Judy Heider, Laura Hrenko, Jim Hsu, Eino Jacobs, Mar-cel Janssens, Patricia Jones, Hann-Hwan Ju, Jayne Kei-th, Bhushan Kerur, Ayub Khan, Keith Knowles, MikeKong, Ashok Krishnamurti, Yen Lee, Patrick Leong, BillLin, Laura Ling, Chialun Lu, Naeem Maan, Nahid Man-sipur, Mike Maynard, Vijay Mehra, Jun Mejia, DerekMeyer, Prabir Mohanty, Saed Muhssin, Chris Nelson,Stephen Ness, Keith Ngo, Francis Nguyen, KathleenNguyen, Derek Noonburg, Ciaran O’Donnel, Sang-JuPark, Charles Peplinski, Gene Pinkston, Maryam Piray-ou, Pardha Potana, Bill Price, Victor Ramamoorthy,Babu Rao Kandamilla, Ehsan Rashid, Selliah Rathnam,Margaret Redmond, Donna Richardson, Alan Rodgers,Tilakray Roychoudhury, Hani Salloum, Chris Salzmann,Bob Seltzer, Ravi Selvaraj, Jim Shimandle, DeepakSingh, Bill Sommer, Juul van der Spek, Manoj Srivasta-va, Renga Sundararajan, Ken-Sue Tan, Ray Ton, SteveTran, Cynthia Tripp, Ching-Yih Tseng, Allan Tzeng, Bar-bara Vendelin, John Vivit, Rudy Wang, Rogier Wester,Wayne Wonchoba, Anthony Wong, Sara Wu, David Wy-land, Ken Xie, Vincent Xie, Bettina Yeung, Robert Yin,Charles Young, Grace Yun, Elena Zelayeta and VivianZhu.
Expert help and feedback was received from many. Inparticular, I’d like to mention Kees van Zon of PhilipsEindhoven for the help with filtering-related issues, andCraig Clapp of PictureTel for excellent feedback on allaspects of the architecture.
My special thanks go to Joe Kostelec. He made me un-derstand that my ambitions could better be realized inCalifornia than in Europe. Furthermore, his vision and hiswisdom are credited with keeping this project alive andgrowing until the ‘investment decision.’
The vision of a universal media accelerator is credited toJaap de Hoog. Jaap, I wish you were here to see it cometo fruition.
–Gerrit Slavenburg
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Pin List Chapter 1
by Fuad Abunofal, Naeem Maan, Gert Slavenburg
1.1 TM1100 VERSUS TM1000
TM1100 is 100% upwards pinout compatible with TM1000. TM1100 is usable at 100 MHz SDRAM speed in anyTM1000 board design. For new 133 MHz SDRAM speed designs, a change in the use of MATCHOUT-MATCHIN isrecommended. See Section 1.10.3.1. Furthermore, board series terminator resistors as close as possible to theTM1100 are recommended for the outputs MM_CLK0, MM_CLK1, VO_CLK, AI_OSCLK, AI_SCK, AO_OSCLK andAO_SCK.
1.2 BOUNDARY SCAN NOTICE
TM1100 implements full IEEE 1149.1 boundary scan. Any TM1100 pin designated “IN” only (from functionality point ofview), can become an output during boundary scan.
1.3 DOCUMENT STATUS
This chapter has been updated to reflect tm1100-1.5 silicon.
1.4 I/O CIRCUIT SUMMARY
TM1100 has a total of 163 functional pins, not counting VDDQ, VSSQ, VREF_PCI and VREF_PERIPH and digital pow-er/ground. TM1100 pins use 1 of the 6 electrical I/O types below.
For the pins with 5 Volt input tolerance capability, the special pins VREF_PCI or VREF_PERIPH determine 3.3 or 5Volt mode, as per the table in Section 1.7.
The above I/O types are used in the modes listed in the following table.
Pad Type Pad Type Description
PCI PCI2.1 compliant I/O, capable of using 3.3V or 5V PCI signalling conventions.
PCIOD PCI2.1 compliant Open Drain I/O, capable of using 3.3V or 5V PCI signalling conventions.
STRG3 3.3-Volt only low impedance I/O. Requires board level series terminator resistor to match PCB trace.
NORM3 3.3-Volt only I/O circuit with normal drive strength and board trace matched drive impedance.
NORM5 5-Volt tolerant I/O circuit with normal drive strength and board trace matched drive impedance.
IICOD Open drain 3.3 or 5 Volt capable I/O for I2C bus.
Modes Description
IN Input only, except during boundary scan
OUT Output only, except during boundary scan
OD Open Drain Output - active pull low, no active drive high, requires external pullup
I/O Output or input
I/OD Open drain output or input - active pull low, no active drive high, requires external pullup
PWR Always connected to a supply source
GND Always connected to ground
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1.5 SIGNAL PIN LIST
In the table below, a pin name ending in a ‘#’ designates an active-low signal (the active state of the signal is a lowvoltage level). All other signals have active-high polarity.
Pin NameMSQFP
PadType Modes Description
Main Clock Interface
TRI_CLKIN 143 STRG3 IN Main Input Clock. The SDRAM clock outputs (MM_CLK0 and MM_CLK1) can be set to 2x or 3x this frequency. The on-chip DSPCPU clock (DSPCPU_CLK) can be set to 1x, 5/4, 4/3, 3/2 or 2x the SDRAM clock frequency.
VDDQ 142 N/A PWR Quiet VDD for the PLL subsystem.
VSSQ 144 N/A GND Quiet VSS for the PLL subsystem.
Miscellaneous System Interface
TRI_RESET# 209 PCI IN TM1100 RESET input. This pin can be tied to the PCI RST# signal in PCI bus systems. Upon receiving RESET, TM1100 initiates its boot protocol.
BOOT_CLK 146 STRG3 IN Used for testing purposes. Must be connected to TRI_CLKIN for normal operation.
RESERVED1 145 STRG3 IN Reserved input. Has to be connected to VDDQ for proper operation.
VREF_PCI 240 N/A PWR VREF_PCI must be connected to 5V for use in a 5 Volt PCI signalling environment or to VSS (0 Volt) for use in 3.3 Volt PCI signalling environment. The supply to this pin should be AC bypassed and provide 40 mA of DC sink or source capability. Note that this pin can not be directly connected to the PCI ‘I/O designated power pins’ in a dual voltage PCI plug-in card. Board level conversion circuitry is required. Refer to Section 1.7 for the pins whose operation is affected by VREF_PCI.
VREF_PERIPH 184 N/A PWR VREF_PERIPH should be connected to 5V if any of the (non-PCI) inputs provided to TM1100 are 5 Volt inputs. VREF_PERIPH should be connected to VSS (0 Volt) if all input signals, with the possible exception of PCI signals are 3.3 Volt inputs. The supply to this pin should be AC bypassed and provide 40 mA of DC sink or source capability. Refer to Section 1.7 for the pins whose operation is affected by VREF_PERIPH.
TRI_USERIRQ 147 PCI IN General purpose level/edge interrupt input. Vectored interrupt source number 4.
TRI_TIMER_CLK 141 PCI IN External general purpose clock source for timers. Max 40 MHz.
Main Memory Interface
MM_CLK0MM_CLK1
8683
STRG3 OUT SDRAM Output Clock at 2x or 3x TRI_CLKIN frequency. Two identical outputs are pro-vided to reliably drive several small memory configurations without external glue.A series terminating resistor close to TM1100 is recommended to reduce ringing.For driving a 50 Ohm trace, a resistor of 15 to 22 Ohm is recommended. For a higher impedance trace, adjust accordingly.
MM_MATCHOUT 89 STRG3 OUT Phase match clock output. This output can be used to construct an optimally sampling MM_MATCHIN. For normal usage, tie directly to MM_MATCHIN with a minimal length PCB trace.
MM_MATCHIN 92 NORM3 IN Phase match clock input. Refer to MM_MATCHOUT above.
NORM3 OUT Clock enable output to SDRAMs. Two identical outputs are provided in order to reliably drive several small memory configurations without external glue.
MM_CS0#MM_CS1#MM_CS2#MM_CS3#
4713648
133
NORM3 OUT Chip select for DRAM rank n; active low
MM_RAS# 102 NORM3 OUT Row address strobe; active low
MM_CAS# 104 NORM3 OUT Column address strobe; active low
MM_WE# 105 NORM3 OUT Write enable; active low
MM_DQM0MM_DQM1MM_DQM2MM_DQM3
1381195062
NORM3 OUT MM_DQ Mask Enable; these are byte enable signals for the 32-bit MM_DQ bus
PCI Interface (note: buffer design allows drive/receive from either 3.3 or 5V PCI bus)
PCI_CLK 39 PCI IN All PCI input signals are sampled with respect to the rising edge of this clock. All PCI outputs are generated based on this clock
Pin NameMSQFP
PadType Modes Description
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PCI_SERR# 14 PCIOD OD System Error. This signal is asserted when operating as target and detecting an address parity error.
Pin NameMSQFP
PadType Modes Description
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PCI_INTA#PCI_INTB#PCI_INTC#PCI_INTD#
210212213215
PCIODPCI
PCIODPCIOD
I/OD • Can operate as input (power up default) or output, as determined by direction con-trol bits in PCI MMIO register INT_CTL.
• As input, a PCI_INT# pin can be used to receive PCI interrupt requests (normal PCI use is active low, level sensitive mode, but the VIC can be set to treat these as pos-itive edge triggered mode). As input, a PCI_INT# pin can also be used as general interrupt request pin if not needed for PCI.
• As output, the value of a PCI_INT# can be programmed through PCI MMIO regis-ters to generate interrupts for other PCI masters.
• Whenever XIO bus functionality is active, PCI_INTB# is a push-pull CMOS I/O pin, but when the XIO bus is not active and regular PCI bus functionality is activated, then PCI_INTB# has a PCI compatible Open Drain output.
JTAG Interface (debug access port and 1149.1 boundary scan port)
JTAG_TDI 171 NORM5 IN JTAG Test Data Input
JTAG_TDO 173 NORM5 I/O JTAG Test Data Output. This pin acts as logic output, or can float. It is never an input.
JTAG_TCK 172 NORM5 IN JTAG Test Clock Input
JTAG_TMS 174 NORM5 IN JTAG Test Mode Select Input
Video In
VI_CLK 175 PCI I/O • If configured as input (power up default): A positive transition on this incoming video clock pin samples all other VI_DATA input signals below if VI_DVALID is HIGH. If VI_DVALID is LOW, VI_DATA is ignored. Clock and data rates of up to 54 MHz are supported.
• If configured as output: Programmable output clock to drive an external video A/D converter. Can be programmed to emit integral dividers of DSPCPU_CLK.
If used as output, a board level 22 Ohm series resistor is recommended to reduce ring-ing.
VI_DVALID 190 PCI IN VI_DVALID indicates that valid data is present on the VI_DATA lines. If HIGH, VI_DATA will be accepted on the next VI_CLK positive edge. If LOW, no VI_DATA will be sam-pled.
PCI IN CCIR656 style YUV 4:2:2 data from a digital camera, or general purpose high speed data input pins. Sampled on VI_CLK if VI_DVALID HIGH.
VI_DATA8VI_DATA9
187189
PCI IN Extension high speed data input bits to allow use of 10 bit video A/D converters in raw10 modes. VI_DATA[8] serves as START and VI_DATA[9] as END message input in message passing mode.Sampled on positive transitions of VI_CLK if VI_DVALID HIGH.
NORM3 OUT CCIR656 style YUV 4:2:2 digital output data, or general purpose high speed data out-put channel. Output changes on positive edge of VO_CLK.
VO_IO1 204 NORM5 I/O This pin can function as HS output or as STMSG (Start Message) output.• If set as HS output, it outputs the horizontal sync signal• In message passing mode, this pin acts as STMSG output.
Pin NameMSQFP
PadType Modes Description
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VO_IO2 206 NORM5 I/O This pin can function as FS (Frame Sync) input, FS output or as ENDMSG output.• If set as FS input, it can be set to respond to positive or negative edge transitions.• If the Video Out operates in external sync mode and the selected transition occurs,
the Video Out sends two fields of video data. Note: this works only once after a reset. • In message passing mode, this pin acts as ENDMSG output.
VO_CLK 203 PCI I/O The Video Out unit emits VO_DATA on a positive edge of VO_CLK. VO_CLK can be configured as input (reset default) or output.• If configured as input: VO_CLK is received from external display clock master cir-
cuitry. • If configured as output, TM1100 emits a programmable clock frequency. The emitted
frequency can be set between approx. 4MHz and 80 MHz with a resolution of 0.07 Hz. The clock generated is frequency accurate and has low jitter properties due to a combination of an on-chip DDS (Direct Digital Synthesizer) and VCO/PLL.
If used as output, a board level 22 Ohm series resistor is recommended to reduce ring-ing.
Audio In (always acts as receiver, but can be master or slave for A/D timing)
AI_OSCLK 153 STRG3 OUT Over-Sampling Clock. This output can be programmed to emit any frequency up to 40-MHz with a resolution of 0.07-Hz. It is intended for use as the 256fs or 384fs over sam-pling clock by external A/D subsystem. A board level 22 Ohm series resistor is recom-mended to reduce ringing.
AI_SCK 152 PCI I/O • When Audio-In is programmed as serial-interface timing slave (power-up default), AI_SCK is an input. AI_SCK receives the serial bit clock from the external A/D sub-system. This clock is treated as fully asynchronous to TM1100 main clock.
• When Audio In is programmed as the serial-interface timing master, AI_SCK is an output. AI_SCK drives the serial clock for the external A/D subsystem. The fre-quency is a programmable integral divide of the AI_OSCLK frequency.
AI_SCK is limited to 20 MHz. The sample rate of valid samples embedded within the serial stream is limited by the bandwidth.latency available in the system (Section 8-7 on page 8-7). If used as output, a board level 22 Ohm series resistor is recommended to reduce ringing.
AI_SD 149 PCI IN Serial Data from external A/D subsystem. Data on this pin is sampled on positive or negative edges of AI_SCK as determined by the CLOCK_EDGE bit in the AI_SERIAL register.
AI_WS 150 NORM5 I/O • When Audio In is programmed as the serial-interface timing slave (power-up default), AI_WS acts as an input. AI_WS is sampled on the same edge as selected for AI_SD.
• When Audio In is programmed as the serial-interface timing master, AI_WS acts as an output. It is asserted on the opposite edge of the AI_SD sampling edge.
AI_WS is the word-select or frame-synchronization signal from/to the external A/D sub-system.
Pin NameMSQFP
PadType Modes Description
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Audio Out (always acts as sender, but can be master or slave for D/A timing)
AO_OSCLK 156 STRG3 OUT Over Sampling Clock. This output can be programmed to emit any frequency up to 40 MHz, with a resolution of 0.07 Hz. It is intended for use as the 256 or 384fs over sam-pling clock by the external D/A conversion subsystem. A board level 22 Ohm series resistor is recommended to reduce ringing.
AO_SCK 158 PCI I/O • When Audio Out is programmed to act as the serial interface timing slave (power up default), AO_SCK acts as input. It receives the Serial Clock from the external audio D/A subsystem. The clock is treated as fully asynchronous to the TM1100 main clock.
• When Audio Out is programmed to act as serial interface timing master, AO_SCK acts as output. It drives the Serial Clock for the external audio D/A subsystem. The clock frequency is a programmable integral divide of the AO_OSCLK frequency.
AO_SCK is limited to 20 MHz. The sample rate of valid samples embedded within the serial stream is limited by the bandwidth.latency available in the system (Section 9-10 on page 9-8). If used as output, a board level 22 Ohm series resistor is recommended to reduce ringing.
AO_SD 159 NORM3 OUT Serial Data to external audio D/A subsystem. The timing of transitions on this output is determined by the CLOCK_EDGE bit in the AO_SERIAL register, and can be on posi-tive or negative AO_SCK edges.
AO_WS 155 NORM5 I/O • When Audio-Out is programmed as the serial-interface timing slave (power-up default), AO_WS acts as an input. AO_WS is sampled on the opposite AO_SCK edge at which AO_SD is asserted.
• When Audio Out is programmed as serial-interface timing master, AO_WS acts as an output. AO_WS is asserted on the same AO_SCK edge as AO_SD.
AO_WS is the word-select or frame-synchronization signal from/to the external D/A subsystem. Each audio channel receives 1 sample for every WS period.
Synchronous Serial Interface (SSI) to an off-chip modem front-end)
SSI_CLK 162 PCI IN Clock signal of the synchronous serial interface to an off-chip modem analog frontend or ISDN terminal adapter. Provided by the receive channel of an external communica-tion device.
SSI_RXFSX 164 PCI IN Receive Frame Sync reference of the synchronous serial interface, provided by the receive channel of an external communication device.
SSI_RXDATA 165 PCI IN Receive Serial Data input. Provided by the receive channel of an external communica-tion device.
SSI_TXDATA 167 NORM3 OUT Transmit Serial Data output. Sent to the transmit channel of the external communica-tion device.
SSI_IO1 168 NORM5 I/O General purpose programmable I/O. Set to input on power up.
SSI_IO2 170 NORM5 I/O General purpose programmable I/O. Set to input on power up. Can also be pro-grammed to function as the transmit channel frame synchronization reference output.
Pin NameMSQFP
PadType Modes Description
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1.6 POWER PIN LIST
PCI Interface Main Memory Interface Peripherals, Miscellaneous System Interface
VSS VDD VSS VDD VSS VDD
MSQFP MSQFP MSQFP MSQFP MSQFP MSQFP
211217223229237
8 111925313743
214220226233
41522283440
495764718285889197
103109117124128131134137140
46536068757984879094
100106113120129135139
151157166177188195202207
154163169180191199205208
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1.10 DC/AC CHARACTERISTIC
1.10.1 Operating Range
Functional operation, long-term reliability and AC/DC characteristics are guaranteed for the operating conditions below.
1.10.2 Absolute Maximum Ratings
Permanent damage may occur if these conditions are exceeded.
Notes: 1. VX for a 5V pin is either VREF_PCI or VREF_PERIPH, see Section 1.7.2. Equivalent to discharging a 150pF capacitor through a 1.5Kohm series resistor.
1.10.3 DC/AC Characteristics
Notes: 1. VX for a 5V pin is either VREF_PCI or VREF_PERIPH, see Section 1.7.2. An artificial stress program can yield higher current consumption.
Symbol Parameter Minimum Typical Maximum Units
VDD Supply voltage 3.135 3.30 3.465 V
Tcase Operating Case Temperature Range 0 85 Deg. C
Symbol Parameter Min. Max Units Notes
VDD Supply voltage -0.5 3.6 V
VI-5V DC input voltage on all 5V pins -0.5 VX+0.5 V 1
VI-3.3V DC input voltage on all 3.3V pins -0.5 VDD+0.3 V
Tstg Storage temperature range -65 150 Deg. C
Tcase Case Temperature Range in operation 0 120 Deg. C
VESD
Electrostatic handling for all pins - +2000 V 2
Symbol Parameter Condition/Notes Min. Max Units
VDD
Supply voltage 3.135 3.465 V
Ip Total supply current 133 MHz, no blocks powered down, typical application. Note 2
1800 mA
Ipdn Total supply current 133 MHz, CPU powered down 400 mAV
IH-5vInput HIGH voltage - for I/O-5 Note 1. 2.0 VX+ 0.5 V
VIH-3.3v Input HIGH voltage - for I/O-3.3v 2.0 VDD + 0.3 V
VIL-5v
Input LOW voltage- for I/O-5 -0.5 0.8 V
VIL-3.3v
Input LOW voltage - for I/O-3.3v -0.3 0.8 V
IIL-5v
Input leakage current - for I/O-5v 0 < VIN < 2.7V -70 70 uA
IIL--3.3v
Input leakage current - for I/O-3.3v 0 < VIN < 2.7V -0 10 uA
VOH-5v
Output HIGH voltage - for I/O-5v IOUT = -2.0mA 2.4 V
VOH-3.3v
Output HIGH voltage - for I/O-3.3v IOUT = -0.5mA 0.9VDD V
VOL-5v
Output LOW voltage - for I/O-5v IOUT = 6.0mA 0.55 V
VOL-3.3v
Output LOW voltage - for I/O-3.3v IOUT = 1.5mA 0.1VDD V
CIN
Input Pin capacitance 8 pF
I2C-Bus, SDA/SCL
VIL-I2C
Input LOW voltage - for I2C pins -0.5 0.8 V
VIH-I2C
Input HIGH voltage - for I2C pins Note 1. 2.0 VX+ 0.5 V
IOL Low Level output Current VOL
= 0.4V 3 mA
IL-I2C
Leakage Current VI = VSS or VDD 10 uA
CIN-I2C
Input Pin capacitance VI = VSS 8 pF
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1.10.3.1 SDRAM Interface Timing
Notes: 1. Maximum output load on MM_CLK0 and MM_CLK1 is 10pF.2. Equal load circuit. MM_CLK0 , MM_CLK1 and MM_MATCHOUT are matched output buffers.3. The center of the two rising edges on MM_CLK0 , MM_CLK1 are used as the reference point.4. MM_MATCHIN is used as a reference clock.5. To optimize read timing margin, MM_MATCHIN must be connected directly to MM_MATCHOUT with a minimal length line.
Optionally, a series RC delay can be used to optimize high frequency SDRAM operation read timing margin. Board tracelengths should be kept to an absolute minimum.
1.10.3.2 PCI Bus Timing
The following specifications meet the PCI specifications, Rev. 2.1 for 33MHz bus operation.
Notes: 1. See the timing measurement conditions in Figure 1-1. 2. Minimum times are measured at the package pin with the load circuit shown in Figure 1-5. Maximum times are measured
with the load circuit shown in Figure 1-3 and Figure 1-4.3. REG# and GNT# are point-to-point signals and have different input setup times. All other signals are bused.4. See the Timing measurement conditions in Figure 1-2.5. RST# is asserted and de-asserted asynchronously with respect to CLK.6. All output drivers are floated when RST# is active.7. For the purpose of Active/Float timing measurements, the Hi-Z or “off” state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
1.10.3.3 JTAG I/O Timing
Notes: 1. See the timing measurement conditions in Figure 1-7.2. See the timing measurement conditions in Figure 1-6.
Symbol Parameter Min. Max Units Notes
fSDRAM MM_CLK frequency 133 MHz 1
TCS skew between MM_CLK0, CLK1, MATCHOUT 0.4 ns 2
TPD Propagation delay of Data, Address, Control 5 ns 3
TOH Output Hold time of Data, Address and Control 1.3 ns 3
TSU Input Data Setup Time 1 ns 4,5
TIH Input Data Hold Time 2 ns 4,5
Symbol Parameter Min. Max Units Notes
Tval-PCI (Bus) Clk to Signal Valid Delay, Bused signals 2 11 ns 1,2,3
Tval-PCI (ptp) Clk to Signal Valid Delay, Point to Point signals 2 12 ns 1,2,3
Ton-PCI Float to Active Delay 2 ns 1
TOff-PCI Active to Float Delay 28 ns 1,7
Tsu-PCI Input Set up Time to CLK- bused signals 7 ns 3,4
Tsu-PCI (ptp) Input Set up Time to CLK - point to point signals 12 ns 3,4
Th-PCI Input Hold Time from CLK 0 ns 4
Trst-PCI Reset Active Time after power stable 1 ms 5
Trst-clk-PCI Reset Active Time after CLK stable 100 us 5
Trst-off-PCI Reset Active to output float delay 40 ns 5,6,7
Symbol Parameter Min. Max Units Notes
Tclk-TDO JTAG_TCK to JTAG_TDO Valid Delay 2 10 ns 1
Tsu-TCK Input Set up Time to JTAG_TCK 3 ns 2
Th-TCK Input Hold Time from JTAG_TCK 2 ns 2
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1.10.3.4 I2C I/O Timing
Notes: 1. See the timing measurement conditions in Figure 1-8.2. See the timing measurement conditions in Figure 1-9.3. See the timing measurement conditions in Figure 1-10.4. See the timing measurement conditions in Figure 1-11.5. See the timing measurement conditions in Figure 1-12.
1.10.3.5 VideoIn I/O Timing
Notes: 1. See the timing measurement conditions in Figure 1-13.
1.10.3.6 VideoOut I/O Timing
Notes: 1. See the timing measurement conditions in Figure 1-14.2. See the timing measurement conditions in Figure 1-15.3. CLKOUT asserted, i.e. Video Out is the source of VO_CLK4. CLKOUT negated, i.e. the external world is the source of VO_CLK5. Limited to 60% of CPU clock
Symbol Parameter Min. Max Units Notes
fSCL SCL clock frequency 400 kHz 1
TBUF Bus Free time 1 us 2
Tsu-STA Start condition set up time 1 us 3
Th-STA Start condition hold time 1 us 3
TLOW SCL LOW time 1 us 1
THIGH SCL HIGH time 1 us 1
Tf SCL and SDA fall time 0.3 us 1
Tsu-SDA Data set-up time 100 ns 4
Th-SDA Data hold time 0 ns 4
Tdv-SDA SCL LOW to data out valid 0.5 us 5
Tdv-STO SCL HIGH to data out 1 ns 5
Symbol Parameter Min. Max Units Notes
fVI-CLK VideoIn clock frequency 54 MHz
Tsu-CLK Input Set up Time to VI_CLK 3 ns 1
Th-CLK Input Hold Time from VI_CLK 2 ns 1
Symbol Parameter Min. Max Units Notes
fVO-CLK VideoOut clock frequency 80 MHz 5
TCLK-DV VO_CLK to VO_DATA (or VO_IO*) out 4 10.5 ns 1,3
TCLK-DV VO_CLK to VO_DATA (or VO_IO*) out 4 10.5 ns 1,4
Tsu-CLK VO_IO* Set up Time to VO_CLK 10 ns 2
Th-CLK VO_IO* Hold Time from VO_CLK 3 ns 2
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1.10.3.7 AudioIn I/O Timing
Notes: 1. See the timing measurement conditions in Figure 1-16.2. The timing measurements are done with respect to the clock edge according to CLOCK_EDGE3. SER_MASTER asserted, i.e. Audio In is the source of AI_WS. See the timing measurement condition in Figure 1-17.
1.10.3.8 AudioOut I/O Timing
Notes: 1. See the timing measurement conditions in Figure 1-18.2. See the timing measurement conditions in Figure 1-20.3. The timing measurements are done with respect to the AO_SCK clock edge according to CLOCK_EDGE4. TM1100 is the serial interface master, i.e. AO_SCK, AO_WS are outputs5. TM1100 is serial interface slave, i.e. AO_SCK, AO_WS are inputs6. See the timing measurement conditions in Figure 1-19.
1.10.3.9 SSI I/O Timing
Notes: 1. Interrupt latency limits SSI to a practical use at a bit rate of 1.2 Mbit/sec2. See the timing measurement conditions in Figure 1-21.3. See the timing measurement conditions in Figure 1-22.
Symbol Parameter Min. Max Units Notes
fAI-SCK AudioIn AI_SCK clock frequency 20 MHz
Tsu-SCK input Set up Time to AI_SCK 3 ns 1,2
Th-SCK input Hold Time from AI_SCK 2 ns 1,2
TSCK-WS AI_SCK to AI_WS 10 ns 3
Symbol Parameter Min. Max Units Notes
fAO-SCK AudioOut AO_SCK clock frequency 20 MHz
TSCK-DV AO_SCK to AO_SD valid 2 12 ns 1,3,4
TSCK-DV AO_SCK to AO_SD valid 2 12 ns 1,3,5
Tsu-SCK Input Set up Time to AO_SCK 3 ns 2,3,5
Th-SCK Intput Hold Time from AO_SCK 2 ns 2,3,5
TSCK-WS AO_SCK to AO_WS 10 ns 3,4,6
Symbol Parameter Min. Max Units Notes
fSSI_CLK SSI_CLK clock frequency 20 MHz 1
TCLK-DV SSI_CLK to data valid 2 12 ns 2
Tsu-CLK Input Set up Time to SSI_CLK 3 ns 3
Th-CLK Input Hold Time from SSI_CLK 2 ns 3
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TM1100 Preliminary Data Book Philips Semiconductors
SCL
SDA
Figure 1-10. I 2C I/O Timing
Th_STATsu_STA
SCL
SDA
Figure 1-11. I 2C I/O Timing
valid
Th_SDATsu_SDA
Figure 1-12. I 2C I/O Timing
SCL
SDA valid
Tdv_STOTdv_SDA
CLK
VideoIN
Figure 1-13. VideoIn I/O Timing
valid
Th_CLKTsu_CLK
Figure 1-14. VideoOut I/O Timing
CLK
VO_DATA valid
TCLK_DV
VO_CLK
VO_IO
Figure 1-15. VideoOut I/O Timing
valid
Th_CLKTsu_CLK
AI_SCK
AI_SD, AI_WS
Figure 1-16. AudioIn I/O Timing
valid
Th_SCKTsu_SCK
Figure 1-17. AudioIn I/O Timing
AI_SCK
AI_WS valid
TSCK_WS
Figure 1-18. AudioOut I/O Timing
AO_SCK
AO_SD valid
TSCK_DV
Figure 1-19. AudioOut I/O Timing
AO_SCK
AO_WS valid
TSCK_WS
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Philips Semiconductors Pin List
AO_SCK
AO_WS
Figure 1-20. AudioOut I/O Timing
valid
Th_SCKTsu_SCK
Figure 1-21. SSI I/O Timing
SSI_CLK
SSI I/O valid
TCLK_DV
SSI_CLK
SSI_IO
Figure 1-22. SSI I/O Timing
valid
Th_CLKTsu_CLK
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TM1100 Preliminary Data Book Philips Semiconductors
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Overview Chapter 2
by Gert Slavenburg
2.1 INTRODUCTION
TM1100 is a successor to the TM1000 media processor.For those familiar with the TM1000, the new featuresspecific to the TM1100 are summarized in Section 2.6.
2.2 TM1100 FUNDAMENTALS
TM1100 is a media processor for high-performance mul-timedia applications that deal with high-quality video andaudio. These applications can range from low-cost, ded-icated systems such as video phones or set-top boxes toreprogrammable, multi-purpose plug-in cards for person-al computers. TM1100 easily implements popular multi-media standards such as MPEG-1 and MPEG-2, but its
orientation around a powerful general-purpose CPU(called the DSPCPU) makes it capable of implementinga variety of multimedia algorithms, whether open or pro-prietary. TM1100 is also easily configured in multiple pro-cessor configurations for very high-end applications.
More than just an integrated microprocessor with unusu-al peripherals, the TM1100 microprocessor is a fluidcomputer system controlled by a small real-time OS ker-nel that runs on the VLIW processor core. TM1100 con-tains a DSPCPU, a high-bandwidth internal bus, and in-ternal bus-mastering DMA peripherals.
Software compatibility between current and future Trime-dia media processor line family members is at thesource-code and library API level; binary compatibilitybetween family members is not guaranteed.
T M 1 1 0 0
Video In
Audio In
Audio Out
I2C Interface
VLDCoprocessor
Video Out
Timers
SynchronousSerial
Interface
ImageCoprocessor
VLIWCPU 16K
D$
32KI$
CCIR656 dig. videoYUV 4:2:2
54 MHz (27 Mpix/sec)
Stereo digital audioI2S DC–100 kHz
2/4/6/8 ch. digital audioI2S DC–100 kHz
I2C bus tocamera, etc.
Huffman decoderSlice-at-a-timeMPEG-1 & 2
CCIR656 digital videoYUV 4:2:280 MHz (40 Mpix.sec)
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TM1100 Preliminary Data Book Philips Semiconductors
Defining software compatibility at the source-code levelgives Philips the freedom to strike the optimum balancebetween cost and performance for all the chips in thefamily. A powerful compiler and software developmentenvironment ensure that programmers never need to re-sort to non-portable assembler programming. Program-mers use the library API’s and multimedia operationsfrom C and C++ source code.
TM1100 is designed both for use as accelerator in a PCenvironment, or as the sole CPU in cost-effective stand-alone systems.
In standalone system applications, the TM1100 externalbus allows for glueless connection of 8 bit wide ROM,EEPROM or Flash memory for code storage. The exter-nal bus also allows intermixing of PCI2.1 master/slaveperipherals and 8 bit simple peripherals, such as UARTsand other 8 bit micro-processor peripherals. This power-ful external bus architecture gives system designers avariety of options to configure low-cost, high-perfor-mance system solutions.
Because it is based on a general-purpose CPU, TM1100can also serve as a multi-function PC enhancement ve-hicle. Typically, a PC must deal with multi-standard videoand audio streams, and users desire both decompres-sion and compression. While the CPU chips used in PCsare becoming capable of low-resolution real-time videodecompression, high-quality video decompression ofstudio resolution video—not to mention compression—isstill out of reach. Further, users demand that their sys-tems provide live video and audio without sacrificing theresponsiveness of the system.
TM1100 enhances a PC system to provide real-time mul-timedia, and it does so with the advantages of a special-purpose, embedded solution—low cost and chip count—and the advantages of a general-purpose processor—reprogrammability. For PC applications, TM1100 far sur-passes the capabilities of fixed-function multimediachips.
Future media processor family members will have differ-ent sets of interfaces appropriate for their intended use.
2.3 TM1100 CHIP OVERVIEW
The key features of TM1100 are:
• A very powerful, general-purpose VLIW processorcore (the DSPCPU) that coordinates all on-chipactivities. In addition to implementing the non-trivialparts of multimedia algorithms, this processor runs asmall real-time operating system that is driven byinterrupts from the other units.
• DMA-driven multimedia input/output units that oper-ate independently and that properly format data tomake software media processing efficient.
• DMA-driven multimedia coprocessors that operateindependently and in parallel with the DSPCPU toperform operations specific to important multimediaalgorithms.
• A high-performance bus and memory system thatprovides communication between TM1100’s pro-cessing units.
• A flexible external bus interface.
Figure 2-1 shows a block diagram of the TM1100 chip.The bulk of a TM1100 system consists of the TM1100microprocessor itself, external synchronous DRAM(SDRAM), and whatever external circuitry is needed tointerface to the incoming and/or outgoing video and au-dio data streams, as well as to communication lines.TM1100’s external peripheral bus can gluelessly inter-face to PCI2.1 components and/or 8 bit microprocessorperipherals.
Figure 2-2 shows a possible TM1100 system applica-tion. A video-input stream might come directly from aCCIR 656-compliant video camera chip in YUV 4:2:2 for-mat; the interface is glueless in this case. A analog cam-era can be connected via a CCIR 656 interface chip(such as the Philips SAA7113). A CCIR656 output videostream is provided directly from the TM1100 to drive adedicated video monitor. Stereo audio input and up to 8channel audio output require only low-cost external ADCand DAC. The operation of the video and audio interfaceunits is highly customizable through programmable pa-rameters.
The glueless PCI interface allows the TM1100 to displayvideo in a host PC’s video card. The Image Coprocessorprovides display support for live video in an arbitrarynumber of arbitrarily overlapped windows.
Finally, the Synchronous Serial Interface interface re-quires only an external ISDN or analog modem front-endchip and phone line interface to provide remote commu-nication support. It can be used to connect TM1100-based systems for video phone or video conferencingapplications, or it can be used for general-purpose datacommunication in PC systems.
The JTAG port on TM1100 is a debug access port thatallows a debugger on a host system to access and con-
Figure 2-2. TM1100 system connections. A minimal TM1100 system requires few supporting compo-nents.
T M 1 1 0 0
CCIR656dig. video
2Mx32 SDRAM
ADCStereoAudio In DAC
2 - 8 chAudio Out
CCIR656dig. video
JTAG ModemFront End
PCI and 8 bi t per ipheral bus
R O M
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Philips Semiconductors Overview
trol state of a TM1100 in a target system. It also imple-ments 1149.1 boundary scan functionality.
2.4 BRIEF EXAMPLES OF OPERATION
The key to understanding TM1100 operation is observ-ing that the DSPCPU and peripherals are time-sharedand that communication between units is throughSDRAM memory. The DSPCPU switches from one taskto the next; first it decompresses a video frame, then itdecompresses a slice of the audio stream, then back tovideo, etc. As necessary, the DSPCPU issues com-mands to the peripheral function units to orchestrate theiroperation.
The DSPCPU can enlist the ICP and other co-proces-sors to help with some of the straightforward, tedioustasks associated with video processing. The ICP is verywell suited for arbitrary size horizontal and vertical videoresizing and color space conversion.
The DSPCPU can enlist the input/output peripherals toautonomously receive or transmit digital video and audiodata with minimal CPU supervision. The I/O units havebeen designed to interface to the outside world throughindustry standard audio and video interfaces, while deliv-ering or taking data in memory in formats suitable forsoftware processing.
2.4.1 Video Decompression in a PC
An example of operation for a TM1100 system is to serveas a video-decompression engine on a PCI card in a PC.In this case, the PC doesn’t need to know the TM1100has a powerful, general-purpose CPU; rather, the PCjust treats the hardware on the PCI card as a “black-box”engine.
Video decompression begins when the PC operatingsystem hands the TM1100 a pointer to compressed vid-eo data in the PC’s memory (the details of the communi-cation protocol are handled by the software driver in-stalled in the PC’s operating system).
The DSPCPU fetches data from the compressed videostream via the PCI bus, decompresses frames from thevideo stream, and places them into local SDRAM. De-compression may be aided by the VLD (variable-lengthdecoder) co-processor unit, which implements Huffmandecoding and is controlled by the DSPCPU.
When a frame is ready for display, the DSPCPU givesthe ICP (image coprocessor) a display command. TheICP then autonomously fetches the decompressedframe data from SDRAM and transfers it over the PCIbus to the frame buffer in the PC’s video display card. Al-ternately, video can be sent to the graphics card usingthe CCIR656 video output.
2.4.2 Video Compression
Another typical application for TM1100 is in video com-pression. In this case, uncompressed video is usuallysupplied directly to the TM1100 system via the video-inunit. A camera chip connected directly to the video-in unit
supplies YUV data in eight-bit, 4:2:2 format. The video-inunit takes care of sampling the data from the camerachip and demultiplexing the raw video to SDRAM in threeseparate areas, one each for Y, U, and V.
When a complete video frame has been read from thecamera chip by the video-in unit, it interrupts theDSPCPU. The DSPCPU compresses the video data insoftware (using a set of powerful data-parallel multime-dia operations) and writes the compressed data to a sep-arate area of SDRAM.
The compressed video data can now be transmitted orstored in any of several ways. It can be sent to a hostsystem over the PCI bus for archival on local mass stor-age, or the host can transfer the compressed video overa network. The data can also be sent to a remote systemusing the modem/ISDN interface to create, for example,a video phone or video conferencing system.
Since the powerful, general-purpose DSPCPU is avail-able, the compressed data can be encrypted before be-ing transferred for security.
2.5 INTRODUCTION TO TM1100 BLOCKS
The remainder of this chapter provides a brief introduc-tion to the internal components of TM1100.
2.5.1 Internal “Data Highway” Bus
The internal data bus connects all internal blocks togeth-er and provides access to internal control/status regis-ters of each block, external SDRAM, and the externalbus peripheral chips. The internal bus consists of sepa-rate 32-bit data and address buses, and transactions onthe bus use a block-transfer protocol. On-chip peripheralunits and co-processors can be masters or slaves on thebus.
Access to the internal bus is controlled by a central arbi-ter, which has a request line from each potential busmaster. The arbiter is programmable to provide guaran-teed bandwidth and latency to requestors so that the ar-bitration algorithm can be tailored for different applica-tions. Peripheral units make requests to the arbiter forbus access, and depending on the arbitration mode, busbandwidth is allocated to the units in different amounts.Each mode allocates bandwidth differently, but eachmode guarantees each unit a minimum bandwidth andmaximum service latency. All unused bandwidth is allo-cated to the DSPCPU.
The bus allocation mechanism is one of the features ofTM1100 that makes it a true real-time system instead ofjust a highly integrated microprocessor with unusual pe-ripherals.
2.5.2 VLIW Processor Core
The heart of TM1100 is its powerful 32-bit DSPCPUcore. The DSPCPU implements a 32-bit linear addressspace and 128, fully general-purpose 32-bit registers.The registers are not separated into banks; any opera-tion can use any register for any operand.
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The core uses a VLIW instruction-set architecture and isfully general-purpose. TM1100 uses a VLIW instructionlength that allows five simultaneous operations to be is-sued every clock cycle. These operations can target anyfive of the 27 functional units in the DSPCPU, includinginteger and floating-point arithmetic units and data-paral-lel multimedia operation units.
Although the processor core runs a real-time operatingsystem to coordinate all activities in the TM1100 system,the processor core is not intended for true general-pur-pose computer use. For example, the TM1100 processorcore does not implement demand paged virtual memory,memory address translation, or 64 bit floating point - allessential features in a general-purpose computer sys-tem.
TM1100 uses a VLIW architecture to maximize proces-sor throughput at the lowest possible cost. VLIW archi-tectures have performance exceeding that of supersca-lar general-purpose CPUs without the cost andcomplexity of a superscalar CPU implementation. Thehardware saved by eliminating superscalar logic reducescost and allows the integration of multimedia-specificfeatures that enhance the power of the processor core.
The TM1100 operation set includes all traditional micro-processor operations. In addition, multimedia operationsare included that dramatically accelerate standard videoand audio compression and decompression algorithms.As just one of the five operations issued in a singleTM1100 instruction, a single “custom” or “media” opera-tion can implement up to 11 traditional microprocessoroperations. These multimedia operations combined withthe VLIW architecture result in tremendous throughputfor multimedia applications.
The DSPCPU core is supported by separate 16-KB dataand 32-KB instruction caches. The data cache is dual-ported to allow two simultaneous accesses, and bothcaches are eight-way set-associative with a 64-byteblock size.
2.5.3 Video-In Unit
The video-in unit interfaces directly to any CCIR 601/656-compliant device that outputs eight-bit parallel, 4:2:2YUV time-multiplexed data. Such devices include directdigital camera systems, which can connect gluelessly toTM1100 or through the standard CCIR 656 connectorwith only the addition of ECL level converters. A singlechip external device can be used to convert to/from serialD1 professional video. Non-CCIR-compliant devices canuse a digital video decoder chip, such as the PhilipsSAA7113, to interface to TM1100.
The video-in unit demultiplexes the captured YUV databefore writing it into local TM1100 SDRAM. Separateplanar data structures are maintained for Y, U, and V.
The video-in unit can be programmed to perform on-the-fly horizontal resolution subsampling by a factor of two ifneeded. Many camera systems capture a 640-pixel/lineor 720-pixel/line image; with subsampling, direct conver-sion to a 320-pixel/line or a 360-pixel/line image can beperformed with no DSPCPU intervention. Performing
this function during video input reduces initial storageand bus bandwidth requirements for applications requir-ing reduced resolution.
2.5.4 Video-Out Unit
The video-out unit essentially performs the inverse func-tion of the video-in unit. Video-out generates an eight-bit,CCIR656 digital video data stream that contains a com-posited video and graphics overlay image. The video im-age is taken from separate Y, U, and V planar data struc-tures in SDRAM. The graphics overlay is taken from apixel-packed YUV data structure in SDRAM. Composit-ing allows both alpha-blending and chroma keying.
The video-out unit can also up-scale the video imagehorizontally by a factor of two to convert from CIF/SIF toCCIR 601 resolution. The overlay image, if enabled, is al-ways in full-pixel resolution.
Video Out is capable of pixel emission rates up to 40Mpix/sec, and allows full programming of horizontal andvertical frame/field structure. It is hence capable of re-fresh of both interlaced as well as non-interlaced (“twofh”) video displays, with 4:3 or 16:9 or other aspect ra-tio’s.
The sample rate for video-out pixels (and audio samples)is independently and dynamically programmable. Thehigh-quality on-chip sample clock generator circuit al-lows the programmer subtle control over the samplingfrequency so that audio and video synchronization canbe achieved in any system configuration. When chang-ing the sample frequency, the instantaneous phase doesnot change, which allows sample frequency manipula-tion without introducing audio or video distortion.
2.5.5 Image Coprocessor (ICP)
The image coprocessor (ICP) is used for several purpos-es to off-load common image scaling or filtering tasksfrom the DSPCPU. Although these tasks can be easilyperformed by the DSPCPU, they are a poor use of therelatively expensive CPU resource. When performed inparallel by the ICP, these tasks are performed efficientlyby simple hardware, which allows the DSPCPU to con-tinue with more complex tasks.
The ICP can operate as either a memory-to-memory ora memory-to-PCI coprocessor device.
In memory-to-memory mode, the ICP can perform eitherhorizontal or vertical image filtering and resizing. A highquality algorithm is used (5 tap polyphase filter in eachdirection). Filtering or scaling is done in either the hori-zontal or vertical direction in one pass. Two invocationsof the ICP are required to filter or resize in both direc-tions.
In memory-to-PCI mode, the ICP can perform horizontalresizing followed by color-space conversion. For exam-ple, assume an n × m pixel array is to be displayed in awindow on the PC video screen while the PC is runninga graphical user interface. The first step (if necessary)would use the ICP in memory-to-memory mode to per-form a vertical resizing. The second step would use the
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ICP in memory-to-PCI mode to perform horizontal resiz-ing and optional colorspace conversion from YUV toRGB.
While sending the final, resampled and converted pixelsover the PCI bus to the video frame buffer, the ICP usesa full, per-pixel occlusion bit mask—accessed in destina-tion coordinates—to determine which pixels are actuallywritten to the graphics card frame buffer for display. Con-ditioning the transfer with the bit mask allows TM1100 toaccommodate an arbitrary arrangement of overlappingwindows on the PC video screen.
Figure 2-3 illustrates a possible display situation and thedata structures in SDRAM that support the ICP’s opera-tion. On the left in Figure 2-3, the PC’s video screen hasfour overlapping windows. Two, Image 1 and Image 2,are being used to display video generated by TM1100.
The right side of Figure 2-3 shows a conceptual view ofSDRAM contents. Two data structures are present, onefor Image 1 and the other for Image 2. Figure 2-3 repre-sents a point in time during which the ICP is displayingImage 2.
When the ICP is displaying an image (i.e., copying it fromSDRAM to a frame buffer), it maintains four pointers tothe data structures in SDRAM. Three pointers locate theY, U, and V data arrays, and the fourth locates the per-pixel occlusion bit map. The Y, U, and V arrays are in-dexed by source coordinates while the occlusion bit mapis accessed with screen coordinates.
As the ICP generates pixels for display, it performs hori-zontal scaling and colorspace conversion. The final RGBpixel value is then copied to the destination address in
the screen’s frame buffer only if the corresponding bit inthe occlusion bit map is a one.
As shown in the conceptual diagram, the occlusion bitmap has a pattern of 1s and 0s that corresponds to theshape of the visible area of the destination window in theframe buffer. When the arrangement of windows on thePC screen is changed, modifications to the occlusion bitmaps are performed by TM1100 or host resident soft-ware.
It is important to note that there is no preset limit on thenumber and sizes of windows that can be handled by theICP. The only limit is the available bandwidth. Thus, theICP can handle a few large windows or many small win-dows. The ICP can sustain a transfer rate of 50 megapix-els per second, which is more than enough to saturatePCI when transferring images to video frame buffers.
2.5.6 Variable-Length Decoder (VLD)
The variable-length decoder (VLD) is included to relievethe DSPCPU of the task of decoding Huffman-encodedvideo data streams. It can be used to help decode highbitrate MPEG-1 and MPEG-2 video streams. The lowerbitrate of video-conferencing can be adequately handledby DSPCPU software without co-processor.
The VLD is a memory-to-memory coprocessor. TheDSPCPU hands the VLD a pointer to a Huffman-encod-ed bit stream, and the VLD produces a tokenized bitstream that is very convenient for the TM1100 image de-compression software to use. The format of the outputtoken stream is optimized for the MPEG-2 decompres-sion software so that communication between theDSPCPU and VLD is minimized.
Figure 2-3. ICP - Windows on the PC screen and data structures in SDRAM for two live video windows.
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2.5.7 Audio-In and Audio-Out Units
The audio-in and audio-out units are similar to the videounits. They connect to most serial ADC and DAC chips,and are programmable enough to handle most serial bitprotocols. These units can transfer MSB or LSB first andleft or right channel first.
The sampling clock is driven by TM1100 and is softwareprogrammable within a wide range from DC to 100 kHz.Sample rates for audio-in and audio-out, as well as vid-eo-out are separately and dynamically programmable.The high-quality on-chip sample clock generator circuitsallows the programmer subtle control over the samplingfrequency so that audio and video synchronization canbe achieved in any system configuration. When chang-ing the sample frequency, the instantaneous phase doesnot change, which allows sample frequency manipula-tion without introducing audio or video distortion.
As with the video units, the audio-in and audio-out unitsbuffer incoming and outgoing audio data in SDRAM. Theaudio-in unit buffers samples in either eight- or 16-bit for-mat, mono or stereo. The audio-out unit transfers eight-or 16-bit sample data for mono, stereo or up to eight au-dio channels from memory to the external DACs. Anymanipulation or mixing of sound data is performed by theDSPCPU since this processing will require only a smallfraction of its processing capacity.
2.5.8 Synchronous Serial Interface
The on-chip synchronous serial interface is specially de-signed to interface to high integration Analog Modemfrontends or ISDN frontend devices. In the analog mo-dem case, all of the modem signal processing is per-formed in the TM1100 DSPCPU.
2.5.9 I2C Interface
The I2C bus is a 2 wire multi-master, multi-slave interfacecapable of transmitting up to 400 kbit/sec. TM1100 im-plements an I2C master for use in single master environ-ments only. This interface allows TM1100 to configureand inspect the status of I2C peripheral devices, such asvideo decoders, video encoders and some cameratypes.
2.6 NEW IN TM1100
TM1100 offers significant improvements over theTM1000:
• DSPCPU and co-processor speed of 133 MHz• New DSPCPU instructions. See Appendix A,
“DSPCPU Operations for TM1100.”• SDRAM speed up to 133 MHz• Support for 64 mbit (x 32) SDRAM• Video Out improvements (8 bit alpha blending,
chroma keying, genlock). See Chapter 7, “VideoOut.”
• Capability to intermix PCI2.1 and 8 bit peripherals orROM/Flash memories on the external bus. SeeChapter 21, “PCI-XIO External I/O Bus.”
• An on-chip DVD authentication/descrambling co-pro-cessor. Information available to DVD product devel-opers on special request.
• Full 1149.1 boundary scan.• Improved PCI DMA read performance. See
Section 10.1.
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DSPCPU Architecture Chapter 3
by Gert Slavenburg, Marcel Janssens
3.1 BASIC ARCHITECTURE CONCEPTS
This section documents the system-programmer or‘bare-machine’ view of the TM1100 microprocessorCPU, also known as the DSPCPU.
3.1.1 Register Model
Figure 3-1 illustrates the DSPCPU registers. TheDSPCPU provides 128 general purpose registers,named r0..r127. In addition to the hardware programcounter PC, there are 4 user-accessible special purposeregisters, PCSW, DPC, SPC, and CCCOUNT. Table 3-1lists the registers and their purposes.
Register r0 always contains the integer value '0', registerr1 always contains the integer value '1'. Note that thisalso corresponds to r0 containing the boolean value'FALSE' or the single precision floating point value +0.0and r1 containing 'TRUE'. The programmer is NOT al-lowed to write to r0 or r1.
Note: Writing to r0 or r1 may cause reads from r0 orr1 scheduled in adjacent clock cycles to return unpre-dictable values. The standard assembler prevents/for-bids the use of r0 or r1 as a destination register.
Registers r2 through r127 are true general purpose reg-isters; the hardware does not in any way imply their use,although compiler or programmer conventions may as-
sign particular roles to particular registers. The DPC(Destination Program Counter) and SPC (Source Pro-gram Counter) relate to interrupt and exception handlingand are treated in Section 3.1.4, “SPC and DPC—Source and Destination Program Counter.” The PCSW(Program Control and Status Word) is treated in Section3.1.3, “PCSW Overview.” CCCOUNT, the 64 bit clockcycle counter is treated in Section 3.1.5, “CCCOUNT—Clock Cycle Counter.”
r0 32 bits Always reads as 0x0; must not be used as destination of operations
r1 32 bits Always reads as 0x1; must not be used as destination of operations
r2–r127 32 bits 126 general-purpose registers
PC 32 bits Program counter
PCSW 32 bits Program Control & Status Word
DPC 32 bits Destination program counter; latches target of taken branch that is inter-rupted
SPC 32 bits Source program counter; latches target of taken branch that is not interrupted
CCCOUNT 64 bits Counts clock cycles since reset
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3.1.2 Basic DSPCPU Execution Model
The DSPCPU issues one ‘long instruction’ every clockcycle. Each instruction consists of several operations(five operations for the TM1100 microprocessor). Eachoperation is comparable to a RISC machine instruction,except that the execution of an operation is conditionalupon the content of a general purpose register. Exam-ples of operations are:
IF r10 iadd r11 r12 → r13
(if r10 true, add r11 and r12 and write sum in r13)IF r10 ld32d(4) r15 → r16
(if r10 true, load 32 bits from mem[r15+4] into r16)IF r20 jmpf r21 r22
(if r20 true and r21 false, jump to address in r22)
Each operation has a specific, known execution latency(in clock cycles). For example, iadd takes 1 cycle. Thismeans that the result of an iadd operation started in clockcycle i is available for use as an argument to operationsissued in cycle i+1 or later. The other operations issuedin cycle i cannot use the result of iadd. The ld32d opera-tion has a latency of 3 cycles. The result of an ld32d op-eration started in cycle j is available for use by other op-erations issued in cycle j+3 or later. Branches, such asthe jmpf example above have three delay slots. Thismeans that if a branch operation in cycle k is taken, alloperations in the instructions in cycle k+1, k+2 and k+3are still executed.
In the above examples, r10 and r20 control the condition-al execution of the operations. This is also referred to as‘guarding’, where r10 and r20 contain the ‘guard’ of theoperation. See Section 3.2.1, “Guarding (Conditional Ex-ecution).”
Certain restrictions exist in the choice of what operationscan be packed into an instruction. For example, theDSPCPU in TM1100 allows no more than two load/storeclass operations to be packed into a single instruction.Also, no more than five results (of previously started op-erations) can be written during any one cycle. The pack-ing of operations is not normally done by the program-mer. Instead, the instruction scheduler (See PhilipsTriMedia SDE Reference Manual) takes care of convert-ing the parallel intermediate format code into packed in-structions ready for the assembler. The rules are formally
described in the machine description file used by the in-struction scheduler and other tools.
3.1.3 PCSW Overview
Figure 3-2 shows the PCSW (Program Control and Sta-tus Word) register. The TM1100 value of PCSW on resetis 0. For compatibility, any undefined PCSW fieldsshould never be modified.
Note that the DSPCPU architecture has no conditioncodes or integer arithmetic status flags. Integer opera-tions that generate out-of-range results deliver an opera-tion specific bit pattern. For example, see dspiadd in Ap-pendix A, “DSPCPU Operations for TM1100.” Predicateoperations exist that take the place of integer status flagsin a classical architecture. Multiword arithmetic is sup-ported by the “carry” operation, which generates a zeroor one depending on the carry that would be generated ifits arguments were summed.
FP-Related Fields. The IEEE mode field determines theIEEE rounding mode of all floating point operations, withthe exception of a few floating point conversion opera-tions that use fixed rounding mode. For example, see if-ixrz, ifloatrz, ifixrz, ifloatrz in Appendix A, “DSPCPU Op-erations for TM1100.”
The FP exception flags are ‘sticky bits’ that get set as aside effect of floating-point computations. Each floatingpoint operation can set one or more of the flags if it incursthe corresponding exception. The flags can only be resetby direct software manipulation of the PCSW (using thewritepcsw operation). The bits have the meanings shownin Table 3-2.
The FP exception trap enable bits determine which FPexception flags invoke CPU exception handling. An ex-ception is requested if the intersection of the exceptionflags and trap enable flags is non-zero. The acceptanceand handling of exceptions is described in Section 3.5,“Special Event Handling.”
BSX (Bytesex). The DSPCPU has a switchable bytesex.The BSX flag in the PCSW can be written by software.Load/store operations observe little- or big-endian byteordering based on the current setting of BSX.
IEN (Interrupt Enable). The IEN flag disables or enablesinterrupt processing for most interrupt sources. Only NMI
IEEE rounding mode0 ⇒ to nearest, 1 ⇒ to zero, 2 ⇒ to positive, 3 ⇒ to negative
Interrupt enable (1 ⇒ allow interrupts)
Byte sex (1 ⇒ little endian)
PCSW[31:16]
PCSW[15:0] UNDEF
Misaligned storeexception trap enable Trap on first exit
FP exceptions
TRPMSE TFE TRP
OFZTRPIFZ
TRPINV
TRPOVF
TRPUNF
TRPINX
TRPDBZ
1617181920212223252627283031
UNDEF U N D E F I N E D
13
WBE RSE
Write back errorReserved exception
TRPWBE
TRPRSE
Write back error trap enableReserved exceptiontrap enable
29
Figure 3-2. TM1100 PCSW (Program Control and Status Word) register format.
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(non maskable interrupt) bypasses IEN. The acceptanceand handling of interrupts is described in Section 3.5.3,“INT and NMI (Maskable and Non-Maskable Interrupts).”
CS (Count Stalls). The CS flag determines the mode ofCCCOUNT, the 64 bit clock cycle counter. If CS = ‘1’, thecycle counter increments on all clock cycles. If CS = ‘0’,the clock cycle counter only increments on non-stall cy-cles. See also Section 3.1.5, “CCCOUNT—Clock CycleCounter.”
MSE and TRPMSE (Misaligned-Store Exception). TheMSE bit will be set when the processor detects a storeoperation to an address that is not aligned. For example,a 32-bit store executed with an address that is not a mul-tiple of four will cause MSE to be set. The TRPMSE bitenables the DSPCPU to raise misaligned address ex-ceptions. An exception is requested if the intersection ofMSE and TRPMSE is non-zero. The acceptance andhandling of exceptions is described in Section 3.5, “Spe-cial Event Handling.”
Unaligned load operations do not cause an exception,because load operations can be speculative (i.e. their re-sult is thrown away).
When the DSPCPU generates an unaligned address, thelow order address bit(s) (one bit in the case of a 16-bitload, two bits for a 32-bit load) are forced to zero and theload/store is executed from this aligned address.
WBE and TRPWBE (Write Back Error). The WBE flagwill be set whenever a program attempts to write backmore than 5 results simultaneously. This is indicative ofa programming error, likely caused by the scheduler orassembler. The TRPWBE bit enables the correspondingexception.
RSE, TRPRSE (Reserved Exception). RSE and TR-PRSE are reserved for diagnostic purposes and not de-scribed here.
TFE (Trap on First Exit). The TFE bit is a support bit forthe debugger. The TFE bit is set by the debugger prior totaking a (non-interruptible) jump to the application pro-gram. On the next interruptible jump (the first interrupt-ible jump in the application being debugged), an excep-tion is requested because the TFE bit is set. Theacceptance and handling of exception processing is de-scribed in Section 3.5, “Special Event Handling.” It is theresponsibility of the exception handler software to clearthe TFE bit. The hardware does not clear or set TFE.
Corner-case note: Whenever a hardware update (e.g. anexception being raised) and a software update (throughwritepcsw) of the PCSW coincide, the new value of thePCSW will be the value that is written by the writepcswinstruction, except for those bits that the hardware is cur-rently updating (which will reflect the hardware value).
3.1.4 SPC and DPC—Source and Destination Program Counter
The SPC and DPC registers are support registers for ex-ception processing. The DPC is updated during every in-terruptible jump with the target address of that interrupt-ible jump. If an exception is taken at an interruptiblejump, the value in the DPC register can be used by theexception handling routine as the return address to re-sume the program at the place of interruption.
The SPC register is updated during every interruptiblejump that is not interrupted by an exception. Thus on aninterrupted interruptible jump, the SPC register is not up-dated. The SPC register allows the exception handlingroutine to determine the start address of the decision tree(a block of uninterruptible, scheduled TM1100 code) thatwas executing when the exception was taken (see alsoSection 3.5, “Special Event Handling”).
Corner-case note: Whenever a hardware update (duringan interruptible jump) and a software update (throughwritedpc or writespc) coincide, the software update takesprecedence.
3.1.5 CCCOUNT—Clock Cycle Counter
CCCOUNT is a 64 bit counter that counts clock cyclessince RESET. Cycle counting can occur in two modes,depending on PCSW.CS. If PCSW.CS = ‘1’, the cyclecount increments on every CPU clock cycle. If PCSW.CS= ‘0’, the clock cycle count only increments on non-stallCPU cycles.
CCCOUNT is implemented as a master counter/slaveregister pair. The master 64-bit counter gets updatedcontinuously. The value of the CCCOUNT slave registeris updated with the current master cycle count duringsuccessful interruptible jumps only. The cycles and hicy-cles DSPCPU operations return the content of the 32LSBs and 32 MSBs, respectively, of the slave register.This ensures that the value returned by hicycles and cy-cles is coherent, as long as there is no intervening inter-ruptible jump, which makes these operations suitable for64 bit high resolution timing from C source code pro-grams. The curcycles DSPCPU operation returns the 32LSBs of the master counter. The latter operation can beused for instruction cycle precise timing. When used, itmust - of course - be precisely placed, probably at the as-sembly code level.
3.1.6 Boolean Representation
The bit pattern generated by boolean valued operations(ileq, fleq etc.) is '00...00' (FALSE) or '00...01' (TRUE).When interpreting a bit pattern as a boolean value, onlythe LSB is taken into account, i.e. 'xx..x0' is interpretedas FALSE and 'xx..x1' is interpreted as TRUE. In partic-
Table 3-2. PCSW FP Exception Flag Definitions
Flag Function
INV Standard IEEE invalid flag
OVF Standard IEEE overflow flag
UNF Standard IEEE underflow flag
INX Standard IEEE inexact flag
DBZ Standard IEEE divide-by-zero flag
OFZ “Output flushed to zero;” set if an operation caused a denormalized result
IFZ “Input flushed to zero;” set if an operation was applied to one or more denormalized operands
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ular, wherever a general purpose register is used as a‘guard’, the LSB determines whether execution of theguarded operation takes place.
3.1.7 Integer Representation
The architecture supports the notion of 'unsigned inte-gers' and 'signed integers.' Signed integers use the stan-dard two’s-complement representation.
Arithmetic on integers does not generate traps. If a resultis not representable, the bit pattern returned is operationspecific, as defined in the individual operation descriptionsection. The typical cases are:
• Wrap around for regular add- and subtract-type oper-ations.
• Clamping against the minimum or maximum repre-sentable value for DSP-type operations.
• Returning the least significant 32-bit value of a 64-bitresult (e.g., integer/unsigned multiply).
3.1.8 Floating Point Representation
The TM1100 architecture supports single precision (32-bit) IEEE-754 floating point arithmetic.
All arithmetic conforms to the IEEE-754 standard inflush-to-zero mode.
All floating point compute operations round according tothe current setting of the PCSW IEEE mode field. Thecurrent setting of the field determines result rounding (tonearest, to zero, to positive infinity, to negative infinity).Conversions from float to integer/unsigned are availablein two forms: a PCSW rounding-mode-observing formand an ANSI-C-specific-rounding form. The ANSI-C-specific form forces round to zero regardless of thePCSW IEEE rounding mode. Conversion from integer/unsigned to float always observes the IEEE roundingmode.
Floating point exceptions are supported with two mecha-nisms. Each individual floating point operation (e.g. fadd)has a counterpart operation (faddflags) that computesthe exception flag values. These operations can be usedfor precise exception identification1. The second mecha-nism uses the ‘sticky’ exception bits in the PCSW thatcollect aggregate exception events. The PCSW excep-tion bits can selectively invoke CPU exception handling.See Section 3.5.2, “EXC (Exceptions).”
Table 3-3 shows the representation choices that weremade in TM1100’s floating point implementation.
3.1.9 Addressing Modes
The addressing modes shown in Table 3-4 are support-ed by the DSPCPU architecture (store operations allowonly displacement mode).
In these addressing modes, R[i] indicates one of the gen-eral purpose registers. The scale factor applied (1/2/4) isequal to the size of the item loaded or stored, i.e. 1 for abyte operation, two for a 16-bit operation and four for a32-bit operation. The range of valid 'i', 'j' and 'k' valuesmay differ between implementations of the architecture;the minimum values for implementation-dependent char-acteristics are shown in Table 3-5.
Note that the assembly code specifies the true displace-ment, and not the value to be scaled. For example‘ld32d(–8) r3’ loads a 32 bit value from address (r3 – 8).This is encoded in the binary operation pattern as a –2 inthe seven-bit field by the assembler. At runtime, thescale factor four is applied to reconstruct the intendeddisplacement of –8.
3.1.10 Software Compatibility
The DSPCPU architecture expressly does not supportbinary compatibility between family members. The ANSIC compiler ensures that all family members are compat-ible at the source-code level.
1. This mechanism allows precise exception identificationin the context of our multi-issue microprocessor core—where many floating point operations may issue simul-taneously—at the expense of additional operationsgenerated by the compiler. It also allows the compiler toissue compute operations speculatively and computeexceptions precisely.
Table 3-3. Special Float Value Representation
Item Representation
+inf 0x7f800000
-inf 0xff800000
self generated qNaN 0xffffffff
result of operation on any NaN argu-ment
argument | 0x00400000 (forcing the NaN to be quiet)
signalling NaN never generated by TM1100, accepted as per IEEE-754
Table 3-4. Addressing Modes
Mode Suffix Applies to Name
R[i] + scaled(#j) d Load & Store Displacement
R[i] + R[k] r Load only Index
R[i] + scaled(R[k]) x Load only Scaled index
Table 3-5. Minimum Values for Implementation-Dependent Addressing Mode Components
Parameter Minimum Range
‘i’ and ‘k’ 0..127 (i.e., each implementation has at least 128 registers)
‘j’ -64..63 (i.e., displacements will be at least 7 bits long and signed)
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3.2 INSTRUCTION SET OVERVIEW
3.2.1 Guarding (Conditional Execution)
In the TM1100 architecture, all operations are optionally'guarded'. A guarded operation executes conditionally,depending on the value in the ‘guard' register. For exam-ple, a guarded add is written as:
IF R23 iadd R14 R10 → R13
This should be taken to mean
if R23 then R13 ← R14 + R10.
The ’if R23' clause controls the execution of the opera-tion based on the LSB of R23. Hence, depending on theLSB of R23, R13 is either unchanged or set to containthe integer sum of R14 and R10.
Guarding applies to all DSPCPU operations, except theiimm and uimm (load-immediate) operations. Guardingcontrols the effect on all programmer visible state of thesystem, i.e. register values, memory content, exceptionraising and device state.
3.2.2 Load and Store Operations
Memory is byte addressable. Loads and stores have tobe ‘naturally aligned’, i.e. a 16-bit load or store must tar-get an address that is a multiple of two. A 32-bit load orstore must target an address that is a multiple of four.The BSX bit in the PCSW determines the byte order ofloads and stores. For example, see ld32 and st32 in Ap-pendix A, “DSPCPU Operations for TM1100.”
Only 32-bit load and store operations are allowed to ac-cess MMIO registers in the MMIO address aperture (seeSection 3.4, “Memory and MMIO”). The results are unde-fined for other loads and stores. A load from a non-exis-tent MMIO register returns an undefined result. A store toa non-existent MMIO register times out and then doesnot happen. There are no other sideeffects of an accessto a nonexistent MMIO register. The state of the BSX bithas no effect on the result of MMIO accesses.
Loads are allowed to be issued speculatively. Loads thatare outside the range of valid data memory addresses forthe active process return an implementation dependentvalue and do not generate an exception. Misalignedloads also return an implementation dependent valueand do not generate an exception.
If a pair of memory operations involves one or more com-mon bytes in memory, the effect on the common bytes isas defined in Table 3-6.
The addressing modes supported are shown inTable 3-4 and the minimum values of implementation-dependent addressing-mode components are shown inTable 3-5.
Note: The index and scaled-index modes are notallowed with store opcodes, due to the hardware
restriction that each operation have at most twosource operand registers and 1 condition register—stores use one operand register for the value to bestored, which leaves only one register to form anaddress.
The scale factor applied (1/2/4) in the scaled addressingmodes is equal to the size of the item loaded or stored,i.e. 1 for a byte operation, 2 for a 16-bit operation and 4for a 32-bit operation.
Table 3-7 lists the available load and store mnemonicsfor the three addressing modes.
Example usage of load and store operations:
IF r10 ild16d(12) r12 → r13
If the LSB of r10 is set, load 16 bits starting at address (r12+12) using the byte ordering indicated in PCSW.BSX, sign-extend the value to 32 bits and store the result in r13.
IF r10 st32d(40) r12 r13
if the LSB of r10 is set, store the 32-bit value from r13 to the address (r12+40) using the byte ordering indicated in PCSW.BSX.
Table 3-6. Behavior of Loads and Stores with Coincident Addresses
Condition Behavior
Tstore < Tload If a store is issued before a load, the value loaded contains the new bytes.
Tload < Tstore If a load is issued before a store, the value loaded contains the old bytes.
Tstore1 < Tstore2 If store1 is issued before store2, the result-ing value contains the bytes of store2.
Tstore = Tload If a load and store are issued in the same clock cycle, the result is UNDEFINED.
Tstore1 = Tstore2 If two stores are issued in the same clock cycle, the resulting stored value is unde-fined.
Table 3-7. Load and Store Mnemonics
Operation Displacement Index Scaled-Index
8-bit signed load ild8d ild8r —
8-bit unsigned load uld8d uld8r —
16-bit signed load ild16d ild16r ild16x
16-bit unsigned load uld16d uld16r uld16x
32-bit load ld32d ld32r ld32x
8-bit store st8d — —
16-bit store st16d — —
32-bit store st32d — —
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3.2.3 Compute Operations
Compute operations are register-to-register operations.The specified operation is performed on one or twosource registers and the result is written to the destina-tion register.
Immediate Operations. Immediate operations load animmediate constant (specified in the opcode) and pro-duce a result in the destination register.
Floating-Point Compute Operations. Floating-pointcompute operations are register-to-register operations.The specified operation is performed on one or twosource registers and the result is written to the destina-tion register. Unless otherwise mentioned all floatingpoint operations observe the rounding mode bits definedin the PCSW register. All floating-point operations notending in “flags” update the PCSW exception flags. Alloperations ending in “flags” compute the exception flagsas if the operation were executed and return the flag val-ues (in the same format as in the PCSW); the exceptionflags in the PCSW itself remain unchanged.
Multimedia Operations. These special compute opera-tions are like normal compute operations, but the speci-fied operations are not usually found in general purposeCPU’s. These operations provide special support formulti-media applications.
3.2.4 Special-Register Operations
Special register operations operate on the special regis-ters: PCSW, DPC, SPC and CCCOUNT.
3.2.5 Control-Flow Operations
Control-flow operations change the value of the programcounter. Conditional jumps test the value in a register,and based on this value, change the program counter tothe address contained in a second register or continueexecution with the next instruction. Unconditional jumpsalways change the program counter to the specified im-mediate address.
Control-flow operations can be interruptible or non-inter-ruptible. The execution of an interruptible jump is the onlyoccasion where the TM1100 allows special event han-dling to take place (see Section 3.5, “Special Event Han-dling”).
3.3 TM1100 INSTRUCTION ISSUE RULES
The TM1100 VLIW CPU allows issue of 5 operationseach clock cycle according to a set of specific issuerules. The issue rules impose issue time constraints anda result writeback constraint. Any set of operations thatmeets all constraints constitutes a legal TM1100 instruc-tion. A more extensive description and a few special caseissue rules and limitations can be found in “Philips TriMe-dia SDE Reference Manual, TM1100 Constraints”.
Issue time constraints:
• an operation implies a need for a functional unit type(as documented in Appendix A, “DSPCPU Opera-tions for TM1100.”)
Figure 3-3. TM1100 issue slots, functional units and latency.
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• each operation requires an issue slot that has aninstance of the appropriate functional unit typeattached
• functional units should be ‘recovered’ from any prioroperation issues
Writeback constraint:
• No more than 5 results should be simultaneouslywritten to the register file at any point in time (write-back occurs ‘latency’ cycles after issue)
Figure 3-3 shows all functional units of TM1100, includ-ing the relation to issue slots, and each functional unit’slatency (e.g. 1 for CONST, 3 for FALU, etc.). With the ex-ception of FTOUGH, each functional unit can except anoperation every clock cycle, i.e. has a recovery time of 1.The binding of operations to functional unit types is sum-marized in Table 3-8. In Appendix A, “DSPCPU Opera-tions for TM1100”, each operation lists the precise func-tional unit and unit latency.
3.4 MEMORY AND MMIO
TM1100 defines four apertures in its 32-bit addressspace: the memory hole, the DRAM aperture, the MMIOaperture and the PCI apertures (See Figure 3-4).Thememory hole covers addresses 0..0xff. The DRAM andMMIO apertures are defined by the values in MMIO reg-isters; the PCI apertures consist of every address thatdoes not fall in the other three apertures.
3.4.1 Memory Map
DRAM is mapped into an aperture extending from theaddress in DRAM_BASE to the address inDRAM_LIMIT. The maximum DRAM aperture size is 64MB.
The MMIO aperture is located at address MMIO_BASEand is fixed 2 MB in size.
In the default operating mode, all memory accesses notgoing to either the hole, DRAM or MMIO space are inter-preted as PCI accesses. This behavior can be overrid-
den as described in Section 5.3.8, “Memory Hole andPCI Aperture Disable.”
The MMIO aperture and the DRAM aperture can be atany naturally aligned location, in any order, but shouldnot overlap; if they do, the consequences are undefined.The values of DRAM_BASE, DRAM_LIMIT, andMMIO_BASE are set during the boot process. In thecase of a PCI host assisted boot, the values are deter-mined by the host BIOS. In case of stand-alone boot (i.e.,TM1100 is the PCI host), the values are taken from theboot ROM. Refer to Chapter 12, “System Boot” for de-tails. DSPCPU update of DRAM_BASE andMMIO_BASE is possible, but not recommended, seeSection 10.7.3, “MMIO/DRAM_BASE updates.”
3.4.2 The Memory Hole
The memory hole from address 0 to 0xff serves to protectthe system from performance loss due to speculativeloads. Due to the nature of C program references, mostspeculative loads issued by the DSPCPU fall in therange covered by the hole. The hole, which is activatedby default upon RESET, serves to ensure that thesespeculative loads do NOT cause PCI read accesses andslow down the system. The value returned by any dataload from the hole is 0. The hole only protects loads.Store operations in the hole do cause writes to PCI,SDRAM or MMIO as determined by the aperture baseaddress values. If the SDRAM aperture overlaps thememory hole, the memory hole is ignored.
The hole can be temporarily disabled through theDC_LOCK_CTL register. This is described in Section5.3.8, “Memory Hole and PCI Aperture Disable.”
3.4.3 MMIO Memory Map
Devices are controlled through memory-mapped deviceregisters, referred to as MMIO registers. To ensure com-patibility with future devices, any undefined MMIO bitsshould be ignored when read, and written as zeroes.
Table 3-8. Functional Unit Operations
unit type operation category
const immediate operations
alu 32 bit arithmetic, logical, pack/unpack
dspalu dual 16 bit, quad 8 bit multimedia arithmetic
dspmul dual 16 bit and quad 8 bit multimedia multiplies
dmem loads/stores
dmemspec cache coherency, cache control, prefetch
shifter multi-bit shift
branch control flow
falu floating point arithmetic & conversions
ifmul 32 bit integer and floating point multiplies
fcomp single cycle floating point compares
ftough iterative floating point square root and division
hole256byte0x0000 0000
PCI
MMIO_BASE
MMIO Aperture
DRAM_LIMIT
DRAM_BASE
DRAM Aperture
0xFFFF FFFFF
PCI
2MB
1MB–64MB
PCI
Figure 3-4. TM1100 Memory Map.
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Some devices can autonomously access data memory(DMA) and most devices can cause CPU interrupts.
The MMIO aperture is 2 MB in size and initially located ataddress 0xEFE00000 on RESET; it is relocated by thePCI BIOS for PC hosted TM1100 boards; its final loca-tion is determined by the boot EEPROM for stand-alonesystems. See Chapter 12, “System Boot” for more infor-mation. Figure 3-5 gives a detailed overview of theMMIO memory map (addresses used are offsets with re-spect to the MMIO base). The operating system onTM1100 can change MMIO_BASE by writing to theMMIO_BASE MMIO location. User programs should notattempt this. Refer to the TriMedia SDE Reference Man-ual for the standard method to access the device regis-ters from C language device drivers.
Only 32-bit load and store operations are allowed to ac-cess MMIO registers in the MMIO address aperture. Theresults are undefined for other loads and stores. Readsfrom non-existent MMIO registers return undefined val-ues. Writes to nonexistent MMIO registers time out.There are no sideeffects of accesses to non-existentMMIO registers. The state of the PCSW BSX bit has noeffect on the result of MMIO accesses.
The Icache tag & LRU bit access aperture gives theDSPCPU read-only access to the Icache status. RefertoSection 5.4.8, “Reading Tags and Cache Status” fordetails.
The EXCVEC MMIO location is explained in Section3.5.2, “EXC (Exceptions).” Section 3.5.3, “INT and NMI(Maskable and Non-Maskable Interrupts),” describesthe locations that deal with the setup and handling of in-terrupts: ISETTING, IPENDING, ICLEAR, IMASK andthe interrupt vectors. The timer MMIO locations are de-scribed in Section 3.8, “Timers.” The instruction anddata breakpoint are described in Section 3.9, “DebugSupport.” The MMIO locations of each device are treat-ed in the respective device chapters.
3.5 SPECIAL EVENT HANDLING
The TM1100 microprocessor responds to the specialevents shown in Table 3-9, ordered by priority.
With the exception of RESET, which is enabled at alltimes, the architecture of the DSPCPU allows specialevent handling to begin only during an interruptible jumpoperation (ijmpt, ijmpf or ijmpi) that succeeds (i.e., is ataken jump). EXC, NMI and INT handling can be initiatedduring handling of an EXC or an INT, but only during suc-cessful interruptible jumps.
The instruction scheduler uses interruptible jumps exclu-sively for inter-decision tree jumps. Hence, within a deci-sion tree, no special-event processing can be initiated. Ifa tree-to-tree jump is taken, special-event processing isallowed. Since the only registers live at this point (i.e.,that contain useful data) are the global registers allocat-
Figure 3-5. Memory map of MMIO address space (addresses are offset from MMIO_BASE).
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ed by the ANSI C compiler, only a subset of the registersneeds to be preserved by the event handlers. Refer tothe TriMedia SDE Reference Manual to find details onwhich registers can be in use. The DSPCPU registerstate can be described by the contents of this subset ofthe general purpose registers and the contents of thePCSW and the DPC (Destination Program Counter) val-ue (the target of the inter-tree jump).
The priority resolution mechanism built into the DSPCPUhardware dispatches the highest-priority non-maskedspecial event request at the time of a successful inter-ruptible jump operation. In view of the simple, real-time-oriented nature of the mechanisms provided, only limitednesting of events should be allowed.
3.5.1 RESET
RESET is the highest priority special event. It is assertedby external hardware or by the host CPU. TM1100 willrespond to it at any time.
External hardware reset through the TRI_RESET# pininitiates boot protocol execution, as described in Chapter12, “System Boot.” This causes (a.o.) the current PC val-ue to be lost and instruction execution to start from ad-dress DRAM_BASE.
A PCI host CPU can perform a TM1100 DSPCPU onlyreset by a MMIO write to the BIU_CTL.SR and CR bits.Such a reset does not cause a full boot, instead theDSPCPU resumes execution from DRAM_BASE.
3.5.2 EXC (Exceptions)
The DSPCPU enters EXC special-event processing un-der the following conditions:
1. RESET is de-asserted.2. The intersection PCSW[15,6:0] & PCSW[31,22:16] is
non-empty or PCSW.TFE is set.3. A successful interruptible jump is in the final jump ex-
ecution stage.
DSPCPU hardware takes the following actions on the ini-tiation of EXC processing:
1. DPC gets assigned the intended destination address of the successful jump.
2. Instruction processing starts at EXCVEC.
All other actions are the responsibility of the EXC handlersoftware. Note that no other special event processing willtake place until the handler decides to execute an inter-ruptible jump that succeeds.
3.5.3 INT and NMI (Maskable and Non-Maskable Interrupts)
The on-chip Vectored Interrupt Controller (VIC) provides32 INT request input hardware lines. The interrupt con-troller prioritizes and maps attention requests from sev-eral different peripherals onto successive INT requeststo the DSPCPU.
INT special event processing will occur under the follow-ing conditions:
1. RESET is de-asserted.2. The intersection PCSW[15,6:0] & PCSW[31,22:16] is
empty and PCSW.TFE is not set.3. The intersection of IPENDING and IMASK is non-
empty.4. The interrupt is at level NMI or PCSW.IEN = 1.5. A successful interruptible jump is in the final jump ex-
ecution stage.
DSPCPU hardware takes the following actions on the ini-tiation of NMI or INT processing:
1. DPC gets assigned the intended destination address of the successful jump.
2. Instruction processing starts at the appropriate inter-rupt vector.
All other actions are the responsibility of the INT handlersoftware. Note that no other special event processing willtake place until the handler decides to execute an inter-ruptible jump that succeeds.
3.5.3.1 Interrupt Vectors
Each of the 32 interrupt sources can be assigned an ar-bitrary interrupt vector (the address of the first instructionof the interrupt handler). A vector is setup by writing theaddress to one of the MMIO locations shown inFigure 3-6. The state of the MMIO vector locations is un-defined after RESET. (Addresses of the MMIO vectorregisters are offset with respect to MMIO_BASE.)
Programmer’s note: Please see the TriMedia Program-mer’s Reference Manual for information on writing inter-rupt handlers.
3.5.3.2 Interrupt Modes
DSPCPU interrupt sources can be programmed to oper-ate in either level-sensitive or edge-triggered mode. Op-eration in edge-triggered or level-sensitive mode is de-termined by a bit in the ISETTING MMIO locationscorresponding to the source, as defined in Figure 3-7.On RESET, all ISETTING registers are cleared.
In edge-triggered mode, the leading edge of the signalon the device interrupt request line causes the VIC (Vec-tored Interrupt Controller) to set the interrupt pending flagcorresponding to the device source number. Note that,for active high signals, the leading edge is the positiveedge, whereas for active low request signals (such asPCI INTA#), the negative edge is the leading edge. Theinterrupt remains pending until one of two events occurs:
Table 3-9. Special Events and Event Vectors
Event Vector
RESET (Highest priority) vector to DRAM_BASE
EXC (All exceptions) vector to EXCVEC (programmable)
NMI, INT
(Non-maskable interrupt, maskable interrupt) use the programmed vector (one of 32 vectors depend-ing on the interrupt source)
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• The VIC successfully dispatches the vector corre-sponding to the source to the TM1100 CPU, or
• TM1100 CPU software clears the interrupt-pendingflag by a direct write to the ICLEAR location.
No interrupt acknowledge to ICLEAR is needed for de-vices operating in edge-triggered mode, since the vectordispatch clears the IPENDING request. The device itselfmay however need a device specific interrupt acknowl-edge to clear the requesting condition. Edge-triggeredmode is not recommended for devices that can signalmultiple simultaneous interrupt conditions. The on-chiptimers must be operated in edge triggered mode.
In level-sensitive mode, the device requests an interruptby asserting the VIC source request line. The deviceholds the request until the device interrupt handler per-forms a device interrupt acknowledge. It is highly recom-mended that all off-chip and on-chip sources, with the ex-ception of the timers, are operated in level sensitivemode.
3.5.3.3 Device Interrupt Acknowledge
All devices capable of generating level-triggered inter-rupts have interrupt acknowledge bits in their memorymapped control registers for this purpose. An interruptacknowledge is performed by a store to such control reg-ister, with a ‘1’ in the bit position(s) corresponding to thedesired acknowledge flags.
Programmers note: the store operation that performs theinterrupt acknowledge should be issued at least 2 cyclesbefore the (interruptible) jump that ends an interrupt han-dler. This ensures that the same interrupt is not dis-patched twice due to request de-assertion clock delays.
3.5.3.4 Interrupt Priorities
Each interrupt source can be programmed to requestone out of eight levels of priorities. The highest prioritylevel (level seven) corresponds to requesting an NMI—an interrupt that cannot be masked by the DSPCPU PC-SW.IEN bit. The other levels request regular interrupts,that can be masked as a group by the PCSW.IEN flag.Level six represents the highest priority normal interruptlevel and level zero represents the lowest. Refer toFigure 3-7 for details of programming the priority level.
The VIC arbitrates the highest-priority pending interruptrequestor. Sources programmed to request at the samelevel are treated with a fixed priority, from source numberzero (highest) to thirty-one (lowest). At such time as theDSPCPU is willing to process special events, the vectorof highest priority NMI source will be dispatched. If noNMI is pending, and the DSPCPU allows regular inter-rupts (PCSW.IEN is asserted), the vector of the highestpriority regular source is dispatched. Once a vector isdispatched, the corresponding interrupt pending flag isde-asserted (edge triggered mode sources only).
3.5.3.5 Interrupt Masking
A single MMIO register (IMASK in Figure 3-8) allowsmasking of an arbitrary subset of the interrupt sources.Masking applies to both regular as well as NMI level re-questors. Masking is used by software to disable unuseddevices and/or to implement nested interrupt handling. Inthe latter case, each interrupt handler can stack the oldIMASK content for later restoration and insert a newmask that only allows the interrupts it is willing to handle.For level-triggered device handlers, IMASK should also
Figure 3-7. Interrupt mode and priority MMIO locations and formats.
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exclude the device itself to prevent repeated handler ac-tivation.
Each interrupt source device typically has its own inter-rupt enable flag(s), that determine whether certain keydevice events lead to the request of an interrupt. In addi-tion, the PCSW.IEN flag determines whether theDSPCPU is willing to handle regular interrupts. Nonmaskable interrupts ignore the state of this flag.
All three mechanisms are necessary: the PCSW.IEN flagis used to implement critical sections of code duringwhich the RTOS (Real-Time Operating System) is un-able to handle regular interrupts. The IMASK is used toallow full control over interrupt handler nesting. The de-vice interrupt flags set the operational mode of the de-vice.
When RESET is asserted, IPENDING, ICLEAR, andIMASK are set to all zeroes. (MMIO register addressesshown in Figure 3-8 are offset addresses with respect toMMIO_BASE.)
3.5.3.6 Software Interrupts and Acknowledgment
The IPENDING register shown in Figure 3-8 can be readto observe the currently pending interrupts. Each bit readdepends on the mode of the source:
• For a level-sensitive source, a bit value correspondsto the current state of the device interrupt requestline.
• For an edge-triggered interrupt, a ‘1’ is read if andonly if an interrupt request occurred and the corre-sponding vector has not yet been dispatched.
Software can request an interrupt for sources operatingin edge-triggered mode. Writes to the IPENDING registerassert an interrupt request for all sources where a 1 oc-curred in the bit position of the written value. The state ofsources where a 0 occurred in the written value is un-changed. Writes have no effect on level-sensitive modesources. The interrupt request, if not masked, will occurat the next successful interruptible jump. This differs fromthe conventional software interrupt-like semantics ofmany architectures. Any of the 32 sources can be re-quested in software. In normal operation however, soft-
ware-requested interrupts should be limited to sourcevectors not allocated for hardware devices. Note that an-other PCI master can request interrupts by manipulatingthe IPENDING location in the MMIO aperture. This isuseful for inter-processor communication.
The ICLEAR register reads the same as the IPENDINGregister. Writes to the ICLEAR register serve to clearpending flags for edge-triggered mode sources. All IP-ENDING flags corresponding to bit positions in which ‘1’sare written are cleared. IPENDING flags correspondingto bit positions in which ‘0’s are written are not affected.Writes have no effect on level-sensitive mode sources.When a pending interrupt bit is being cleared through awrite to the ICLEAR register at the same time that thehardware is trying to set that interrupt bit, the hardwaretakes precedence.
3.5.3.7 NMI Sequentialization
In most applications, it is desirable not to nest NMI’s. TheNMI interrupt handler can accomplish this by saving theold IMASK content and clearing IMASK before the firstinterruptible jump is executed by the NMI handler.
3.5.3.8 Interrupt Source Assignment
Table 3-10 shows the assignment of devices to interruptsource numbers, as well as the recommended operatingmode (edge or level triggered). Note that there are a totalof 5 external pins available to assert interrupt requests.The PCI INTA to INTD requests are asserted by activelow signal conventions, i.e. a zero level or a negativeedge asserts a request. The USERIRQ pin operates withactive high signalling conventions.
3.6 TM1100 TO HOST INTERRUPTS
In systems where TM1100 is operating in the presenceof a host CPU on PCI, TM1100 can generate interruptsto the host, using any combination of the four PCI INTA#to INTD# pins. In a typical host system, only one of thesepins needs to be wired to the PCI bus interrupt requestlines. Any unused pins of this group are then available foruse as software programmable I/O pins.
IMASK (r/w)0x10 082831 0
MMIO_BASEoffset: 723 15
ICLEAR (r/w)0x10 0824
IPENDING (r/w)0x10 0820
Each IMASK(i) bit: On read or write, 0 ⇒ disallow source i interrupt request On read or write, 1 ⇒ allow source i interrupt request
Each ICLEAR(i) bit: On read, same as IPENDING(i) On write, 1 ⇒ clear source i interrupt request
Each IPENDING(i) bit: On read, 1 ⇒ source i interrupt request is pending On write, 1 ⇒ software source i interrupt request
Figure 3-8. Interrupt controller request, clear, and mask MMIO registers.
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The INT_CTL register (see Figure 3-9) IEx bits, whenset, enable the open collector driver of the fourINTD#..INTA# pins. The INTx bits determine the outputvalue generated (if enabled). A ‘1’ in INTx causes thecorresponding PCI interrupt pin to be asserted (low IN-Tx# pin). The ISx bits are read-only and reflect the cur-rent actual state of the pins. Note that the pins have neg-ative logic (active low) polarity, and are of the opencollector output type. Hence the pin voltage is low (ac-tive) when the logical value set or seen in the INT_CTLregister is a ‘1’.
The assertion and de-assertion of host interrupts is theresponsibility of TM1100 software.
See also Section 10.7.17, “INT_CTL Register.”
3.7 HOST TO TM1100 INTERRUPTS
A host CPU can generate an interrupt to TM1100 in sev-eral ways:
• by a PCI MMIO write to IPENDING to assert theHOSTCOMM interrupt (bit 28)
• by a hardware circuit that asserts one of the interruptrequest pins TRI_USERIRQ, or INTA..INTD.
The first method is the method used most common. Itdoes not require any circuitry and leaves the interruptpins available for other purposes.
3.8 TIMERS
The DSPCPU contains four programmable timer/counters. All timer/counters have the same function. Thefirst three (TIMER1, TIMER2, TIMER3) are intended forgeneral use. The fourth timer/counter (SYSTIMER) is re-served for use by the system software and should not beused by applications.
Each timer has three registers as shown in Figure 3-10.The MMIO register addresses shown are offset address-es with respect to the timer’s base address.
Each timer/counter can be set to count one of the eventtypes specified in Table 3-12. Note that theDATABREAK event is special, in that the timer/countermay increment by zero, one or two in each clock cycle.For all other event types, increments are by zero or one.The CACHE1 and CACHE2 events serve as cache per-formance monitoring support. The actual event selectedfor CACHE1 and CACHE2 is determined by theMEM_EVENTS MMIO register, see Section 5.7, “Perfor-mance Evaluation Support.” If a TM1100 pin signal (VI-CLK, etc.) is selected as an event, positive-going edgeson the signal are counted.
Each timer increments its value until the modulus isreached. On the clock cycle where the incremented val-ue would equal or exceed the modulus, the value wrapsaround to zero or one (in the case of an increment bytwo), and an interrupt is generated as defined inTable 3-10. The timer interrupt source mode should beset as edge-sensitive. No software interrupt acknowl-edge to the timer device is necessary.
Counting starts and continues as long as the run bit isset.
Loading a new modulus does not affect the contents ofthe value register. If a store operation to either the mod-ulus or value register results in value and modulus beingthe same, no interrupt will be generated. If the run bit isset, the next value will be modulus+1 or modulus+2, and
Table 3-10. Interrupt Source Assignments
SOURCE NAME
SRC NUM MODE SOURCE DESCRIPTION
PCI INTA 0 level PCI_INTA# pin signal
PCI INTB 1 level PCI_INTB# pin signal
PCI INTC 2 level PCI_INTC# pin signal
PCI INTD 3 level PCI_INTD# pin signal
TRI_USERIRQ 4 either external general-purpose pin
TIMER1 5 edge general-purpose timer
TIMER2 6 edge general-purpose timer
TIMER3 7 edge general-purpose timer
SYSTIMER 8 edge reserved for debugger
VIDEOIN 9 level video in block
VIDEOOUT 10 level video out block
AUDIOIN 11 level audio in block
AUDIOOUT 12 level audio out block
ICP 13 level image co-processor
VLD 14 level VLD co-processor
SSI 15 level SSI interface
PCI 16 level PCI BIU (DMA, etc.; see Table 10-14 for possible interrupt causes)
IIC 17 level IIC interface
JTAG 18 level JTAG interface
t.b.d. 19..27 reserved for future devices
HOSTCOM 28 edge (software) host communi-cation
APP 29 edge (software) application
DEBUGGER 30 edge (software) debugger
RTOS 31 edge (software) RTOS
Figure 3-9. Host Interrupt Control register.
31 0
MMIO_BASEoffset:
0x10 3038371115192327
INT_CTL (r/w)
IS[D:A]IE[D:A]
INT[D:A]
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the counter will have to loop around before an interrupt isgenerated.
A modulus value of zero causes a wrap-around as if themodulus value was 232.
On RESET, the TCTL registers are cleared, and the val-ue of the TMODULUS and TVALUE registers is unde-fined.
3.9 DEBUG SUPPORT
This section describes the special debug support offeredby the DSPCPU. Instruction and data breakpoints can bedefined through a set of registers in the MMIO registerspace. When a breakpoint is matched, an event is gen-erated that can be used as a timer source (see Section3.8, “Timers”). The timer TMODULUS has to be set togenerate a DSPCPU interrupt after the desired numberof breakpoint matches.
3.9.1 Instruction Breakpoints
The instruction-breakpoint control register is shown inFigure 3-11. On RESET, the BICTL register is cleared.(MMIO-register addresses shown are offset with respectto MMIO_BASE.)
The instruction-breakpoint address-range registers areshown in Figure 3-12. After RESET, the value of theseregisters is undefined. (MMIO-register addresses shownare offset with respect to MMIO_BASE.)
When the IC bit in the breakpoint control register is set to‘1’, instruction breakpoints are activated. Any instructionaddress issued by the TM1100 chip is compared againstthe low and high address-range values. The IAC bit inthe breakpoint control register determines whether theinstruction address needs to be inside or outside of therange defined by the low and high address-range regis-ters. A successful comparison takes place when either:
• IAC = ‘0’ and low ≤ iaddr ≤ high, or• IAC = ‘1’ and iaddr < low or iaddr > high.
On a successful comparison, an instruction breakpointevent is generated, which can be used as a clock inputto a timer. After counting the programmed number of in-struction breakpoint events, the timer will generate an in-terrupt request.
Table 3-11. Timer base MMIO address
TIMER1 MMIO_BASE+0x10,0C00
TIMER2 MMIO_BASE+0x10,0C20
TIMER3 MMIO_BASE+0x10,0C40
SYSTIMER MMIO_BASE+0x10,0C60
Table 3-12. Timer Source Selections
Source NameSource
Bits Value
Source Description
CLOCK 0 CPU clock
PRESCALE 1 prescaled CPU clock
TRI_TIMER_CLK 2 external clock pin
DATABREAK 3 data breakpoints
INSTBREAK 4 instruction breakpoints
CACHE1 5 cache event 1
CACHE2 6 cache event 2
VI_CLK 7 video in clock pin
VO_CLK 8 video out clock pin
AI_WS 9 audio in word strobe pin
AO_WS 10 audio out word strobe pin
SSI_RXFSX 11 SSI receive frame sync pin
SSI_IO2 12 SSI transmit frame sync pin
— 13-15 undefined
MODULUSTMODULUS (r/w)031 0Timer base offset:
TVALUE (r/w)4
TCTL (r/w)8
371115192327
“PRESCALE”: Prescale value is 2^PRESCALE, i.e., in the range [1..32768]
“SOURCE” select:see table Table 3-12
VALUE
PRESCALE SOURCE
“RUN” bit: 0 Timer stopped 1 Timer running
R
Figure 3-10. Timer register definitions.
31 0
MMIO_BASEoffset:
BICTL (r/w)0x10 1000371115192327
“IAC” Instruction Address Control: 0 Breakpoint if address inside range 1 Breakpoint if address outside range
Figure 3-11. Instruction-breakpoint control register.
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3.9.2 Data Breakpoints
The data-breakpoint address-range and compare-valueregisters are shown in Figure 3-13. After RESET, the val-ue of the data breakpoint registers is undefined. (MMIO-register addresses shown are offset with respect toMMIO_BASE.)
The data-breakpoint control register is shown inFigure 3-14. On RESET, the BDCTL register is cleared.(The register address shown is offset with respect toMMIO_BASE.)
When the DC bits in the data breakpoint control registerare not set to ‘0’, data breakpoints are activated. Whenthe value of the DC bits is ‘1’ or ‘3’, any data address fromload operations (if the BL bit is set) and/or store opera-tions (if the BS bit is set) issued by the DSPCPU is com-pared against the low and high address-range values.The DAC bit in the breakpoint control register determineswhether data addresses need to be inside or outside of
the range defined by the low and high address-rangeregisters. A successful comparison occurs when either:
• DAC = ‘0’ and low ≤ daddr ≤ high, or • DAC = ‘1’ and daddr < low or daddr > high.
Note that this comparison works for all addresses re-gardless of the aperture to which they belong. When thevalue of the DC bits is ‘2’ or ‘3’, any data value from loadoperations (if the BL bit is set) and/or store operations (ifthe BS bit is set) issued by the TM1100 CPU is comparedagainst the value in the BDATAVAL register. Only thebits for which the corresponding BDATAMASK registerbits are set to ‘1’ will be used in the comparison. TheDVC bit in the breakpoint control register determineswhether the data value needs to be equal or not equal tothe comparison value. A successful comparison occurswhen either of the following are true:
Figure 3-13. Data-breakpoint address-range and value-compare registers.
31 0
MMIO_BASEoffset:
BDCTL (r/w)0x10 1020371115192327
“DVC” Data Value Control: 0 Breakpoint if data equal 1 Breakpoint if data not equal
DCBS BL
“BS” Break on Store: 0 Don’t check data stores 1 Do check data stores
“DAC” Data Address Control: 0 Breakpoint if address inside range 1 Breakpoint if address outside range
“BL” Break on Load: 0 Don’t check data loads 1 Do check data loads
“DC” Data Control: 0 No checking 1 Check data addresses 2 Check data values 3 Check data value and addresses
Figure 3-14. Data-breakpoint control register.
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Note: use a nonzero datamask or the result is undefined.
When a successful comparison has taken place, a databreakpoint event is generated, which can be used as aclock input to a timer. After counting the set number ofdata breakpoint events, the timer will generate an inter-rupt request.
When the value of the DC bits is equal to 3, a data break-point event is generated if and only if a successful com-parison occurs on both address and data simultaneous-ly.
Note that up to two data breakpoint events can occur perclock cycle, due to the dual load/store capability of theCPU and data cache.
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Custom Operations for Multimedia Chapter 4
by Gert Slavenburg, Pieter v.d. Meulen, Yong Cho, Sang-Ju Park
4.1 CUSTOM OPERATION OVERVIEW
Custom operations in the TM1100 DSPCPU architectureare specialized, high-function operations designed todramatically improve performance in important multime-dia applications. When properly incorporated into appli-cation source code, custom operations enable an appli-cation to take advantage of the highly parallel TM1100microprocessor implementation. Achieving a similar per-formance increase through other means—e.g., execut-ing a higher number of traditional microprocessor in-structions per cycle—would be prohibitively expensivefor TM1100’s low-cost target applications.
Custom operations are simple to understand and consis-tent in their definition, but their unusual functions make itdifficult for automatic code generation algorithms to usethem effectively. Consequently, custom operations areinserted into source code by the programmer. To makethis process as painless as possible, custom operationsyntax is consistent with the C programming language,and, just as with all other operations generated by thecompiler, the scheduler takes care of register allocation,operation packing, and flow analysis.
4.1.1 Custom Operation Motivation
For both general-purpose and embedded microproces-sor-based applications, programming in a high-level lan-guage is desirable. To effectively support optimizingcompilers and a simple programming model, certain mi-croprocessor architecture features are needed, such asa large, linear address space, general-purpose registers,and register-to-register operations that directly supportthe manipulation of linear address pointers. A commonchoice in microprocessor architectures is 32-bit linearaddresses, 32-bit registers, and 32-bit integer opera-tions. TM1100 is such a microprocessor architecture.
For the data manipulation in many algorithms, however,32-bit data and operations are wasteful of expensive sil-icon resources. Important multimedia applications, suchas the decompression of MPEG video streams, spendsignificant amounts of execution time dealing with eight-bit data items. Using 32-bit operations to manipulatesmall data items makes inefficient use of 32-bit executionhardware in the implementation. If these 32-bit resourcescould be used instead to operate on four eight-bit dataitems simultaneously, performance would be improvedby a significant factor with only a tiny increase in imple-mentation cost.
Getting the highest execution rate from standard micro-processor resources is one of the motivations behindcustom operations in TM1100. A range of custom opera-tions is provided that each process—simultaneously—four eight-bit or two sixteen-bit data items. There is littlecost difference between a standard 32-bit ALU and onethat can process either one pair of 32-bit operands orfour pairs of eight-bit operands, but there is a big perfor-mance difference for TM1100’s target applications.
TM1100’s custom operations go beyond simply makingthe best use of standard resources. Custom operationsthat combine several simple operations are provided.These combinations of operations are tailored specifical-ly to the needs of important multimedia applications.Some high-function custom operations eliminate condi-tional branches, which helps the scheduler make effec-tive use of all five operation slots in each TM1100 in-struction. Filling up all five slots is especially important inthe inner loops of computational intensive multimediaapplications.
In short, custom operations help TM1100 reach its goalsof extremely high multimedia performance at the lowestpossible cost.
4.1.2 Introduction to Custom Operations
Table 4-1 and Table 4-2 contain two listings of the cus-tom operations available in the TM1100 architecture.Table 4-1 groups the custom operations by type of func-tion while Table 4-2 lists the operations by operand size.For more detailed information about the custom opera-tions, Appendix A, “DSPCPU Operations for TM1100.”
Some operations exist in several versions that differ inthe treatment of their operands and results, and the mne-monics for these versions make it easy to select the ap-propriate operation. For example, the sum of productsoperations all have “fir” in their mnemonics; the prefixand suffix of the mnemonic expresses the treatment ofthe operands and result. The ifir8ii operation treats bothof its operands as signed (ifir8ii) and produces a signedresult (ifir8ii). The ifir8iu operation treats its first operandas signed (ifir8iu), the second as unsigned (ifir8iu), andproduces a signed result (ifir8iu). The ume8ii operationimplements an eight-bit motion-estimation; it treats bothoperands as signed but produces an unsigned result.
The operations beginning with “dsp” implement a clip-ping (sometimes called saturating) function before stor-ing the result(s) in the destination register. Otherwise,their naming follows the rules given above where appro-priate. For example, the dspuquadaddui operation imple-
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ments four eight-bit additions; it treats the first operand ofeach addition as unsigned, the second operand assigned, and produces an unsigned result for each addi-tion. Each result, which is computed with no loss of pre-cision, is clipped into the representable range of a byte(0..255).
Table 4-1. Key Multimedia Custom Operations Listed by Function Type
Function Custom Op Description
DSPabsolutevalue
dspiabs Clipped signed 32-bit absolute value
dspidualabs Dual clipped absolute values of signed 16-bit halfwords
Shift dualasr dual-16 arithmetic shift right
Clip dualiclipi dual-16 clip signed to signed
dualuclipi dual-16 clip signed to unsigned
Min,max quadumax Unsigned bytewise quad max
quadumin Unsigned bytewise quad min
DSP add dspiadd Clipped signed 32-bit add
dspuadd Clipped unsigned 32-bit add
dspidualadd Dual clipped add of signed 16-bit halfwords
dspuquadaddui Quad clipped add of unsigned/signed bytes
DSPmultiply
dspimul Clipped signed 32-bit multiply
dspumul Clipped unsigned 32-bit multi-ply
dspidualmul Dual clipped multiply of signed 16-bit halfwords
DSPsubtract
dspisub Clipped signed 32-bit subtract
dspusub Clipped unsigned 32-bit sub-tract
dspidualsub Dual clipped subtract of signed 16-bit halfwords
Sum ofproducts
ifir16 Signed sum of products of signed 16-bit halfwords
ifir8ii Signed sum of products of signed bytes
ifir8iu Signed sum of products of signed/unsigned bytes
ufir16 Unsigned sum of products of unsigned 16-bit halfwords
ufir8uu Unsigned sum of products of unsigned bytes
dspidualmul Dual clipped multiply of signed 16-bit halfwords
dspidualabs Dual clipped absolute values of signed 16-bit halfwords
dspidualadd Dual clipped add of signed 16-bit halfwords
dspidualsub Dual clipped subtract of signed 16-bit halfwords
ifir16 Signed sum of products of signed 16-bit halfwords
ufir16 Unsigned sum of products of unsigned 16-bit halfwords
pack16lsb Pack least-significant 16-bit halfwords
pack16msb Pack most-significant 16-bit halfwords
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4.1.3 Example Uses of Custom Ops
The next three sections illustrate the advantages of usingcustom operations. Also, the more complex examples il-lustrate how custom operations can be integrated intoapplication code by providing listings of C-language pro-gram fragments. The examples progress in complexityfrom simple to intricate; the most interesting examplesare taken from actual multimedia codes, such as MPEGdecompression.
4.2 EXAMPLE 1: BYTE-MATRIX TRANSPOSITION
The goal of this example is to provide a simple, introduc-tory illustration of how custom operations can significant-ly increase processing speed in small kernels of applica-tions. As in most uses of custom operations, the powerof custom operations in this case comes from their abilityto operate on multiple data items in parallel.
Imagine that our task is to transpose a packed, four-by-four matrix of bytes in memory; the matrix might, for ex-ample, contain eight-bit pixel values. Figure 4-1 illus-trates both the organization of the matrix in memory and,in standard mathematical notation, the task to be per-formed.
Performing this operation with traditional microprocessorinstructions is straight forward but time consuming. Oneway to perform the manipulation is to perform 12 load-byte instructions (since only 12 of the 16 bytes need tobe repositioned) and 12 store-byte instructions that placethe bytes back in memory in their new positions. Another
way would be to perform four load-word instructions, re-position the bytes in registers, and then perform fourstore-word instructions. Unfortunately, repositioning thebytes in registers would require a large number of in-structions to properly shift and mask the bytes. Perform-ing the 24 loads and stores makes implicit use of theshifting and masking hardware in the load/store units andthus yields a shorter instruction sequence.
The problem with performing 24 loads and stores is thatloads and stores are inherently slow operations becausethey must access at least the cache and possibly slowerlayers in the memory hierarchy. Further, performing byteloads and stores when 32-bit word-wide accesses runjust as fast wastes the power of the cache/memory inter-face. We would prefer a fast algorithm that takes full ad-vantage of cache/memory bandwidth while not requiringan inordinate number of byte-manipulation instructions.
TM1100 has instructions that merge and pack bytes and16-bit halfwords directly and in parallel. Four of these in-structions can be applied in this case to speed up themanipulation of bytes that are packed into words.
Figure 4-2 shows the application of these instructions tothe byte-matrix transposition problem, and the left side ofFigure 4-3 shows a list of the operations needed to im-plement the matrix transpose. When assembled into ac-tual TM1100 instructions, these custom operationswould be packed as tightly as dependencies allow, up tofive operations per instruction.
Note that a programmer would not need to program atthis level (TM1100 assembler). The matrix transposewould be expressed just as efficiently in C-languagesource code, as shown on the right side of Figure 4-3.The low-level code is shown here for illustration purpos-es only.
The first sequence of four load-word operations inFigure 4-3 brings the packed words of the input matrixinto registers R10, R11, R12, and R13. The next se-quence of four merge operations produces intermediateresults into registers R14, R15, R16, and R17. The nextsequence of four pack operations could then replace theoriginal operands or place the transposed matrix in sep-
8-bit quadumax Unsigned bytewise quad max
quadumin Unsigned bytewise quad min
dspuquadaddui Quad clipped add of unsigned/signed bytes
ifir8ii Signed sum of products of signed bytes
ifir8iu Signed sum of products of signed/unsigned bytes
ufir8uu Unsigned sum of products of unsigned bytes
mergelsb Merge least-significant bytes
mergemsb Merge most-significant bytes
packbytes Pack least-significant bytes
quadavg Unsigned byte-wise quad aver-age
quadumulmsb Unsigned quad 8-bit multiply most significant
ume8ii Unsigned sum of absolute val-ues of signed 8-bit differences
ume8uu Unsigned sum of absolute val-ues of unsigned 8-bit differ-ences
Table 4-2. Key Multimedia Custom Operations Listed by Operand Size
Op. Size Custom Op Description31 0
aei
m
bfjn
cgko
dhlp
abcd
efgh
ijkl
mnop
Row Major Column Major
Transpose
a b c d
e f g h
i j k l
m n o p
31 0
a e i m
b f j n
c g k o
d h l p
Transpose
n+0:
n+4:
n+8:
n+12:
MemoryLocation
Figure 4-1. Byte-matrix transposition. Top shows byte matrices packed into memory words; bottom shows mathematical matrix representation.
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arate registers if the original matrix operands were need-ed for further computations (the TM1100 optimizing Ccompiler performs this analysis automatically). In this ex-ample, the transpose matrix is placed in registers R18,R19, R20, and R21. The final four store-word operationsput the transposed matrix back into memory.
Thus, using the TM1100 custom operations, the byte-matrix transposition requires four load-word operationsand four store-word operations (the minimum possible)and eight register-to-register data-manipulation opera-tions. The result is 16 operations, or byte-matrix transpo-sition at the rate of one operation per byte.
While the advantage of the custom-operation-based al-gorithm over the brute-force code that uses 24 load- andstore-byte instruction seems to be only eight operations(a 33% reduction), the advantage is actually much great-er. First, using custom operations, the number of memo-ry references is reduced from 24 to eight (a factor ofthree). Since memory references are slower than regis-ter-to-register operations (such as the custom operationsin this example), the reduction in memory references issignificant.
Further, the ability of the TM1100 compiling system toexploit the performance potential of the TM1100 micro-processor hardware is enhanced by the custom-opera-tion-based code. This is because it is easier for the com-piling system to produce an optimal schedule(arrangement) of the code when the number of memoryreferences is in balance with the number of register-to-register operations. The TM1100 CPU (like all high-per-
formance microprocessors) has a limit on the number ofmemory references that can be processed in a single cy-cle (two is the current limit). A long sequence of code thatcontains only memory references can result in empty op-eration slots in the long TM1100 instructions. Empty op-eration slots waste the performance potential of theTM1100 hardware.
As this example has shown, careful use of custom oper-ations has the potential to not only reduce the absolutenumber of operations needed to perform a computationbut can also help the compiling system produce codethat fully exploits the performance potential of theTM1100 CPU.
4.3 EXAMPLE 2: MPEG IMAGE RECONSTRUCTION
The complete MPEG video decoding algorithm is com-posed of many different phases, each with computation-al intensive kernels. One important kernel deals with re-constructing a single image frame given that the forward-and backward-predicted frames and the inverse discretecosine transform (IDCT) results have already been com-puted. This kernel provides an excellent opportunity to il-lustrate of the power of TM1100’s specialized custom op-erators.
In the code fragments that follow, the backward-predict-ed block is assumed to have been computed into an ar-ray back[], the forward-predicted block is assumed to
aei
m
bfjn
cgko
dhlp
abcd
efgh
ijkl
mnop
Row Major Column Major
mergemsb
mergemsb
a e b f
i m j n
mergelsb
mergelsb
c g d h
k o l p
pack16msb
pack16lsb
pack16msb
pack16lsb
Figure 4-2. Application of merge and pack instructions to the byte-matrix transposition of Figure 4-1 .
Figure 4-3. On the left is a complete list of operations to perform the byte-matrix transposition of Figure 4-1 and Figure 4-2 . On the left is an equivalent C-language fragment.
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Philips Semiconductors Custom Operations for Multimedia
have been computed into forward[], and the IDCT resultsare assumed to have been computed into idct[].
A straightforward coding of the reconstruction algorithmmight look as shown in Figure 4-4. This implementationshares many of the undesirable properties of the first ex-ample of byte-matrix transposition. The code accessesmemory a byte at a time instead of a word at a time,which wastes 75% of the available bandwidth. Also, in
light of the many quad-byte-parallel operations intro-duced in Section 4.1.2, “Introduction to Custom Opera-tions,” it seems inefficient to spend three separate addi-tions and one shift to process a single eight-bit pixel.Perhaps even more unfortunate for a VLIW processorlike TM1100 is the branch-intensive code that performsthe saturation testing; eliminating these branches couldreap a significant performance gain.
Since MPEG decoding is the kind of task for whichTM1100 was created, there are two custom operations—quadavg and dspuquadaddui—that exactly fit this impor-tant MPEG kernel (and other kernels). These custom op-erations process four pairs of eight-bit pixel values in par-allel. In addition, dspuquadaddui performs saturationtests in hardware, which eliminates any need to executeexplicit tests and branches.
For readers familiar with the details of MPEG algorithms,the use of eight-bit IDCT values later in this example maybe confusing. The standard MPEG implementation callsfor nine-bit IDCT values, but extensive analysis hasshown that values outside the range [–128..127] occur
so rarely that they can be considered unimportant. Pur-suant to this observation, the IDCT values are clippedinto the eight-bit range [–128..127] with saturating arith-metic before the frame reconstruction code runs. The as-sumption that this saturation occurs permits some ofTM1100’s custom operations to have clean, simple defi-nitions.
The first step in seeing how custom operations can be ofvalue in this case, is to unroll the loop by a factor of four.The unrolled code is shown in Figure 4-5. This createscode that is parallel with respect to the four pixel compu-tations. As it is easily seen in the code, the four groups of
void reconstruct (unsigned char *back, unsigned char *forward, char *idct, unsigned char *destination) int i, temp;
for (i = 0; i < 64; i += 1) temp = ((back[i] + forward[i] + 1) >> 1) + idct[i];
if (temp > 255) temp = 255; else if (temp < 0) temp = 0;
destination[i] = temp;
Figure 4-4. Straightforward code for MPEG frame reconstruction.
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computations (one group per pixel) do not depend oneach other.
After some experience is gained with custom operations,it is not necessary to unroll loops to discover situationswhere custom operations are useful. Often, a good pro-grammer with knowledge of the function of the customoperations can see by simple inspection opportunities toexploit custom operations.
To understand how quadavg and dspuquadaddui can beused in this code, we examine the function of these cus-tom operations.
The quadavg custom operation performs pixel averagingon four pairs of pixels in parallel. Formally, the operationof quadavg is as follows:
quadavg rscr1 rsrc2 -> rdest
takes arguments in registers rsrc1 and rsrc2, and it com-putes a result into register rdest. rsrc1 = [abcd], rsrc2 =[wxyz], and rdest = [pqrs] where a, b, c, d, w, x, y, z, p, q,r, and s are all unsigned eight-bit values. Then, quadavgcomputes the output vector [pqrs] as follows:
p = (a + w + 1) >> 1q = (b + x + 1) >> 1r = (c + y + 1) >> 1s = (d + z + 1) >> 1
The pixel averaging in Figure 4-5 is evident in the firststatement of each of the four groups of statements. Therest of the code—adding idct[i] value and performing thesaturation test—can be performed by the dspuquadad-dui operation. Formally, its function is as follows:
dspuquadaddui rsrc1 rsrc2 -> rdest
takes arguments in registers rsrc1 and rsrc2, and it com-putes a result into register rdest. rsrc1 = [efgh], rsrc2 =[stuv], and rdest = [ijkl] where e, f, g, h, i, j, k, and l are
unsigned eight-bit values; s, t, u, and v are signed eight-bit values. Then, dspuquadaddui computes the outputvector [ijkl] as follows:
The uclipi operation is defined in this case as it is for theseparate TM1100 operation of the same name describedin Appendix A, “DSPCPU Operations for TM1100,”. Itsdefinition is as follows:
uclipi (m, n) if (m < 0) return 0; else if (m > n) return n; else return m;
To make is easier to see how these operations can sub-sume all the code in Figure 4-5, Figure 4-6 shows thesame code rearranged to group the related functions.Now it should be clear that the quadavg operation can re-place the first four lines of the loop assuming that we canget the individual 8-bit elements of the back[] and for-ward[] arrays positioned correctly into the bytes of a 32-bit word. That, of course, is easy: simply align the byte ar-rays on word boundaries and access them with word (in-teger) pointers.
Similarly, it should now be clear that the dspuquadadduioperation can replace the remaining code (except, ofcourse, for storing the result into the destination[] array)assuming, as above, that the 8-bit elements are alignedand packed into 32-bit words.
Figure 4-7 shows the new code. The arrays are now ac-cessed in 32-bit (int-sized) chunks, the loop iteration con-trol has been modified to reflect the “four-at-a-time” oper-
void reconstruct (unsigned char *back, unsigned char *forward, char *idct, unsigned char *destination) int i, temp;
for (i = 0; i < 64; i += 4) temp = ((back[i+0] + forward[i+0] + 1) >> 1) + idct[i+0]; if (temp > 255) temp = 255; else if (temp < 0) temp = 0; destination[i+0] = temp;
Figure 4-5. MPEG frame reconstruction code using TM1100 custom operations; compare with Figure 4-4 .
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Philips Semiconductors Custom Operations for Multimedia
ations, and the quadavg and dspuquadaddui operationshave replaced the bulk of the loop code. Finally,Figure 4-8 shows a more compact expression of the loop
code, eliminating the temporary variable (Note thatTM100 C compiler does the optimization by itself).
Again, note that the code in Figure 4-7 and Figure 4-8assumes that the character arrays are 32-bit wordaligned and padded if necessary to fill an integral numberof 32-bit words.
The original code required three additions, one shift, twotests, three loads, and one store per pixel. The new codeusing custom operations requires only two custom oper-
ations, three loads, and one store for four pixels, which ismore than a factor of six improvement. The actual perfor-mance improvement can be even greater depending onhow well the compiler is able to deal with the branches inthe original version of the code, which depends in part onthe surrounding code. Reducing the number of branches
void reconstruct (unsigned char *back, unsigned char *forward, char *idct, unsigned char *destination) int i, temp0, temp1, temp2, temp3;
void reconstruct (unsigned char *back, unsigned char *forward, char *idct, unsigned char *destination) int i, temp;
int *i_back = (int *) back; int *i_forward = (int *) forward; int *i_idct = (int *) idct; int *i_dest = (int *) destination;
for (i = 0; i < 16; i += 1) temp = QUADAVG(i_back[i], i_forward[i]);
temp = DSPUQUADADDUI(temp, i_idct[i]);
i_dest[i] = temp;
Figure 4-7. Using the custom operation dspquadaddui to speed up the loop of Figure 4-6 .
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almost always improves the chances of realizing maxi-mum performance on the TM1100 CPU.
The code in Figure 4-8 illustrates several aspects of us-ing custom operations in C-language source code. First,the custom operations require no special declarations orsyntax; they appear to be simple function calls. Second,there is no need to explicitly specify register assignmentsfor sources, destinations, and intermediate results; thecompiler and scheduler assign registers for custom oper-ations just as they would for built-in language operationssuch as integer addition. Third, the scheduler packs cus-tom operations into TM1100 VLIW instructions as effec-tively as it packs operations generated by the compilerfor native language constructs.
Thus, although the burden of making effective use ofcustom operations falls on the programmer, that burdenconsists only of discovering the opportunities for exploit-ing the operations and then coding them using standardC-language notation. The compiler and scheduler takecare of the rest.
4.4 EXAMPLE 3: MOTION-ESTIMATION KERNEL
Another part of the MPEG coding algorithm is motion es-timation. The purpose of motion estimation is to reducethe cost of storing a frame of video by expressing thecontents of the frame in terms of adjacent frames. A giv-en frame is reduced to small blocks, and a subsequentframe is represented by specifying how these smallblocks change position and appearance; usually, storingthe difference information is cheaper than storing a
whole block. For example, in a video sequence wherethe camera pans across a static scene, some frames canbe expressed simply as displaced versions of their pre-decessor frames. To create a subsequent frame, mostblocks are simply displaced relative to the output screen.
The code in this example is for a match-cost calculation,a small kernel of the complete motion-estimation code.As with the previous example, this code provides an ex-cellent example of how to transform source code to makethe best use of TM1100’s custom operations.
Figure 4-9 shows the original source code for the match-cost loop. Unlike the previous example, the code is not aself-contained function. Somewhere early in the code,the arrays A[][] and B[][] are declared; somewhere be-tween those declarations and the loop of interest, the ar-rays are filled with data.
4.4.1 A Simple Transformation
First, we will look at the simplest way to use a TM1100custom operation.
We start by noticing that the computation in the loop ofFigure 4-9 involves the absolute value of the differenceof two unsigned characters (bytes). By now, we are fa-miliar with the fact that TM1100 includes a number of op-erations that process all four bytes in a 32-bit word simul-taneously. Since the match-cost calculation isfundamental to the MPEG algorithm, it is not surprisingto find a custom operation—ume8uu—that implementsthis operation exactly.
To understand how ume8uu can be used in this case, weneed to transform the code as in the previous example.
Figure 4-9. Match-cost loop for MPEG motion estimation.
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Though the steps are presented here in detail, a pro-grammer with a even a little experience can often per-form these transformations by visual inspection.
If we hope to use a custom operation that processes fourpixel values simultaneously, we first need to create fourparallel pixel computations. Figure 4-10 shows the loopof Figure 4-9 unrolled by a factor of four. Unfortunately,the code in the unrolled loop is not parallel because eachline depends on the one above it.
Figure 4-11 shows a more parallel version of the codefrom Figure 4-10. By simply giving each computation itsown cost variable and then summing the costs all atonce, each cost computation is completely independent.
Excluding the array accesses, the loop body inFigure 4-11 is recognizable now as exactly the functionperformed by the ume8uu custom operation: the sum offour absolute values of four differences. To use theume8uu operation, however, the code must access thearrays with 32-bit word pointers instead of with 8-bit bytepointers.
Figure 4-12 shows the loop recoded to access A[][] andB[][] as one-dimensional instead of as two-dimensionalarrays. We take advantage of our knowledge of C-lan-guage array storage conventions to perform this codetransformation. Recoding to use one-dimensional arraysprepares the code for the transformation to 32-bit arrayaccesses.
(From here on, until the final code is shown, the declara-tions of the A and B arrays will be omitted from the codefragments for the sake of brevity.)
Figure 4-13 shows the loop of Figure 4-12 recoded touse ume8uu. Once again taking advantage of our knowl-edge of the C-language array storage conventions, theone-dimensional byte array is now accessed as a one-di-mensional 32-bit-word array. The declarations of thepointers IA and IB as pointers to integers is the key, butalso notice that the multiplier in the expression for rowoff-set has been scaled from 16 to four to account for the factthat there are four bytes in a 32-bit word.
Of course, since we are now using one-dimensional ar-rays to access the pixel data, it is natural to use a singlefor loop instead of two. Figure 4-14 shows this stream-lined version of the code without the inner loop. Since C-language arrays are stored as a linear vector of values,we can simply increase the number of iterations of theouter loop from 16 to 64 to traverse the entire array.
The recoding and use of the ume8uu operation has re-sulted in a substantial improvement in the performanceof the match-cost loop. In the original version, the code
Figure 4-14. The loop of Figure 4-13 with the inner loop eliminated.
unsigned int *IA = (unsigned int *) A;unsigned int *IB = (unsigned int *) B;
for (i = 0; i < 64; i += 1) cost += UME8UU(IA[i], IB[i]);
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executed 1280 operations (including loads, adds, sub-tracts, and absolute values); in the restructured version,there are only 256 operations—128 loads, 64 ume8uuoperations, and 64 additions. This is a factor of five re-duction in the number of operations executed. Also, theoverhead of the inner loop has been eliminated, furtherincreasing the performance advantage.
4.4.2 More Unrolling
The code transformations of the previous sectionachieved impressive performance improvements, butgiven the VLIW nature of the TM1100 CPU, more can bedone to exploit TM1100’s parallelism.
The code in Figure 4-14 has a loop containing only fouroperations (not counting the loop overhead). SinceTM1100’s branches have a delay of three instructionsand each instruction can contain up to five operations, afully utilized minimum-sized loop can contain 16 opera-tions (20 minus the loop overhead).
The TM1100 compiling system performs a wide varietyof powerful code transformation and scheduling optimi-zations to ensure that the VLIW capabilities of the CPUare exploited. It is still wise, however, to make programparallelism explicit in source code when possible. Explicitparallelism can only help the compiler produce a fast run-ning program.
To this end, we can unroll the loop of Figure 4-14 somenumber of times to create explicit parallelism and helpthe compiler create a fast running loop. In this case,
where the number of iterations is a power-of-two, itmakes sense to unroll by a factor that is a power-of-twoto create clean code.
Figure 4-15 shows the loop unrolled by a factor of eight.The compiler can apply common subexpression elimina-tion and other optimizations to eliminate extraneous op-erations in the array indexing, but, again, improvementsin the source code can only help the compiler producethe best possible code and fastest-running program.
Figure 4-16 shows one way to modify the code for sim-pler array indexing.
Figure 4-12. The loop of Figure 4-11 recoded with one-dimensional array accesses.
Figure 4-15. Unrolled version of Figure 4-14 . This code makes good use of TM1100’s VLIW capabili-ties.
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Cache Architecture Chapter 5
by Eino Jacobs
5.1 MEMORY SYSTEM OVERVIEW
The high-performance video and audio throughput ofTM1100 is implemented by the DSPCPU and the auton-omous I/O and graphics units, but the foundation of thisprocessing is the TM1100 memory hierarchy. To get thefull potential of the chip’s processing units, the memoryhierarchy must read and write data (and instructions forthe DSPCPU) fast enough to keep the units busy.
To meet the requirements of its target applications,TM1100’s memory hierarchy must satisfy the conflictinggoals of low cost, simple system design (e.g., low partscount), and high performance. Since multimedia videostreams can require relatively large temporary storage, asignificant amount of external DRAM is required. Keep-ing the cost of this bulk memory as low as possible is im-portant.
TM1100’s memory system achieves a good compromisebetween cost and performance by coupling substantialon-chip caches with a glueless interface to synchronousDRAM (SDRAM), which provides higher bandwidth thanstandard DRAM for only a small cost premium. A blockdiagram of the memory system is shown in Figure 5-1.The high bandwidth of SDRAM permits TM1100 to use anarrower and simpler interface than would be required toachieve similar performance with standard DRAM.
The separate on-chip data and instruction caches serveonly the DSPCPU since the data access patterns of the
autonomous I/O and graphics units exhibit little or no lo-cality of reference (they access each piece of the multi-media data stream once only in each operation).
Without the caches, the CPU would not be able toachieve its performance potential. SDRAM has enoughbandwidth to handle serial streams of multimedia data,but its bandwidth and latency are insufficient to satisfythe CPU’s high rate of random data accesses and re-peated instruction accesses.
Table 5-1 shows bandwidth parameters for the TM1100DSPCPU and the main-memory interface. Although 400MB/s is a lot of bandwidth, it is clear that the SDRAMalone cannot keep up with the CPU’s maximum require-ments for instructions and data. Luckily, multimedia algo-rithms resemble other computer programs in terms of lo-cality of reference, so the on-chip caches typically supplythe majority of instructions and data to the DSPCPU. The
VLIWCPU
ThreeBranchUnits
Decompressor
32KB, 8-wayInstruction
Cache
TwoMemory
Units
16KB, 8-wayData
Cache
Three sets, each has address,opcode, condition, & guard
224 bits of decompressedinstruction
Two sets, each has: guard, opcode, data, and two address components
MainMemoryInterface
SDRAMMain
Memory
Internal data highway:32-bit address, 32-bit data
To on-chip peripherals
Main-memory bus: glueless, SDRAM control with 32-bit data
Figure 5-1. The main components of the TM1100 memory system.
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wide paths to the caches are matched to the bandwidthrequirements of the DSPCPU.
To improve cache behavior and thus program perfor-mance, the caches have a locking mechanism. In addi-tion, the instruction cache is coupled with an instructiondecompression unit. The compressed instruction formatimproves the cache hit rate and reduces the bus band-width required between main memory and cache. In-structions in main memory and cache use the com-pressed format.
TM1100’s processing units access the external SDRAMthrough the on-chip central “data highway” bus. Thehighway consists of separate 32-bit address and data
buses, and use of the bus is mediated by the main-mem-ory interface unit. The main-memory interface containsthe SDRAM controller and a central arbiter that deter-mines how much of the available SDRAM memory band-width is allocated to each unit. Unused bandwidth is al-ways made available to the VLIW CPU for cache refilland memory accesses that bypass the caches.
Table 5-2 gives a summary description of each compo-nent of TM1100’s memory system.
5.2 DRAM APERTURE
TM1100 implements a 32-bit linear address space ofbytes. Within that address space, TM1100 supports sev-eral different apertures for specific purposes. The DRAMaperture describes the part of the address space intowhich the external SDRAM is mapped. SDRAM mustconsist of a single, contiguous region of memory, whichis the most practical configuration for TM1100 systems.
The location and size of the DRAM aperture is defined bytwo registers, DRAM_BASE and DRAM_LIMIT. Theseregisters are both readable and writeable as MMIO reg-isters and as PCI configuration space registers. The viewof the registers in MMIO space is shown in Figure 5-2.The view of the registers in PCI configuration space isdescribed in Chapter 10, “PCI Interface.” In normal oper-ation, the base address registers are assigned once dur-ing boot, and not changed when the DSPCPU is running.Refer to Chapter 10, “PCI Interface,” and Chapter 12,“System Boot,” for a description of this process.
DRAM_LIMIT must be set equal to DRAM_BASE plusthe actual size of SDRAM present. The amount of theSDRAM is not required to be a power of two, but it mustbe a multiple of 64 KB. Note that the size of the apertureas set in the PCI configuration space can be larger, be-cause it must be a power of 2.
A memory operation will access SDRAM if its addresssatisfies:
[DRAM_BASE] ≤ address < [DRAM_LIMIT]
Any address outside this range cannot access SDRAM.
When TM1100 is reset, DRAM_BASE_FIELD is set to0x0 and DRAM_LIMIT is set to 0x0010 0000 (1-MBDRAM aperture starting at address 0x0). The boot pro-cess described in Chapter 12, “System Boot,” overridesthese initial settings.
5.3 DATA CACHE
The data cache serves only the DSPCPU and is con-trolled by two memory units that execute the load andstore operations issued by the DSPCPU. The following
Table 5-2. Summary Of Memory System Characteristics
Unit Description
Branch units Branch units execute branch operations. Up to three branch operations can be executed in parallel, but the program must guarantee that only one branch is taken.
Decompres-sion unit
Instructions are stored in memory and in the instruction cache in a space-saving, com-pressed format. The decompression unit expands instruction to their full, 28-byte size before they are issued to the CPU.
Instruction Cache
The instruction cache holds 32K bytes, is eight-way set-associative, and has a 64-byte block size. A miss in a block causes the entire block to be read from SDRAM. The cache can sustain an issue rate of one instruction per cycle on cache hits.
Memory units Memory units execute load and store opera-tions. The data cache is dual ported to allow the memory units to operate concurrently.
Data Cache The data cache holds 16K bytes, is eight-way set-associative, has a 64-byte block size, and implements a copyback, allocate-on-write pol-icy. A miss in a block causes the entire block to be read from SDRAM. The cache supports memory-mapped I/O through non-cacheable address regions.
Data highway The on-chip data highway bus serves all on-chip units. The highway has separate 32-bit data and address buses. Bandwidth on the bus is allocated by the highway arbiter accord-ing to one of several modes.
Main-memoryinterface
The main-memory interface contains the data-highway access arbiter, the SDRAM control-ler, and MMIO logic.
SDRAM main memory
External SDRAM connects gluelessly to TM1100 over the 32-bit main-memory bus.
31 0371115192327
DRAM_BASE (r/w)0x10 0000 DRAM_BASE_FIELD
DRAM_LIMIT (r/w)0x10 0004 DRAM_LIMIT_FIELD
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
MMIO_BASEoffset:
0000
Figure 5-2. Formats of the DRAM_BASE and DRAM_LIMIT registers.
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sections describe the data cache and its operation;Table 5-3 summarizes the important characteristics foreasy reference.
5.3.1 General Cache Parameters
The data cache on TM1100 is 16 KB in size with a 64-Bblock size. Thus, the cache contains 256 blocks each
with its own address tag. The cache is eight-way set-as-sociative, so there are 32 sets, each containing eighttags. A single valid bit is associated with a block, so eachblock and associated address tag is either entirely validin the cache or invalid; on a cache miss, 64 bytes areread from SDRAM to make the entire block valid.
Each block also contains a dirty bit, which is set whenev-er a write to the block occurs. Each set contains ten bitsto support the hierarchical LRU replacement policy.
The geometry of the data cache is available to softwareby reading the MMIO register DC_PARAMS, which hasthe format shown in Figure 5-3. Table 5-4 lists the fieldvalues for TM1100’s DC_PARAMS register.
The product of the block size, associativity, and numberof sets gives the total cache size (16 KB in this case).
5.3.2 Address Mapping
TM1100 data addresses are mapped onto the datacache storage structure as shown in Figure 5-4. A dataaddress is partitioned into four fields as described inTable 5-5.
Table 5-3. Summary Of Data Cache Characteristics
Characteristic TM1100 Implementation
Cache size 16K bytes
Cache associativity 8-way set-associative
Block size 64 bytes
Valid bits One valid bit per 64-byte block
Dirty bits One dirty bit per 64-byte block
Miss transfer order Miss transfers begin with the critical word first.
Replacement poli-cies
Copyback, allocate on write, hierarchical LRU
Endianness Either little- or big-endian, determined by PCSW bit
Ports The cache is quasi dual ported; two accesses can proceed concurrently if they reference different banks (deter-mined by bits [4:2] of the computed addresses)
Alignment Access must be naturally aligned (32-bit words on 32-bit boundaries, 16-bit half-words on 16-bit boundaries); the appro-priate number of LSBs of un-naturally aligned addresses are set to zero.For misaligned stores, PCSW.MSE is asserted to generate an exception
Partial word opera-tions
The cache implements 8-bit and 16-bit accesses with the same performance as 32-bit accesses
Operation latency Three cycles for both load and store operations
Coherency enforce-ment
Software uses special operations to enforce cache coherency
Cache locking Up to 1/2 (four out of 8 blocks of each set) of the cache contents can be locked; granularity is 64-byte
Non-cacheable region
One non-cacheable aperture in the DRAM address space is supported.
Table 5-4. DC_PARAMS Field Values
Field Name Value
BLOCKSIZE 64
ASSOCIATIVITY 8
NUMBER_OF_SETS 32
Table 5-5. Data Address Field Partitioning
Field Address Bits Purpose
Byte 1..0 Byte offset within a word for byte or half-word accesses
Word 5..2 Selects one of the words in a set (one of 16 words in the case of TM1100)
Set 10..6 Selects one of the sets in the cache (one of 32 in the case of TM1100)
Tag 31..11 Compared against address tags of set members
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5.3.3 Miss Processing Order
When a miss occurs, the data cache fills the block con-taining the requested word from the critical word first.The CPU is stalled until the first word is transferred. Theblock is then filled up while the CPU keeps running.
5.3.4 Replacement Policies, Coherency
The cache implements a copyback replacement policywith one dirty bit per 64-B block. Thus, when a miss oc-curs and the block selected for replacement has its dirtybit set, the dirty block must be written to main memory topreserve its modified contents. On TM1100, the dirtyblock is written to memory before the needed block isfetched.
Coherency is not maintained in any way by hardware be-tween the data cache, the instruction cache, and mainmemory. Special operations are available to implementcache coherency in software. See Section 5.6, “CacheCoherency,” for a discussion of coherency issues.
Write misses are handled with an allocate-on-write poli-cy—the write that caused the miss stores its data in thecache after the missing block is fetched into the cache.
The cache implements a hierarchical LRU replacementalgorithm to determine which of the eight elements(blocks) in a set is replaced. The algorithm partitions theeight set elements into four groups, each group with twoelements. The hierarchical LRU replacement victim isdetermined by selecting the least-recently used group oftwo elements and then selecting the least-recently usedelement in that group. This hierarchical algorithm yieldsperformance close to full LRU but is simpler to imple-ment.
See Section 5.5, “LRU Algorithm,” for a full discussion ofthe LRU algorithm.
The cache implements 32-bit word, 16-bit half-word, and8-bit byte transfers. All transfers, however, must be toaddresses that are naturally aligned; that is, 32-bit wordsmust be aligned on 32-bit boundaries, and 16-bit half-words must be aligned on 16-bit boundaries.
As TM1100’s other processing units, the CPU have thecapability to use either big- or little-endian byte order.Detailed endian-ness description can be found in Appen-dix C, “Endian-ness.”
5.3.6 Dual Ports
To allow two accesses to proceed in parallel, the datacache is quasi-dual ported. The cache is implemented aseight banks of single-ported memory, but the hardwareallows each bank to operate independently. Thus, whenthe addresses of two simultaneous accesses select twodifferent banks, both accesses can complete simulta-neously. Bank selection is determined by the three low-order address bits [4..2] of each address. Thus, thewords in a 64-byte cache block are distributed among theeight blocks, which prevents conflicts between two simul-taneously issued accesses to adjacent words in a cacheblock. The TM1100 compiling system attempts to avoidbank conflicts as much as possible.
The dual-ported cache can execute the load and storeopcodes (ild8d, uld8d, ild16d, uld16d, ld32d, h_st8d,h_st16d, h_st32d, ild8r, uld8r, ild16r, uld16r, ld32r,ild16x, uld16x, ld32x) in either or both of the two ports.
The special opcodes alloc, dcb, dinvalid, pref, rdtag andrdstatus can only be executed in the second port, not inthe first port. Whenever any of these special opcodes isissued in the second port, there should not be a concur-rent load or store operation in the first. This is a specialscheduling constraint.
5.3.7 Cache Locking
The data cache allows the contents of up to one-half ofits blocks to be locked. Thus, on TM1100, up to 8K bytesof the cache can be used as a high-speed local datamemory. Only four out of eight blocks in any set can belocked.
A locked block is never chosen as a victim by the re-placement algorithm; its contents remain undisturbeduntil either (1) the block’s locked status is changed ex-plicitly by software, or (2) a dinvalid operation is executedthat targets the locked block.
Cache locking occurs only for the data in the addressrange described by the MMIO registersDC_LOCK_ADDR and DC_LOCK_SIZE. The granulari-ty of the address range is one 64-byte cache block. TheMMIO register DC_LOCK_CTL contains the cache-lock-ing enable bit DC_LOCK_ENABLE. Figure 5-5 showsthe layout of the data-cache lock registers. Locking willoccur for an address if locking is enabled and both of thefollowing are true:
1. The address is greater than or equal to the value in DC_LOCK_ADDR.
Figure 5-5. Formats of the registers in charge of data-cache locking.
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2. The address is less than the sum of the values in DC_LOCK_ADDR and DC_LOCK_SIZE.
Programmers (or compilers) must combine all data thatneeds to be locked into this single linear address range.
Setting DC_LOCK_ENABLE to ‘1’ causes the followingsequence of events:
1. All blocks that are in cache locations that will be used for locking are copied back to main memory (if they are dirty) and removed from the cache.
2. All blocks in the lock range are fetched from main memory into the cache. If any block in the lock range was already in the cache, it’s first copied back (if it’s dirty) and invalidated.
3. The LRU status of any set that contains locked blocks is set to the initialization value.
4. Cache locking is activated so that the locked blocks cannot be victims of the replacement algorithm.
This sequence of events is triggered by writing ‘1’ toDC_LOCK_ENABLE even if the enable is already set to‘1’. Setting DC_LOCK_ENABLE to ‘0’ causes no actionexcept to allow the previously locked blocks to be re-placement victims.
To program a new lock range, the following sequence ofoperations is used:
1. Disable cache locking by writing ‘0’ to DC_LOCK_ENABLE.
2. Define a new lock range by writing to DC_LOCK_ADDR and DC_LOCK_SIZE.
3. Enable cache locking by writing ‘1’ to DC_LOCK_ENABLE.
Dirty locked blocks can be written back to main memorywhile locking is enabled by executing copyback opera-tions in software.
Programmer’s note: Software should not execute din-valid operations on a locked block. If it does, the blockwill be removed from the cache, creating a ‘hole’ in thelock range (and the data cache) that cannot be reuseduntil locking is deactivated.
Cache locking is disabled by default when TM1100 is re-set.
The RESERVED field in DC_LOCK_CTL should be ig-nored on reads and written as all zeroes.
Locking should not be enabled by PCI accesses to theMMIO registers.
5.3.8 Memory Hole and PCI Aperture Disable
Bits 6 and 5 in DC_LOCK_CTL comprise theAPERTURE_CONTROL field. This field can be used to
change the memory map as seen by the DSPCPU. Thehardware RESET value of the field corresponds to thememory map as described in Section 3.4.1, “MemoryMap.”
5.3.9 Non-Cacheable Region
The data cache supports one non-cacheable address re-gion within the DRAM address space aperture. The baseaddress of this region is determined by the value in theDRAM_CACHEABLE_LIMIT MMIO register, which isshown in Figure 5-6. Since uncached memory opera-tions always incur many stall cycles, the non-cacheableregion should be used sparingly.
A memory operation is non-cacheable if its target ad-dress satisfies:
[dram_cacheable_limit] <= address < [dram_limit]
Thus, the non-cacheable region is at the high end of theDRAM aperture. The format of theDRAM_CACHEABLE_LIMIT register forces the size ofthe non-cacheable region to be a multiple of 64 KB.
When TM1100 is reset, DRAM_CACHEABLE_LIMIT isset equal to DRAM_LIMIT, which results in a zero-lengthnon-cacheable region.
Programmer’s note: When DRAM_CACHEABLE_LIMITis changed to enlarge the region that is non-cacheable,software must assure coherency. This is accomplishedby explicitly copying back dirty data (using dcb opera-tions) and invalidating (using dinvalid operations) thecache blocks in the previously unlocked region.
5.3.10 Special Data Cache Operations
A program can exercise some control over the operationof the data cache by executing special operations. Thespecial operations can cause the data cache to initiatethe copyback or invalidation of a block in the cache.
Table 5-6. Aperture Control field
value Memory Map properties
00 (RESET) normal operation memory map (Section 3.4.1):• loads to 0..0xff always return 0 and cause no
PCI read (memory hole is enabled)• PCI aperture(s) are enabled
01 • loads to address 0..0xff cause a PCI read, i.e. the memory hole is disabled
• PCI aperture(s) are enabled
10 PCI apertures are disabled for both loads and stores• loads return a 0 and cause no PCI read• stores have no effect
Figure 5-6 Formats of the DRAM_CACHEABLE_LIMIT register.
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These operations are typically used by software to keepthe cache coherent with main memory.
In addition, there are special operations that allow a pro-gram to read tag and status information from the datacache.
Special data cache operations are always executed onthe memory port associated with issue slot 5.
5.3.10.1 Copyback and Invalidate Operations
The data cache controller recognizes a copyback and aninvalidate operation as shown in Table 5-7.
The dcb and dinvalid operations both compute a targetword address that is the sum of a register and seven-bitoffset. The offset can be in the range [–256..252] andmust be divisible by four.
dcb operation. The dcb operation computes the targetaddress, and if the block containing the address is foundin the data cache, its contents are written back to mainmemory if the block is both valid and dirty. If the block isnot present, not valid, or not dirty, no action results fromthe dcb operation. If the dcb causes a copyback to occur,the CPU is stalled until the copyback completes. If theblock is not in cache, the operation causes no stall cy-cles. If the block is in cache but not dirty, the operationcauses 4 stall cycles. If the block is dirty, then the dcb op-eration causes a writeback and takes at least 19 stall cy-cles.
The dcb operation clears the dirty bit but leaves a validcopy of the written-back block in the cache.
dinvalid operation. The dinvalid operation computesthe target address, and if the block containing the ad-dress is found in the data cache, its valid and dirty bitsare cleared. No copyback operation will occur even if theblock is valid and dirty prior to executing the dinvalid op-eration. The CPU is stalled for 2 cycles, if the target blockis in the cache; otherwise, no stall cycles occur.
A dinvalid or dcb operation updates the LRU informationto least recently used in its set.
Programmer’s note: Software should not execute din-valid operations on locked blocks; otherwise, a ‘hole’ iscreated that cannot be reused until locking is deactivat-ed.
5.3.10.2 Data-Cache Tag and Status Operations
The data cache controller recognizes two DSPCPU op-erations for reading cache status as shown in Table 5-8.
The rdtag and rdstatus operations both compute a targetword address that is the sum of a register and scaledseven-bit offset. The offset must be divisible by four andin the range [–256..252].
rdtag operation. The target address computed by rdtagselects the data cache block by specifying the cache setand set element directly. Address bits [10..6] specify thecache set (one of 32), and bits [13..11] specify the set el-ement (one of eight). All other target address bits are ig-nored. This operation causes no CPU stall cycles.
The result of the rdtag operation is a full 32-bit word withthe format shown in Figure 5-7.
rdstatus operation. The target address computed by rd-status selects the data cache set by specifying the setnumber directly. Address bits [10..6] specify the cacheset (one of 32); all other target address bits are ignored.This operation causes 1 CPU stall cycle.
The result of the rdstatus operation is a full 32-bit wordwith the format shown in Figure 5-7. See Section 5.5.4,“LRU Bit Definitions,” for a description of the LRU bits.
5.3.10.3 Data-Cache Allocation Operation
The data cache controller recognizes allocation opera-tions as shown in Table 5-9. The allocation operations al-
Table 5-7. Copyback And Invalidate Operations
Mnemonic Description
dcb(offset) rsrc1 Data-cache copyback block. Causes the block that contains the target address to be copied back to main memory if the block is valid and dirty.
dinvalid(offset) rsrc1 Data-cache invalidate block. Causes the block that contains the target address to be invalidated. No copy-back occurs even if the block is dirty.
Table 5-8. Cache Read-Status Operations
Mnemonic Description
rdtag(offset) rsrc1 Read data-cache tag. The target address selects a data-cache block directly; the operation returns a 32-bit result containing the 21-bit cache tag and the valid bit.
rdstatus(offset) rsrc1 Read data-cache status. The target address selects a data-cache set directly; the operation returns a 32-bit result containing the set’s eight dirty bits and ten LRU bits.
31 0371115192327
VALID
rdtag Result Format TAG
rdstatus Result Format LRUDIRTY0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0
0 0 0
Figure 5-7. Result formats for rdtag and rdstatus operations.
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locate a block and set the status of this block to valid. Nodata is fetched from main memory. The allocated blockis undefined after this operation. The programmer has tofill it with valid data by store operations. Allocation oper-ations to other apertures than cacheable DRAM will bediscarded. Allocation of a non-dirty block causes 3 stallcycles. Allocation of a dirty block will cause writeback ofthis block to the SDRAM and take at least 11 stall cycles.
5.3.10.4 Data-Cache Prefetch Operation
The data cache controller recognizes prefetch opera-tions as shown in Table 5-10. The prefetch operationsload a full cache block from memory concurrently withother computation. If the prefetched block is already incache, no data is fetched from main memory. Prefetchoperations to other apertures than cacheable DRAM arediscarded. This operation is not guaranteed to execute -it will not execute if the cache is already occupied withtwo cache misses when the operation is issued. Theprefetch operations cause 3 stall cycles, if there is nocopyback of a dirty block. If a dirty block is the target ofthe prefetch, the dirty block will be written back toSDRAM, and at least 11 stall cycles are taken.
5.3.11 Memory Operation Ordering
The TM1100 memory system implements traditional or-dering for memory operations that are issued in differentclock cycles. That is, the effects of a memory operationissued in cycle j occur before the effects of a memory op-eration issued in cycle j+1.
For memory operations issued in the same cycle, how-ever, it is not possible to execute memory operations ina traditional order. So long as the simultaneous memoryoperations access different addresses (aliasing is notpossible in TM1100), no problems can occur. If two si-multaneous operations do access the same address,however, TM1100 behavior is undefined. Specifically,two cases are possible:
1. When multiple values are written to the same address in the same cycle, the resulting value in memory is un-defined.
2. When a read and a write occur to the same address in the same clock cycle, the value returned by the read is undefined.
The behavior of simultaneous accesses to the same ad-dress is undefined regardless of whether one or bothmemory operations hit in the cache.
Hidden Memory System Concurrency . Some cacheoperations may be overlapped with CPU execution. Ingeneral, a program cannot determine in what ordercache misses will complete nor can a program determinewhen and in what order copyback operations will com-plete. A program can, however, enforce the completionof copyback transactions to main memory because copy-back and invalidate operations can complete only ifpending copyback transactions for the same block havecompleted. Thus, a program can synchronize to the com-pletion of a copyback operation by dirtying a block, issu-ing a copyback operation for the block, and then issuingan invalidate operation for the block.
Ordering Of Special Memory Operations. The follow-ing are special memory operations:
1. Loads or stores to MMIO addresses.2. Non-cached loads or stores.3. Any copyback or invalidate operation.4. Loads or stores that cause a PCI-bus access.
The CPU is stalled until these special memory opera-tions are completed; there is no overlap of CPU execu-tion with these special memory operations. Thus, a pro-grammer can assume that traditional memory operationordering applies to special memory operations. Note,however, that ordering is undefined for two special mem-ory operations issued in the same cycle.
5.3.12 Operation Latency
Load and store operations have an operation latency ofthree cycles, regardless of the size of the data transfer.
Table 5-9. Data cache allocation operations
Mnemonic Description
allocd(offset) rsrc1 Data-cache allocate block with dis-placement. Causes the block with address (rsrc1+offset) & (~(cache_block_size - 1)) to be allo-cated and set valid.
allocr rsrc1 rsrc2 Data-cache allocate block with index. Causes the block with address (rsrc1+rsrc2) & (~(cache_block_size - 1)) to be allocated and set valid.
allocx rsrc1 rsrc2 Data-cache allocate block with scaled index. Causes the block with address (rsrc1 + 4 * rsrc2) & (~(cache_block_size - 1)) to be allo-cated and set valid.
Table 5-10. Data cache prefetch operations
Mnemonic Description
prefd(offset) rsrc1 Data-cache prefetch block with dis-placement. Causes the block with address (rsrc1+offset) & (~(cache_block_size - 1)) to be prefetched
prefr rsrc1 rsrc2 Data-cache prefetch block with index. Causes the block with address (rsrc1+rsrc2) & (~(cache_block_size - 1)) to be prefetched.
pref16x rsrc1 rsrc2 Data-cache prefetch block with scaled 16 bit index. Causes the block with address (rsrc1 + 2 * rsrc2) & (~(cache_block_size - 1)) to be prefetched.
pref32x rsrc1 rsrc2 Data-cache prefetch block with scaled 32 bit index. Causes the block with address (rsrc1 + 4 * rsrc2) & (~(cache_block_size - 1)) to be prefetched.
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5.3.13 MMIO Register References
Memory operations that reference MMIO registers arenot cached, and the CPU is stalled until the MMIO refer-ence completes. A MMIO register reference occurs whenan address is in the range:
[MMIO_BASE] ≤ address < ([MMIO_BASE] + 0x200000)
The size of the MMIO aperture is hardwired at 2M bytes.
5.3.14 PCI Bus References
Any CPU memory operation that references an addressoutside the SDRAM and MMIO address apertures is as-sumed to reference a device or memory on the PCI bus.PCI-bus data transfers are not cached, and the CPU isstalled until the PCI transfer completes.
5.3.15 CPU Stall Conditions
The data cache causes the CPU to stall when:
1. Any cache miss occurs.2. Two simultaneously issued, cacheable memory oper-
ations need to access the same cache bank (bank conflict).
3. An access that references an address in the MMIO aperture is issued.
4. An access to the PCI bus is issued.5. A non-trivial copyback or invalidate operation is is-
sued.6. An access to the non-cacheable region in the DRAM
aperture is issued.
5.3.16 Data Cache Initialization
When TM1100 is reset, the data cache executes an ini-tialization sequence. The cache asserts the CPU stallsignal while it sequentially resets all valid and dirty bits.The cache de-asserts the stall signal after completing theinitialization sequence.
5.4 INSTRUCTION CACHE
The instruction cache stores compressed CPU instruc-tions; instructions are decompressed before being deliv-ered to the CPU. The following sections describe the in-struction cache and its operation; Table 5-11summarizes instruction-cache characteristics.
5.4.1 General Cache Parameters
The instruction cache on TM1100 is 32 KB in size with a64-B block size. Thus, the cache contains 512 blockseach with its own address tag. The cache is eight-way
set-associative, so there are 64 sets, each containingeight tags. A single valid bit is associated with a block, soeach block and associated address tag is either entirelyvalid or invalid; on a cache miss, 64 bytes are read fromSDRAM to make the entire block valid.
The geometry of the instruction cache is available to soft-ware by reading the MMIO register IC_PARAMS, whichhas the format shown in Figure 5-8. Table 5-12 lists thefield values for TM1100’s IC_PARAMS register.
The product of the block size, associativity, and numberof sets gives the total cache size (32 KB in this case).
5.4.2 Address Mapping
TM1100 instruction addresses are mapped onto the datacache storage structure as shown in Figure 5-9. An in-struction address is partitioned into three fields as de-scribed in Table 5-13.
5.4.3 Miss Processing Order
When a miss occurs, the instruction cache starts fillingthe requested block from the beginning of the block. TheDSPCPU is stalled until the entire block is fetched andstored in the cache.
Table 5-11. Summary Of Instruction Cache Characteristics
Characteristic TM1100 Implementation
Cache size 32K bytes
Cache associativity 8-way set-associative
Block size 64 bytes
Valid bits One valid bit per 64-byte block
Replacement policy Hierarchical LRU (least-recently used) among the eight blocks in a set
Operation latency Branch delay is three cycles
Coherency enforce-ment
Software uses a special operation to enforce cache coherency
Cache locking Up to 1/2 (four out of eight blocks of each set) of the cache contents can be locked; granularity is 64 bytes
Figure 5-8. Format of the instruction-cache parameters register.
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5.4.4 Replacement Policy
The hierarchical LRU replacement policy implementedby the instruction cache is identical to that implementedby the data cache. See Section 5.3.4, “Replacement Pol-icies, Coherency,” for a description of the hierarchicalLRU algorithm.
5.4.5 Location of Program Code
All program code must first be loaded into SDRAM. Theinstruction cache cannot fetch instructions from othermemories or devices. In particular, the cache cannotfetch code from on-chip devices or over the PCI bus.
5.4.6 Branch Units
The instruction cache is closely coupled to three branchunits. Each unit can accept a branch independently, sothree branches can be processed simultaneously in thesame cycle.
Branches in TM1100 are so-called delayed branches be-cause the effect of a successful (taken) branch is notseen in the flow of control until some number of cycles af-ter the successful branch is executed. The number of cy-cles of latency is called the branch delay, and onTM1100, the branch delay is three cycles.
Although three branches can be executed simultaneous-ly, correct operation of the DSPCPU requires that onlyone be successful (taken) in any one cycle. DSPCPU op-eration is undefined if more than one concurrent branchoperation is successful.
Each branch unit takes four inputs from the DSPCPU:the branch opcode, a guard bit, a branch condition, anda branch target address. A branch is deemed successfulif and only if the opcode is a branch opcode, the guard bit
is TRUE (i.e., = 1), and the condition (determined by theopcode) is satisfied.
5.4.7 Coherency: Special iclr Operation
A program can exercise some control over the operationof the instruction cache by executing the special iclr op-eration. This operation causes the instruction cache toclear the valid bits for all blocks in the cache, includinglocked blocks. The LRU replacement status of all blocksis reset to their initialization value. The CPU is stalledwhile iclr is executing.
See Section 5.6, “Cache Coherency,” for further discus-sion of coherency issues.
5.4.8 Reading Tags and Cache Status
The instruction cache supports read access to its tag andstatus bits, but not with special operations as with thedata cache. Since the instruction cache and branch unitscan execute only resultless operations, access to the in-struction-cache tags and status bits is implemented us-ing normal load operations that reference a special re-gion in the MMIO address aperture. The region is 64 KBlong and starts at MMIO_BASE. Instruction cache tagsand status bits are read-only; store operations to this re-gion have no effect. MMIO operations to this special re-gion are only allowed by the DSPCPU, not by any othermasters of the on-chip data highway, such as externalPCI initiators.
Programmer’s note: Tag and status information can notbe read by PCI access, but only by DSPCPU access.Tag and status read cannot be scheduled in the samecycle with or one cycle after an iclr operation.
Reading A Tag And Valid Bit. To read the tag and validbit for a block in the instruction cache, a program can ex-ecute a ld32 operation directed at the instruction-cacheregion in the MMIO aperture. The top of Figure 5-10shows the required format for the target address. Themost-significant 16 bits must be equal to MMIO_BASE,the least-significant 15 bits select the block (by namingthe set and set member), and bit 15 must be set to zeroto perform a tag read. Note that in TM1100, valid setnumbers range from 0 to 63. Space to encode set num-bers 64 to 511 is provided for future extensions.
A ld32 with an address as specified above returns a 32-bit result with the format shown at the top of Figure 5-11.
Table 5-13. Instruction Address Field Partitioning
Field Address Bits Purpose
Offset 5..0 Byte offset into a set
Set 11..6 Selects one of the sets in the cache (one of 64 in the case of TM1100)
Tag 31..12 Compared against address tags of set members
Figure 5-10. Required address format for reading instruction-cache tags and status.
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Bit 20 contains the state of the valid bit, and the least-sig-nificant 20 bits contain the tag for the block addressed bythe ld32.
Reading The LRU Bits. To read the LRU bits for a set inthe instruction cache, a program can execute a ld32 op-eration as above but using the address format shown atthe bottom of Figure 5-10. In this format, bit 15 is set toone to perform the read of the LRU bits, and thetag_i_mux field is set to zeros because it is not needed.
Reading the LRU bits produces a 32-bit result with theformat shown at the bottom of Figure 5-11. The least-sig-nificant ten bits contain the state of the LRU bits whenthe ld32 was executed. See Section 5.5.4, “LRU Bit Def-initions,” for a description of the LRU bits.
Note that the tag_i_mux and set fields in the address for-mats of Figure 5-10 are larger than necessary for the in-struction cache in TM1100. These fields will allow futureimplementations with larger instruction caches to use acompatible mechanism for reading instruction cache in-formation. The tag_i_mux field can accommodate acache of up to 16-way set-associativity, and the set fieldcan accommodate a cache with up to 512 sets. ForTM1100, the following constraints of the values of thesefields must be observed:
1. 0 ≤ tag_i_mux ≤ 72. 0 ≤ set ≤ 63
5.4.9 Cache Locking
Like the data cache, the instruction cache allows up toone-half of its blocks to be locked. A locked block is nev-er chosen as a victim by the replacement algorithm; itscontents remain undisturbed until the locked status ischanged explicitly by software. Thus, on TM1100, up to16 KB of the cache can be used as a high-speed instruc-tion ‘ROM.’ Only four out of eight blocks in any set canbe locked.
The MMIO registers IC_LOCK_ADDR, IC_LOCK_SIZE,and IC_LOCK_CTL—shown in Figure 5-12—are used todefine and enable instruction locking in the same waythat the similarly named data-cache locking registers are
used. Section 5.3.7, “Cache Locking,” describes the de-tails of cache locking; they are not repeated here.
Setting the IC_LOCK_ENABLE bit (in IC_LOCK_CTL) to‘1’ causes the following sequence of events:
1. The instruction cache invalidates all blocks in the cache.
2. The instruction cache fetches all blocks in the lock range (defined by IC_LOCK_ADDR and IC_LOCK_SIZE) from main memory into the cache.
3. Cache locking is activated so that the locked blocks cannot be victims of the replacement algorithm.
The only difference between this sequence and the ini-tialization sequence for data-cache locking is that dirtyblocks (which cannot exist in the instruction cache) arenot first written back.
Programmer’s note: Programmers (or compilers) mustcombine all instructions that need to be locked into thesingle linear instruction-locking address range.
The special iclr operation also removes locked blocksfrom the cache. If blocks are locked in the instructioncache, then instruction cache locking should be disabledin software (by writing ‘0’ to IC_LOCK_CTL) before aniclr operation is issued.
Locking should not be enabled by PCI accesses to theMMIO register.
5.4.10 Instruction Cache Initialization and Boot Sequence
When TM1100 is reset, the instruction cache executesan initialization and processor boot sequence. While re-set is asserted, the instruction cache forces NOP opera-tion to the DSPCPU, and the program counter is set tothe default value reset_vector. When reset is deassert-ed, the initialization and boot sequence is as follows.
1. The stall signal is asserted to prevent activity in the DSPCPU and data cache.
2. The valid bits for all blocks in the instruction cache are reset.
31 0371115192327
VALID
I-Cache Tag-Read Result Format
I-Cache Status-Read Result Format LRU0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0
0 0 0
0
0 0 0 0 0 0 0 0
TAG
Figure 5-11. Result formats for reads from the instruction-cache region of the MMIO aperture.
Figure 5-12. Formats of the registers that control instruction-cache locking.
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3. At the completion of the block invalidation scan, the stall signal to the DSPCPU and data cache are deas-serted.
4. The DSPCPU begins normal operation with an in-struction fetch from the address reset_vector.
The initialization process takes 512 clock cycles. Resetsets reset_vector equal to DRAM_BASE so that programexecution starts at the initial value of DRAM_BASE. Theinitial value of DRAM_BASE is determined as describedin Section 5.2, “DRAM Aperture.”
5.5 LRU ALGORITHM
When a cache miss occurs, the block containing the re-quested data must be brought in to the cache, and thisrequested block must replace an existing block in thecache. The LRU algorithm is responsible for selectingthe replacement victim, and the algorithm attempts to se-lect the least-recently-used block.
The eight-way set-associative caches implement a hier-archical LRU replacement algorithm, which works as fol-lows:
• The eight sets are partitioned into four groups of twoelements each. To select the LRU element:
• First, the LRU pair out of the four pairs is selectedusing a four-way LRU algorithm.
• Second, the LRU element of the pair is selectedusing a two-way LRU algorithm.
5.5.1 Two-Way Algorithm
The two-way LRU requires an administration of one bitper pair of elements. On every cache hit to one of the twoblocks, the cache writes once to this bit (just a write, nota read-modify-write). If the even-numbered block is ac-cessed, the LRU bit is set to one; if the odd-numberedblock is accessed, the LRU bit is set to zero. On a miss,the cache replaces the LRU element, i.e. if the LRU bit iszero, the even numbered element will be replaced; if theLRU bit is one, the odd numbered element will be re-placed.
5.5.2 Four-Way Algorithm
For administration of the four-way algorithm, the cachemaintains an upper-left triangular matrix R of one-bit ele-ments without the diagonal. R contains six bits (in gener-al, n×(n–1)/2 bits for n-way LRU). If set element k is ref-erenced, the cache sets row k to one and column k tozero:
R[k, 0..n–1] ← 1, R[0..n–1, k] ← 0
The LRU element is the one for which the entire row iszero (or empty) and the entire column is one (or empty):
R[k, 0..n–1] = 0 and R[0..n–1, k] = 1
For a four-way set-associative cache, this algorithm re-quires six bits per set of four cache blocks. On everycache hit, the LRU info is updated by setting three of thesix bits to zero or one, depending on the set element thatwas accessed. The bits need only be written, no read-modify-write is necessary. On a miss, the cache readsthe six LRU bits to determine the replacement block.
TM1100 combines the two-way and four-way algorithmsinto an eight-way hierarchical LRU algorithm. A total often administration bits are required: six to maintain thefour-way LRU plus four bits maintain the four two-wayLRUs.
The hierarchical algorithm has performance close to fulleight-way LRU, but it requires far fewer bits—ten insteadof 28 bits—and is much simpler to implement.
To update the LRU bits on a cache hit to element j (with0 <= j <= 7), the cache applies m = (j div 2) to the four-way LRU administration and (j mod 2) is applied to thetwo-way administration of pair m. To select a replace-ment victim, the cache first determines the pair p fromthe four-way LRU and then retrieves the LRU bit q of pairp. The overall LRU element is the p×2+q.
5.5.3 LRU Initialization
Reset causes the LRU administration bits to initialized toa legal state:
The ten LRU bits per set are mapped as shown inFigure 5-13. This is the format of the LRU field as re-turned by the special operation rdstatus for the datacache and a ld32 from MMIO space (see Section 5.4.8,“Reading Tags and Cache Status”) for the instructioncache.
5.5.5 LRU for the Dual-Ported Cache
For the TM1100 dual-ported data cache, two memoryoperations to the same set are possible in a single clockcycle. To support this concurrency, two updates of theLRU bits of a single set must be possible.
The following rules are used by TM1100:
1. LRU bits that are changed by exactly one port receive the value according to the algorithm described above.
LRU bit 1LRU bit 2LRU bit 3LRU bit 4LRU bit 5LRU bit 6LRU bit 7LRU bit 8LRU bit 9
Figure 5-13. LRU bit definitions; 2_way[k] is the two-way LRU bit of pair k = (j div 2) for set element j.
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2. LRU bits that are changed by both ports receive a val-ue as if the algorithm were first applied for the access in port zero and then for the access in port one.
5.6 CACHE COHERENCY
The TM1100 hardware does not implement coherencybetween the caches and main memory. Generalized co-herency is the responsibility of software, which can usethe special operations dcb, dinvalid, and iclr to enforcecache/memory synchronization.
5.6.1 Example 1: Data-Cache/Input-Unit Coherency
Before the CPU commands the video-in unit to capture avideo frame, the CPU must be sure that the data cachecontains no blocks that are in the address region that thevideo-in unit will use to store the input frame. If the video-in unit performs its input function to an address regionand the data cache does hold one or more blocks fromthat region, any of the following may happen:
• A miss in the data cache may cause a dirty block tobe copied back to the address region being used bythe video-in unit. If the video-in unit already storeddata in the block, the write-back will corrupt the framedata.
• The CPU will read stale data from the cache insteadof from the block in main memory. Even though thevideo-in unit stored new video data in the block inmain memory, the cache contents will be usedinstead because it is still valid in the cache.
To prevent erroneous copybacks or the use of stale data,the CPU must use dinvalid operations to invalidate allblocks in the address region that will be used by the vid-eo-in unit.
5.6.2 Example 2: Data-Cache/Output-Unit Coherency
Before the CPU commands the video-out unit to send aframe of video, the CPU must be sure that all the data forthe frame has been written from the data cache to the re-gion of main memory that the video-out unit will output.Explicit action is necessary because the data cache—with its copyback write policy—will hold an exclusivecopy of the data until it is either replaced by the LRU al-gorithm or the CPU explicitly forces it to be copied backto main memory.
Before an output command is issued to the video-outunit, the CPU must execute dcb operations to force co-herency between cache contents and main memory.
5.6.3 Example 3: Instruction-Cache/Data-Cache Coherency
If code prepared by a program running on the CPU mustbe subsequently executed, coherency between the in-struction and data caches must be enforced. This is ac-complished by a two-step process:
1. Coherency between the data cache and main memo-ry must be enforced since the instruction cache can fetch instructions only from main memory.
2. Coherency between the instruction cache and main memory is enforced by executing an iclr operation.
The CPU will now be able to fetch and execute the newinstructions.
5.6.4 Example 4: Instruction-Cache/Input-Unit Coherency
When an input unit is used to load program code intomain memory, the iclr operation must be issued beforeattempting to execute the new code.
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5.7 PERFORMANCE EVALUATION SUPPORT
The caches implement support for performance evalua-tion. Several events that occur in the caches can becounted using the TM1100 timer/counters, by selectingthe source CACHE1 and/or CACHE2, as described inSection 3.8, “Timers.” Two different events can betracked simultaneously by using 2 timers.
The MMIO register MEM_EVENTS determines whichevents are counted. See Figure 5-14 for the format ofMEM_EVENTS. Table 5-14 lists the events that can betracked and the corresponding values for theMEM_EVENTS fields. Event1 selects the actual sourcefor the TIMER CACHE1 source. Event2 selects thesource for TIMER CACHE2.
5.8 MMIO REGISTER SUMMARY
Table 5-15 lists the MMIO registers that pertain to the op-eration of TM1100’s instruction and data caches.
Table 5-14. Trackable Cache-Performance Events
Encoding Event
0 No event counted
1 Instruction-cache misses
2 Instruction-cache stall cycles (including data-cache stall cycles if both instruction-cache and data-cache are stalled simultaneously)
3 Data-cache bank conflicts
4 Data-cache read misses
5 Data-cache write misses
6 Data-cache stall cycles (that are not also instruc-tion-cache stall cycles)
7 Data-cache copyback to SDRAM
8 Copyback buffer full
9 Data-cache write miss with all fetch units occu-pied
10 Data cache stream miss
11 Prefetch operation started and not discarded
12 Prefetch operation discarded (because it hits in the cache or there is no fetch unit available)
13 Prefetch operation discarded (because it hits in the cache)
Figure 5-14. Format of the memory_events MMIO register.
Table 5-15. MMIO Register Summary
Name Description
DRAM_BASE Sets location of the DRAM aperture
DRAM_LIMIT Sets size of the DRAM aperture
DRAM_CACHEABLE_LIMIT
Divides DRAM aperture into cache-able and non-cacheable portions
MEM_EVENTS Selects which two events will be counted by timer/counters
DC_LOCK_CTL Data-cache locking enable and aper-ture control.
DC_LOCK_ADDR Sets low address of the data-cache address lock aperture
DC_LOCK_SIZE Sets size of the data-cache address lock aperture
DC_PARAMS Read-only register with data-cache parameter information
IC_PARAMS Read-only register with instruction-cache parameter information
IC_LOCK_CTL Instruction-cache locking enable
IC_LOCK_ADDR Sets low address of the instruction-cache address lock aperture
IC_LOCK_SIZE Sets size of the instruction-cache address lock aperture
MMIO_BASE Sets location of the MMIO aperture
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5-14 PRELIMINARY INFORMATION File: cache.fm5, modified 7/24/99
Video In Chapter 6
by Gert Slavenburg
6.1 SUMMARY OF FUNCTIONS
The Video In (VI) unit provides the following functions:
• Digital video input from a digital camera or analogcamera (using a video decoder).
• High bandwidth (54 MB/sec) raw input data channel.• Direct 8-10 bit interface for video A/D converters at
up to 54-MHz sample rate.• Receiver port for TM1100-to-TM1100 unidirectional
message passing
The Video In unit operates in one of the modes as perTable 6-1.
Digital video input is in YUV 4:2:2 with eight-bit resolutionmultiplexed in CCIR656 format1 from a digital camera orCCIR656 capable video decoder (such as the PhilipsSAA7111 or SAA7113), across an eight-bit-wide inter-face. Resolutions up to CCIR601 are accepted at 50 or60 fields per second. A programmable rectangular imageis captured from a video frame and written in planar for-mat to TM1100 SDRAM. The video camera or decodercan be programmed using the TM1100 I2C bus. In fullrescapture mode, luminance (Y) and chrominance (U, V)
pass unmodified. In halfres capture mode, luminanceand chrominance are horizontally decimated by a factorof two to convert to CIF-like resolution with YUV 4:2:2 orMPEG sampling rules. If vertical subsampling on chromi-nance is desired, it is performed by software on theDSPCPU or by the on-chip Image Coprocessor (ICP).
When operating as raw input data channel, VI acceptseight-bit-wide data. The operation mode is raw8 capture.No data selection or data interpretation is done. Data iswritten in packed form, four bytes to a word, to localSDRAM. There is no hardware control over the rate atwhich the source sends data. Instead, VI maintains twopointer/counter registers to ensure that no data is lostwhen the local SDRAM memory buffer fills. Data is ac-cepted at the clock of the sender. If desired, VI_CLK canbe programmed as an output to drive the data transfer ata programmable rate.
VI can accept data from up to 10-bit A/D converters, atsampling rates up to 54 MHz. VI can operate in raw8,raw10u, or raw10s capture mode for eight-bit, unsigned10-bit or signed 10-bit data. In the 10-bit modes, data iszero- or sign-extended to 16 bits and stored in packedform in local SDRAM. As with the raw8-capture mode, VImaintains two pointer/counter registers to ensure that nodata is lost when the local SDRAM memory buffer fills.Data is accepted at the externally set sampling rate. Ifdesired, VI_CLK can be programmed as an output toserve as a programmable sampling clock.
VI can act as receiver from the Video Out unit of anotherTM1100. One Video Out can broadcast to multiple re-ceiving VI’s. In this message passing mode, no data se-lection or data interpretation is done. Each message ofthe sender is written as byte-packed data to a separatelocal SDRAM memory buffer. Message start and end isindicated by the sender. The receiving VI will accept datauntil the sender indicates message end or until the cur-rent memory buffer is full. If the memory buffer fills beforemessage end is encountered, the received data is trun-cated and an error condition is raised.
6.1.1 Interface
Besides the Video-In-specific pins in Table 6-2, theTM1100 I2C interface is typically used to control the ex-ternal camera or video decoder.
Figure 6-1 through Figure 6-4 illustrate typical connec-tions for commonly used external sources. Note thatVI_DVALID is only used in special circumstances, e.g.when sending data through a channel that results inclock periods both with and without data transfers.
Table 6-1. Video In Mode Selection.
Mode Function Explanation
0000 fullres capture YUV 4:2:2 capture without dec-imation
0001 halfres capture YUV 4:2:2 capture with deci-mate by 2
0010 raw8 capture raw 8 bits data capture, pack 4 bytes to a word
0011 raw10s capture raw 10 bits data capture, sign extend to 16 bits, pack 2 to a word
0100 raw10u capture raw 10 bits data capture, zero-extend to 16 bits, pack 2 to a word
0101 message passing VO to VI message passing
0110..
1111
Reserved
1. Refer to CCIR recommendation 656: Interfaces for dig-ital component video signals in 525 line and 625 linetelevision systems. Recommendation 656 is included inthe Philips Desktop Video Data Handbook.
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6.1.2 Diagnostic Mode
The Video-In logic can be set to operate in diagnosticmode, which connects the inputs of VI to the outputs ofVideo Out. This mode provides boot diagnostics with the
ability to verify major operational aspects of the chip be-fore handing control to an operating system.
Diagnostic mode is entered by writing a control word witha ‘1’ in the DIAGMODE bit position to the VI_CTL register(see Figure 6-11). Video Out has to be setup to providea clock before starting DIAGMODE. After a Video-In soft-ware reset, the DIAGMODE bit has to be set back to ‘1’.In diagnostic mode, the Video In signals are exactly asshown in Figure 6-2, except that the inputs come fromthe on-chip Video Out unit. Note that the inputs are trulytaken from the TM1100 Video-Out external pins, i.e. if anexternal (board level) source is driving Video Out pins,diagnostic mode is not capable of testing Video-Out.
Note that the diagnostic mode only controls an input mul-tiplexer. VI can be programmed and operated in all usualmodes. The raw modes are particularly attractive for di-agnostics purposes, since they allow VI to operate al-most as an on-chip logic analyzer.
6.1.3 Power Down
The Video In logic participates in global TM1100 chippower down, unless the SLEEPLESS bit in the VI_CTLregister is asserted.
6.1.4 Hardware and Software Reset
Video In is reset by a TM1100 hardware reset (pinTRI_RESET#) or by a Video In software reset. The latteris accomplished by writing a control word of 0x00080000to the VI_CTL register. After a software reset, allow for 5video clock cycles delay before enabling Video In cap-ture. Upon hardware or software reset, the VI_CTL,VI_STATUS, and VI_CLOCK registers are set to all ze-ros. The state of the other registers after RESET is unde-fined. Note that the Video-In clock has to be presentwhile applying the software reset.
Table 6-2. Video In Interface Pins
VI_CLK I/O-5 • If configured as input (power up default): A positive transition on this incoming video clock pin samples all other VI_DATA input signals below if VI_DVALID is HIGH. If VI_DVALID is LOW, VI_DATA is ignored. Clock and data rates of up to 54 MHz are supported.
• If configured as output: Program-mable output clock to drive an external video A/D converter. Can be programmed to emit integral dividers of DSPCPU_CLK.
• See section 6.2 for clock program-ming details.
VI_DVALID IN-5 VI_DVALID indicates that valid data is present on the VI_DATA lines. If HIGH, VI_DATA will be accepted on the next VI_CLK positive edge. If LOW, no VI_DATA will be sampled.
VI_DATA[7:0] IN-5 CCIR656 style YUV 4:2:2 data from a digital camera, or general purpose high speed data input pins. Sampled on positive transitions of VI_CLK if VI_DVALID HIGH.
VI_DATA[9:8] IN-5 Extension high speed data input bits to allow use of 10 bit video A/D convert-ers in raw10 modes. VI_DATA[8] serves as START and VI_DATA[9] as END message input in message pass-ing mode.Sampled on positive transi-tions of VI_CLK if VI_DVALID HIGH.
DATA[7:0]
CLOCK
SDA, SCL GND Cable Connector
VI_DATA[7:0]VI_DVALIDVI_CLK
VSS
SDA, SCL
TM1100
logic ‘1’
VI_DATA[9:8]GND
Termination &Receivers
I2C bus 2
Figure 6-1. Video In connected to an 8-bit CCIR656 digital camera.
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6.2 CLOCK GENERATOR
The Video In block can operate in two distinct clockingmodes, as controlled by the VI_CLOCK control register(see Figure 6-11).
SELFCLOCK = 0: “External clocking mode”. This isthe most common mode of operation. In this mode, theVI_CLK pin is an asynchronous clock input. All other in-puts are sampled on positive edges of the VI_CLK clocksignal. On chip synchronizers ensure reliable asynchro-nous capture. This mode can be combined with DIAG-MODE, in which case the Video Out clock acts as theasynchronous clock source. In external clocking mode,the value of DIVIDER is ignored.
SELFCLOCK = 1: “Internal clocking mode”. Thismode is typically intended for use with external A/D con-verters or other sources that require a clock. In thismode, VI_CLK is an output pin. Positive edges ofVI_CLK are used to sample all other inputs. The gener-ated clock frequency can be programmed using the DI-VIDER field in the VI_CLOCK register.
On RESET, VI_CLOCK is set to zero, i.e. external clock-ing mode is the default with DIVIDER ignored.
VI_DATA[7:0]
VI_DVALID
VI_CLK
TM1100 2
logic ‘1’
VI_DATA[8]VI_DATA[9]
VO_DATA[7:0]
VO_CLK
(STMSG) VO_IO1(ENDMSG) VO_IO2
TM1100 1
Figure 6-2. Video In connected to Video Out.
VI_DATA[7:0]VI_DVALIDVI_CLK
IIC_SCLIIC_SDA
TM1100
logic ‘1’
VI_DATA[9:8]GNDVPO[15:8]
LLC
SCLSDA
SAA7111
Analog video 1–2 S-VHS Y/C 1–4 CVBS
To other I2C devices
I2C bus
24.576 MHz
Figure 6-3. Video In connected to a video decoder.
VI_DATA[9:0]VI_DVALID
VI_CLK
TM1100
logic ‘1’
Analog video 10-bit Video A/D
Figure 6-4. Video In connected to a 10-bit video A/D converter.
f VICLK
f DSPCPUDIVIDER------------------------=
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6.3 FULLRES CAPTURE MODE
In fullres capture mode Video In receives all three videocomponents Y, U, and V, as well as synchronization in-formation (SAV and EAV codes) on the VI_DATA[7:0]pins in CCIR656 format. See Figure 6-8. The three videocomponents Y, U, and V are separated into three differ-ent streams. Each component is written in packed forminto separate Y, U, and V buffers in the SDRAM. This iscommonly called a planar format1 (see Figure 6-10).
The CCIR656 standard specifies that the camera has toobey the sampling rules illustrated in Figure 6-5. VI is ca-
pable of chrominance resampling, and can producesamples in memory in two ways:
VI_CTL.SC=0. “Co-sited sampling” places luminanceand chrominance samples in memory without any modi-fication. Hence, a planar format results with sampling po-sitions as per co-sited luminance and chrominance YUV4:2:2 convention.
1. The planar format is most suitable as input to softwarecompression algorithms.
Chrominance (U,V) samples
Luminancesamples
Figure 6-5. Camera YUV 4:2:2 sampling (co-sited luminance/chrominance).
YUV 4:2:2 CCIR656input samples
a b c d e f g h i j k l
a b c d e f g h i j k lResampled sample
values
Y g' Y g=
Uef U– c 13Ue 5Ug Ui–+ +( ) 16⁄=
V ef V c– 13V e 5V g V i–+ +( ) 16⁄=
Figure 6-6. Chrominance re-sampling to achieve interspersed sampling.
Active area
a b c d e f g h i jd c b zu zv zw zx zy zz zy zx zwzs zt
• • •
Figure 6-7. Filtering at the edge of the active area.
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VI_CTL.SC=1: “Interspersed sampling” serves togenerate an in memory sampling structure wherechrominance samples are spatially midway between lu-minance samples, as shown in Figure 6-6. This ‘inter-spersed’ format is suitable for use in MPEG-1 encoding.
The Video In hardware applies a (–1 13 5 –1)/16 filter asillustrated in Figure 6-6 to the chrominance samples be-fore writing them to memory. This filter computes chromi-nance values at sample points midway between lumi-nance samples1. Computed video data is clamped to01h if result of the filter is less than 01h and clamped toFFh if greater than FFh. Interspersed data format is pre-ferred by some video compression standards. TheMPEG-1 standard, for example, requires YUV 4:2:0 datawith chrominance sampling positions horizontally andvertically midway between luminance samples. This canbe achieved from the horizontally interspersed samplingformat by vertical subsampling with a (1 1) / 2 or more so-phisticated filter. Vertical filtering can be performed bysoftware using the DSPCPU’s efficient multi-media oper-ations or by hardware in the Image Coprocessor (ICP).
The filtering process exercises special care at the leftand right edges of the active area of the CCIR656 datastream, as defined by the SAV, EAV code positions. SeeFigure 6-7. Since no pixels exist to the left of the first pix-el, nor to the right of the last pixel, filtering can result inartifacts. To minimize artifacts, the image is extended bymirroring pixels around the left-most and right-most pixel.Note that the image is mirrored around pixel ‘a’, the firstpixel after the SAV code and around pixel ‘zz’, the lastpixel before the EAV2 code. Pixel ‘a’ in Figure 6-7 is the
(chroma, luma) pair defined by the first three camerabytes of the UYVYUYVY... stream after SAV.
Refer to Figure 6-11 for an overview of the memorymapped I/O (MMIO) registers that are used to controland observe the operation of VI in fullres capture mode.To ensure compatibility with future devices, any unde-fined MMIO bits should be ignored when read, and writ-ten as zeroes.
Upon hardware or software reset (Section 6.1.4, “Hard-ware and Software Reset”), the VI_CTL, VI_STATUS,and VI_CLOCK registers are set to all zeros.
At any point in time, the VI_STATUS register fields (seeFigure 6-11) indicate the current camera status:
• CUR_X: The pixel index (0 to M–1) of the mostrecently received camera pixel. CUR_X gets set tozero for the first pixel following receipt of a SAVcode3, and incremented on every valid Y samplereceived thereafter.
• CUR_Y: The line index (0 to N–1) within the currentfield of the camera line that is currently beingreceived. CUR_Y gets set to zero upon receipt of anegative edge of V, i.e., upon the first SAV code con-taining V=0 after one or more SAV codes containingV=1. This is equivalent to the first line after the end ofvertical retrace. CUR_Y gets incremented uponevery successive SAV code.
Preamble
1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 F V H P P P P
Timing reference code
Protection bits (error correction)
H = 0 for SAVH = 1 for EAV
V = 1 during field blankingV = 0 elsewhere
F = 0 during field 1F = 1 during field 2
Figure 6-8. Format of CCIR656 SAV and EAV timing reference codes.
Captured Image
START_X
WIDTH
HE
IGH
T
START_Y
Pixel 0 Pixel M–1Line 0
Line N–1
Figure 6-9. Video-in capture parameters.
1. All filters perform full precision intermediate computa-tions and saturation upon generating the result bits.
2. EAV codes with multiple bit errors are accepted and doenable the mirroring function.
3. Note that VI uses the SAV protection bits to implementsingle error correction and double error detection. AnSAV code with double error is ignored.
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• FIELD2: Indicates whether the field currently beingreceived is a field1 or 2. This flag gets updated basedon the F field of every received SAV code. Note thatfield1 is the ‘top’ field, i.e. the field containing the top-most visible line. Field1 contains lines 1,3,5 etc.Field2 contains lines 2,4,6,8 etc.
Table 6-3 illustrates common digital camera standardsand the number of active pixels per line, lines per fieldand fields per second. Note that any source is accept-able to VI, as long as the maximum VI_CLK rate is notexceeded.
Figure 6-9 shows the details of an incoming field and thecaptured image. The incoming field consists of N hori-zontal lines, each line having M pixels labeled 0 throughM–1. Lines are numbered from 0 through N–1. The cap-tured image is a subset of the incoming image. It is de-fined by the capture parameters (START_X, START_Y,WIDTH, HEIGHT) held in the VI_CAP_START andVI_CAP_SIZE MMIO registers (see Figure 6-11).
• START_X: Defines the starting pixel number or (X-coordinate of the starting pixel). START_X must beeven, and greater or equal zero.
• START_Y: Defines the starting line number or (Y-coordinate of the starting pixel). START_Y must begreater or equal zero.
• WIDTH: Defines the width of the captured image inpixels. WIDTH must be even.
• HEIGHT: Defines the height of the captured image inlines.
Image capture starts after the following conditions aremet:
• VI_CTL.CAPTURE ENABLE is asserted.• VI_STATUS.CAPTURE COMPLETE is de-asserted,
indicating that any previously captured image hasbeen acknowledged.
• CUR_Y = START_Y occurs.
Once image capture is started, HEIGHT ‘lines’ are cap-tured. Each ‘line’ capture starts if:
• The previous line capture, if any, is completed.• CUR_X = START_X
Once line capture starts, it continues for 2*WIDTH pixelclocks1 in which VI_DVALID is asserted, irrespective ofthe presence of 1 or more EAV codes.
Note that capture continues regardless of any horizontalor vertical retrace and associated CUR_Y or CUR_X re-set. This provides special applications with the ability tocapture information embedded inside the horizontal orvertical blanking interval. If it is desirable to capture ‘pix-els’ in the horizontal blanking interval, a minimum timeseparation of 1 µs is required between the last pixel cap-tured on line y and the first pixel captured on line y+1. Anexception to this rule is allowed if and only if the storageparameters below are chosen such that the last and firstpixel end up in adjacent memory locations. Note thatblanking information capture only makes sense in fullresmode, with co-sited sampling. All other modes apply fil-tering, which will distort the numeric sample values.
The captured image is stored in SDRAM at a location de-fined by the storage parameters in MMIO registers(Y_BASE_ADR, Y_DELTA, U_BASE_ADR, U_DELTA,V_BASE_ADR, V_DELTA). Note that the base-addressregisters force alignment to 64-byte boundaries (sixLSBs are always zero). The default memory packing isbig-endian although little-endian packing is also support-ed by setting the LITTLE_ENDIAN bit in the VI_CTL reg-ister.
• Y_BASE_ADR: The desired starting (byte) addressin SDRAM memory where the first Y (Luminance)sample of the captured image will be stored. Thisaddress is forced to be 64-byte aligned (six LSBsalways zero).
• Y_DELTA: The desired address difference betweenthe last sample of a line and the address of the firstsample on the next line. Note that the value ofY_DELTA must be chosen so that all line-startaddresses are 64-byte aligned.
• U_BASE_ADR, U_DELTA, V_BASE_ADR,V_DELTA: Same functions and alignment restrictionsas above, but for chrominance-component samples.
Horizontally-adjacent samples are stored at successivebyte addresses, resulting in a packed form (four 8-bitsamples are packed into one 32-bit word). Upon horizon-tal retrace, pixel storage addresses are incremented bythe corresponding DELTA to compute the starting byteaddress for the next line. Note that DELTA is a 16-bit un-signed quantity. This process continues until HEIGHTlines of WIDTH samples have been stored in memory forluminance (Y). For chrominance, HEIGHT lines of halfthe WIDTH are stored2. See Figure 6-10.
Modifications to Y_BASE_ADR, U_BASE_ADR andV_BASE_ADR have no effect until the start of next cap-ture, i.e. VI hardware maintains a separate pointer totrack the current address. Modifications to Y_DELTA,
Table 6-3. Common Video Source Parameters.
Video Source M(# active pixels)
N(# active lines)
Field Rate(Hz)
CCIR60150 Hz/625 lines
720 288 50
CCIR60160 Hz/525 lines
720 240 60
square pixel50 Hz/625 lines
768 288 50
square pixel60 Hz/525 lines
640 240 60
1. Four clocks for each Cb,Y,Cr,Y group representing twoluminance pixels
2. Note that consecutive pixel components of each lineare stored in consecutive memory addresses but con-secutive lines need not be in consecutive memory ad-dresses
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Philips Semiconductors Video In
U_DELTA and V_DELTA do affect the next horizontal re-trace. Hence, under normal circumstances, the DELTAvariables should not be changed during capture.
When capture is complete, i.e. any internal VI buffershave been flushed and the entire captured image is in lo-cal SDRAM, VI raises the STATUS register flag CAP-TURE COMPLETE. If enabled in the VI_CTL register,this event causes a DSPCPU interrupt to be requested.
The programmer can determine whether the capturedimage is a field1 or field2 by inspection of the FIELD2 flagin VI_STATUS. Note that the FIELD2 flag changes at thestart of the vertical blanking interval of the next field.
The CAPTURE COMPLETE flag is cleared by writing aword to VI_CTL with a ‘1’ in the CAPTURE COMPLETEACK bit position. This action has the following effect:
• it tells the hardware that a new Y,U and V DMA bufferis available (or the old one has been copied)
• it clears the CAPTURE COMPLETE flag• it tells VI to capture the next image
The user can program the Y_THRESHOLD field to gen-erate pre-completion (or post-completion) interrupts.Whenever CUR_Y reaches Y_THRESHOLD, theTHRESHOLD REACHED flag in the STATUS register isset. If enabled in the VI_CTL register, this event causesa DSPCPU interrupt request. The THRESHOLDREACHED flag is cleared by writing a word to VI_CTLwith a ‘1’ in the THRESHOLD REACHED ACK bit posi-tion. Note that, due to internal buffering in the Video Inunit, it is NOT guaranteed that all samples from lines upto and including CUR_Y have been written to localSDRAM upon THRESHOLD REACHED. The implemen-tation guarantees a fixed maximum time of 2 µs betweenraising the interrupt and completion of all writes toSDRAM. The THRESHOLD interrupt mechanism works
regardless of CAPTURE ENABLE. Hence, it can also beused to skip a desired number of fields without constantDSPCPU polling of VI_STATUS.
If VI internal buffers overflow due to insufficient internaldata-highway bandwidth allocation, the HIGHWAYBANDWIDTH ERROR condition is raised in theVI_STATUS register. If enabled, this causes assertion ofa VI interrupt request. Capture continues at the correctmemory address as soon as the internal buffers can bewritten to memory, but one or more pixels may havebeen lost, and the corresponding memory locations arenot written. The HBE condition can be cleared by writinga ‘1’ to the HIGHWAY BANDWIDTH ERROR ACK bit inVI_CTL. Refer to Section 6.7, “Highway Latency andHBE” for more information.
Any interrupt event of VI (CAPTURE COMPLETE,THRESHOLD REACHED, HIGHWAY BANDWIDTH ER-ROR) leads to the assertion of a single VI interrupt(SOURCE 9) to the TM1100 Vectored Interrupt Control-ler. The interrupt handler routine should check the STA-TUS register to determine the set of VI events associatedwith the request. The vectored interrupt controller shouldalways be set to have Video In (SOURCE 9) operate inlevel sensitive mode. This ensures that each event getshandled.
VI asserts the interrupt request line as long as one ormore enabled events are asserted. The interrupt handlerclears one or more selected events by writing a ‘1’ to thecorresponding ACK field in VI_CTL. The clearing of thelast event leads to immediate (next DSPCPU clock edge)de-assertion of the interrupt request line to the VectoredInterrupt Controller. See Section 3.5.3, “INT and NMI(Maskable and Non-Maskable Interrupts),” for informa-tion on how to program interrupt handler routines.
WIDTH pixels
HE
IGH
T li
nes
pix0 pix1 pix2pix
W–1• • •
. . .
Y_BASE_ADR
WIDTH/2 pixels
HE
IGH
T li
nes
pix0 pix2 • • •
. . .
U_BASE_ADR
(Repeated for V_BASE_ADDR, V_DELTA)
Y_DELTA
U_DELTA
Figure 6-10. Video In YUV 4:2:2 planar memory format.
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TM1100 Preliminary Data Book Philips Semiconductors
Figure 6-11. YUV capture view of Video In MMIO registers.
WIDTH/2 pixels
HE
IGH
T li
nes
pix0 pix1 pix2pix
W/2–1• • •
. . .
Y_BASE_ADR
WIDTH/4 pixels
HE
IGH
T li
nes
pix0 pix2 • • •
. . .
U_BASE_ADR
(Repeated for V_BASE_ADDR, V_DELTA)
Y_DELTA
U_DELTA
Figure 6-12. Video In halfres planar memory format.
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Philips Semiconductors Video In
6.4 HALFRES CAPTURE MODE
Halfres capture mode is identical in operation to fullrescapture mode except that horizontal resolution is re-duced by a factor of two on both luminance and chromi-nance data.
Referring to Figure 6-9 and Figure 6-11, if VI is pro-grammed to capture HEIGHT lines of WIDTH pixels inhalfres mode, the resulting captured planar data is asshown in Figure 6-12. Note that WIDTH/2 luminance andWIDTH/4 chrominance samples are captured. In thismode, START_X and WIDTH must be a multiple of four.
Horizontal-resolution reduction is performed as shown inFigure 6-13 or Figure 6-14. The spatial sampling con-ventions of the pixels in memory depends on the SC(Sampling Convention) bit in the VI_CTL register. As-suming that the camera sampling positions obey the con-ventions shown in Figure 6-5, two possible spatial for-mats are supported in memory:
• If SC=0, co-sited luminance and chrominance sam-ples result as shown in Figure 6-13. This corre-sponds to the standard YUV 4:2:2 samplingconventions.
• If SC=1, interspersed chrominance samples result,as shown in Figure 6-14. This form is (after vertical
subsampling of the chroma components) identical tothe MPEG-1 sampling conventions. If vertical sub-sampling is desired, it can either be performed insoftware on the DSPCPU, or in hardware using theImage Coprocessor (ICP).
The filtering process applies mirroring at the edge of theactive video area, as per Figure 6-7.
For both filters, computed video data is clamped to 01h ifresult of the filter is less than 01h and clamped to FFh ifgreater than FFh.
6.5 RAW CAPTURE MODES
All raw capture modes (raw8, raw10s and raw10u) be-have similarly. VI_DATA information is captured at therate of the sender’s clock, without any interpretation orstart/stop of capture on the basis of the data values. Anyclock cycle in which VI_DVALID is asserted leads to thecapture of one data sample. Samples are eight or 10 bitslong (raw8 versus raw10 modes). For the eight-bit cap-ture mode, four samples are packed to a word. For the10-bit capture modes, two samples (of 16 bits each) arepacked to a word. The extension from 10 to 16 bits usessign extension (raw10s) or zero extension (raw10u).
YUV 4:2:2 CCIR656input samples
a b c d e f g h i j k l
Halfres capturesample results
Uf ' 3Uc– 19Ue 19Ug 3Ui–+ +( ) 32⁄=
V f ' 3V c– 19V e 19V g 3V i–+ +( ) 32⁄=
Y h' 3Y e– 19Y g 32Y h 19Y i 3Y k–+ + +( ) 64⁄=
Figure 6-13. Halfres co-sited sample capture.
YUV 4:2:2 CCIR656input samples
a b c d e f g h i j k l
Halfres capturesample results
Y g' 3Y d– 19Y f 32Y g 19Y h 3Y j–+ + +( ) 64⁄=
Uf ' 3Uc– 19Ue 19Ug 3Ui–+ +( ) 32⁄=
V f ' 3V c– 19V e 19V g 3V i–+ +( ) 32⁄=
Figure 6-14. Halfres interspersed sample capture.
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For 8-bit and 16-bit capture, successive captured valuesare written to increasing memory addresses. For 16-bitcapture, the byte order with which the 16-bit data is writ-ten to memory is governed by the LITTLE ENDIAN bit.The VI LITTLE ENDIAN bit should be set the same as theDSPCPU endianness (PCSW.BSX). This ensures thatthe DSPCPU sees correct 16-bit data.
Figure 6-15 illustrates the ‘raw mode’ view of the VIMMIO registers. Figure 6-16 shows the major Video Instates associated with raw-mode capture. The initialstate is reached on software or hardware reset as de-scribed in Section 6.1.4, “Hardware and Software Re-set”. Upon reset, all status and control bits are set to ze-ro. In particular, CAPTURE_ENABLE is set to 0 and nocapture takes place.
Once the software has programmed BASE1 and BASE2(with the start addresses of two SDRAM buffer areas1)and SIZE (in number of samples), it is safe to enable cap-turing by setting CAPTURE_ENABLE. Note that SIZE isin samples, and must be a multiple of 64, hence settinga minimum buffer size of 64 bytes for raw8 mode and 128bytes for raw10 modes. At this point, buffer1 is the activecapture buffer. Data is captured in buffer1 until capture isdisabled or until SIZE samples have been captured. Afterevery sample, a running address pointer is incrementedby the sample size (one or two bytes). If SIZE sampleshave been captured, capture continues (without missinga sample) in buffer2. At the same time, BUF1FULL is as-
serted. This causes an interrupt on the DSPCPU, if en-abled by BUF1FULL INTERRUPT ENABLE.
Buffer2 is now the active capture buffer, and behaves asdescribed above. In normal operation, the DSPCPU willrespond to the BUF1FULL event by assigning a newBASE1 and (optionally) SIZE and performing an ACK1.If the DSPCPU fails to assign a new buffer1 and performan ACK1 before buffer2 also fills up, the OVERRUN con-dition is raised and capture stops. Capture continuesupon receipt of an ACK1, ACK2, or both, regardless ofthe OVERRUN state. The buffer in which capture re-sumes is as indicated in Figure 6-16. The OVERRUNcondition is ‘sticky’ and can only be cleared by software,by writing a ‘1’ to the ACK_OVR bit in the VI_CTL regis-ter.
If insufficient bandwidth is allocated from the internaldata highway, the VI internal buffers may overflow. Thisleads to assertion of the HIGHWAY BANDWIDTH ER-ROR condition. One or more data samples are lost. Cap-ture resumes at the correct memory address as soon asthe internal buffer is written to memory. The HBE errorcondition is sticky. It remains asserted until it is clearedby writing a ‘1’ to HIGHWAY BANDWIDTH ERRORACK. Refer to Section 6.7, “Highway Latency and HBE.”
Note that VI hardware uses copies of the BASE andSIZE registers once capture has started. Modifications ofBASE or SIZE, therefore, have no effect until the start ofthe next use of the corresponding buffer.
Note also that the VI_BASE1 and VI_BASE2 addressesmust be 64-byte aligned (the six LSBs are always zero).1. SDRAM buffers must start on a 64 byte boundary.
VI_STATUS (r)0x10 140031 0
MMIO_BASEoffset:
VI_CLOCK (r/w)0x10 1408
VI_BASE1 (r/w)0x10 1414
VI_BASE2 (r/w)0x10 1418
371115192327
DIVIDER
BUF1ACTIVE
BUF2FULLBUF1FULL
VI_CTL (r/w)0x10 1404 MODE
BUF1FULL
ACK2ACK1
BUF2FULLLittle endian
Capture enable
software RESET
DIAGMODE
SELFCLOCK
BASE1
BASE2
VI_SIZE (r/w)0x10 141C SIZE (in samples)
OVERFLOW(message mode only)
OVERRUN
ACK_OVFACK_OVR
OVFOVR
Interrupt enables
Highway bandwidth error
Highway bandwidth errorINT enable
Highway bandwidth error ACKSLEEPLESS
000000
000000
000000
RESERVED
Figure 6-15. Raw & message passing modes view of Video In MMIO registers.
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Philips Semiconductors Video In
6.6 MESSAGE-PASSING MODE
In this mode, VI receives eight-bit message data over theVI_DATA[7:0] pins. The message data is written inpacked form (four eight-bit message bytes per 32-bitword) to SDRAM. Message data capture starts on re-ceipt of a START event on VI_DATA[8]. Message data isreceived until EndOfMessage (EOM) is received onVI_DATA[9] or the receive buffer is full. Note that theVI_SIZE MMIO register determines the buffer size, andhence maximum message length. It should not bechanged without a Video In (soft) reset.
Figure 6-17 illustrates an example of an eight-byte mes-sage transfer. The first byte (D0) is sampled on the risingedge of the VI_CLK clock after a valid START was sam-pled on the preceding rising clock edge. The last byte(D7) is sampled on the rising clock edge where EOM issampled asserted.
The message passing mode view of the VI MMIO regis-ters is shown in Figure 6-15. The major states are shown
in Figure 6-18. The operation is almost identical to theoperation in raw-capture mode, except that transitions toanother active buffer occur upon receipt of EOM ratherthan on buffer full. OVERRUN is raised if the secondbuffer receives a complete message before a new bufferis assigned by the DSPCPU.
OVERFLOW is raised if a buffer is full and no EOM hasbeen received. If enabled, it causes a DSPCPU interrupt.Since digital interconnection between devices is reliable,overflow is indicative of a protocol error between the twoTM1100’s involved in the exchange (failure to agree onmessage size). Detection of overflow leads to total halt ofcapture of this message. Capture resumes in the nextbuffer upon receipt of the next START event onVI_DATA[8]. The OVERFLOW flag is sticky and can onlybe cleared by writing a ‘1’ to ACK_OVF.
Highway Bandwidth Error behavior in message passingmode is identical to that of raw mode.
ACTIVE = BUF2BUF1FULL
ACTIVE = BUF1
ACTIVE = BUF2
ACTIVE = BUF1BUF2FULL
BUF1FULLBUF2FULL
raise OVERRUN*
* OVERRUN is a sticky flag. It gets set but does not affect operation. It can only be cleared by software, by writing a ‘1’ to ACK_OVR. (See text in Section 6.5)
ACK1 & ~ACK2
ACK1 & ACK2
~ACK1 & ACK2
Buffer2 Full
Buffe
r1 F
ull
Buffer1Full
ACK1
Buffer2Full
ACK2
RESET
Figure 6-16. Video In raw mode major states.
VI_DATA[7:0]
VI_DATA[8]
VI_DATA[9]
VI_CLK
XX D0 D1 D2 D3 D4 D5 D6 D7 XX XX
Start ofmessage
End ofmessage
Figure 6-17. Video In message passing signal example.
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6.7 HIGHWAY LATENCY AND HBE
Refer to Chapter 19, “Arbiter,” for a description of the ar-biter terminology used here. Video In uses internal buff-ering before writing data to SDRAM. There are two inter-nal buffers, each 64 entries of 32 bits.
In fullres mode, each internal buffer is used for 128 Ysamples, 64 U samples and 64 V samples. Once the firstinternal buffer is filled, 4 highway transactions need tooccur before the second buffer fills completely. Hence,the requirement for not loosing samples is:
• 4 requests have to be served within 256 Video Inclock cycles.
For the typical CCIR601 resolution NTSC or PAL 27 MHzVideo In clock rate, the latency requirement is 4 requestsin 25600/27 = 9481 ns, which can be used as one re-quest every 2370 or with a TM1100 SDRAM clock speedof 100 MHz, every 237 SDRAM clock cycles. The one re-quest latency is used to define the priority raising value(see Section 19.6.3 on page 19-8).
In halfres mode, the Y, U and V decimation by 2 takesplace before writing to the internal buffers. Hence, the re-quirement for not loosing samples is:
• 4 requests have to be served within 512 Video Inclock cycles.
For halfres subsampling NTSC or PAL 27 MHz Video Inclock rate and TM1100 SDRAM clock speed of 100 MHz,latency is 4 requests in 51200/27 = 18962 ns (1896 high-way clock cycles) or one request every 4740 ns (474SDRAM clock cycles).
For raw8 capture and message passing mode, each in-ternal buffer stores 64 samples at the incoming Video Inclock rate. The latency requirement is:
• 1 request has to be served every 64 Video In clockcycles.
For the raw10 capture modes, each internal buffer stores32 samples. Hence, the requirement for not loosing sam-ples is:
• 1 request has to be served every 32 Video In clockcycles.
For a 38 MHz data rate on the incoming 10-bit samplesand a TM1100 SDRAM clock speed of 100 MHz, latencyfor the highway should hence be set to guarantee lessthan 3200/38 = 842 ns (84 SDRAM clock cycles) perclock cycles which cannot be met if any of the other pe-ripherals is enabled.
Table 6-4 summarizes the maximum allowed highwaylatency, in SDRAM clock cycles) to guarantee that no
ACTIVE = BUF2BUF1FULL
ACTIVE = BUF1
ACTIVE = BUF2
ACTIVE = BUF1BUF2FULL
BUF1FULLBUF2FULL
raise OVERRUN*
* OVERRUN and OVERFLOW are sticky flags. They get set, but they do not affect operation. They can only be cleared by software, by writing a ‘1’ to ACK_OVR or ACK_OVF. (See text in Section 6.6)
ACK1 & ~ACK2
ACK1 & ACK2
~ACK1 & ACK2
EOM
EOM
EOM
ACK1
EOM
ACK2
RESET
No EOM ⇒ raise OVERFLOW*(See text in Section 6.6)
No EOM ⇒ raise OVERFLOW*(See text in Section 6.6)
Figure 6-18. Video In message passing mode major states.
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Philips Semiconductors Video In
samples are lost. The general formula uses ‘F’ to repre-sent the Video In clock frequency (in MHz).
Bandwidth requirement (in bytes) per video line with ac-tive image for Video In in fullres mode is:
• Bfullr = ceil(WIDTH*2/256) * 4 * 64
ceil(X) function is the least integral value greater than orequal to X.
In halfres mode the bandwidth is:
• Bhalfr = ceil(WIDTH*2/512) * 4 * 64
Raw8 mode and message passing mode bandwidth de-pends only on Video In clock speed. For raw10 modeeach 10 bit value counts as 2 bytes for bandwidth com-putations.
Table 6-4. Video In highway latency requirements (27 MHz data rate, 100 MHz TM1100 highway clock)
ModeMax latency
setting(27 MHz, 100 MHz)
Formula
fullres capture 237 6400/F
halfres capture 474 12800/F
raw8 237 6400/F
raw10s 118 3200/F
raw10u 118 3200/F
message passing 237 6400/F
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6-14 PRELIMINARY INFORMATION File: vin.fm5, modified 7/24/99
Video Out Chapter 7
by Marc Duranton, Dave Wyland, Gert Slavenburg
7.1 NEW IN TM1100
The TM1100 Video Out has a number of enhancementswith respect to TM1000 Video Out, in particular:
• Full 129-level alpha blending (8-bit alpha value)• addition of chroma keying• genlock capability• programmable YUV output clipping values
7.2 DOCUMENT STRUCTURE
The chapter below first describes the TM1000 Video Outfunctionality, with updated TM1100 clock generator, andthen has a separate section with the other TM1100 im-provements. This chapter will soon be replaced by an in-tegrated, TM1100 specific chapter.
7.3 SUMMARY OF FUNCTIONS
The TM1100 Video Out unit (VO) generates and trans-mits continues digital video images. It connects to an offchip video subsystem such as a digital video encoderchip (DENC), a digital video recorder or the video inputof another TM1100 through a CCIR 656 compatible byteparallel video interface. The VO can either supply or re-ceive video pixel clock and/or synchronization signals to/from the external interface. Pixel clock frequency andvideo field/frame format can be precisely controlledthrough programmable registers, to support PAL, NTSC,16:9 and other video format including double pixel ratenon-interlaced video formats.
VO combines a background video image from SDRAMwith an optional foreground graphics overlay image fromSDRAM using per-pixel alpha blending, and sends thecomposite result out as continuous video. Video imagedata is taken from a planar memory format, with separateY,U and V planes in memory in YUV 4:2:2 or 4:2:0 for-mat. The optional graphics overlay is taken from a pixelpacked YUV 4:2:2+α data structure in memory.
VO can also be used to emit raw data or send uni-direc-tional messages from one TM1100 to one or more otherTM1100’s. In the Data Streaming mode, the VO gener-ates a continuous stream of arbitrary byte data using in-ternal or external clocking. Dual buffers allow continuousdata streaming in this mode by allowing the DSPCPU toset up a buffer while another is being emptied by the VO.Messages can be sent to one or more TM1100 Video In
ports in the Message Passing mode. Start and end-of-message signals are provided in this mode to synchro-nize message passing to the other TM1100 message re-ceivers.
The Video Out unit provides the following key functional-ity:
• Continuous digital video output of PAL or NTSC for-mat data according to CCIR601.
• YUV 4:2:2 co-sited pixel data output is transmittedacross a standard 8 bit parallel CCIR6561 interface.Embedded SAV and EAV synchronization codes aswell as separate sync control signals compatible withPhilips DENC encoders are available.
• A nominal PAL/NTSC data rate of 27 megabytes/sec-ond = 13.5 megapixels/second, but any data rate upto 60% of DSPCPU clock is supported.
• Custom video formats with frames or fields of up to4095 lines of up to 4095 pixels are supported, sub-ject only to the data rate limitation.
• The video image can be in planar YUV 4:2:2 co-sited, planar YUV 4:2:2 interspersed, or planar YUV4:2:0 memory format.
• The optional graphics overlay image is in pixel-packed YUV 4:2:2+α format, and is alpha blended ontop of the video image. Each pixel has a 1-bit alpha,which selects one of two global 8-bit alpha values.With overlay enabled, the output pixel data rate islimited to 45% of the SDRAM clock, or 60% ofDSPCPU clock, whichever is smaller.
• The video image can optionally be horizontallyupscaled by a factor of 2 for display. The overlay isalways in display format.
• In data streaming mode, VO acts as a high band-width output data channel. The data rate is limited to60% of DSPCPU clock.
• In message passing mode, VO acts as transmitterport for TM1100 to multi-TM1100 unidirectional mes-sage passing. Byte data rate is limited to 60% ofDSPCPU clock.
• VO output data can be internally looped back to theVideo In for diagnostic purposes. This is controlledby the Video In DIAGMODE bit.
1. Refer to CCIR recommendation 656: Interfaces for dig-ital component video signals in 525 line and 625 linetelevision systems. Recommendation 656 is included inthe Philips Desktop Video Data Handbook.
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The VO normally supplies continuous video data to itsoutputs. The VO is programmed and started by theTM1100 DSPCPU. The VO issues an interrupt to theDSPCPU at the end of each transmitted field, and/or at aprogrammable vertical position in the field. The DSPCPUupdates the VO video image data pointers with pointersto the next field during the vertical blanking interval tomaintain continuous video output. During video output,the VO supplies embedded CCIR656 SAV and EAV synccodes and optionally supplies horizontal and frame syncsignals. The VO can either internally supply the timing forthe pixel clock and for the horizontal and frame timingsignals or can genlock to external timing signals such assupplied by a Philips SAA7125 DENC digital encoder orsimilar sync source.
7.4 INTERFACE
Table 7-1 lists the interface pins for the VO block.Figure 7-1, Figure 7-2, and Figure 7-3 illustrate typicalconnections for commonly used external devices that in-terface to the VO. The most common way to generateanalog video is Figure 7-1. In this setup, the SAA7125Digital Encoder (DENC) can be programmed to eithertake sync from the VO_DATA stream EAV/SAV codes,or from the RCV1/2 pins. Figure 7-3 illustrates how tocreate a byte parallel ECL level standard CCIR656 inter-face. In certain professional applications, serial D1 videois also used. In that case, connect VO to a GennumGS9022 Digital Video Serializer or similar part (notshown).
7.5 BLOCK DIAGRAM
Figure 7-4 shows a block diagram of the Video Outblock. It consists of a clock generator, a frame timinggenerator and an image or data generator. The imagegenerator produces either a CCIR 656 digital video datastream with optional YUV overlay or a raw data or mes-sage-data stream. It also performs optional format con-versions and optional 2:1 horizontal scaling.
TM1100
VO_DATA[7:0]
(HS) VO_IO1
(FS) VO_IO2
VO_CLKSAA7125
MP[7:0]
RCV1
RCV2
LLC
Figure 7-1. Video Out connected to a digital video encoder (DENC).
TM1100 A
VO_DATA[7:0]
(STMSG) VO_IO1
(ENDMSG) VO_IO2
VO_CLK
TM1100 B
VI_DATA[7:0]
VI_DATA[8]
VI_DATA[9]
VI_CLK
VI_DVALIDlogic ‘1’
Figure 7-2. Video Out connected to Video In of a second TM1100.
Table 7-1. Video Out Interface Pins
Signal Name Type Description
VO_DATA[7:0] OUT CCIR656 style YUV 4:2:2 digital out-put data, or general purpose high speed data output channel. Output changes on positive edge of VO_CLK.
VO_IO1 I/O-5 This pin can function as HS output or as STMSG (Start Message) output.• If set as HS output, it outputs the
horizontal sync signal• In message passing mode, this pin
acts as STMSG output. See Figure 7-14.
VO_IO2 I/O-5 This pin can function as FS (Frame Sync) input, FS output or as ENDMSG output.• If set as FS input, it can be set to
respond to positive or negative edge transitions.
• If the Video Out operates in external sync mode and the selected transi-tion occurs, the Video Out sends two fields of video data. Note: this works only once after a reset.
• In message passing mode, this pin acts as ENDMSG output. See Figure 7-14.
TM1100
VO_DATA[7:0]
VO_CLK
8
1
16
2
TTL to ECL
CCIR 656Subminiature
“D” Connector
Data A,B[7:0]
Clock A,B
Figure 7-3. Video Out connected to a CCIR 656 vid-eo-output connector.
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Philips Semiconductors Video Out
The frame timing generator provides programmable im-age timing including horizontal and vertical blanking,SAV and EAV code insertion, overlay start and end tim-ing, and horizontal and frame timing pulses. It also sup-plies start-of-message and end-of-message timing in themessage passing mode. The sync timing pulses can begenerated by the frame timing unit, or the frame timingunit can be driven by externally supplied sync timingpulses, as determined by the SYNC_MASTER bit.
The video clock generator produces a programmablevideo clock. The video clock generator can supply thevideo clock for the frame timing generator and externaldevices, or it can be driven by an external clock signal.
7.6 CLOCK SYSTEM
Positive edges of VO_CLK drive all VO output events. Ablock diagram of the VO clock system is shown inFigure 7-5. The VO clock is either supplied externally orinternally generated by the VO, as controlled by the CLK-OUT bit in the VO_CTL register. When the CLKOUT bitis zero, the VO clock is supplied by an external sourcethrough the VO_CLK pin as an input. This is the defaultmode, entered at hardware reset. When CLKOUT is aone, an internal clock generator supplies the VO clockand drives the VO_CLK pin as an output.
At the heart of the internal clock generator system is asquare wave DDS (Direct Digital Synthesizer). The DDScan be programmed to emit frequencies from 0 Hz to 40MHz. The output of the DDS is sent to a phase lockedloop filter, which removes clock jitter from the DDS out-put signal. The PLL can also be used to divide or doublethe DDS frequency. The PLL VCO operates from 8 MHzto 90 MHz. The PLL needs to be enabled/programmed,as described in section 7.15. DDS programming is ac-complished by setting the FREQUENCY field in theVO_CLOCK register according to the TM1100 specificequation in Figure 7-6. Note that the VO_CLK frequencycan be a divider or multiple of fDDS., as determined by thePLL subsystem settings.
7.6.1 TM1000 Compatibility Mode
TM1000 DDS compatibility mode is provided so thatTM1000 software runs without changes. It should NOTbe used for new software development, since clock jitterin TM1000 mode is 3x larger than in the new TM1100mode. TM1000 mode is automatically entered wheneverFREQUENCY[31] = 0. In TM1000 mode, DDS frequencyis set as follows:
7.7 IMAGE TIMING
The VO emits a serial byte data stream used by a CCIR656 device to generate a displayed image. Figure 7-7shows an NTSC-compatible, 525-line interlaced image.The field and line numbers are shown for reference.
Interlaced images are generated by the display hardwareby controlling the vertical retrace timing. A timing dia-gram of NTSC compatible interlaced frame timing illus-trating the analog vertical retrace signal is shown inFigure 7-8 for reference. The vertical retrace signal forthe second field begins in the middle of the horizontal linethat ends the first field. This causes the first line of thesecond field to begin halfway across the display screen
VO_CLK I/O-5 The Video Out unit emits VO_DATA on a positive edge of VO_CLK. VO_CLK can be configured as input (reset default) or output.• If configured as input: VO_CLK is
received from external display clock master circuitry.
• If configured as output, TM1100 emits a programmable clock fre-quency. The emitted frequency can be set between approx. 4MHz and 80 MHz with a resolution of 0.07 Hz. The clock generated is frequency accurate and has low jitter proper-ties due to a combination of an on-chip DDS (Direct Digital Synthe-sizer) and VCO/PLL.
Table 7-1. Video Out Interface Pins
Signal Name Type Description
Video Frame Timing
Generator
Video Clock Generator
Image GeneratorOverlay Generator
Message/Data Generator
VO_IO1(HS or Start Msg)
VO_IO2(VS or End Msg)
VO_CLK
VO_DATA[0:7]
SD
RA
M H
ighw
ay
Figure 7-4. Video Out block diagram.
Square-Wave DDS
FREQUENCY
PLLFilter
VO_CLK
VO_CLK Internal(to Frame Timing Gen.)
CLKOUT3 × CPU Clock
03
Figure 7-5. Video Out clock system.
Figure 7-6. DDS Oscillator Frequency (TM1100)
FREQUENCY 231 f DDS 2
32⋅9 f DSPCPU⋅-------------------------------+=
FREQUENCYf DDS 2
32⋅3 f DSPCPU⋅-------------------------------=
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and the lines of the second field to be scanned betweenthe lines of the first field (interlaced).
The analog timing to generate the interlaced signal issupplied by the display device. The CCIR 656 digital vid-eo signals generated by the VO use frame synchroniza-tion timing and do not generate any vertical retrace tim-ing.
7.7.1 CCIR 656 Pixel Timing
The VO generates pixels according to CCIR 656 timingin YUV 4:2:2 co-sited format and outputs these pixels as
shown in Figure 7-9. Pixels are generated in groups oftwo, with four bytes per two pixels. Each pair of pixelshas two luminance bytes (Y0, Y1) and one pair ofchrominance bytes (U0, V0) arranged in the sequenceshown. The chrominance samples U0 and V0 are sam-pled spatially co-sited with luminance sample Y0. ForPAL or NTSC video, pixels are generated at a nominalrate of 13.5 megapixels per second (27 MB/sec). Pixelsare clocked out on the positive edge of VO_CLK.
Figure 7-8. Interlaced timing–NTSC analog sync. signals.
U0 Y0 V0 Y1 U2 Y2 V2 Y3 U4
Byte 0
Line Scan @ 27 MHz = 13.5 MPixels/sec
VO_DATA[0:7]
VO_CLK
Y4
Figure 7-9. CCIR 656 pixel timing.
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7.7.2 CCIR 656 Line Timing
The CCIR 656 line timing is shown in Figure 7-10. Eachline begins with an EAV code, a blanking interval and anSAV code, followed by the line of active video. The EAVcode indicates end of active video for the previous line,and the SAV code indicates start of active video for thecurrent line.
7.7.3 SAV and EAV Codes
The EAV (End Active Video) and SAV (Start Active Vid-eo) codes are issued at the start of each video line. EAVand SAV codes have a fixed format: a three-byte pream-ble of FFh, 00h, 00h followed by the SAV or EAV codebyte. The EAV and SAV code byte format is shown inFigure 7-11 for reference. The EAV and SAV codes de-fine the start and end of the horizontal blanking interval,and they also indicate the current field number and thevertical blanking interval.
The SAV and EAV codes have a four-bit protection fieldto insure valid codes. The VO generates these protectionbits as part of the SAV and EAV codes as defined byCCIR656. There are eight possible valid SAV and EAVcodes. These eight codes with their correct protectionbits are shown in Table 7-2. The VO generates SAV andEAV sync codes and inserts them into the video out datastream according to the CCIR656 specification under allconditions, whether it is generating or receiving horizon-tal and frame timing information.
7.7.4 F0h and 10h Video Clamps
SAV and EAV codes are identified by a three-byte pre-amble of FFh, 00h and 00h. This combination must beavoided in the video data that the VO sends out to pre-vent accidental generation of an invalid sync code. TheVO includes maximum and minimum value clamps onthe video data to prevent this possibility. After all internalprocessing has been done the VO automatically con-verts resulting image data values in the range F1h..FFhto F0h and values in the range 00h..0Fh to 10h.
7.7.5 CCIR 656 Frame Timing
The frame timing for CCIR 656 is shown in Table 7-3.CCIR 656 defines interlaced frame timing. Lines arenumbered from 1 to 525 for 525-line, 60-Hz systems andfrom 1 to 625 for 625-line, 50-Hz systems. The Field andVertical Blanking columns indicate whether the field andvertical blanking bits, respectively, are set in the SAVand EAV codes for the indicated lines. The 525 and 625formats have similar timing but differ in their line number.
Table 7-2. SAV and EAV Codes
Code Binary Value Field Vertical Blanking
SAV 1000 0000 1
EAV 1001 1101 1
SAV 1010 1011 1 X
EAV 1011 0110 1 X
SAV 1100 0111 2
E S SE E
Blanking Active VideoBlanking
Active Video
Line i Line i+1
SAV, EAV Codes YUV 4:2:2 pixels
Figure 7-10. CCIR 656 line timing.
Figure 7-11. Format of SAV and EAV timing codes.
Preamble
1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 F V H P P P P
Timing reference code
Protection bits (error correction)
H = 0 for SAVH = 1 for EAV
V = 1 during field blankingV = 0 elsewhere
F = 0 during field 1F = 1 during field 2
EAV 1101 1010 2
SAV 1110 1100 2 X
EAV 1111 0001 2 X
Table 7-3. CCIR 656 Frame Timing
Line NumberF bit V bit Comments
525/60 625/50
1–3 624–625 1 1 Vertical blanking for field 1, SAV/EAV code still indicates field 2
Table 7-2. SAV and EAV Codes
Code Binary Value Field Vertical Blanking
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7.8 VIDEO OUT TIMING GENERATION
The VO generates timing for frames, active video areaswithin frames, images within the active video area, andoverlays within the image area. The relationship betweenthese four is shown in Figure 7-12. The frame includesthe timing for both interlaced fields. Progressive scan, ornon-interlaced video, is accomplished by setting the tim-ing parameters such that 2 identical successive fields aregenerated.
The active image area begins after the horizontal andvertical blanking intervals and represents the pixels thatare visible on the screen. The image area is the actualdisplayed image within the active video area. It can beslightly smaller than the active video area to avoid edgeeffects at the top, bottom and sides of the image. Theoverlay area is within the image area.
The VO uses two sets of counters to generate and con-trol image timing: frame counters and image counters.The Frame Line Counter and Frame Pixel Counter con-trol the overall timing for the frame and define the totalnumber of pixels per line, lines per frame and interlacetiming, including horizontal and vertical blanking inter-vals. Note that the Frame Line Counter has a starting val-ue of one, not zero, and it counts from 1 to 525 or 625,consistent with CCIR 656 line numbering. The ImageLine Counter and Image Pixel Counter define the visibleimage within the field.
The geometry of active video is defined by the contentsof several MMIO registers; see Figure 7-25. The FIELD2 START value defines the start line of field 2. Field 2 isactive when the Field Line Counter contents equal or ex-ceed this value. The active video area is defined by theF1 VIDEO LINE and F2 VIDEO LINE values for eachfield of the frame and VIDEO PIXEL START value foreach line of the frame. The active video area beginswhen the contents of the Frame Line Counter and FramePixel Counter equals or exceeds these values.
The CCIR 656 compliant 525/60 and 625/50 timing spec-ifications define an overlap period where the field num-ber in the SAV and EAV codes from field 1 persist intothe vertical blanking interval for field 2, and the codes forfield 2 persist into the vertical blanking interval for field 1.
The F1 OLAP and F2 OLAP values define these overlapintervals. During the overlap interval, the vertical blank-ing for the next field has begun; however, the field num-ber flag in the SAV and EAV codes still shows the fieldnumber for the previous field. The field number is updat-ed to the correct field value at the end of the overlap in-terval.
F1 OLAP defines the overlap from field 1 to field 2. Thisoverlap occurs during the beginning of vertical blankingfor field 2; The SAV and EAV codes continue to showfield 1 during this overlap interval, and they change tofield 2 at the end of the interval.
F2 OLAP defines the overlap from field 2 to field 1. Thisoverlap occurs during the beginning of vertical blankingfor field 1; The SAV and EAV codes continue to showfield 2 during this overlap interval, and they change tofield 1 at the end of the interval.
F1 OLAP and F2 OLAP are small two’s complement val-ues in the range -8 .. +7 . A positive value indicates thatthe overlap extends into the current field, while a nega-tive value indicates that it extends backward into the pre-vious field. See Figure 7-26 for the effect of negative andpositive values.
The frame and image counters have different start andstop points. The frame counters begin in the verticalblanking interval of the first field and the horizontal blank-ing interval of the first line. They stop counting when theyreach the height and width values of the frame. When theVO generates the frame timing, the frame counters are
4–19 1–22 0 1 Vertical blanking for field 1, change SAV/EAV code to field 1
20–263 23–310 0 0 Active video, field 1
264–265 311–312 0 1 Vertical blanking for field 2, SAV/EAV code still indicates field 1
266–282 313–335 1 1 Vertical blanking for field 2, change SAV/EAV code to field 2
283–525 336–623 1 0 Active video, field 2
Table 7-3. CCIR 656 Frame Timing
Line NumberF bit V bit Comments
525/60 625/50
Overlay
Image Area, Field 1
Vertical Blanking, Field 1
Hor
izon
tal
Bla
nkin
g
Overlay
Image Area, Field 2
Vertical Blanking, Field 2
Hor
izon
tal
Bla
nkin
g
Image V Offset
Image V Offset
Imag
e H
Offs
etIm
age
H O
ffset
Image Width Imag
e H
eigh
t
Frame
Active Video Area
Active Video Area
Start Pixel
StartLine
Figure 7-12. Frame, field, active video, image, and overlay definitions.
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reset to their start values when they reach their stop val-ues; when the VO receives frame timing signals, theframe counters continue counting until reset by the exter-nal signals.
The image area is defined by the IMAGE VOFF and IM-AGE HOFF values. These values are added to the VF1or F2 VIDEO LINE and VIDEO PIXEL START values todefine the starting line and pixel, respectively of the im-age area. The image area is active when the contents ofthe Frame Line Counter and Frame Pixel Counter equalor exceed these values.
The Image Line Counter and Image Pixel Counter startcounting at the first active pixel in the image area and thefirst active line in the image area, respectively. The im-age counters start at zero and stop counting when theyreach their image height and width values. The imagecounters are reset by frame counter values indicating thestart of the image pixel in a line and the start of the imageline in a field.
The image counters define the active image area of theframe, the area of interest for image processing. This al-lows the overlay start address to be defined relative tothe active image area, for example. When the VO is notsending out active pixels from the image area, it sendsout blanking codes. These blanking codes are (0x80,0x10, 0x80, 0x10) for each two pixel group in YUV 4:2:2image data format, as defined by CCIR 656 and shownin Figure 7-9.
7.8.1 Horizontal and Frame Timing Signals
The VO can supply horizontal and frame timing signalsor receive a frame timing signal. When theSYNC_MASTER bit is set, the VO generates the hori-zontal and frame timing for the external video device.When the SYNC_MASTER bit is cleared, Video Out op-erates in external sync mode and an external device,such as a DENC, is responsible for providing frame sync.
If SYNC_MASTER is set, VO_IO1 acts as output andgenerates a horizontal timing signal, and VO_IO2 gener-ates a frame timing signal. Figure 7-13 shows how thegenerated signals relate to the VO line and field timing.The horizontal timing signal corresponds to the horizon-tal-blanking interval, and the frame timing signal corre-sponds to the field-2 active interval. The horizontal timingsignal is active low from the EAV code at the start of theline to the SAV code at the start of active video for theline. The frame timing signal is active high from the EAVcode that begins the first line of vertical blanking for field2 to the EAV code that begins the first line of blanking forfield 1. Note: The VO_IO2 signal does not take the F1and F2 overlap regions into account and therefore differsfrom the field value indicated by the SAV and EAV codesduring the overlap times.
If SYNC_MASTER is clear, VO expects frame timing sig-nals on the VO_IO2 pin. The active edge of the signalcan be programmed using VO_IO2_POS. The selectedtransition of the frame timing signal on VO_IO2 causesthe Frame Line Counter to be set to the FRAME PRE-SET value and video output to start. Horizontal sync startis taken from the transition on VO_IO2, and generatedinternally subsequently. Note: due to implementation lim-itations FRAME PRESET must be 1. Due to implemen-tation limitations this works only once after reset. To con-tinuously use this genlock feature, a periodic softwarereset is required.
7.9 DATA TRANSFER TIMING
In the data streaming and message passing modes, theVO supplies a stream of 8-bit data. No data selection ordata interpretation is done, and data is transferred at onebyte per VO_CLK. Data is clocked out on the positiveedge of VO_CLK.
The message passing mode issues signals on VO_IO1and VO_IO2 to indicate the start and end of the mes-sage. The timing for these signals is shown inFigure 7-14.
Image Line: Image WidthBlanking
Image Width, Pixels
Field Width, Pixels
SAVEAV
VO_IO1
Image Data
EAV
Blanking
Field 1 Field 2V Blanking
Frame Height, Lines (2 fields)
VO_IO2
Image Data V Blanking
Field 1 Field 2
Figure 7-13. Horizontal and vertical timing signals given as output.
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7.10 IMAGE DATA MEMORY FORMATS
7.10.1 Video Image Formats
The VO accepts memory-resident video image data inthree formats: YUV 4:2:2 co-sited, YUV 4:2:2 inter-spersed and YUV 4:2:0. These formats are shown inFigure 7-15 through Figure 7-17.
7.10.2 Planar Storage of Video Image Data in Memory
Video image data is stored in memory with one table foreach of the Y, U and V components. This is called planarformat. This is shown in Figure 7-18 for YUV 4:2:2 imagedata. The VO merges bytes from each of the three tablesto generate the CCIR 656 compatible output data. The Uand V tables have the same number of lines but half thenumber of pixels per line as the Y table. The transfer isthe same for YUV 4:2:0 format except the U and V tables
VO_DATA[7:0]
VO_IO1
VO_IO2
VO_CLK
XX D0 D1 D2 D3 D4 D5 D6 D7 XX XX
Start ofmessage
End ofmessage
Figure 7-14. Video Out message-passing START and END events.
Chrominance (U,V) samples
Luminancesamples
Figure 7-15. YUV 4:2:2 co-sited format.
Chrominance (U,V) samples
Luminancesamples
Figure 7-16. YUV 4:2:2 interspersed format.
Chrominance (U,V) samples
Luminancesamples
Figure 7-17. YUV 4:2:0 format.
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will be 1/4 the size of the Y table. The U and V tableshave the half the number of lines and half the number ofpixels per line as the Y table.
7.10.3 Graphics Overlay Image Format
Graphics overlay image data is stored in a pixel packedformat in SDRAM. Graphics images are stored in YUV4:2:2+alpha formats. Figure 7-19 shows this format. TheYUV overlay is always in the image output resolution.The VO does not upscale the graphics overlay image. Ifthe VO is upscaling the video image by 2×, the graphicsoverlay must be provided in upscaled format.
7.10.4 Alpha Blending
The VO provides alpha blending of the background videoimage with the foreground graphics overlay image. Nochroma keying is supported.
Alpha blending combines the graphics overlay imagewith the video image according to an alpha value provid-
ed with each overlay pixel. In the YUV 4:2:2+α format,each pixel has a single α-bit supplied as the least signif-icant bit of the U and V pixels. The U byte lsb corre-sponds to the alpha for pixel Y0, the V byte lsb for pixelY1, respectively. When the α-bit is zero, the ALPHAZERO register supplies the actual 8 bit α value. Whenthe α-bit is one, the ALPHA ONE register supplies the 8bit α value. Alpha blending combines video and overlayaccording to Table 7-4. Although 7 bits of blending reso-lution are provided for in the architecture, the actual num-ber of bits implemented depends on the TM1000 version.TM1000 and TM1000 compatibility mode of TM1100only implements 25% step resolution. TM1100 EVOmode and successor chips provide all 129 blending lev-els.
In the YUV 4:2:2 format, only one set of U and V valuesis supplied for the two Y pixels, Y0 and Y1. The alpha bitin U0 determines the alpha value for U, Y0 and V. Thealpha blend bit in V0 only sets the alpha value for Y1 anddoes not affect the U or V values.
7.11 VIDEO IMAGE CONVERSION ALGORITHMS
The memory video image data formats are converted tothe output YUV 4:2:2 co-sited format and optionally up-scaled 2x horizontally. The conversion algorithms aredetailed below.
7.11.1 YUV 4:2:2 Interspersed to YUV 4:2:2 Co-sited Conversion
The VO can accept data from SDRAM in either YUV4:2:2 co-sited, YUV 4:2:2 interspersed or YUV 4:2:0 in-terspersed formats. If the input data is in YUV 4:2:2 orYUV 4:2:0 interspersed format, interspersed-to-co-sitedconversion is performed to generate co-sited output. TheVO uses a four-tap, (–1, 5, 13, –1)/16 filter to perform thisconversion on the U and V chroma data. An example ofinterspersed to co-sited conversion is shown inFigure 7-20.
7.11.2 YUV 4:2:0 to YUV 4:2:2 Co-sited Conversion
YUV 4:2:0 to YUV 4:2:2 conversion is a variation of YUV4:2:2 interspersed-to-co-sited conversion. The YUV4:2:0 format has the U and V pixels positioned betweenlines as well as between pixels within each line. It also
WIDTH pixels
HE
IGH
T li
nes
pix0 pix1 pix2pix
W–1• • •Y_BASE_ADR
WIDTH/2 pixels
HE
IGH
T li
nes
pix0 pix2 • • •U_BASE_ADR
(Repeated for V_BASE_ADDR,
V_OFFSET)
Y_OFFSET
U_OFFSET
Figure 7-18. Image storage in planar memory format for YUV 4:2:2.
Figure 7-20. YUV interspersed to co-sited conversion.
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has half the number of U and V pixels compared to YUV4:2:2 formats. The VO converts YUV4:2:0 to YUV 4:2:2co-sited by using the U and V chrominance pixels valuesfor both surrounding lines and converting the resulting Uand V pixels from interspersed to co-sited format. This isshown in Figure 7-21. If true vertical resampling of U andV is desired, the TM1100 image co-processor can be in-
voked on U and V to convert from YUV 4:2:0 to YUV4:2:2 interspersed.
7.11.3 YUV-2X Upscaling
In the YUV-2X modes, the VO performs 2× horizontal up-scaling of the YUV data from SDRAM. No vertical up-scaling is performed. The width of the result image (IM-AGE WIDTH) should be an even number. Upscaling isperformed by four-tap filtering. For all 3 memory formats,Y luminance data is upscaled using a (–3,19,19,–3)/32filter to generate the missing output pixels. The outputpixels that are at the same location as the input pixelsuse the corresponding input pixel values. This is shownin Figure 7-22.
The U and V chrominance values are generated in thesame way as the Y luminance signal for 2× upscaling,assuming that both the input and output use YUV 4:2:2
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co-sited chrominance coding. The U and V output pixelsthat are at the same location as the U and V input pixelsuse the corresponding input pixel values. The U and Voutput pixels that are between the U and V input pixelsare generated using the (–3,19,19,–3)/32 filter. This isshown in Figure 7-22.
If the input chroma is interspersed, a (–1,13,5,–1)/16 fil-ter is used to generate the U and V output pixels that aredisplaced by half a Y pixel from the U and V input pixels,and a (–1,5,13,–1)/16 filter is used to generate the addi-tional upscaled U and V output pixels that are displacedby 1.5 pixels from the U and V input pixels. This is shownin Figure 7-23.
7.11.4 Pixel Mirroring for Four-tap filters
The VO uses a four-tap filter for upscaling and for con-verting from interspersed to co-sited format. One extrapixel is needed at the beginning and two at the end ofeach line that is processed by this filter. These pixels aresupplied automatically by mirroring the first and last pix-els of each line. For example:
• Output pixel 1 uses input pixel 1 to generate its value.(same location, no filtering).
• Output pixel 2 uses pixels 1,1, 2 and 3 to generate itsvalue.
• Output pixel 3 uses pixel 2 to generate its value.• Output pixel 4 pixel uses pixels 1, 2, 3 and 4, etc.• .......• Output pixel 2N–2 uses pixels N–2, N–1, N, and N–1
to generate its value.• Output pixel 2N–1 uses pixel N to generate its value.• Output pixel 2N uses pixels N–1, N, N, and N–1 to
generate its value.
Figure 7-24 shows an example of six pixels upscaled to12 pixels.
7.12 OPERATING MODES
The Video Out operation is set by the MODE field in com-bination with the OL_EN (overlay enable) control bit. TheMODE field determines video refresh, message passingor data streaming mode. It further defines the video im-age format and whether or not 2x horizontal upscalingtakes place. The OL_EN bit determines whether a videorefresh mode has a graphics overlay present. Thesemodes are shown in Table 7-5.
Data Streaming mode, continuous transmission of raw 8-bit data.
1001 Message Passing
VO to VI message passing: exchange of raw 8 bit data with STMSG and ENDMSG signalling
1Input Pixels: Y
Output Pixels: Y’
2 3 4 5 6
1 3 5 7 9 112 4 6 8 10 12
Y’=Y1 Y’=Y2 Y’=Y3 Y’=Y4 Y’=Y5 2N–1:Y’=Y6
Y’=F(Y1,Y1,Y2,Y3)
Y’=F(Y1,Y2,Y3,Y4)
Y’=F(Y2,Y3,Y4,Y5)
Y’=F(Y3,Y4,Y5,Y6)
Y’=F(Y4,Y5,Y6,Y6)
2N:Y’=F(Y5,Y6,Y6,Y5)
Figure 7-24. Mirroring pixels in 2 × upscaling.
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7.13 MMIO REGISTERS
The MMIO Control Registers are shown in Figure 7-25.The register fields are described in Table 7-6, Table 7-7and Table 7-8. To ensure compatibility with future devic-es, any undefined MMIO bits should be ignored whenread, and written as zeroes.
1010thru1111
Reserved
Table 7-5. Video Out Operating Modes
Mode Function Explanation
VO_STATUS (r)0x10 180031 0
MMIO_BASEoffset:
VO_CLOCK (r/w)0x10 1808
VO_FRAME (r/w)0x10 180C
VO_FIELD (r/w)0x10 1810
CUR_Y(12)371115192327
FREQUENCY
FRAME PRESET
F2 OLAP
CUR_X(12)
VO_CTL (r/w)0x10 1804 MODE
FIELD 2 START
F2 VIDEO LINE
VO_LINE (r/w)0x10 1814 VIDEO PIXEL START
VO_IMAGE (r/w)0x10 1818 IMAGE HEIGHT
VO_YTHR (r/w)0x10 181C Y THRESHOLD
VO_OLSTART (r/w)0x10 1820 OL START LINE
VO_OLHW (r/w)0x10 1824
OL START PIXEL
BFR1_EMPTYBFR2_EMPTY
HBEURUN
YTRFIELD2
VBLANK
RESETSLEEPLESS
CLKOUTSYNC_MASTER
VO_IO1_POSVO_IO2_POS
OL_EN
BFR1_ACKBFR2_ACK
HBE_ACK
URUN_INTENYTR_INTEN
URUN_ACKYTR_ACK
LTL_ENDVO_ENABLE
31 0371115192327
VO_YADD (r/w)0x10 1828 Y_BASE_ADR or BFR1BASE_ADR
VO_UADD (r/w)0x10 182C U_BASE_ADR or BFR2BASE_ADR
VO_VADD (r/w)0x10 1830 V_BASE_ADR or SIZE1
VO_OLADD (r/w)0x10 1834 OL_BASE_ADR or SIZE2
VO_VUF (r/w)0x10 1838 U_OFFSET(16)
VO_YOLF (r/w)0x10 183C Y_OFFSET(16)
V_OFFSET(16)
31 0371115192327
FRAME LENGTH
F1 VIDEO LINEF1 OLAP
FRAME WIDTH
IMAGE WIDTH
IMAGE VOFF IMAGE HOFF
GLOBAL ALPHA 1
OVERLAY HEIGHT OVERLAY WIDTH
OL_OFFSET(16)
GLOBAL ALPHA 0
BFR2_INTENHBE_INTEN
BFR1_INTEN
CLOCK_SELECTPLL_S
PLL_T
reserved
31 0371115192327
Figure 7-25. Video Out MMIO registers.
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Philips Semiconductors Video Out
7.13.1 Status Register
The VO_STATUS register is a read-only register that shows the current status of the VO. Its fields are shown inTable 7-6.
7.13.2 Control Register
The VO_CTL register sets the operating mode, interrupt enables and clears interrupt flags and initiates VO operations.Its fields are shown in Table 7-7.
Table 7-6. Status Register Fields
Field Description
CUR_Y Current Y: image line index of the current line in the current field being output by VO. CUR_Y reflects current state of the Image Line Counter. CUR_X & CUR_Y form a single 24-bit output data byte counter (CUR_X=counter LSBs) when VO in data-streaming or message-passing mode. This counter reflects the status of the SIZE counter for the currently active buffer. The two LSBs of this counter are not valid for reading during transfers; only the upper 22 bits (the word count) are valid.
CUR_X Current X: image pixel index of the most-recently output pixel. CUR_X reflects the current state of the Image Pixel Counter.
BFR1_EMPTYBFR2_EMPTY
Buffers 1 & 2 Empty: these bits are valid in video refresh, data-streaming & message-passing modes. • In video refresh modes, only buffer 1 is used. BFR1_EMPTY indicates that the last byte of a field has been trans-
ferred. It is actually raised at the completion of the transmission of the Overlap area of the field, as per Figure 7-26. At this point, software should assign a new field of imagery to Y,U,V_BASE_ADR and perform a BFR1_ACK. If BFR1_EMPTY is not cleared by BFR1_ACK before the start of emission of the active video area of the next field, the VO sets the URUN bit.
• In data-streaming mode, BFR1_EMPTY and BFR2_EMPTY indicate that the last byte in their corresponding buffer has been transferred. When BFR1_EMPTY or BFR2_EMPTY is set, transfer stops from the corresponding buffer.
• In message passing mode, BFR1_EMPTY signals completion of message transmission.These bits cause an interrupt if their interrupts enables are set, and one interrupt per buffer is signaled.
HBE Highway Bandwidth Error: HBE is set when the SDRAM highway fails to respond in time to a highway read request and data was not ready in time to be set on VO data lines. HBE can be set in both image- and data-transfer modes. HBE indicates insufficient bandwidth was requested from the highway arbiter.
YTR In video refresh modes, YTR indicates that the Image Line Counter value is equal to the Y THRESHOLD value in VO_YTHR. The Y THRESHOLD value can be set to provide an interrupt on any line in the valid image area.
URUN Underrun: in video refresh and data-streaming modes, this bit indicates that the CPU did not perform an acknowl-edge to indicate updated address pointers for the next field or buffer in time for continuous image or data transfer. URUN causes an interrupt if corresponding enable set.• In video refresh modes, URUN indicates the SAV code marking beginning of active video has been generated
without BFR1_ACK resetting BFR1_EMPTY. In this case, video refresh continues with previous address pointers.• In data-streaming mode, URUN indicates the last byte in active buffer was transferred, and no BFR1_ACK or
BFR2_ACK occurred to enable next buffer. In this case, transfer continues with previous address pointers.
FIELD2 • Field 2/Bfr 2 Active: in data streaming modes, zero when buffer 1 is active; one when buffer 2 is active.• In video refresh modes, FIELD2 indicates that VO is actively sending out a video image for field 2, as defined by
Figure 7-26.
VBLANK Vertical Blanking: indicates VO is in a vertical-blanking interval. VBLANK active only in video refresh modes.
Table 7-7. VO_CTL Register Fields
Field Description
RESET Software reset of VO. The recommended software reset procedure is:1. Write desired VO_CTL state with RESET bit set, VO_ENABLE clear.2. Write desired VO_CTL state with RESET bit clear, VO_ENABLE clear.3. Wait at least 5 VO-clocks.4. Write desired VO_CTL with RESET bit clear, VO_ENABLE set.Note:A hardware reset clears CLKOUT & SYNC_MASTER bits and put VO_CLK, VO_IO1, & VO_IO2 in input state. This results in a VO_CTL value of 32400000h.In contrast a software reset does not change device registers. So software reset results in a state as specified by the VO_CTL word value written during the above procedure.
SLEEPLESS Prevents power down of the VO when TM1100 power down is active.
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PLL_S This field sets the PLL input divider division ratio. A value of k selects division by k+1.The hardware reset default for the field value is 1, causing division by 2.
PLL_T This field sets the PLL feedback loop divider division ratio. A value of k selects division by k+1.The hardware reset default for the field value is 1, causing division by 2.
CLKOUT • When one, CLKOUT enables VO clock generator and makes VO_CLK an output.• When zero (hardware reset default), VO_CLK is input, and VO clock is provided by the external device.
SYNC_MASTER • When one, VO_IO1 and VO_IO2 are outputs. In video refresh modes, the VO generates horizontal and frame timing signals on VO_IO1 and VO_IO2 respectively. In message passing mode, this bit should always be set so that VO_IO1 and VO_IO2 generate START and END message signals respectively.
• When zero (hardware reset default), VO_IO2 is an input. In video refresh modes VO_IO2 serves as frame time reference. The active edge is selected by VO_IO2_POS. Note: This works only once after reset. To use this feature you have to periodically do a software reset.
VO_IO1_POSVO_IO2_POS
• VO_IO1_POS has currently no function• VO_IO2_POS determines input polarity on VO_IO2.• When zero, the corresponding input triggers on the negative (high-to-low) transition of the input signal.• When one, the input triggers on the positive (low-to-high) transition.
OL_EN Overlay Enable: enables the YUV overlay function in video refresh modes.
MODE Defines the video output major operating mode, as listed in Table 7-5 on page 7-11.
BRF1_ACKBFR2_ACK
Buffer-1 & buffer-2 acknowledge: when active in data-transfer modes, writing a one to BFR1_ACK clears BFR1_EMPTY and enables buffer 1 for transfer until BFR1_EMPTY is set. Writing a zero to BFR1_ACK has no effect. BRF2_ACK operates similarly for buffer 2. Writing a one to VO_ENABLE in the data-streaming mode is the same as writing a one to both BFR1_ACK & BFR2_ACK and enables both buffers 1 & 2 for transfer. Writing a one to VO_ENABLE in message-passing mode is the same as writing a one to BFR1_ACK and enables buffer 1 for transfer. BFR2_ACK is not used in message-passing mode, since only buffer 1 is used.
HBE_ACK URUN_ACK
Writing a one to these bits clears the HBE or URUN flags and resets their corresponding interrupt conditions.
YTR_ACK Writing a one to this bit clears the YTR flag and resets its interrupt condition. YTR signals the CPU to set new pointers for the next field. If YTR_ACK is not received by the time the active image area for the next field starts, the URUN flag is set. Data transfer continues with the old pointer values.
BFR1_INTEN BFR2_INTENHBE_INTENURUN_INTENYTR_INTEN
Enable corresponding interrupts when the BFR1_EMPTY, BFR2_EMPTY, HBE, URUN (underrun/end of transfer), and YTR (end of field/buffer) flags are set, respectively.Note: BFR2_INTEN, URUN_INTEN, YTR_INTEN must be 0 in message passing mode.
LTL_END Little-endian: specifies that data in SDRAM is stored in little-endian format. This only affects the overlay packed image format interpretation in the video refresh modes. Refer to Appendix C, “Endian-ness,” for details on Byte Ordering.
VO_ENABLE Enables the VO to send image data or message data to its output.Note: This bit should not be simultaneously asserted with the VO_CTL.RESET bit.The correct sequence to reset and enable VO is:1. Write desired VO_CTL with RESET bit set, VO_ENABLE clear.2. Write desired VO_CTL with RESET bit clear, VO_ENABLE clear.3. Wait at least 5 VO-clocks.4. Write desired VO_CTL with RESET bit clear, VO_ENABLE set.Setting VO_ENABLE in video refresh modes starts the VO sending image data beginning with the first pixel in the image. Setting VO_ENABLE in data-streaming and message-passing modes starts the VO sending data begin-ning with the first byte in buffer 1. In video refresh and data-streaming modes, VO_ENABLE remains set until cleared by the CPU. In message-passing mode, VO_ENABLE is cleared with BFR1_EMPTY is set indicating the end of message transfer.De-asserting VO_ENABLE in video refresh modes causes SDRAM reads to stop, but sync framing and BFR1_EMPTY generation/interrupts remain fully operational. Transmitted active image data is undefined. To fully halt Video Out, a software reset is required.
Table 7-7. VO_CTL Register Fields
Field Description
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7.13.3 Video Out Registers
The remaining VO registers and their fields are shown in Table 7-8.
Table 7-8. Video Out Register FIelds
Register Field Description
VO_CLOCK FREQUENCY VO_CLK frequency. See the DDS equation in Figure 7-6, and PLL description in Section 7.15.
VO_FRAME FRAME LENGTH Total number of lines per frame, the ending value of Frame Line Counter. Typically set to 525 or 625. Note frame counter counts from 1 to 525 or 625, consistent with CCIR 656 line numbering.
FIELD 2 START Start line number in Frame Line Counter where second field of frame begins. If non inter-laced pictures are desired, then the same value is programmed for field 1 and field 2.field 1 becomes frame 1 and field 2 becomes frame 2.
FRAME PRESET Value loaded into Frame Line Counter when frame timing edge is received on VO_IO2. Note: currently this must be set to 1.
VO_FIELD F1 VIDEO LINE Line number in the Frame Line Counter of first active video line of field 1 of the frame.
F2 VIDEO LINE Line number in the Frame Line Counter of first active video line of field 2 of the frame.If non interlaced pictures are desired this is programmed to the same value as F1 VIDEO LINE
F1 OLAP Overlap of the SAV and EAV codes from field 1 to field 2. Overlap is defined as the delay in lines from start of blanking for field 2 until SAV and EAV codes for field 2 are emitted. Typ-ical values are +2 for 525/60 and +2 for 625/50.
F2 OLAP Overlap in lines of the SAV and EAV code from field 2 to field 1. Overlap is defined as the delay in lines from start of blanking for field 1 until the SAV and EAV codes for field 1 are emitted. Typical values are +3 for 525/60 and –2 for 625/50. The negative value means field 1 blanking actually starts two lines before end of field 2 of previous frame. This over-lap is described in Table 7-3 on page 7-5, and illustrated in Figure 7-26.
VO_LINE FRAME WIDTH Total line length in pixels including blanking. This is also the ending value for the Frame Pixel Counter. Lines always begin with horizontal blanking interval, and image starts after blanking interval and runs to end of the line.
VIDEO PIXEL START Pixel number in Frame Pixel Counter of starting pixel of active video area within the line.Note: This must be even.
VO_IMAGE IMAGE HEIGHT Video Image line height in lines.
IMAGE WIDTH Video Image line (scaled) output width in pixels. Must be even for upscaling by 2x.
VO_YTHR Y THRESHOLD Threshold image line number in the Image Line Counter for the YTR interrupt.Can be reprogrammed on a frame by frame basis.
IMAGE VOFF Image vertical offset in lines from the top of active video window.
IMAGE HOFF Image horizontal offset in pixels from the start of active video window.
VO_OLSTART OL START LINE Starting image line of YUV overlay within the image. Zero indicates overlay starts at same line as the image.
OL START PIXEL Starting image pixel of the YUV overlay within the image. Zero indicates overlay starts at same pixel as the image. Note: Must be even.
ALPHA ONE Alpha blend value used for YUV 4:2:2+alpha format overlays when alpha bit = 1.
VO_OLHW OVERLAY HEIGHT Height of YUV overlay image in lines. The height of the overlay should be chosen such that it does not extend beyond the image area.
OVERLAY WIDTH Width of YUV overlay image in pixels. Note: must be even.
ALPHA ZERO Alpha blend value used for YUV 4:2:2+alpha format overlays when alpha bit = 0.
VO_YADD Y_BASE_ADRBFR1BASE_ADR
• In video refresh modes, Y-component starting byte address.• In data-streaming and message-passing mode, buffer 1 starting byte address. Note:
Must be 64-byte aligned in data-streaming mode. Note: Must be 4-byte aligned in mes-sage passing mode.
VO_UADD U_BASE_ADRBFR2BASE_ADR
• In video refresh modes, U-component starting byte address.• In data-streaming mode, buffer 2 starting byte address. Note: Must be 64-byte aligned
in data-streaming mode• Not used in message-passing mode.
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7.13.4 Frame and Field Timing Control
The frame timing for 525/60 and 625/50 cases is shownpictorially in Figure 7-26 for reference. CCIR 656 linedefinitions are used.
7.13.5 Timing Registers Recommended Values
The recommended values for the various fields of thetiming registers are shown in Table 7-9 for 525/60 and625/50 timing cases. The FREQUENCY field valueshown is for 27.0 MHz assuming a DSPCPU clock of100.0 MHz.
7.14 VIDEO OUT OPERATION
The VO operates in either video refresh or data transfermodes. The DSPCPU starts the VO by setting the Modefield to the appropriate transfer mode, setting the appro-priate addresses, address offsets, image timing registersand the associated control bits in the Control register andsetting the VO Enable bit. The VO transfers the image ormessage as commanded. In the video refresh and data-streaming modes, the VO runs continuously. In the mes-sage-passing mode, the VO runs only until the messagehas been transferred.
VO_VADD V_BASE_ADRSIZE1
• In video refresh modes, V-component starting byte address.• In data-streaming and message-passing mode, buffer 1 length in bytes. Note: Must be
multiple of 64 in data-streaming mode. SIZE1 is limited to 24bits, giving 16Mbyte maxi-mum buffer or message length.
VO_OLADD OL_BASESIZE2
• In video refresh modes, overlay-image starting byte address. Note: Can be repro-grammed on a frame by frame basis.
• In data-streaming mode, buffer 2 length in bytes. Note: Must be multiple of 64 in data-streaming mode. SIZE2 is limited to 24bits, giving 16Mbyte maximum buffer size.
• Not used in message-passing mode.
VO_VUF U_OFFSET Offset in bytes from start of one line to start of next line.
V_OFFSET Offset in bytes from start of one line to start of next line.
VO_YOLF Y_OFFSET Offset in bytes from start of one line to start of next line.
OL_OFFSET Offset in bytes from start of one line to start of next line.
Table 7-8. Video Out Register FIelds
Register Field Description
Blanking: Field 2 Overlap
Blanking: Field 1
Video Image: Field 1
Blanking: Field 1 Overlap
Blanking: Field 2
Video Image: Field 2
525 Line / 60 Hz
4
20
264
266
283
525
Blanking: Field 1
Video Image: Field 1
Blanking: Field 1 Overlap
Blanking: Field 2
Video Image: Field 2
625 Line / 50 Hz
1
23
311
313
336
623
Blanking: Field 2 Overlap624625
1
Figure 7-26. Video Out frame timing.
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The VO unit is reset by the TM1100 hardware reset, orby a software VO reset, as described in Table 7-7, RE-SET bit.
The VO_CLK is normally set as output to drive the datatransfer for all modes at a programmable rate. TheVO_CLK signal can be an input or output, as controlledby the CLKOUT bit in the VO_CTL register. When CLK-OUT is set, VO_CLK is an output, and its frequency is setby the VO_CLOCK register value. When CLKOUT is azero, VO_CLK is an input and the VO generates data atthe clock rate of the sender.
In video refresh modes, the VO receives or generateshorizontal and frame synchronization signals on theVO_IO1 and VO_IO2 lines, as described in Section7.8.1, “Horizontal and Frame Timing Signals.”
7.14.1 Video Refresh Modes
In the video refresh modes, the VO transfers an imagefrom SDRAM to the VO port. The Mode field in theVO_CTL register defines the video image memory dataformat and whether the VO is to perform horizontal up-scaling (see Table 7-5). The VO accepts memory imagedata in YUV 4:2:2 co-sited, YUV 4:2:2 interspersed andYUV 4:2:0 formats, and generates a CCIR 656 compati-ble, YUV 4:2:2 co-sited image output stream. Scaling isidentified by the YUV-1× and YUV-2× modes. In YUV-1×modes, luminance and chrominance pass unmodified. InYUV-2× modes, luminance and chrominance are hori-zontally upscaled by a factor of two.
During video refresh, the YTR bit is set in the status reg-ister when the Image Line Counter reaches the YTHRESHOLD value. When an image field has been
transferred, the BFR1_EMPTY bit is set in the status reg-ister. The DSPCPU is interrupted when either the YTR orBFR1_EMPTY flag is set and its corresponding interruptis enabled. To maintain continuous transfer of imagefields, the DSP CPU supplies new pointers for the nextfield following each BFR1_EMPTY interrupt. If theDSPCPU does not supply new pointers before the nextfield, the URUN bit is set, and the VO uses the samepointer values until they are updated.
Graphics OverlayThe graphics overlay is enabled by the OL_EN bit in theVO_CTL register. The graphics overlay is typically a soft-ware-generated graphic overlaid onto the output videoimage stream. The graphics overlay is either generatedin YUV by the DSPCPU or converted by the DSPCPUfrom a RGB to a YUV overlay image. The DSPCPU per-forms RGB to YUV conversion, because this conversioncan potentially lose information. Since the DSPCPU typ-ically generates the image, the DSPCPU has the mostinformation about performing this conversion in the mosteffective manner.
The overlay height should be chosen such that the over-lay does not vertically extend beyond the image area. Aheight greater than this causes undefined results andmay result in vertical overlay wraparound.
Note: The emitted byte data rate is limited to 45% of theDRAM clock when overlays are enabled.
The YUV overlay logic assembles the U0, Y0, V0, Y1bytes for a pair of YUV 4:2:2 pixels for both the main im-age and the overlay image. The alpha bit for pixel 0 (theLSB of the U0 byte of the overlay image) selects ALPHAZERO or ALPHA ONE as the alpha source, and the al-pha blend logic combines U0, Y0, and V0 from the mainand overlay images to generate the U0, Y0 and V0 out-put values. The alpha bit for pixel 1 (the LSB of the V0byte of the overlay image) selects ALPHA ZERO or AL-PHA ONE as the alpha source for blending the Y1 pixelsto generate the Y1 output value. The alpha blended U0,Y0, V0 and Y1 bytes are sent to the VO output port in theYUV 422 sequence. The overlay U and V values usedassume a LSB of zero.
Video Image AddressingThe output image is read from SDRAM at a location de-fined by Y_BASE_ADR, Y_OFFSET, U_BASE_ADR,U_OFFSET, V_BASE_ADR, and V_OFFSET. The de-fault memory packing is big-endian although little-endianpacking is also supported by setting the LTL_END bit inthe VO_CTL register.
Horizontally adjacent samples are stored at successivebyte addresses, resulting in a packed form (four 8-bitsamples are packed into one 32-bit word). Upon horizon-tal retrace, the starting byte address for the next line iscomputed by adding the corresponding OFFSET valueto the previous line’s starting byte address. Note thatOFFSET is a 16-bit unsigned quantity. This process con-tinues until the total image—height in lines and width inpixels per line—have been read from memory for lumi-nance (Y). For chrominance, the same number of lines
Table 7-9. Timing Register Recommended Values
Register Field 525/60 Value 625/50 Value
VO_CLOCK FREQUENCY 170A3D70h 170A3D70h
VO_FRAME FRAME-LENGTH
525 625
FIELD 2 START
264 311
FRAME PRE-SET
1 1
VO_FIELD F1 VIDEO LINE
20 23
F2 VIDEO LINE
283 336
F1 OLAP 2 2
F2 OLAP 3 -2 (0xE)
VO_LINE FRAME WIDTH
858 864
VIDEO PIXEL START
138 144
VO_IMAGE IMAGE HEIGHT
240 288
IMAGE WIDTH 720 720(704 visible)
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are read but half the number of pixels per line are read inYUV 4:2:2 and YUV 4:2:0 formats1. The YUV 4:2:0 for-mat has half the number of U and V lines in memory thatthe YUV 4:2:2 formats have, but each line of U and Vdata is read and used twice. See Figure 7-15 throughFigure 7-18.
7.14.2 Data Streaming and Message Passing Modes
In the data streaming and message passing modes, theVO supplies a stream of eight-bit data at up to 80MHzdata rate to the VO_DATA[7:0] pins. Note: In TM1100implementation the data rate is limited to 60% of thehighway clock. The data is read from SDRAM in packedform (four 8-bit bytes per 32-bit word).No data selectionor data interpretation is done, and data is transferred atone byte per VO_CLK from successive byte addresses.
Data-Streaming Mode. In the data streaming mode,data is stored in SDRAM in two buffer tables. When theVO has transferred out the contents of one table, it inter-rupts the DSPCPU and begins transferring out the con-tents of the second table. The DSPCPU supplies point-ers to both tables. The VO can provide a continuousstream of data to the VO output if the DSPCPU updatesthe pointer to the next table before the VO starts trans-ferring data from the next table.
When each buffer has been transferred, the correspond-ing buffer empty bit is set in the status register, and theDSPCPU is interrupted if the buffer empty interrupt is en-abled. To maintain continuous transfer of data, theDSPCPU supplies new pointers for the next data bufferfollowing each buffer empty interrupt. If the DSPCPUdoes not supply new pointers before the next field, theURUN bit is set, and the VO uses the same pointer val-ues until they are updated.
Message-Passing Mode . In the message passingmode data is stored in SDRAM in one buffer table. In thismode, it is required that SYNC_MASTER is set to ensurecorrect operation of VO_IO1 and VO_IO2 as outputs.When message passing is started by settingVO_ENABLE in the VO_CTL register, the VO sends aStart condition on VO_IO1. When the VO has transferredout the contents of the table, it sends an End conditionon VO_IO2 as shown in Figure 7-14, setsBFR1_EMPTY, and interrupts the DSPCPU. The VOstops and no further operation takes place until theDSPCPU sets VO_ENABLE for another message or oth-er VO operation.
7.14.3 Interrupts and Error Conditions
The VO has five interrupt conditions defined by bits in theVO_STATUS register. These are BFR1_EMPTY,BFR2_EMPTY, HBE, URUN, and YTR. Each of these
conditions has a corresponding interrupt enable flag andinterrupt acknowledge action bit in the VO_CTL register.
VO asserts a SOURCE 10 interrupt request to theTM1100 vectored interrupt controller as long as one ormore enabled events are asserted. The interrupt control-ler should always be set such that the Video Out interruptoperates in level triggered mode. This ensures that noevent is lost to the interrupt handler. Refer to Section3.5.3, “INT and NMI (Maskable and Non-Maskable Inter-rupts),” for a description of setting level triggered modeas well as recommendations on writing interrupt han-dlers.
The BFR1_EMPTY, BFR2_EMPTY and YTR interruptsare status flags to the DSPCPU indicating that a bufferhas been emptied or that the Y threshold has beenreached.
The URUN flag indicates that the DSPCPU did not per-form a timely ACK to indicate the update of the addresspointers for the next field or buffer. In this case, the VOuses the old address pointer value and continues imageor data transfer. When the DSPCPU updates the pointer,the new pointer value will be used at the start of the nextframe or buffer transfer. The URUN flag is therefore astatus flag that tells the DSPCPU that the VO is using theold pointer values because it did not receive the newones in time. The URUN flag is set if the previous buffer-empty interrupt was not acknowledged. Note: the actualwrite of the buffer pointer MMIO registers is not seen bythe hardware - the ACK bit write signals buffer availabili-ty.
The HBE, Hardware Bandwidth Error flag indicates thatthe VO did not get data from SDRAM via TM1100’s inter-nal data highway in time to continue the data transfer orvideo refresh. Data or video refresh will continue, usingwhatever data is in the VO internal data buffers. The ad-dress counter for the failing buffer(s) will continue tocount, and the VO will continue to request data from theSDRAM over the highway until the highway can providethe requested data in time.
The VO has no error conditions that cause system hard-ware problems. The VO is a read only device, transfer-ring data from SDRAM to the VO output port. Unlike Vid-eo In, the VO does not modify SDRAM data.
URUN and HBE are the only VO error conditions. In thecase of URUN or HBE, the worst that happens is ascrambled image may be displayed for one frame or thatincorrect data is sent for one buffer cycle.
Even changing operating modes does not cause a sys-tem hardware problem. Changing the MODE bits, theOverlay Enable and Format bits, or the Little Endian bitmay cause wrong data to be displayed or transferred.However, the VO does not detect this or stop for it.
In normal operation, the user should not change themode or transfer control bits while the VO is enabled.TheVO should be disabled before changing the MODE bits,the OL_EN bit, or the LTL_END bit. However if these bitsare changed while the VO is running, they will take effectat the beginning of the next field or buffer.
1. Note that consecutive Pixel components of each lineare stored in consecutive memory addresses but con-secutive lines need not be in consecutive memory ad-dresses
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7.14.4 Latency and Bandwidth Requirements
In order to avoid Hardware Bandwidth Errors the internalhighway bus arbiter (see Chapter 19, “Arbiter”) has to beset accordingly to the latency requirements of VO unit. Inthe following all the numbers are given assuming data fora new video line (Y, U, V and OL (overlay) planar mem-ory format stored in memory) is aligned to 64 bytes. Inother words, it means OL,Y,U,V_OFFSET fields are amultiple of 64 bytes. Otherwise internal VO arbitration forOL, Y, U and V requests is changed, and following laten-cies are not guaranteed. VO uses internal 64 byte buff-ers.
Latency requirements for VO in image mode 4:2:2 or4:2:0 co-sited or interspersed without up scaling andoverlay disabled, is expressed as:
• During 128 VO clock cycles, VO block requires to have 2 requests acked ([2 Ys, one U and one V]/2).
If VO clock is 27 MHz then VO has to get two requests(128 bytes) from SDRAM in 128/.027 = 4740 ns.
Bandwidth (in bytes) requirement per video line withinthe active image is:
• B1x = [ceil(W/64) + ceil[(W/2)/64]*2 + 4] * 64
ceil(X) function is the least integral value greater than orequal to X and W is the IMAGE_WIDTH field value.
In the same modes but with overlay enabled the latencybecomes:
• During the first 64 VO clock cycles at least onerequest must be acked (the OL data).
• During 128 VO clock cycles, VO unit requires to have 4 requests acked ([4 OLs, 2 Ys, 1 V and 1 U]/2).
If VO clock runs at 54 MHz then VO has to get the firstrequest from SDRAM in 64/.054 = 1185 ns and averagea bandwidth/latency of 4 requests in 128/.054 = 2370 ns.
Bandwidth (in bytes) per video line within the active im-age becomes:
• B1x,OL = B1x + [ceil(W*2/64) + 4]*64
When VO mode is set to image mode with 2x up scalingmode the latency requirements are multiplied by a factorof 2 (i.e. instead of, for example, 1 request per 64 VO
clock cycles, the latency becomes 1 request per 128 VOclock cycles). Bandwidth is roughly divided by 2:
• During 64 VO clock cycles, VO block requires to get 1request from SDRAM.
If VO clock runs at 38 MHz then the latency is 64/.038 =1684 ns and bandwidth is 38 MB/s.
7.15 DDS AND PLL FILTER DETAILS
The PLL filter serves to reduce the phase jitter of theDDS synthesizer output. It can also be used to multiplythe DDS output frequency by 2x. The DDS and PLL filtertogether provide a high quality, accurately programma-ble output video clock. The complete system is sketchedin Figure 7-27. On hardware reset, the output multiplexeris set in the ‘11’ position, and the PLL system is disabled.To start the system, the following steps are needed:
• Assign a DDS frequency (this starts the DDS). Allowfor at least 31 DSPCPU cycles for the DDS fre-quency setting to take effect.
• Choose a value for PLL_S, PLL_T (for 8-40 MHzoperation, a value of 1 for division by 2 is recom-mended).
• Choose a value for CLOCK_SELECT (for 8-80 MHzoperation, CLOCK_SELECT=00 is recommended).
• Assign a VO_CTL word containing the abovechoices. The first assignment with CLOCK_SELECTunequal 11 enables the PLL system. Allow for max.50 microseconds to achieve lock.
Once the PLL is locked, small changes to the DDS fre-quency are allowed, and the VO_CLK output willsmoothly track the frequency change.
Note that most consumer electronics equipment impos-es very high precision requirements on the value of thecolor burst frequency. A video encoder derives the colorburst frequency from VO_CLK. In the case of changingthe VO_CLK frequency to software phase lock to a mas-ter reference, special care is required to keep the colorburst signal frequency within a tolerance of some 50
00
01
10
11
Square-Wave DDS
FREQUENCY
VCO8 - 90 MHz
VO_CLK
VO_CLK Internal(to Frame Timing Gen.)CLKOUT
3 × CPU Clock
03
LoopFilter
PhaseDetect
PLL_S div T+1
PLL_T
CLOCK_SELECT
div S+1
Figure 7-27. PLL filter block diagram
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ppm. When using a Philips DENC (Digital Encoder), thecolor burst frequency is derived from the master DENCfrequency by a programmable synthesizer on the DENCchip. In this case, VO_CLK changes larger than 50 ppm
are allowed by changing the DENC synthesizer over I2Cto compensate for the VO_CLK change.
Table 7-10 illustrates recommended settings.
7.16 NEW FEATURES OF TM1100
The remainder of this document contains the specifica-tions of the Enhanced Video Out unit (EVO) for theTM1100 processor. The EVO is fully functional and bina-ry compatible with the Video Out unit of TM1000.
7.17 BACKWARD COMPATIBILITY
The Enhanced Video Out unit (called EVO in the rest ofthis document) is fully compatible with the current VideoOut unit. All features of TM1000 VO are supported exact-ly in the same fashion in EVO. A code controllingTM1000 VO identically controls the EVO.
All the new features are controlled through new MMIOregisters, and the EVO_ENABLE (Enhanced Video OutEnable) bit in the new EVO_CTL MMIO register switcheson (EVO_ENABLE=1) or off the new features.
7.18 SUMMARY OF NEW EVO FEATURES
The new EVO will have the following features that are notpresent in the previous versions of TM1000:
1. Full 129-level alpha blending (8-bit alpha value).2. Chroma-key: A particular register (in YUV4:2:2+a) is
used as the key that signifies full transparency for the overlay.
3. Genlock mode frame synchronization by an external signal on VO_IO2).
4. The frame synchronization signal on VO_IO2 is mod-ified to follow the field number generated in the EAV/SAV code
5. The YUV output value can be clipped at programma-ble values.
6. In data streaming mode, a Data valid signal is gener-ated on VO_IO2.
7. The message passing mode can support short mes-sages (1 word). VO_IO2 (ENDMSG) only toggles when it is necessary.
7.19 CONTROLS: MMIO REGISTERS
New features of EVO are controlled by setting the appro-priate flags in the EVO_CTL MMIO register.
After reset, all bits of all registers of EVO are set to “0”,except for the CLIPPING register which is initialized to0xF010EB10 and the EVO_CTL register which is set to0x10000000.
The MMIO Control Registers are shown in Figure 7-28.The register fields are described in the Table 7-11 andTable 7-12. To ensure compatibility with future devices,any undefined MMIO bits should be ignored when read,and written as zeroes.
Table 7-10. DDS and PLL example settings
Desired Frequency DDS frequency PLL_S PLL_T CLOCK_SELECT Usage
4 - 10 MHz 8 - 20 MHz 1 (divide by 2) 1 (divide by 2) 01 (T divider) custom low speed video
8 - 45 MHz 8 - 45 MHz 1 (divide by 2) 1 (divide by 2) 00 (VCO) standard or 16:9 digital video
40 - 80 MHz 20 - 40 MHz 1 (divide by 2) 3 (divide by 4) 00 (VCO) high pixel rate custom video
7-20 PRELIMINARY INFORMATION File: evo.fm5, modified 7/24/99
EVO_CTL EVO_ENABLE When set to 1, enables the new features of EVO. When set to 0 (reset value), the EVO behaves exactly like TM1000 Video Out.
FULL_BLENDING When set, activates the real 7 bits alpha blending. When set to “0”, only the 5 TM1000 blending levels are performed (0%, 25%, 50%, 75%, 100%)
CLIPPING_ENABLE When enabled (set to “1”), the values stored in EVO_CLIP are used for the clip-ping of output data. Otherwise, TM1000 default values (240 and 16 for Y, U and V) are used.
SYNC_STREAMING When set in Data Streaming mode, VO_IO2 will generate a DATA_VALID signal.
FIELD_SYNC When set, VO_IO2 will generate frame synchronization signal that follows the field number in SAV/EAV codes (Field1 gives a low VO_IO2, Field2 gives a high VO_IO2)
GENLOCK Activates the genlock mode when set to “1”
PWDN Does a selective powerdown for the EVO block when set
KEY_ENABLE When set, this bit activates chroma key. The overlay values (Y, U and V) are com-pared to the values stored in the EVO_KEY register. Bits that correspond to bits set in MASK_Y and MASK_UV are ignored for the comparison. When there is an exact match between the pixel value and the value in EVO_KEY register (less the bits selected by MASK_Y and MASK_UV), then the overlay value is not present in the output stream (full transparency).The key is full 24-bits (Y, U and V on 8 bits)
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The bit 4 of VO_STATUS (VO_STATUS[4]) allows to de-termine if the EVO extra registers are present, or if it is aclassical Video Out unit. On Video Out unit,VO_STATUS[4] is a copy of the HBE flag. On EVO unit,it is hard-wired to 1. Software can easily determine thetype of Video Out unit by clearing the HBE bit then read-ing VO_STATUS[4].
The four MSB of the EVO_CTL MMIO register indicatethe EVO revision that is implemented. For the TM1100,EVO_CTL[31:28] = 0x1. This 4-bit number will be in-creased for each version of EVO that add new function-alities.
7.20 CLIPPING FUNCTION
The CLIPPING MMIO register is used to store four 8-bitvalues that are used to clip the output components. TheY output component is clipped between the value storedin LOWER_CLIPY and HIGHER_CLIPY registers. A val-ue lower or equal to LOWER_CLIPY is forced toLOWER_CLIPY and a value higher than or equal toHIGHER_CLIPY is forced to HIGHER_CLIPY.
Same behavior for U and V with the values stored inLOWER_CLIPUV and HIGHER_CLIPUV.
This mode allows to program the fully compliant 16 to235 Y and 16 to 240 Cb, Cr clipping range. This are the
default values of the EVO_CLIP register after reset. IfCLIPPING_ENABLE bit is not set, the clipping is per-formed for Y, U and V between 16 and 240, as it is imple-mented in TM1000.
When LOWER_CLIP registers are set to 0 andHIGHER_CLIP registers to 255, no clipping is per-formed.
The clipping is performed in the last step of the videopipeline, after chroma keying and blending. It is appliedonly on the images areas (field 1 and field 2) defined byIMAGE_WIDTH, IMAGE_HEIGHT, IMAGE_VOFF andIMAGE_HOFF inside the Active Video Area. Blankingvalues are not clipped.
Table 7-12. EVO Related MMIO Registers Fields
Register Field Description
EVO_MASK MASK_Y This 4-bit value is used to mask the four lower bits of the overlay Y compo-nent during the chroma key process. Example: Setting MASK_Y to “1” will eliminate the influence of the LSB of KEY_Y in the keying process.
MASK_UV This 4-bit value is used to mask the four lower bits of the overlay U and V components during the chroma key process. Example: Setting MASK_UV to “1” will eliminate the influence of the LSB of KEY_U and KEY_V in the keying process.
EVO_CLIP LOWER_CLIPY An Y value lower or equal to LOWER_CLIPY is forced to LOWER_CLIPY.
HIGHER_CLIPY An Y value higher or equal to HIGHER_CLIPY is forced to HIGHER_CLIPY.
LOWER_CLIPUV An U or an Y value lower or equal to LOWER_CLIPUV is forced to LOWER_CLIPUV.
HIGHER_CLIPUV An U or and an V value higher or equal to HIGHER_CLIPUV is forced to HIGHER_CLIPUV.
EVO_KEY KEY_Y Value compared to the Y component of the overlay for chroma keying.
KEY_U Value compared to the U component of the overlay for chroma keying.
KEY_V Value compared to the V component of the overlay for chroma keying.
EVO_SLVDLY Number of VO_CLK cycles of internal delay for VO_IO2 in genlock mode.
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7.21 EVO DATA-STREAMING MODE
When EVO_ENABLE and SYNC_STREAMING flagsare set, the pin VO_IO2 indicates a data valid signal.This signal is set when EVO start outputting valid data(i.e. data streaming mode enable and video out running),
and is reset when the data streaming mode is cancelledThe data valid signal on VO_IO2 is set just before thatthe first valid byte is present on VO_DATA[7:0], and re-set just after the last valid byte was sent, or if HBE erroris signaled. All signal start change on rising VO_CLKedge. VO_IO1 generates a one VO_CLK pulse one
VO_CLK cycle before the first valid data.
7.22 FRAME SYNCHRONIZATION
When EVO_ENABLE and FIELD_SYNC are set,VO_IO2 will indicate the field number (low= field 1, high= field 2), according to the SAV/EAV field indication(bit[6]). The pin VO_IO2 toggles just before the first byte
of the preamble that protects the EAV code, and after theSAV code. Non-interlaced output is simulated by pro-gramming Video Out to generate fields equivalent to thedesired frames. In this case, VO_IO2 indicates odd oreven frames.
7.23 ALPHA BLENDING
The alpha blending uses a 8-bit word alpha as value formerging the overlay plane with the image plane. TheMSB is used to switch on the blending (MSB = 0) or toselect the overlay plane as only output (MSB = 1). There-fore, we have 128 + 1 (00h to 0x7F for blending values,
and 0x80 to 0xFF for 100% overlay). A 00h alpha valueleads to 100% image plane and 0% overlay. Similarly, a40h value lead to 50% image and 50% overlay. EVOsupports the 129 levels that can be encoded in 8 bits(Video Out only supports 5 levels for blending). Theequation for the blending is:
VO_DATA[7:0]
VO_IO2
VO_IO1
VO_CLK
XX XX D0 D1 D2 D3 D4 D5 Dk XX XX
DATA_VALID
Figure 7-29. EVO Data-Streaming mode
4 19 20 265 266 283 1 4
One Frame
One Line
Field 2Field 1
Blanking BlankingActive Video Active VideoVerticalSync
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When FULL_BLENDING is “0”, only the 5 TM1000blending levels are performed and the 5 LSB of the alphavalue are ignored like in TM1000:
7.24 GENLOCK MODE
Genlock mode is only working when the Video Out is notmaster for synchronization (SYNC_MASTER =”0” inVO_CTL MMIO register). If GENLOCK is set, EVO ex-
pects frame timing signals on the VO_IO2 pins. The ac-tive edge can be programmed using VO_IO2_POS. Theselected transition of the frame timing signal on VO_IO2causes the Frame Line Counter to be set to the FRAMEPRESET value. After reaching FRAME LENGTH, theFrame Line Counter start counting again from 1.
Internally, the active edge of VO_IO2 is delayed bySLAVE_DLY VO_CLK clock cycles to be able to receivethe synchronization anywhere in a line. SLAVE_DLY istypically a value to compensate for the delay in the frametiming source and for the internal pipeline delay. Typical-ly, it will allow to load FRAME_PRESET at the beginningof a new line.
With the correct values of SLAVE_DLY and FRAMEPRESET, TM1100 can generate frames totally synchro-nized with the active edge of VO_IO2. All the internalMMIO registers (except VO_CTL of course) should beprogrammed with the same values than for aSYNC_MASTER mode active.
In GENLOCK mode, the EVO is free running accordingto the values programmed in its internal registers beforeany VO_IO2 active edge. Just after receiving the activeedge that will synchronize Video Out, output values maybe erroneous during several VO_CLK cycles, but it isguarantee that the next frame will be correct.
After a first synchronizing edge, if the next one happensaccordingly to the values programmed in VO MMIO reg-isters, no change will appears in the output timing of VO.If the active edge of VO_OI2 does not match the pro-grammed value, a new synchronization phase is per-formed.
A typical programming is the following: SLAVE_DLY isloaded with the number of clock cycles for one video lineminus the number of delay cycles used by VO to syn-chronize itself. FRAME_PRESET is programmed withthe value 2. With this programming, the active edge ofVO_IO2 is supposed to happen just before the first byte(Preamble) of the first line.
For the first active edge of VO_IO2, it is delayed internal-ly by SLAVE_DLY VO_CLK cycle so that it internally itseems to appear just before the start of the second lineminus the internal VO pipeline delay. After this internalpipeline delay, the line counter is loaded byFRAME_PRESET, i.e. 2, and VO starts sending data forline 2.
For the next frame, if the internal VO programming matchthe VO_IO2 timing, VO will seem to start the first byte ofthe first line just after VO_IO2 active signal.
7.25 BLOCK POWER DOWN
EVO_CTL.PWDN bit is a TM1100 feature only. It is re-served in future implementations. Upon setting of PWDNbit, EVO block goes into power down mode. It is onlypowered up again by a hardware RESET. See alsoChapter 20, “Power Management,”.
Table 7-13: Blending value in TM1000 compatibility mode
Alpha Code Alpha Value Image Overlay
00h-1Fh 0 100% 0%
20h-3Fh 32 75% 25%
40h-5Fh 64 50% 50%
60h-7Fh 96 25% 75%
80h–FFh 128–255 0% 100%
EAV
Image Data
EAV
Line 525/625
One Frame
VO_IO2
Delay SLAVE_DLY in VO_CLK cycles
Line 1 Line 2 Line FRAME PRESET Line 525/625 Line 1
EAV
Line counter loaded by FRAME PRESET
Figure 7-31. Genlock mode
7-24 PRELIMINARY INFORMATION File: evo.fm5, modified 7/24/99
Audio In Chapter 8
by Gert Slavenburg
8.1 AUDIO IN OVERVIEW
The TM1100 Audio In unit connects to an off-chip stereoA/D converter subsystem through a flexible bit-serialconnection. Audio In provides all signals needed to inter-face to high quality, low cost oversampling A/D convert-ers, including a generator for a precisely programmableoversampling A/D system clock. The Audio In unit andexternal A/D together provide the following capabilities:
• One or two channels of audio input.• Eight- or 16-bit samples per channel.• Programmable sampling rate.• Internal or external sampling clock source.• Audio In autonomously writes sampled audio data to
memory using double buffering (DMA).• Eight-bit mono and stereo as well as 16-bit mono and
stereo PC standard memory data formats are sup-ported.
• Little- and big-endian memory formats are sup-ported.
8.2 NEW IN TM1100
• improved internal clock source with less jitter
8.3 EXTERNAL INTERFACE
Four TM1100 pins are associated with the Audio In unit.The AI_OSCLK output is an accurately programmableclock output intended to serve as the master systemclock for the external A/D subsystem. The other threepins (AI_SCK, AI_WS and AI_SD) constitute a flexibleserial input interface. Using the Audio In MMIO registers,these pins can be configured to operate in a variety of se-rial interface framing modes, including but not limited to:
• Standard stereo I2S (MSB first, 1-bit delay fromAI_WS, left & right data in a frame).1
• LSB first, with 1–16 bit data per channel.• Complex serial frames of up to 512 bits/frame, with
‘valid sample’ qualifier bit.
The Audio In can be used with many serial A/D converterdevices, including the Philips SAA7366 (stereo A/D),Crystal Semiconductor CS5331, CS5336 (stereo A/D’s),CS4218 (codec), Analog Devices AD1847 (codec).
1. A definition of the Philips I2S serial interface protocol,among others, can be found in the Philips IC01 da-tabook.
Table 8-1. Audio-In Unit External Signals
Signal Type Description
AI_OSCLK OUT Over-Sampling Clock. This output can be programmed to emit any frequency up to 40-MHz with a resolution of 0.07-Hz. It is intended for use as the 256fs or 384fs over sampling clock by external A/D sub-system.
AI_SCK I/O-5 • When Audio-In is programmed as serial-interface timing slave (power-up default), AI_SCK is an input. AI_SCK receives the serial bitclock from the external A/D subsystem. This clock is treated as fully asynchronous to TM1100 main clock.
• When Audio In is programmed as the serial-interface timing master, AI_SCK is an output. AI_SCK drives the serial clock for the external A/D subsystem. The frequency is a programmable inte-gral divide of the AI_OSCLK frequency.
AI_SCK is limited to 20 MHz. The sample rate of valid samples embedded within the serial stream is also limited by the bandwidth.latency available in the system (Section 8-7).
AI_SD IN-5 Serial Data from external A/D subsystem. Data on this pin is sampled on positive or negative edges of AI_SCK as determined by the CLOCK_EDGE bit in the AI_SERIAL register.
AI_WS I/O-5 • When Audio In is programmed as the serial-interface timing slave (power-up default), AI_WS acts as an input. AI_WS is sampled on the same edge as selected for AI_SD.
• When Audio In is programmed as the serial-interface timing master, AI_WS acts as an output. It is asserted on the opposite edge of the AI_SD sampling edge.
AI_WS is the word-select or frame-syn-chronization signal from/to the external A/D subsystem.
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8.4 CLOCK SYSTEM
Figure 8-1 illustrates the different clock capabilities of theAudio In unit. At the heart of the clock system is a squarewave DDS (Direct Digital Synthesizer). The DDS can beprogrammed to emit frequencies from ca. 1 Hz to 40MHz with a resolution of better than 0.3 Hz.
The output of the DDS is always sent on the AI_OSCLKoutput pin. This output is intended to be used as the256fs or 384fs system clock source instead of a fixed fre-quency crystal for oversampling A/D converters, such asthe Philips SAA7366T, or Analog Devices AD1847.
The TM1100 Audio In DDS frequency is set by writing tothe FREQUENCY MMIO register. The programmer isfree to change the FREQUENCY setting dynamically, soas to adjust the input sampling rate to track an applica-tion dependant master reference.
Depending on bit 31 (msb), the DDS runs in 1 of twomodes:
• bit 31 = 1 - TM1100 improved mode• bit 31 = 0 - TM1000 compatibility mode
8.4.1 TM1100 Improved Mode
In improved mode, a high quality, low-jitter AI_OSCLK isgenerated. The setting of the FREQUENCY register toaccomplish a given AI_OSCLK frequency is given by theformula:
This mode, and the above formula, should be used for allnew software development on TM1100. It is not availableon TM1000.
8.4.2 TM1000 Compatibility Mode
TM1000 compatibility mode is provided so that TM1000software runs without changes. It should NOT be usedfor new software development. TM1000 mode is auto-matically entered whenever FREQUENCY[31] = 0. InTM1000 mode, AI_OSCLK frequency is set as follows:
8.5 CLOCK SYSTEM OPERATION
AI_SCK and AI_WS can be configured as input or out-put, as determined by the SER_MASTER control field.As output, AI_SCK is a divider of the DDS output fre-quency. Whether input or output, the AI_SCK pin signalis used as the bit clock for serial-parallel conversion.
If set as output, AI_WS can similarly be programmed us-ing WSDIV to control the serial frame length from 1 to512 bits.
The preferred application of the clock system options isto use AI_OSCLK as A/D master clock, and let the A/Dconverter be timing master over the serial interface(SER_MASTER=0).
In case of use of an external codec (e.g. the AD1847 orCS4218) for common Audio In and Audio Out use, it maynot be possible to independently control the A/D and D/A system clocks. In that case it is recommended that theAudio Out clock system DDS is used to provide a singlemaster A/D and D/A clock. The Audio Out, or the D/Aconverter, can be used as serial interface timing master,and Audio In is set to be slave to the serial frame deter-
FREQUENCY
AI_OSCLK
AI_SCK
AI_WS
div N+1 SCKDIV
div N+1
Square Wave DDS
3 × DSPCPUCLK
AI_SD
SER_MASTER
Serial To Parallel Converter
16
16LEFT[15:0]RIGHT[15:0]sample_clock
(e.g. 64×fs)
WSDIV
31 0
7 0
08
(e.g. 256×fs)
Figure 8-1. Audio In clock system and I/O interface.
f AIOSCLKSCKDIV 1+-----------------------------------=
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mined by Audio Out (Audio In SER_MASTER=0,AI_SCK and AI_WS externally wired to the correspond-ing Audio Out pins). In such systems, independent soft-ware control over A/D and D/A sampling rate is not pos-sible, but component count is minimized.
8.6 SERIAL DATA FRAMING
The Audio In unit can accept data in a wide variety of se-rial data framing conventions. Figure 8-2 illustrates thenotion of a serial frame. If POLARITY=1 andCLOCK_EDGE=0, a frame is defined with respect to thepositive transition of the AI_WS signal, as observed by apositive clock transition on AI_SCK. Each data bit sam-pled on positive AI_SCK transitions has a specific bit po-sition: the data bit sampled on the clock edge after theclock edge on which the AI_WS transition is seen has bitposition 0. Each subsequent clock edge defines a newbit position. As defined in Table 8-4, other combinationsof POLARITY and CLOCK_EDGE can be used to definea variety of serial frame bitposition definitions.
The capturing of samples is governed by FRAMEMODE.If FRAMEMODE=00, every serial frame results in onesample from the serial-parallel converter. A sample is de-fined as a left/right pair in stereo modes or a single leftchannel value in mono modes. If FRAMEMODE=1y, theserial frame data bit in bit position VALIDPOS is exam-ined. If it has value ‘y’, a sample is taken from the datastream (the valid bit is allowed to precede or follow the
left or right channel data provided it is in the same serialframe as the data).
The left and right sample data can be in a LSB-first orMSB-first form, at an arbitrary bit position, and with an ar-bitrary length.
In MSB-first mode, the serial-to-parallel converter as-signs the value of the bit at LEFTPOS to LEFT[15]. Sub-
Table 8-3. Audio In MMIO Clock & Interface Control Bits
Field Name Description
SER_MASTER 0 ⇒ (RESET default), the A/D converter is the timing master over the serial inter-face. AI_SCK and AI_WS are set to be input.1 ⇒ TM1100 is the timing master over the Audio In serial interface. The AI_SCK and AI_WS pins are set to be outputs.
FREQUENCY Sets the clock frequency emitted by the AI_OSCLK output. RESET default 0.
SCKDIV Sets the divider used to derive AI_SCK from AI_OSCLK. Set to 0..255, for divi-sion by 1..256. RESET default 0.
WSDIV Sets the divider used to derive AI_WS from AI_SCK. Set to 0..511 for a serial frame length of 1..512. RESET default 0.
Figure 8-2. Audio In serial frame and bit position definition (POLARITY=1, CLOCK_EDGE=0).
Table 8-4. Audio In MMIO Serial Framing Control Fields
Field Name Description
POLARITY 0 ⇒ serial frame starts on AI_WS negedge (RESET default)1 ⇒ serial frame starts on AI_WS posedge
FRAMEMODE 00 ⇒ accept a sample every serial frame (RESET default)01 ⇒ unused, reserved10 ⇒ accept sample if valid bit = 011 ⇒ accept sample if valid bit = 1
VALIDPOS • Defines the bit position within a serial frame where the valid bit is found.
• Default 0.
LEFTPOS • Defines the bit position within a serial frame where the first data bit of the left channel is found.
• Default 0.
RIGHTPOS • Defines the bit position within a serial frame where the first data bit of the right channel is found.
• Default 0.
DATAMODE 0 ⇒ MSB first (RESET default)1 ⇒ LSB first
SSPOS • Start/Stop bit position. Default 0.• If DATAMODE=MSB first, SSPOS deter-
mines the bit index (0..15) in the parallel word of the last data bit. Bits 15 (MSB) up to/including SSPOS are taken in order from the serial frame data. All other bits are set to zero.
• If DATAMODE=LSB first, SSPOS deter-mines the bit index (0..15) in the parallel word of the first data bit. Bits SSPOS up to/including 15 are taken in order from the serial frame data. All other bits are set to zero.
CLOCK_EDGE • if 0 (RESET default) the AI_SD and AI_WS pins are sampled on positive edges of the AI_SCK pin. If SER_MASTER =1, AI_WS is asserted on negative edges of AI_SCK.
• if 1, AI_SD and AI_WS are sampled on neg-ative edges of AI_SCK. As output, AI_WS is asserted on positive edges of AI_SCK.
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sequent bits are assigned, in order, to decreasing bit po-sitions in the LEFT data word, up to and includingLEFT[SSPOS]. Bits LEFT[SSPOS–1:0] are cleared.Hence, in MSB-first mode, an arbitrary number of bits arecaptured. They are left-adjusted in the 16-bit parallel out-put of the converter.
In LSB-first mode, the serial to parallel converter assignsthe value of the bit at LEFTPOS to LEFT[SSPOS]. Sub-sequent bits are assigned, in order, to increasing bit po-sitions in the LEFT data word, up to and including
LEFT[15]. Bits LEFT[SSPOS–1:0] are cleared. Hence, inLSB- first mode, an arbitrary number of bits are captured.They are returned left-adjusted in the 16-bit parallel out-put of the converter.
Refer to Figure 8-3 and Table 8-5 to see an example ofhow the Audio In unit MMIO registers are set to collect 16bits samples using the Philips SAA7366 I2S 18-bit A/Dconverter. The setup assumes the SAA7366 acts as theserial master.
For the sake of example, if it were desired to use only the12 MSBs of the A/D converter in Figure 8-3, use the set-tings of Table 8-5 with SSPOS set to four. This results inLEFT[15:4] being set with data bits 0..11, and LEFT[3:0]being set equal to zero. RIGHT[15:4] is set with data bits32..43 and RIGHT[3:0] is set to zero.
8.7 MEMORY DATA FORMATS
The Audio In unit autonomously writes samples to mem-ory in mono and stereo 8 and 16 bits per sample formats,as shown in Figure 8-4. Successive samples are alwaysstored at increasing memory address locations. The set-
ting of the LITTLE_ENDIAN bit in the AI_CTL register de-termines how increasing memory addresses map to bytepositions within words. Refer to Appendix C, “Endian-ness,”for details on byte ordering conventions.
The Audio In unit hardware implements a double buffer-ing scheme to ensure that no samples are lost, even ifthe DSPCPU is highly loaded and slow to respond to in-terrupts. The DSPCPU software assigns buffers by writ-ing a base address and size to the MMIO control fieldsdescribed in Table 8-6. Refer to section 8.8 for details onhardware/software synchronization.
In eight-bit capture modes, the eight MSBs of the serialparallel converter output data are written to memory. In16-bit capture modes, all bits of the parallel data are writ-ten to memory. If SIGN_CONVERT is set to one, theMSB of the data is inverted, which is equivalent to trans-lating from two’s complement to offset binary represen-tation. This allows the use of an external two’s comple-ment 16-bit A/D converter to generate eight-bit unsignedsamples, which is often used in PC audio.
Figure 8-3. Serial frame of the SAA7366 18 bit I 2S A/D converter (format 2 SWS).
16362525150343332311918
AI_SCK
AI_WS
AI_SD
leftn(18)
3210
rightn(18)
0
leftn+1(18)
Table 8-5. Example Setup For SAA7366
Field Value Explanation
SER_MASTER 0 SAA7366 is serial master
FREQUENCY 161628209 256fs 44.1 kHz
SCKDIV 3 AI_SCK set to AI_OSCLK/4 (not needed since SER_MASTER=0)
WSDIV 63 Serial frame length of 64 bits (not needed since SER_MASTER=0)
POLARITY 0 Frame starts with neg. AI_WS
FRAMEMODE 00 Take a sample each ser. frame
VALIDPOS n/a Don’t care
LEFTPOS 0 Bit position 0 is MSB of left channel and will go to LEFT[15]
RIGHTPOS 32 Bit position 32 is MSB of right channel and will go to RIGHT[15]
DATAMODE 0 MSB first
SSPOS 0 Stop with LEFT/RIGHT[0]
CLOCK_EDGE 0 Sample WS and SD on posi-tive SCK edges for I2S
Table 8-6. Audio In MMIO DMA Control Fields
Field Name Description
LITTLE_ENDIAN 0 ⇒ capture in big endian memory format (RESET default)1 ⇒ capture little endian
BASE1 Base Address of buffer1. This must be a 64-byte aligned address in local SDRAM. RESET default 0.
BASE2 Base Address of buffer2. This must be a 64-byte aligned address in local SDRAM. RESET default 0.
SIZE • Number of samples to be placed in buffer before switching to other buffer.
• In stereo modes, a pair of 8- or 16-bit data counts as 1 sample. In mono modes, a single value counts as a sam-ple.
• RESET default 0.
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Note that the Audio In hardware does not generate A-lawor µ-law 8-bit data formats. If such formats are desired,the DSPCPU can be used to convert from 16-bit lineardata to A-law or µ-law data.
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TM1100 Preliminary Data Book Philips Semiconductors
8.8 AUDIO IN OPERATION
Figure 8-5, Table 8-9 and Table 8-8 describe the func-tion of the control and status fields of the Audio In unit.To ensure compatibility with future devices, undefinedbits in MMIO registers should be ignored when read, andwritten as zeroes.
The Audio In unit is reset by a TM1100 hardware reset,or by writing 0x80000000 to the AI_CTL register. UponRESET, capture is disabled (CAP_ENABLE = 0), andbuffer1 is the active buffer (BUF1_ACTIVE=1). A mini-mum of 5 valid AI_SCK clock cycles is required to allowinternal Audio In circuitry to stabilize before enablingcapture. This can be accomplished by programmingAI_FREQ and AI_SERIAL and then delaying for the ap-propriate time interval.
The DSPCPU initiates capture by providing two equalsize empty buffers and putting their base address andsize in the BASEn and SIZE registers. Once two valid (lo-cal memory) buffers are assigned, capture can be en-abled by writing a ‘1’ to CAP_ENABLE. The Audio In unithardware now proceeds to fill buffer 1 with input sam-
ples. Once buffer 1 fills up, BUF1_FULL is asserted, andcapture continues without interruption in buffer 2. IfBUF1_INTEN is enabled, a SOURCE 11 interrupt re-quest is generated.
Note that the buffers must be 64-byte aligned, and a mul-tiple of 64 samples in size (the six LSBs of AI_BASE1,AI_BASE2 and AI_SIZE are always zero).
The DSPCPU is required to assign a new, empty bufferto BASE1 and perform an ACK1, before buffer 2 fills up.Capture continues in buffer 2, until it fills up. At that time,BUF2_FULL is asserted, and capture continues in thenew buffer 1, etc.
Upon receipt of an ACK, the Audio In hardware removesthe related interrupt request line assertion at the nextDSPCPU clock edge. Refer to Section 3.5.3, “INT andNMI (Maskable and Non-Maskable Interrupts),” for therules regarding ACK and interrupt re-enabling. The Au-dio In interrupt should always be operated in level sensi-tive mode, since Audio In can signal multiple conditionsthat each need independent ACKs over the single inter-nal SOURCE 11 request line.
Figure 8-5. Audio In status/control field MMIO layout.
MMIO_baseoffset:
AI_STATUS (r/w)0x10 1C00
AI_CTL (r/w)0x10 1C04
AI_SERIAL (r/w)0x10 1C08 SCKDIV
AI_FRAMING (r/w)0x10 1C0C
AI_FREQ (r/w)0x10 1C10
AI_BASE1 (r/w)0x10 1C14
FREQUENCY
BUF1_ACTIVE
AI_BASE2 (r/w)0x10 1C18 BASE2
AI_SIZE (r/w)0x10 1C1C SIZE (in samples)
31 0371115192327
VALIDPOS
BASE1
OVERRUNHBE (Highway bandwidth error)
BUF2_FULL
RESETCAP_ENABLE
CAP_MODESIGN_CONVERT
LITTLE_ENDIAN
0
DIAGMODE
OVR_INTENHBE_INTEN
BUF2_INTENBUF1_INTEN
ACK_OVRACK_HBE
ACK2
ACK1
WSDIV
SER_MASTERDATAMODE
FRAMEMODE
POLARITY
LEFTPOS RIGHTPOS SSPOS
00000
000000
BUF1_FULL
SLEEPLESS
CLOCK_EDGE
000000
31 0371115192327
31 0371115192327
31 0371115192327
31 0371115192327
RESERVED
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Philips Semiconductors Audio In
In normal operation, the DSPCPU and Audio In hard-ware continuously exchange buffers without ever loosinga sample. If the DSPCPU fails to provide a new buffer intime, the OVERRUN error flag is raised. This flag is notaffected by ACK1 or ACK2; it can only be cleared by anexplicit ACK_OVR.
8.9 HIGHWAY LATENCY AND HBE
Audio In uses internal buffering before writing data toSDRAM. The internal buffer consists of a 1 stereo sam-ple input holding register and 64 bytes of internal buffermemory. Under normal operation, the 64-byte buffer getswritten to SDRAM while the input register is capable ofreceiving one more sample. This normal operation isguaranteed to be maintained as long as the highway ar-biter is set to guarantee a latency for Audio In that match-es the sampling interval. Given a sample rate fs, and anassociated sample interval T (in nSec), the arbiter shouldbe set to have a latency of at most T-20 nSec. Refer toChapter 19, “Arbiter,” for information on arbiter program-ming. If the requested latency is not adequate, the HBE(Highway Bandwidth Error) condition may result. This er-ror flag gets set when the input register is full, the 64-bytebuffer has not yet been written to memory, and a newsample arrives.
Table 8-7 shows the required arbiter latency settings for
a number of common operating modes. The rightmostcolumn in the table illustrates the nature of the resulting64 byte highway requests. Is not required to compute ar-biter settings, but may be used to compute bus availabil-ity in a given interval.
8.10 ERROR BEHAVIOR
If either an OVERRUN or HBE error occurs, input sam-pling is temporarily halted, and samples will be lost. Incase of OVERRUN, sampling resumes as soon as theDSPCPU makes one or more new buffers availablethrough an ACK1 or ACK2 operation. In the case of HBE,sampling will resume as soon as the internal buffer canbe written to SDRAM.
HBE and OVERRUN are ‘sticky’ error flags. They will re-main set until an explicit ACK_HBE or ACK_OVR.
Table 8-7. Audio In Highway Arbiter Latency Requirement examples
CapModefs
(kHz)T
(nS)
max arbiter latency (nSec)
access pattern
stereo16 bit/sample 44.1 22,676 22,656
1 request every
362,812 nS
stereo16 bit/sample 48.0 20,833 20,813
1 request every
333,333 nS
stereo16 bit/sample 96.0 10,417 10,397
1 request every
166,667 nS
Table 8-8. Audio In MMIO Status Fields (Read Only)
Field Name Description
BUF1_ACTIVE • If 1, buffer 1 is the buffer that will be used for the next incoming sample. If 0, buffer 2 will receive the next sample.
• 1 after RESET.
BUF1_FULL • If 1, buffer 1 is full. If BUF1_INTEN is also 1, an interrupt request (source 11) is pend-ing. BUF1_FUL is cleared by writing a ‘1’ to ACK1, at which point the Audio In hard-ware will assume that BASE1 and SIZE describe a new empty buffer.
• 0 after RESET.
BUF2_FULL • If 1, buffer 2 is full. If BUF2_INTEN is also 1, an interrupt request (source 11) is pend-ing. BUF2_FUL is cleared by writing a ‘1’ to ACK2, at which point the Audio In hard-ware will assume that BASE2 and SIZE describe a new empty buffer.
• 0 after RESET.
HBE • Highway Bandwidth Error. This error condi-tion is raised when the 64-byte internal Audio In buffer is not yet written to SDRAM when a new input sample arrives. This indi-cates an insufficient allocation of TM1100 Highway bandwidth for the audio sampling rate/mode. Refer to Chapter 19, “Arbiter.”
• 0 after RESET.
OVERRUN • An OVERRUN error has occurred, i.e. the CPU failed to provide an empty buffer in time, and 1 or more samples have been lost. If OVR_INTEN is also 1, an interrupt request (source 11) is pending. The OVERRUN flag can ONLY be cleared by writing a ‘1’ to ACK_OVR.
• 0 after RESET.
Table 8-9. Audio In MMIO Control Fields
Field Name Description
RESET The Audio In logic is reset by writing a 0x80000000 to AI_CTL. This bit always reads as a ‘0’. See Section 8.8, “Audio In Operation” for details on software reset.
DIAGMODE 0 ⇒ normal operation (RESET default)1 ⇒ diagnostic mode (see Section 8.11, “Diagnostic Mode”)
SLEEPLESS 0 ⇒ participate in global power down (RESET default)1 ⇒ refrain from participating in power down
CAP_ENABLE Capture Enable flag. If 1, Audio In captures samples and acts as DMA master to write samples to local SDRAM. If 0 (RESET default), Audio In is inactive.
BUF1_INTEN Buffer 1 full Interrupt Enable. Default 0.0 ⇒ no interrupt1 ⇒ interrupt (SOURCE 11) if buffer 1 full
BUF2_INTEN Buffer 2 full interrupt enable. Default 00 ⇒ no interrupt1 ⇒ interrupt (SOURCE 11) if buffer 2 full
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TM1100 Preliminary Data Book Philips Semiconductors
8.11 DIAGNOSTIC MODE
Diagnostic mode is entered by setting the DIAGMODEbit in the AI_CTL register. In diagnostic mode, theAI_SCK, AI_WS and AI_SD inputs of the serial-parallelconverter are taken from the output pins of the TM1100Audio Out unit. This mode can be used during the diag-nostic phase of system boot to verify correct operation ofmost of the logic circuitry of the Audio Out and Audio Inunit.
Note that the inputs are truly taken from the TM1100 Au-dio Out external pins, i.e. if an external (board level)source is driving AO_SCK or AO_WS, diagnostic modeis not capable of testing Audio Out.
Special care must be taken to enable diagnostic mode.The recommended way of entering diagnostic mode is tofirst set Audio Out up such that a AO_SCK is generatedand set DIAGMODE bit followed by a 5 (AI_SCK) cycledelay, then do a software reset of Audio In and immedi-ately set back the DIAGMODE bit.
HBE_INTEN HBE Interrupt Enable. Default 0.0 ⇒ no interrupt1 ⇒ interrupt (SOURCE 11) if a highway bandwidth error occurs.
OVR_INTEN Overrun Interrupt Enable. Default 00 ⇒ no interrupt1 ⇒ interrupt (SOURCE 11) if an overrun error occurs
ACK1 Write a 1 to clear the BUF1_FUL flag andremove any pending BUF1_FUL interrupt request. This bit always reads as 0.
ACK2 Write a 1 to clear the BUF2_FUL flag andremove any pending BUF2_FUL interrupt request. This bit always reads as 0.
ACK_HBE Write a 1 to clear the HBE flag andremove any pending HBE interrupt request. This bit always reads as 0.
ACK_OVR Write a 1 to clear the OVERRUN flag andremove any pending OVERRUN interrupt request. This bit always reads as 0.
Table 8-9. Audio In MMIO Control Fields
Field Name Description
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Audio Out Chapter 9
by Gert Slavenburg, Patrick de Bakker, Charles Peplinski
9.1 AUDIO OUT OVERVIEW
The TM1100 Audio Out unit connects to one to four off-chip stereo D/A converters through a flexible bit-serialconnection. Audio Out provides all signals to interface tohigh quality, low cost oversampling D/A converters, in-cluding a precisely programmable oversampling D/Asystem clock. The Audio Out unit and external D/A to-gether provide the following capabilities:
• Up to 8 channels of audio output.• Eight- or 16-bit samples per channel.• Programmable sampling rate• Internal or external sampling clock source.• Audio Out autonomously reads processed audio data
from memory using double buffering (DMA).• Eight-bit mono and stereo as well as 16-bit mono and
stereo PC standard memory data formats are sup-ported.
• Little- and big-endian memory formats are sup-ported.
• Provides control capability for highly integrated PCcodecs such as the AD1847 and CS4218.
9.2 NEW IN TM1100
• improved internal clock source with less jitter
9.3 EXTERNAL INTERFACE
Four TM1100 pins are associated with the Audio Outunit. The AO_OSCLK output is an accurately program-mable clock output intended to be used as the mastersystem clock for the external D/A subsystem. The otherthree pins (AO_SCK, AO_WS and AO_SD) constitute aflexible serial output interface. Using the Audio OutMMIO registers, these pins can be configured to operatein a variety of serial interface framing modes, includingbut not limited to:
• Standard stereo I2S (MSB first, one-bit delay fromAO_WS, left & right data in a frame).
• LSB first, with 1–16 bit data per channel.• Complex serial frames of up to 512 bits/frame.• Superframes of up to 4 regular frames can be cre-
ated for 4,6 or 8 channel modes.
Table 9-1. Audio-Out Unit External Signals
Signal Type Description
AO_OSCLK OUT Oversampling Clock. This output can be programmed to emit any frequency up to 40 MHz, with a resolution of 0.07 Hz. It is intended for use as the 256 or 384fs oversampling clock by the exter-nal D/A conversion subsystem.
AO_SCK I/O-5 • When Audio Out is programmed to act as the serial interface timing slave (RESET default), AO_SCK acts as input. It receives the Serial Clock from the external audio D/A subsystem. The clock is treated as fully asynchronous to the TM1100 main clock.
• When Audio Out is programmed to act as serial interface timing master, AO_SCK acts as output. It drives the Serial Clock for the external audio D/A subsystem. The clock frequency is a programmable inte-gral divide of the AO_OSCLK fre-quency.
AO_SCK is limited to 20 MHz. The sample rate of valid samples embed-ded within the serial stream is also lim-ited by the bandwidth.latency available in the system (Section 9.10).
AO_SD OUT-5 Serial Data to external audio D/A sub-system. The timing of transitions on this output is determined by the CLOCK_EDGE bit in the AO_SERIAL register, and can be on positive or neg-ative AO_SCK edges.
AO_WS I/O-5 • When Audio-Out is programmed as the serial-interface timing slave (RESET default), AO_WS acts as an input. AO_WS is sampled on the opposite AO_SCK edge at which AO_SD is asserted.
• When Audio Out is programmed as serial-interface timing master, AO_WS acts as an output. AO_WS is asserted on the same AO_SCK edge as AO_SD.
AO_WS is the word-select or frame-synchronization signal from/to the external D/A subsystem. Each audio channel receives 1 sample for every WS period.
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9.4 INTERNAL CLOCK SOURCE
Figure 9-1 illustrates the different clock capabilities of theAudio Out unit. At the heart of the clock system is asquare wave DDS (Direct Digital Synthesizer). The DDScan be programmed to emit frequencies from ca. 1 Hz to40 MHz with a resolution of better than 0.3 Hz.
The output of the DDS is always sent to the AO_OSCLKoutput pin. This output is intended to be used as the256fs or 384fs system clock source for oversampling D/Aconverters, such as the Philips SAA7322, or codecssuch as the AD1847 or CS4218.
The TM1100 DDS frequency is set by writing to the FRE-QUENCY MMIO register. The programmer is free tochange the FREQUENCY setting dynamically, so as toadjust the outgoing audio sample rate. In ATSC transportstream decoding, this is the preferred method by whichaudio sample rate lock to the original program provider isaccomplished.
Depending on bit 31 (msb), the DDS runs in 1 of twomodes:
• bit 31 = 1 - TM1100 improved mode• bit 31 = 0 - TM1000 compatibility mode
9.4.1 TM1100 Improved Mode
In improved mode, a high quality, low-jitter AO_OSCLKis generated. The setting of the FREQUENCY register toaccomplish a given AO_OSCLK frequency is given bythe formula:
This mode, and the above formula, should be used for allnew software development on TM1100. It is not availableon TM1000.
9.4.2 TM1000 Compatibility Mode
TM1000 compatibility mode is provided so that TM1000software runs without changes. It should NOT be usedfor new software development. TM1000 mode is auto-matically entered whenever FREQUENCY[31] = 0. InTM1000 mode, AO_OSCLK frequency is set as follows:
9.5 CLOCK SYSTEM OPERATION
The output of the DDS is always sent to the AO_OSCLKoutput pin. This output is typically used as the 256fs or384fs system clock source for oversampling D/A convert-ers, such as the Philips SAA7322, or codecs such as theAD1847 or CS4218.
AO_SCK is the serial interface bit clock. AO_WS is theword-strobe, i.e. each channel receives one sample foreach word-strobe cycle.
AO_SCK and AO_WS can be configured as input or out-put, as determined by the SER_MASTER control field. Ifset as output, AO_SCK can be set to a divider of the DDSoutput frequency.
Whether set as input or output, the AO_SCK pin signal isalways used as the bit clock for parallel-serial conver-sion. The AO_WS pin always acts as the trigger to startthe generation of a serial frame. AO_WS can similarly beprogrammed using WSDIV to control the serial framelength. The number of bits per frame is equal to WS-DIV+1.
The preferred use of the clock system options is to useAO_OSCLK as D/A master clock, and let the D/A con-verter be timing slave of the serial interface(SER_MASTER=1). This is important in view of compat-ibility with future TriMedia devices, which only supportAudio Out as serial interface master.
Some D/A converters however, like the AD1847, providesomewhat better SNR properties if they are configuredas serial master instead, with Audio Out as slave(SER_MASTER=0). As illustrated by Figure 9-1, the in-ternal parallel to serial converter that constructs the seri-al frame is oblivious to who is serial master, except in thecase of superframes of more than 2 audio channels, asdescribed in Section 9.12, “4, 6 and 8 Channel Audio.”
FREQUENCY 231 f OSCLK 2
32⋅9 f DSPCPU⋅--------------------------------+=
FREQUENCYf OSCLK 2
32⋅3 f DSPCPU⋅--------------------------------=
Table 9-2. Clock System Setting (f DSPCPU=133 MHz)
fs OSCLK SCK FREQUENCY SCKDIV
44.1 kHz 256fs 64fs 2187991971 3
48.0 kHz 256fs 64fs 2191574340 3
44.1 kHz 384fs 64fs 2208246133 5
48.0 kHz 384fs 64fs 2213619686 5
SCKDIV 0 255[ , ]∈f AOSCK
f AOOSCLKSCKDIV 1+-----------------------------------=
Figure 9-2. Definition of serial frame bit positions (POLARITY = 1, CLOCKEDGE = 0)
9-2 PRELIMINARY INFORMATION File: aout.fm5, modified 7/24/99
Philips Semiconductors Audio Out
9.6 SERIAL DATA FRAMING
The Audio Out unit can generate data in a wide variety ofserial data framing conventions. Figure 9-2 illustrates thenotion of a serial frame. If POLARITY=1, a frame startson each positive edge of the AO_WS signal. IfCLOCK_EDGE=0, the parallel to serial converter sam-ples AO_WS on a positive clock edge transition, and out-puts the first bit (bit 0) of a serial frame on the next fallingedge of AO_SCK.
If CLOCK_EDGE = 1, the parallel to serial convertersamples AO_WS on the negative edge of AO_SCK,while audio data is output on the positive edge, i.e. theAO_SCK polarity would be reversed with respect toFigure 9-2.
Every serial frame transmits a single left and right chan-nel sample to the D/A converter. The left and right sam-ple data can be in an LSB first or MSB first form, at anarbitrary bit position, and with an arbitrary length.
In MSB-first mode (DATAMODE = 0), the parallel to se-rial converter assigns the value of LEFT[15] to the bit atLEFTPOS in the serial frame. Subsequently, bits fromdecreasing bit positions in the LEFT dataword, up to andincluding LEFT[SSPOS], are transmitted in order.
In LSB-first mode (DATAMODE = 1), the parallel-to-seri-al converter assigns the value of LEFT[SSPOS] to the bitat LEFTPOS in the serial frame. Subsequent bits fromthe LEFT data word, up to and including LEFT[15], aretransmitted in order.
Frame bits that do not belong to either LEFT[15:SSPOS]or RIGHT[15:SSPOS] are set to zero. This ensures thatTM1100 can be used in combination with a D/A convert-er which has a higher accuracy than the actual numberof transmitted bits.
Refer to Figure 9-3 and Table 9-5 to see how the AudioOut unit MMIO registers would be set to transmit 16 bitsof stereo data via an I2S serial standard to an 18-bit D/Aconverter with a 64-bit serial frame.
Table 9-3. Audio Out MMIO Clock & Interface Control
Field Name Description
SER_MASTER 0 ⇒ (RESET default), the D/A subsystem is the timing master over the Audio Out serial interface. AO_SCK and AO_WS act as inputs.
1 ⇒ TM1100 is the timing master over the serial interface. AO_SCK and AO_WS act as outputs. This mode is required for 4,6 or 8 channel opera-tion.
The SER_MASTER bit should only be changed while Audio Out is disabled, i.e. TRANS_ENABLE = 0.
FREQUENCY Sets the clock frequency emitted by the AO_OSCLK output. RESET default 0.
SCKDIV Sets the divider used to derive AO_SCK from AO_OSCLK. Set to 0..255, for divi-sion by 1..256. RESET default 0.
WSDIV Sets the divider used to derive AO_WS from AO_SCK. Set to 0..511 for a serial frame length of 1..512. RESET default 0.
Table 9-4. Audio Out Serial Framing Control Fields
Field Name Description
POLARITY 0 ⇒ serial frame starts with a AO_WS negedge (RESET default)
1 ⇒ serial frame starts with a AO_WS posedge
This bit should NOT be changed during operation of Audio Out, i.e.only update this bit when TRANS_ENABLE = 0.
LEFTPOS(9) Defines the bit position within a serial frame where the first data bit of the left channel is placed. Default 0.
RIGHTPOS(9) Defines the bit position within a serial frame where the first data bit of the right channel is placed. Default 0.
DATAMODE 0 ⇒ MSB first (RESET default)1 ⇒ LSB first
SSPOS • Start/Stop bit position. Default 0.• If DATAMODE=MSB first, SSPOS deter-
mines the bit index (0..15) in the parallel word of the last data bit. Bits 15 (MSB) up to/including SSPOS are generated. All other bits are output as zero.
• If DATAMODE=LSB first, SSPOS deter-mines the bit index (0..15) in the parallel word of the first data bit. Bits SSPOS up to/including 15 are generated. All other bits are output as zero.
CLOCK_EDGE 0 ⇒ the parallel to serial converter samples AO_WS on positive edges of AO_SCK and outputs data on the negative edge of AO_SCK (RESET default).
1 ⇒ the parallel to serial converter samples AO_WS on negative edges of AO_SCK and outputs data on positive edges of AO_SCK.
WS_PULSE 0 ⇒ emit 50% AO_WS (RESET default).1 ⇒ emit single AO_SCK cycle AO_WS(this bit is ignored if SER_MASTER=0)In case of 6 channel audio (see Section 9.12, “4, 6 and 8 Channel Audio”), WS_PULSE should be set to ‘1’
SFDIV See Section 9.12, “4, 6 and 8 Channel Audio,” on superframes.
Table 9-4. Audio Out Serial Framing Control Fields
Field Name Description
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TM1100 Preliminary Data Book Philips Semiconductors
For the sake of example, if only eight bits were desired tobe transmitted, use the settings of Table 9-5 with SSPOSset to 8. This results in LEFT[15:8] being transmitted indata bits 0..7. RIGHT[15:8] is transmitted in data bits32..39. All other bits in the serial frame are sent as zero.
9.7 CODEC CONTROL
In addition to the left and right data fields that are gener-ated based on autonomous DMA action, a serial framegenerated by Audio Out can be set to contain 1 or 2 con-trol fields up to 16 bits in length. Each control field can beindependently enabled/disabled by the CC1_EN,CC2_EN bits in AO_CTL. The content shifted into theframe is taken from the CC1 and CC2 field in the AO_CCregister. The CC1_POS and CC2_POS fields in theAO_CFC register determine the first bit position in the
frame where the control field is emitted. The field is emit-ted observing the setting of DATAMODE, i.e. LSB orMSB first.
The CC_BUSY bit in AO_STATUS indicates if the AudioOut unit is ready to receive another CC1, CC2 value pair.Writing a new value pair to AO_CC writes the value intoa buffer register, and raises the CC_BUSY status. Assoon as both CC1 and CC2 values have been copied toa shadow register in preparation for transmission,CC_BUSY is negated, indicating that the Audio Out logicis ready to accept a new codec control pair.
Software always needs to ensure that the CC_BUSY sta-tus is negated before writing a new CC1, CC2 pair. Bybusy waiting on CC_BUSY, the DSPCPU can emit a se-quence of individual audio frames with distinct controlfield values reliably. This can for example be used duringcodec initialization. No provision is made for interruptdriven operation of such a sequence of control values - itis assumed that the value of control fields is rarelychanging and can be held constant during the DMA buff-er emission of audio.
It is legal to program the control field positions within theframe such that CC1 and CC2 overlap each other and/orleft/right data fields. If two fields are defined to start at thesame bit position, the priority is left (highest), right, CC1then CC2. The field with the highest priority will be emit-ted starting at the conflicting bit position. If a field f2 is de-fined to start at a bit position i that falls within a field f1starting at a lower bit position, f2 will be emitted startingfrom i and the rest of f1 will be lost. Any bit positions notbelonging to a data or control field will be emitted as ze-ro.
Figure 9-4 shows a 64-bit frame suitable for use with theCS4218 codec. It is obtained by setting POLARITY=1,LEFTPOS=0, RIGHTPOS=32, DATAMODE=0, SS-POS=0, CLOCK_EDGE=1, WS_PULSE=1, CC1_POS =16, CC1_EN=1, CC2_POS=48, CC2_EN=1.
163625251503332313018173210 0
left channel datan+1(18)left channel datan(18) right channel datan(18)
49
Figure 9-3. Serial frame (64 bit) of a hypothetical 18-bit precision I 2S D/A converter.
AO_SCK
AO_WS
AO_SD
Table 9-5. Example Setup For I 2S
Field Value Explanation
POLARITY 0 Frame starts with negedge AO_WS.
LEFTPOS 0 LEFT[15] will go to serial frame position 0.
RIGHTPOS 32 RIGHT[15] will go to serial frame position 32.
DATAMODE 0 MSB first.
SSPOS 0 Stop with LEFT/RIGHT[0], send 0’s after.
CLOCK_EDGE 0 AO_SD change on negedge AO_SCK
WSDIV 63 Serial frame length = 64. Only rele-vant if SER_MASTER=1.
WS_PULSE 0 emit 50% duty cycle AO_WS. Only relevant if SER_MASTER=1.
Figure 9-4. Example codec frame layout for a Crystal Semi CS4218.
16362484732313210 0
left datan+1(16)left channel datan(16) right channel datan(16)
15
CC1(16)
16
lsb lsb lsb CC2(16) lsb
AO_SCK
AO_WS
AO_SD
9-4 PRELIMINARY INFORMATION File: aout.fm5, modified 7/24/99
Philips Semiconductors Audio Out
Note that frames are generated (externally or internally)even when TRANS_ENABLE de-asserted. Writes toCC1 and CC2 should only be done afterTRANS_ENABLE is asserted. The ‘first’ CC values willthen go out on the next frame. Writes to CC1 or CC2 be-fore TRANS_ENABLE can result in erroneous behav-iour.
9.8 MEMORY DATA FORMATS
The Audio Out unit autonomously reads samples frommemory in mono and stereo eight- and 16-bit-per-sam-ple formats, as shown in Figure 9-5. Successive samplesare always read from increasing memory address loca-tions. The setting of the LITTLE_ENDIAN bit in theAO_CTL register determines how increasing memoryaddresses map to byte positions within words. Refer toAppendix C, “Endian-ness,” for details on byte ordering con-ventions.
The Audio Out unit hardware implements a double buff-ering scheme to ensure that there are always samplesavailable to transmit, even if the DSPCPU is highly load-ed and slow to respond to interrupts. The DSPCPU soft-ware assigns buffers by writing a base address and sizeto the MMIO control fields described in Figure 9-6. Referto Section 9.9, “Audio Out Operation,” for details onhardware/software synchronization.
In eight-bit transmit modes, data is MSB-aligned and ex-tended with zeros before it is transmitted to the parallelto serial converter. If SIGN_CONVERT is set to one, theMSB of the data is inverted, which is equivalent to trans-lating from offset binary representation to two’s comple-ment. This allows the use of an external two’s comple-ment 16-bit D/A converter to generate audio from eight-bit unsigned samples.
Note that the Audio Out hardware does not generate A-law or µ-law eight-bit data formats. If such formats aredesired, the DSPCPU can be used to convert from A-lawor µ-law data to 16-bit linear data.
Table 9-6. Audio Out MMIO Codec Control/Status fields
Field Name Description
CC1 (16) The 16-bit value of CC1 is shifted into each emitted serial frame starting at bit position CC1_POS, as long as CC1_EN is asserted.Only write to CC1 if TRANS_ENABLE is set.
CC1_POS Defines the bit position within a serial frame where the first data bit of CC1 is placed. RESET Default 0.
CC2(16) The 16-bit value of CC2 is shifted into each emitted serial frame starting at bit position CC2_POS, as long as CC2_EN is asserted.Only write to CC2 if TRANS_ENABLE is set.
CC2_POS Defines the bit position within a serial frame where the first data bit of CC2 is placed. Default 0.
CC_BUSY 0 ⇒ Audio Out is ready to receive a CC1, CC2 pair (RESET default).
1 ⇒ Audio Out is not ready to receive a CC1, CC2 pair. Try again in a few AO_SCK clock intervals.
Figure 9-5. Audio Out memory DMA formats.
adr
leftn
adr+1
leftn+1
adr+2
leftn+2
adr+3
leftn+3
adr+4
leftn+4
adr+5
leftn+5
adr+6
leftn+6
adr+7
leftn+78-bitmono
adr
leftn
adr+1
rightn
adr+2
leftn+1
adr+3
rightn+1
adr+4
leftn+2
adr+5
rightn+2
adr+6
leftn+3
adr+7
rightn+38-bitstereo
16-bitmono
leftn
adr
leftn+1
adr+2
leftn+2
adr+4
leftn+3
adr+6
16-bitstereo
leftn
adr
rightn
adr+2
leftn+1
adr+4
rightn+1
adr+6
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TM1100 Preliminary Data Book Philips Semiconductors
Figure 9-6. Audio Out status/control field MMIO layout.
MMIO_baseoffset:
AO_STATUS (r/w)0x10 2000
AO_CTL (r/w)0x10 2004
AO_SERIAL (r/w)0x10 2008 SCKDIV
AO_FRAMING (r/w)0x10 200C
AO_FREQ (r/w)0x10 2010
AO_BASE1 (r/w)0x10 2014
FREQUENCY
BUF1_ACTIVE
AO_BASE2 (r/w)0x10 2018 BASE2
AO_SIZE (r/w)0x10 201C SIZE (in samples)
31 0371115192327
BASE1
UNDERRUNHBE (Highway bandwidth error)
BUF2_EMPTY
RESETTRANS_ENABLE
TRANS_MODESIGN_CONVERT
LITTLE_ENDIAN
0
UDR_INTENHBE_INTEN
BUF2_INTENBUF1_INTEN
ACK_UDRACK_HBE
ACK2
ACK1
WSDIV
SER_MASTERDATAMODE
CLOCK_EDGE
POLARITY
LEFTPOS RIGHTPOS SSPOS
00000
000000
SLEEPLESS
BUF1_EMPTY
AO_CC (r/w)0x10 2020
AO_CFC (r/w)0x10 2024 CC1_POS CC2_POS
CC2CC1
CC1_ENCC2_ENWS_PULSE
CC_BUSY
SFDIV
000000
31 0371115192327
31 0371115192327
31 0371115192327
31 0371115192327
RESERVED
9-6 PRELIMINARY INFORMATION File: aout.fm5, modified 7/24/99
Philips Semiconductors Audio Out
9.9 AUDIO OUT OPERATION
Figure 9-6, Table 9-7 and Table 9-8 describe the func-tion of the control and status fields of the Audio Out unit.To ensure compatibility with future devices, any unde-fined or reserved MMIO bits should be ignored whenread, and written as zeroes
The Audio Out unit is reset by a TM1100 hardware reset,or by writing 0x80000000 to the AO_CTL register. Uponreset, transmission is disabled (TRANS_ENABLE = 0),and buffer1 is the active buffer (BUF1_ACTIVE=1). Aftera RESET, 5 AO_SCK clock cycles are required to stabi-lize the internal circuitry and before enabling Audio Out.This can be accomplished by programming theAO_FREQ and AO_SERIAL registers, and then waitingfor the appropriate interval.
The DSPCPU initiates transmission by providing two fullequal size buffers and putting their base address andsize in the BASEn and SIZE registers. Once two validbuffers are assigned, transmission can be enabled bywriting a one to TRANS_ENABLE. The Audio Out unithardware now proceeds to empty buffer 1 by transmis-sion of output samples. Once buffer 1 empties,BUF1_EMPTY is asserted, and transmission continueswithout interruption from buffer 2. If BUF1_INTEN is en-abled, a SOURCE 12 interrupt request is generated.
Note that the buffers must be 64-byte aligned, and buffersizes must be a multiple of 64 samples (the six LSBs ofAO_BASE1, AO_BASE2 and AO_SIZE are zero).
The DSPCPU is required to assign a new, full buffer toBASE1 and perform an ACK1, before buffer 2 empties.Transmission continues from buffer 2, until it is empty. Atthat time, BUF2_EMPTY is asserted, and transmissioncontinues from the new buffer 1, etc. Upon receipt of anACK, the Audio Out hardware removes the interrupt re-quest line assertion at the next DSPCPU clock edge. Re-fer to the interrupt controller documentation for details oninterrupt handler programming. The Audio Out interrupt(SOURCE 12) should always be operated in level sensi-tive mode.
9.10 HIGHWAY LATENCY AND HBE
The Audio Out unit uses an internal 64-byte buffer aswell as a 32-bit output holding register. Under normal op-eration, the internal buffer gets refreshed from SDRAMfast enough to avoid any missing samples, while data ismeanwhile being emitted from the holding register. If thehighway arbiter is set up with an insufficient latency guar-
Table 9-7. Audio Out MMIO DMA control fields
Field Name Description
LITTLE_ENDIAN 0 ⇒ big endian memory format (RESET default)
1 ⇒ little endian
BASE1 Base Address of buffer1. Must be a 64-byte aligned address in local SDRAM. RESET default 0.
BASE2 Base Address of buffer2. Must be a 64-byte aligned address in local SDRAM. RESET default 0.
SIZE Number of samples to be read from a buffer before switching to other buffer. In stereo modes, a left/right pair of eight or 16-bit data counts as a single sample. RESET default 0.
TRANS_MODE 00 ⇒ mono, eight bits/sample. (RESET default). Left data and Right data are the same.
01 ⇒ stereo, two times eight bits/sample10 ⇒ mono, 16 bits/sample. Left data
and Right data are the same.11 ⇒ stereo, two times 16 bits/sample
SIGN_CONVERT 0 ⇒ leave MSB unchanged (RESET default)1 ⇒ invert MSB(not applied to codec control fields)
Table 9-8. Audio Out DMA Status Fields (Read Only)
Field Name Description
BUF1_ACTIVE • If 1, buffer 1 will be used for the next sam-ple to be transmitted.
• If 0, buffer 2 will contain the next sample (set to 1 after RESET).
BUF1_EMPTY • If 1, buffer 1 is empty. • If BUF1_INTEN is also 1, an interrupt
request (source 12) is asserted.• BUF1_EMPTY is cleared by writing a ‘1’
to ACK1, at which point the Audio Out hardware will assume that BASE1 and SIZE describe a new full buffer.
• 0 after RESET.
BUF2_EMPTY • If 1, buffer 2 is empty. • If BUF2_INTEN is also 1, an interrupt
request (source 12) is asserted.• BUF2_EMPTY is cleared by writing a ‘1’
to ACK2, at which point the Audio Out hardware will assume that BASE2 and SIZE describe a new full buffer.
• 0 after RESET.
HBE • Highway Bandwidth Error.• 0 after RESET.• Indicates that no data was transmitted
due to inability to read the local Audio Out buffer from SDRAM in time. This indicates an insufficient allocation of TM1100 High-way bandwidth for the audio sampling rate/mode.
UNDERRUN • An UNDERRUN error has occurred, i.e. the CPU failed to provide a full buffer in time, and no samples were transmitted, although requested by the D/A converter.
• If UDR_INTEN is also 1, an interrupt request (source 12) is pending. The UNDERRUN flag can ONLY be cleared by writing a ‘1’ to ACK_UDR. 0 after RESET.
Table 9-7. Audio Out MMIO DMA control fields
Field Name Description
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TM1100 Preliminary Data Book Philips Semiconductors
antee, the situation can arise that the 64 byte buffer is notrefilled and the holding register is exhausted by the timea new output sample is due. In that case the HBE erroris raised. The last sample (or sample pair) will be repeat-ed until the buffer is refreshed. The HBE condition issticky, and can only be cleared by an explicit ACK_HBE.
Given a sample rate fs, and an associated sample inter-val T (in nSec), the arbiter should be set to have a latency
of at most T-20 nSec for stereo 16-bit mode, 2T-20 nSecfor mono 16-bit and stereo 8-bit modes and 4T-20 nSecfor mono 8-bit mode. Refer to Chapter 19, “Arbiter,” forinformation on arbiter programming.
The latency for 4,6 and 8 channel modes can be comput-ed as if the system is operating in stereo mode with a 2x,3x respectively 4x sample rate.
Table 9-10 shows the required arbiter latency settings fora number of common operating modes. The rightmostcolumn in the table illustrates the nature of the resulting64 byte highway requests. Is not required to compute ar-biter settings, but may be used to compute bus availabil-ity in a given interval.
9.11 ERROR BEHAVIOR
In normal operation, the DSPCPU and Audio Out hard-ware continuously exchange buffers without ever failingto transmit a sample. If the DSPCPU fails to provide anew buffer in time, the UNDERRUN error flag is raised,and the last valid sample or sample pair is repeated untila new buffer of data is assigned by an ACK1 or ACK2.The UNDERRUN flag is not affected by ACK1 or ACK2;it can only be cleared by an explicit ACK_UDR.
If an HBE error occurs, the last valid sample or samplepair is repeated until the Audio Out hardware retrieves anew sample buffer across the highway.
9.12 4, 6 AND 8 CHANNEL AUDIO
The TM1100 Audio Out unit is capable of generating abitstream with 4,6 or 8 channels of audio. This is onlysupported if Audio Out is operating as serial master(SER_MASTER=1). More than two channels of audio
Table 9-9. Audio Out MMIO Control Fields
Field Name Description
RESET Resets the audio-out logic. See Section 9.9, “Audio Out Operation” for a descrip-tion of the recommended procedure.
TRANS_ENABLE Transmission Enable flag.0 ⇒ (RESET default) Audio Out inactive.1 ⇒ Audio Out transmits samples and
acts as DMA master to read samples from local SDRAM.
Do NOT change the SER_MASTER and POLARITY bits while transmission is enabled.
SLEEPLESS 0 ⇒ (power up default) Audio Out goes into power down mode if TM1100 goes to power down mode.
1 ⇒ Audio out continues operation when TM1100 goes to power down mode. Samples are read from memory as needed, and Audio Out interrupts, when enabled, will wake up the DSPCPU.
BUF1_INTEN Buffer 1 Empty Interrupt Enable.0 ⇒ (default) no interrupt1 ⇒ interrupt (SOURCE 12) if buffer 1
empty
BUF2_INTEN Buffer 2 Empty Interrupt Enable.0 ⇒ (default) no interrupt1 ⇒ interrupt (SOURCE 12) if buffer 2
empty
HBE_INTEN HBE Interrupt Enable.0 ⇒ (default) no interrupt1 ⇒ interrupt (SOURCE 12) if a highway
bandwidth error occurs.
UDR_INTEN UNDERRUN Interrupt Enable.0 ⇒ (default) no interrupt1 ⇒ interrupt (SOURCE 12) if an
UNDERRUN error occurs
ACK1 • Write a 1 to clear the BUF1_EMPTY flag and remove any pending BUF1_EMPTY interrupt request.
• ACK1 always reads 0.
ACK2 • Write a 1 to clear the BUF2_EMPTYflag and remove any pending BUF2_EMPTY interrupt request.
• ACK2 always reads 0.
ACK_HBE • Write a 1 to clear the HBE flag and• remove any pending HBE interrupt
request. • ACK_HBE always reads as 0.
ACK_UDR • Write a 1 to clear the UNDERRUN flag and remove any pending UNDERRUN interrupt request.
• ACK_UDR always reads 0.
Table 9-10. Audio Out Highway Arbiter latency requirement examples
TransModefs
(kHz)T
(nSec)
max. arbiterlatency(nSec)
accesspattern
mono8 bit/sample 8.0 125000 499,980
1 request every
8,000,000 nS
stereo16 bit/sample 44.1 22676 22,656
1 request every
362,812 nS
stereo16 bit/sample 48.0 20833 20,813
1 request every
333,333 nS
stereo16 bit/sample 96.0 10417 10,397
1 request every
166,667 nS
6 channel16 bit/sample 44.1 22676 7,539
1 request every
120,937 nS
8 channel16 bit/sample 44.1 22767 5,649
1 request every
90,702 nS
9-8 PRELIMINARY INFORMATION File: aout.fm5, modified 7/24/99
Philips Semiconductors Audio Out
are accomplished by creating a superframe consisting ofseveral serial frames. A superframe is created by divid-ing the internal signal used for parallel-to-serial conver-sion by 2, 3 or 4 and sending the result of the division asthe AO_WS output value.
Modern stereo codecs, such as the CS4218 andAD1847, can easily be set to decode the first, second,third or fourth stereo stream from a superframe of 4 or 8channels.
Figure 9-11 illustrates the logic that creates a super-frame. If SFDIV is set to a value other than 0, a super-frame of SFDIV+1 frames is generated. The divider hard-ware emits a WS edge at the start of each SDRAM
buffer, and every superframe thereafter. By settingWS_PULSE=1, a single AO_SCK duration pulse is sentevery superframe. If WS_PULSE=0, AO_WS is a 50%duty cycle signal, except in the case of 6 channel opera-tion, where the duty cycle is undefined.
Note that the software needs to ensure that a SDRAMbuffer contains an integral number of superframes. Forexample, if SFDIV=2, superframes of 3 stereo streamsare constructed, and each SDRAM buffer must contain amultiple of 6 16-bit samples. This ensures that the D/Aconverter set to the first stereo pair of the superframe al-ways receives the first stereo pair from the SDRAM buff-er, etc.
Figure 9-11. Super frame division block diagram
AO_SCK
AO_WS div N+1
AO_SD
SER_MASTER
Parallel to Serial Converter
16
16LEFT[15:0]RIGHT[15:0]
(e.g. 64×fs)
WSDIV08
32 AO_CC[31:0]
div N+1
pulse
1
0
SFDIV(2)WS_PULSE
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9-10 PRELIMINARY INFORMATION File: aout.fm5, modified 7/24/99
PCI Interface Chapter 10
by Gert Slavenburg, Ken-Sue Tan, Babu Kandimalla
10.1 NEW IN TM1100
TM1100 DMA read transactions use the more efficient“memory read multiple” PCI transactions, unless explic-itly disabled. Section 10.7.5.
TM1100 contains an on board PCI_CLK generator forlow-cost configurations. It can be enabled/disabled atboot time. See Section 12.2.
TM1100 has a sideband control signal that allows glue-less connection of simple slave peripherals direct to thePCI bus wires. This can be used to connect Flash, ROM,SRAM, UARTs etc. with 8 bit data and demultiplexed ad-dress. Refer to Chapter 21, “PCI-XIO External I/O Bus.”
10.2 PCI OVERVIEW
TM1100 includes a PCI interface for easy integration intopersonal computer applications—where the PCI-bus isthe standard for high-speed peripherals. In embeddedapplications, with TM1100 serving as the main CPU, thePCI bus can interface to peripheral devices that imple-ment functions not provided by the on-chip peripherals.See Figure 10-1.
The main function of the PCI interface is to connect theTM1100 on-chip highway and PCI buses. A bus cycle onthe internal highway that targets an address mapped intoPCI space will cause the PCI interface to create a PCIbus cycle. Similarly, a bus cycle on PCI that targets anaddress mapped into TM1100 memory space will causethe PCI interface to create a highway bus cycle targetedat SDRAM. For some operations, the PCI interface is ex-plicitly programmed by the DSPCPU.
From TM1100, only the DSPCPU and the ICP (image co-processor) can cause the PCI interface to create PCI bus
cycles; the other on-chip peripherals cannot see externalhardware through the PCI interface. From PCI, SDRAMand a most of the registers in MMIO space can be ac-cessed by external PCI initiators.
The PCI interface implements DMA (also called block orburst) and non-DMA transfers. DMA transfers are inter-ruptible on 64-byte boundaries. The PCI interface canservice outbound (TM1100 → PCI) and inbound (PCI →TM1100) data flows simultaneously.
Table 10-1 lists some of the features of the PCI interface.
PCI Agent PCI Agent PCI Agent
TM1100 PCI BusArbiter
Host CPU(e.g., x86)Interrupt
Controller
PCI Agent PCI Agent PCI Agent
TM1100 PCI BusArbiter
a) TM1100 as peripheral b) TM1100 as host CPU
PCI Bus PCI Bus
PCI Bridge
Figure 10-1. Two typical system implementations. (a) shows TM1100 as a PCI peripheral in a desktop PC. (b) shows an embedded system with TM1100 as the host CPU.
Table 10-1. PCI Interface Characteristics
Characteristic Comments
PCI Compliance PCI Local Bus Specification Revi-sion 2.1
PCI Speed Up to 33 MHz
Data bus width 32-bit only
Address space 32 bits (4G bytes)
Voltage levels Drive & receive at either 3.3V or 5V
Burst mode Yes, w/ double buffering so maxi-mum transfer rate (132 MB/s) is sus-tainable
Posted write Yes, can be disabled
PCI ‘special cycle’ Not recognized
PCI ‘memory write & invalidate’
Supported for TM1100 as initiator
PCI ‘interrupt acknowl-edge’
Not generated
PCI ‘dual-address cycle’
Not generated
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10.3 PCI INTERFACE AS AN INITIATOR
The following classes of operations invoked by TM1100cause the PCI interface to act as a PCI initiator:
• Transparent, single-word (or smaller) transactionscaused by DSPCPU loads and stores to the PCIaddress aperture.
• Explicitly programmed single-word I/O or configura-tion read or write transactions.
From the point of view of programs executed byTM1100’s DSPCPU, there are three apertures intoTM1100’s 4-GB memory address space:
• SDRAM space (0.5 to 64 MB in size; programmable).• MMIO space (2 MB in size).• PCI space.
MMIO registers control the positions and extents of theaddress-space apertures (see Chapter 3, “DSPCPU Ar-chitecture”). The SDRAM aperture begins at the addressspecified in the MMIO register DRAM_BASE and ex-tends upward to the address in the DRAM_LIMIT regis-ter. The 2-MB MMIO aperture begins at the address inMMIO_BASE (defaults to 0xEFE00000 after power-up).All addresses that fall outside these two apertures areassumed to be part of the PCI address aperture. Refer-ences by DSPCPU loads and stores to the PCI apertureare reflected to external PCI devices by the coordinatedaction of the data cache and PCI interface.
When a DSPCPU load or store targets the PCI aperture(i.e., neither of the other two apertures), the DSPCPU’sdata cache automatically carries out a special sequenceof events. The data cache writes to the PCI_ADR and (ifthe DSPCPU operation was a store) PCI_DATA regis-ters in the PCI interface and asserts (load) or deasserts(store) the internal signal pci_read_operation (a directconnection from the data cache to the PCI interface).
While the PCI interface executes the PCI bus transac-tion, the DSPCPU is held in the stall state by the datacache. When the PCI interface has completed the trans-action, it asserts the internal signal pci_ready (a directconnection from the PCI interface to the data cache).
When pci_ready is asserted, the data cache finishes theoriginal DSPCPU operation by reading data from thePCI_DATA register (if the DSPCPU operation was aload) and releasing the DSPCPU from the stall state.
Explicit Writes to PCI_ADR, PCI_DATA
The PCI_ADR and PCI_DATA registers are intended tobe used only by the data cache. Explicit writes are not al-lowed and may cause undetermined results and/or datacorruption.
10.3.2 I/O Operations
Explicit programming by DSPCPU software is the onlyway to perform transactions to PCI I/O space. DSPCPU
software writes three MMIO registers in the following se-quence:
1. The IO_ADR register.2. The IO_DATA register (if PCI operation is a write).3. The IO_CTL register (controls direction of data move-
ment and which bytes participate).
The PCI interface starts the PCI-bus I/O transactionwhen software writes to IO_CTL. The interface can raisea DSPCPU interrupt at the completion of the I/O transac-tion (see BIU_CTL register definition in Section 10.7.5,“BIU_CTL Register”) or the DSPCPU can poll the appro-priate status bit (see BIU_STATUS register definition inSection 10.7.4, “BIU_STATUS Register”). Note that PCII/O transactions should NOT be initiated if a PCI config-uration transaction described below is pending. This is astrict implementation limitation.
The fully detailed description of the steps needed can befound in Section 10.7.13, “IO_CTL Register.”
10.3.3 Configuration Operations
As with I/O operations, explicit programming byDSPCPU software is the only way to perform transac-tions to PCI configuration space. DSPCPU softwarewrites three MMIO registers in the following sequence:
1. The CONFIG_ADR register.2. The CONFIG_DATA register (if PCI operation is a
write).3. The CONFIG_CTL register (controls direction of data
movement and which bytes participate).
The PCI interface starts the PCI-bus configuration trans-action when software writes to CONFIG_CTL. As withthe I/O operations, the biu_status and BIU_CTL registersmonitor the status of the operation and control interruptsignalling. Note that PCI configuration space transac-tions should NOT be initiated if a PCI I/O transaction de-scribed above is pending. This is a strict implementationlimitation.
The fully detailed description of the steps needed can befound in Section 10.7.10, “CONFIG_CTL Register.”
10.3.4 DMA Operations
The PCI interface can operate as an autonomous DMAengine, executing block-transfer operations at maximumPCI bandwidth. As with I/O and configuration operations,DSPCPU software explicitly programs DMA operations.
General-purpose DMA For DMA between SDRAM and PCI, DSPCPU softwarewrites three MMIO registers in the following sequence:
1. The SRC_ADR and DEST_ADR registers.2. The DMA_CTL register (controls direction of data
movement and amount of data transferred).
The PCI interface begins the PCI-bus transactions whensoftware writes to DMA_CTL. As with the I/O and config-uration operations, the BIU_STATUS and BIU_CTL reg-
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Philips Semiconductors PCI Interface
isters monitor the status of the operation and control in-terrupt signalling.
The fully detailed description of the steps needed can befound in Section 10.7.16, “DMA_CTL Register.”
Image-Coprocessor DMAThe PCI interface also executes DMA transactions forthe Image Coprocessor (ICP). The ICP performs rapidpost-processing of image data and writes it at PCI DMAspeed to a PCI graphics card frame buffer. The ICP can-not perform PCI read transactions. BIU_CTL.IE (ICPDMA Enable) should be asserted before attempting ICPPCI operation. Programming of ICP DMA is described inSection 13.6, “Operation and Programming.”
10.4 PCI INTERFACE AS A TARGET
The TM1100 PCI interface responds as a target to exter-nal initiators for a limited set of PCI transaction types:
• Configuration read/write• Memory read/write, read line and read multiple to the
TM1100 SDRAM or MMIO apertures. See Section10.9, “Limitations.”
TM1100 ignores PCI transactions other than the above.
10.5 TRANSACTION CONCURRENCY, PRIORITIES, AND ORDERING
The PCI interface can be processing more than one op-eration at a given time. There are five distinct classes ofoperations implemented by the PCI interface:
If the active general-purpose DMA transaction is a read,up to five transactions, one from each, can be active si-multaneously. If the active general-purpose DMA opera-tion is a write, then only four transactions can be activesimultaneously because general-purpose DMA writesforce ICP DMA writes to wait until the general-purposeDMA completes. When a general-purpose DMA write ispending, an in-progress ICP DMA operation is suspend-ed at the next 64-byte block boundary and waits until thecompletion of the DMA write operation. General-purposeDMA reads are interleaved with ICP DMA writes, so bothcan be active concurrently.
PCI single-data-phase transactions (DSPCPU load/store, I/O read/write, and configuration read/write) areexecuted in the order they are issued to the PCI inter-face. Note the strict implementation limitation that PCI -I/O and PCI configuration transactions cannot be simul-taneously active.
10.6 REGISTERS ADDRESSED IN PCI CONFIGURATION SPACE
Since it is a PCI device, TM1100 has a set of configura-tion registers to determine PCI behavior. PCI configura-tion registers allow full relocation of interrupt binding andaddress mapping by the system’s host processor. Thisrelocatability of PCI-space parameters eases installa-tion, configuration, and system boot.
The PCI standard specifies a 64-byte PCI configurationheader region within a reserved 256-byte block. Duringsystem initialization, host system software scans the PCIbus, looking for PCI headers, to determine what PCI de-vices are present in the system. The fields in the headerregion uniquely identify the PCI device and allow the hostto control the device in a generic way. Figure 10-2 showsthe layout of the configuration header region.
Figure 10-2 also shows the initial values for the configu-ration registers. Some registers, such as Device ID, havehardwired values, while others are programmed by soft-ware. Still others are set automatically from the externalboot ROM during TM1100’s power-up initialization.
10.6.1 Vendor ID Register
For TM1100, the value of the 16-bit Vendor ID field ishardwired to 0x1131 (Philips). This value identifies themanufacturer of a PCI device. Valid vendor identifiersare assigned by the PCI special interest group (PCI SIG)to assure uniqueness. The value 0xFFFF is reservedand must be returned by the host/PCI bridge when an at-tempt is made to read a non-existent device’s Vendor IDconfiguration register.
10.6.2 Device ID Register
For TM1100, the value of the 16-bit Device ID field ishardwired to 0x5400. The Device ID is assigned by themanufacturer to uniquely identify each PCI device itmakes.
10.6.3 Command Register
The 16-bit command register provides basic control overa PCI device’s ability to generate and/or respond to PCIbus cycles. According to the PCI specification, after re-set, all bits in this register are cleared to zero (except fora device that must be initially enabled). Clearing all bitsto zero logically disconnects the device from the PCI busfor all accesses except configuration accesses.
The command register format is shown in Figure 10-3.Table 10-2 summarizes the field values. Note that thevalues listed as “normally taken” are not necessarily thereset values, i.e. the Command register is reset to all ze-ros, meaning the features are disconnected on reset.
Following are detailed descriptions of the command reg-ister fields.
I/O (I/O access enable). This bit controls a device’s abil-ity to respond to I/O-space accesses. A value of zero dis-ables PCI device response; a value of one enables re-
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TM1100 Preliminary Data Book Philips Semiconductors
sponse. This bit is hardwired to zero because all TM1100internal registers are memory mapped.
MA (Memory Access enable). This bit controls re-sponse to memory-space accesses. A value of zero dis-
ables TM1100 response; a value of one enables re-sponse. This bit is set to zero at power-up; software canset this bit to one with a configuration write.
31
00
0 Normally zero 0 Hardwired to ground sp Set by software if aperture size allows p Set by software
1 Normally one 1 Hardwired to Vdd s Set by hardware from boot EEPROM
015
Device ID (0x5400) Vendor ID (0x1131)
004
0 1 0 0 0 reserved reserved 1 1 1 1
Status Command
0 0 0 0 0
008
1 0 1 0 0 0 0 0 0 0 0 0 0 1
Class Code (0x048000) Revision ID (see text)0 0 0 0 0 0 0 0 00 0 0 00 0 00
Figure 10-2. PCI configuration header region register layout and initial values. (All values in hex.)
15 0
Command Register I/O
1
MA
2
EM
3
SC
4
MWI
5
VGA
6
PAR
7
Wait
8
SERR#
9
FB
10
Reserved
Figure 10-3. Command Register format.
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EM (Enable Mastering). This bit controls the TM1100PCI interface’s ability to act as a PCI master. A value ofzero prevents the PCI interface from initiating PCI ac-cesses; a value of one allows the PCI interface to initiatePCI accesses.
Note that the EM bit is automatically set to one wheneverthe HE bit in the BIU_CTL register is set to one (see Sec-tion 10.7.5, “BIU_CTL Register”). Mastering must be en-abled for TM1100 to serve as PCI host processor.
EM is set to zero at power-up. Host system software canset this bit to one with a configuration write.
SC (Special Cycle). This bit controls PCI device recog-nition of special-cycle operations. A value of zero causesa PCI device to ignore all special cycles; a value of oneallows a PCI device to monitor special cycle operations.This bit is hardwired to zero in TM1100.
MWI (Memory Write and Invalidate). This bit deter-mines a PCI devices’s ability to generate memory-write-and-invalidate commands. A value of one allows a PCIdevice to generate memory-write-and-invalidate com-mands; a value of zero forces the PCI device to usememory-write commands instead. TM1100 implementsthis bit. The conditions under which TM1100 DMA trans-actions generate memory-write-and-invalidate are de-scribed in Section 10.7.16, “DMA_CTL Register.” De-tails of operation can be found in Section 10.6.7, “CacheLine Size Register.” Image Coprocessor DMA writes al-ways use regular memory-write transactions.
VGA (VGA palette snoop). This bit controls how VGA-compatible PCI devices handle accesses to their paletteregisters. This bit is hardwired to zero.
PAR (Parity error response). This bit controls signallingof parity errors (data or address). A value of zero causesthe PCI interface to ignore parity errors; a value of onecauses the PCI interface to report parity errors on theperr# PCI signal. This bit is set to zero at power-up; sincethe PCI interface checks parity, software can set this bitto one with a configuration write.
Wait (Wait-cycle control). This bit controls whether ornot a PCI device does address/data stepping. PCI devic-es that never do stepping must hardwire this bit to 0.Since TM1100 does not implement stepping, this bit ishardwired to zero.
SERR# (serr# enable). This bit is an enable for the driv-er of the serr# pin (system error). A value of zero disablesthe serr# pin; a value of one enables it. All PCI devicesthat have an serr# pin must implement this bit. This bit isset to zero after reset; this bit can be set to one with aconfiguration write. SERR# and PAR must both be set toone to allow signalling of address parity errors on theserr# signal.
FB (Fast Back-to-back enable). This bit controls wheth-er or not a PCI master can do fast back-to-back transac-tions to different devices. A value of zero means fastback-to-back transactions are only allowed when thetransactions are to the same agent; a value of onemeans the master is allowed to generate fast back-to-back transactions to different agents. Initialization soft-ware will set this bit if all targets are capable of fast back-to-back transactions. In TM1100, this bit is hardwired tozero.
Reserved. Reads from reserved bits return zero; writesto reserved bits cause no action.
10.6.4 Status Register
The status register is used to record information aboutPCI bus events. The status register format is shown inFigure 10-4. Table 10-3 lists the Status register fields.
Reserved. Reads from reserved bits return zero; writesto reserved bits cause no action.
66M (66-MHz capable). This bit is hardwired to zero forTM1100 (PCI runs at 33-MHz maximum).
UDF (user Definable Features). Since the TM1100 PCIinterface does not implement PCI user-definable fea-tures, this bit is hardwired to zero.
FBC (Fast Back-to-back Capable). The TM1100 PCIinterface does not support fast back-to-back capability,so this bit is hardwired to zero.
DPD (Data Parity Detected). Since the TM1100 PCI in-terface can act as a PCI bus initiator, this bit is imple-mented. DPD is set in the initiator’s status register when:
Table 10-2. Field values for Command Register
Field Value Explanation
I/O Hardwired to 0 (ignore I/O space accesses)
MA 0 ⇒ no recognition of memory-space accesses1 ⇒ recognizes memory-space accesses
EM 0 ⇒ cannot act as PCI initiator1 ⇒ can act as PCI initiator
SC Hardwired to 0 (ignore special cycle accesses)
MWI 0 ⇒ cannot generate memory write and invalidate1 ⇒ can generate memory write and invalidate
VGA Hardwired to 0
Par 0 ⇒ ignore parity errors1 ⇒ acknowledge parity errors
SERR# 0 ⇒ disable driver for serr# pin1 ⇒ enable driver for serr# pin
FB 0 ⇒ fast back-to-back only to same agent1 ⇒ fast back-to-back to different agents
Reserved Write ignored; reads return 0
15 0
Status Register45
66M
6
UDF
7
FBC
8
DPD
910
Reserved
14
SSEDPE
13
RMA
12
RTA
11
STA DEVSEL
Figure 10-4. Status register format.
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• The PAR (parity-error response) bit in the commandregister is set, and
• The initiator asserted perr# or detected it asserted bythe target (during a write cycle).
DEVSEL (Device Select timing). This read-only fielddefines the slowest timing that will be used for thedevsel# signal when TM1100 is a target on the PCI bus.Table 10-4 shows the allowable encodings and mean-ings. These bits are hardwired to ‘01’ to indicate that
TM1100 uses a ‘medium’ devsel# timing.
STA (Signalled Target Abort). TM1100’s PCI interfacesets this bit when it is a target device and aborts a trans-action.
RTA (Receive Target Abort). TM1100’s PCI interfacesets this bit when it is the initiating device and the trans-action is aborted by the target device. (All initiating devic-es must implement this bit.)
RMA (Receive Master Abort). TM1100’s PCI interfacesets this bit when it is the initiating device and aborts atransaction (except when the transaction is a special cy-cle). (All initiating devices must implement this bit.)
SSE (Signaled System Error). TM1100’s PCI interfacesets this bit when it asserts the serr# signal. (TM1100
can generate serr#, so this bit is implemented; devicesincapable of generating serr# need not implement SSE.)
DPE (Detected Parity Error). TM1100’s PCI interfacesets this bit when it detects a parity error, even if parityerror handling is disabled. (The PAR bit in the commandregister enables the handling of parity errors.)
10.6.5 Revision ID Register
The value in the Revision ID register is a read only valuechosen by the manufacturer to indicate product revi-sions. For the TM1100 product family, the two MSB’s ofthe revision ID indicate the fab (00 ST, 01 MOS4, 10TSMC, 11 other). The next two bits indicate an all layerrevision number, and the 4 lsb’s indicate metal layer re-visions. Each all layer revision adds 0x10 to the revisionID and resets the 4 lsb’s to zero. Non pin or function com-patible TriMedia devices will use the same Revision IDconvention, but with a revised Device ID.
10.6.6 Class Code Register
The value in the Class Code register is read-only. Sys-tem software uses the Class Code register to identify thegeneric function of the device, and in some cases, theClass Code can specify a register-level programming in-terface.
Class Code consists of three one-byte fields as shown inFigure 10-5. The value of the upper byte, Base ClassCode, broadly classifies the function of the device. Thevalue of the middle byte, Subclass Code, identifies thefunction more specifically. The value of the lower bytespecifies a register-level programming interface so thatdevice-independent software can interact with the de-vice. The meanings of the Base Class byte values areshown in Table 10-6.
The value of Base Class is hardwired to 0x04 sinceTM1100 is a multimedia device. Currently, there are nospecific register-level programming interfaces definedfor multimedia devices.
Table 10-3. Status Register Fields
Field Characteristics
Reserved Writes ignored; reads return 0
66M PCI bus speed (hardwired to 0 ⇒ 33-MHz)
UDF User-definable features (hardwired to 0 ⇒ none)
FBC Fast back-to-back capable (hardwired to 0 ⇒ unsupported)
DPD Data parity detected
DEVSEL devsel# signal timing (hardwired to 1 ⇒ ‘medium’)
STA Signaled target abort
RTA Receive target abort
RMA Receive master abort
SSE Signaled system error
DPE Detected parity error
Table 10-4. DEVSEL Encodings
DEVSEL Meaning
00 Fast
01 Medium
10 Slow
11 Reserved
Table 10-5. Actual Revision Id values
Value (hex) Product description
0x00 CTC (CPU Test Chip) - all versions
0x01 ST fab TM1000 0.50 µ original mask version as well as first metal revision
0x10 ST fab TM1000 0.35 µ original mask
0x11 ST fab TM1000 0.35 µ first metal revision
0x90 TSMC fab TM1000 0.35 µ original mask
0x91 TSMC fab TM1000 0.35 µ first metal revision
0x20 early version of TM1100
0x61 MOS4 fab TM1100 0.35u first metal revision
23 0
Class Code Programming InterfaceBase Class Code
15 7
Subclass Code
Figure 10-5. Class-code register format.
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Table 10-7 lists the defined subclasses of multimedia de-vices. TM1100 is both a video and audio multimedia de-vice, so its subclass value is hardwired to 0x80.
10.6.7 Cache Line Size Register
This field only matter when the MWI bit in configurationspace is set. The value of the Cache Line Size registerspecifies the host system cache line size in units of 32-bit words Initiating devices, such as the TM1100, thatcan generate memory-write-and-invalidate commandsmust implement this register. When implemented, thecache line size allows initiators participating in the PCIcaching protocol to retry burst accesses at cache-lineboundaries.
This register is implemented in TM1100. In the TM1100,PCI DMA performs write-and-invalidate cycles as per thetable below. ICP DMA and CPU PCI writes are per-formed using normal memory-write cycles.
10.6.8 Latency Timer Register
The value of the Latency Timer register specifies theminimum number of PCI clock cycles the TM1100 BIU asinitiator is allowed to own the PCI bus. This register isreadable and writable in PCI configuration space.
This register must be writable in any PCI initiating devicethat can burst more than two data phases. In the TM1100PCI interface, the least-significant three bits are hard-wired to zero and software can program any value intothe most-significant five bits. This permits software tospecify the time slice with a minimum granularity of eightPCI clocks. A value of zero signifies maximum latency,i.e. 256 PCI clocks.
10.6.9 Header Type Register
The value of the Header Type register defines the formatof words 16 through 63 in configuration space andwhether or not the device contains multiple functions.Figure 10-6 shows the format of Header Type.
Bit 7 of Header Type is zero for single-function devices,one for multi-function devices. TM1100 is a single-func-tion device, so bit 7 is zero. Table 10-9 shows the encod-ings of the Layout field.
10.6.10 Built-In Self Test Register
When implemented, the BIST register is used to controlthe operation of a device’s built-in self testing capability.TM1100 does not implement BIST, so this register ishardwired to return zeros when read.
10.6.11 Base Address Registers
The TM1100 PCI interface implements two configurationspace memory Base Address registers: DRAM_BASEand MMIO_BASE. DRAM_BASE relocates TM1100’sSDRAM within the system address space; MMIO_BASErelocates the 2-MB memory-mapped I/O address aper-ture.
Table 10-6. Base Class Encodings
Base Class (in hex) Meaning
00 Device was built before class code definitions were finalized
0000,0100 write-and-invalidates are done in 4 DWORD, i.e. 16 byte chunks
0000,1000 write-and-invalidate in 8 DWORD chunks
0001,0000 write-and-invalidate in 16 DWORD chunks
all other values only normal ‘memory-write’ is performed
Table 10-9. Layout Encodings
Layout (in hex) Meaning
00 Non-bridge PCI device
01 PCI-to-PCI bridge device
Table 10-8. Cache Line Size values
Cache Line Size(binary) Effect
7
Header Type0
Layout
6
MF
Figure 10-6. Header Type register format.
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The values in the Base Address registers determine theaddress map as seen by both the DSPCPU and externalPCI masters. These values are normally set once, andnot changed dynamically once the DSPCPU operates.
Hardware RESET initializes DRAM_BASE to 0x0 andMMIO_BASE to 0xefe0,0000, after which the TM1100boot protocol sets the final value.
In stand-alone systems, the autonomous boot sequenceis executed., In this case, the values of DRAM_BASEand MMIO_BASE are copied from the content of the se-rial boot EEPROM, as described in Section 12.3.2, “Ini-tial DSPCPU Program Load for Autonomous Bootstrap.”
In X86 or other host assisted platforms, the PCI host as-sisted boot sequence is executed. In this case, the baseregisters are not set from the EEPROM. Instead, the hostBIOS executes a scan for devices on each PCI bus. Dur-ing this scan, memory apertures needed by each deviceare determined, and a suitable base is assigned by thehost BIOS. The details of this process are described be-low.
Figure 10-7 shows the formats for DRAM_BASE andMMIO_BASE. Following are descriptions of the registerfields.
M (Memory). The value of the M bit indicates whetherthe desired resource is a memory or PC I/O aperture.The M bit is hardwired to zero, indicating a memory typeaperture for both the DRAM_BASE and MMIO_BASEregisters.
T (Type). The value of the T field indicates the size of thebase address register and constraints on its relocatabili-ty. Table 10-10 lists the encodings and meanings of theT field.
TM1100’s PCI-interface base registers are 32 bits wideand can be relocated in the 32 bit address space; thus,the value of the T field is 00 for both DRAM_BASE andMMIO_BASE.
P (Prefetchable). The value of the P bit indicates to oth-er devices whether or not prefetching is allowed. BothSDRAM and MMIO are not prefetchable, so the P bit ishardwired to zero for both DRAM_BASE andMMIO_BASE.
(A Base Address register has a P bit set to one if thereare no side effects caused by reads. Reads from aprefetchable space return all bytes regardless of byte en-ables. Host bridges can merge writes to a prefetchabledevice without causing errors.)
DRAM/MMIO Base Address. In X86 or other host plat-forms, the configuration space DRAM Base Address andMMIO Base Address fields serve two purposes. First, thehost BIOS software can use them to determine the sizesof the SDRAM and MMIO apertures. Second, the BIOScan write to these fields to cause the apertures to be re-located within the PCI memory address space.
To determine the sizes of an aperture, the BIOS firstwrites all ones (0xFFFFFFFF) to the address field. Whenthe BIOS reads the field immediately after, the value re-turned will have zeros in all don’t-care bits and ones in allrequired address bits. Required address bits form a left-aligned (i.e., starting at the MSB) contiguous field ofones, thus effectively specifying the size of the aperture.
For example, the MMIO aperture is a fixed 2-MB space.After writing all ones to the MMIO Base Address field, asubsequent read returns the value 0xFFE00000. The M,T, and P fields are all zero indicating the aperture ismemory (not I/O), can be relocated anywhere in a 32-bitaddress space, and is not prefetchable. Since the aper-ture has 21 address bits (the position of the first one bit),MMIO space is a 2-MB aperture (221 bytes). The hostBIOS now assigns a suitable 2 MB aligned base addressby writing to the MMIO_BASE register in configurationspace.
The DRAM aperture can range in size from 1 MB to 64MB (but the size must be a power of two). Thus, the num-ber of required address bits can range from 20 to 26. Theactual amount of SDRAM present is determined by thecontent of the first byte of the boot EEPROM, as de-scribed in Section 12.5, “Detailed EEPROM Contents.”The PCI BIU uses this size to determine which of the bitsmarked ‘sp’ in Figure 10-7 are writable and which are setto 0. This causes the BIOS to determine the correct ac-tual DRAM aperture size.
10.6.12 Subsystem ID, Subsystem Vendor ID Register
The subsystem and subsystem vendor ID are new perPCI Rev 2.1. These fields are optional, but their use is
Table 10-10. Type Field Encodings
Type Meaning
00 Base register is 32 bits wide; mapping can relocate anywhere in 32-bit memory space
01 Base register is 32 bits wide; mapping must relocate below 1MB in memory space
10 Base register is 64 bits wide; mapping can relocate anywhere in 64-bit address space
11 Reserved
31 0
DRAM_BASE MDRAM Base Address
123
TP
MMIO_BASE MTP
4
00000000spspspspspsp 000000 00
25 19
MMIO Base Address000000000 000000 00
31 0123420
Figure 10-7. Base Address register format.
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highly recommended as a means to have software driv-ers identify the board rather than the chip on the board.
This register is implemented starting with TM1100 andonwards, and replaces the ‘Personality’ register function-ality in the TriMedia CTC chip.
The board manufacturer chooses the values of both 16bits fields by modifying the TM1100 Boot EEPROM. Thelocation of these bits is described in Section 12.5, “De-tailed EEPROM Contents.” A legal Vendor ID must beobtained from the PCI SIG. The vendor is free to assignsubsystem ID’s.
10.6.13 Expansion ROM Base Address Register
The Expansion ROM Base Address register is similar inpurpose to the SDRAM and MMIO Base Address regis-ters. This register relocates a separate memory aperturefor PCI devices that wish to implement additional ROM.
TM1100 does not implement expansion ROM; conse-quently, the least-significant bit of this register—which in-dicates whether or not TM1100 responds to expansionROM accesses—is hardwired to zero. All other bits alsoread as zeros.
10.6.14 Interrupt Line Register
The value of the Interrupt Line Register determineswhich input of the system interrupt controller is driven byTM1100’s interrupt pin. As it configures the system andassigns resources, host system software writes this reg-ister to assign one of the system interrupt lines toTM1100.
10.6.15 Interrupt Pin Register
The value of the Interrupt Pin Register determines whichinterrupt pin TM1100 uses. Table 10-11 lists the possiblevalues for this register.
Since TM1100 uses inta#, the value of this register ishardwired to 1.
10.6.16 Max_Lat, Min_Gnt Registers
The value in the Max_Lat register specifies how often theTM1100 PCI interface needs access to the PCI bus. Thevalue in the Min_Gnt register specifies the minimumlength for a burst period on the PCI bus.
Both of these timer values are specified as multiples of250 ns. Values of zero indicate that a device has no spe-cific requirements for latency and burst-length.
For TM1100, Max_Lat is hardwired to 0x01 (250 ns), andMin_Gnt is hardwired to 0x03 (750 ns).
10.7 REGISTERS IN MMIO SPACE
The TM1100 PCI interface contains 13 MMIO registers;most, except the status bits in BIU_Status, are usuallywritten only by the DSPCPU. Table 10-12 lists the inter-nal cycles sequenced by the PCI interface and the regis-ters each involves. To ensure compatibility with futuredevices, all undefined MMIO bits should be ignoredwhen read, and written as zeroes.
The MMIO registers are all accessible to DSPCPU soft-ware, and all but the PCI_ADR and PCI_DATA registersare accessible to external PCI initiators. The facilities ofTM1100’s PCI interface can be useful to external initia-tors in certain circumstances; for example:
• The PCI DMA engine might be useful during host-assisted boot.
• Host-resident diagnostics may want to test the PCIinterface during boot.
• The MMIO registers can be used to diagnose mal-functioning parts.
Note, however, that external PCI initiators can accessMMIO registers in only one way: as 32-bit words on nat-urally aligned, 32-bit addresses. If any other type of ac-cess is attempted, the results are undefined. Also, thebyte order of the external initiator and the PCI interfacemust be the same; otherwise, the result of an access withdisagreeing byte order is undefined.
For easy reference, Table 10-13 lists the MMIO registerstogether with their offsets from MMIO_BASE and theiraccessibility by the DSPCPU and external PCI initiators.
Figure 10-8 shows the formats of the PCI interfaceMMIO registers. Following are detailed descriptions ofthe MMIO registers.
10.7.1 DRAM_BASE Register
The DRAM_BASE register in MMIO space is a shadowcopy of the DRAM_BASE register in PCI Configurationspace. See Section 10.6.11, “Base Address Registers,”for more details. This shadow copy provides MMIO-space access to this register. The P,T and M bitfields ofthis MMIO register are read-only.
10.7.2 MMIO_BASE Register
The MMIO_BASE register in MMIO space is a shadowcopy of the MMIO_BASE register in PCI Configurationspace. See Section 10.6.11, “Base Address Registers,”for more details. This shadow copy provides MMIO-space access to this register. The P,T and M bitfields ofthis MMIO register are read-only.
Table 10-11. Interrupt Pin Encodings
Interrupt Pin Meaning
1 Use interrupt pin inta#
2 Use interrupt pin intb#
3 Use interrupt pin intc#
4 Use interrupt pin intd#
all others Reserved
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10.7.3 MMIO/DRAM_BASE updates
The DRAM_BASE and MMIO_BASE register are notnormally written through MMIO - their value is deter-mined by the boot process. Although not recommended,the registers are writable in MMIO. Special care needs tobe exercised when writing these registers:
• writing to SDRAM_BASE moves the origin of anyexecuting DSPCPU program, which will cause it tofail
• writing to MMIO_BASE moves devices around, andmoves MMIO_BASE and SDRAM_BASE around
• writing to both registers in sequence requires a delay,due to the implementation. It is recommended tospace such writes far apart, or iterate until the firstregister written to reads back with the new valuebefore writing the second one
10.7.4 BIU_STATUS Register
The BIU_Status register holds bits that track the status ofbus cycles initiated by the DSPCPU and bus cycles fromexternal devices that write into SDRAM.Two bits of sta-tus are provided for each type of bus cycle: a busy bit and
Figure 10-8. PCI interface registers accessible in MMIO address space.
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a done bit. The DSPCPU can read both bits; a done bitis cleared by writing a one to it. The status register alsoholds two error-flag bits.
DSPCPU software must check the busy bits to avoid is-suing a PCI interface bus cycle request while a requestof a similar type is in progress. If a bus cycle is issuedwhile a request of similar type is in progress, the PCI in-terface ignores the second command and sets the ap-propriate error bit in the status register.
When the DSPCPU issues either an io_cycle orconfig_cycle request while a previous request of eithertype is already in progress, the PCI interface sets bit 8 inBIU_STATUS. When the DSPCPU issues a dma_cyclewhile a previous one is already in progress, the PCI in-terface sets bit 9 in BIU_STATUS.
To reset either of the error bits 8 and 9 in BIU_STATUSwrite a ‘1’ to it.
RTA (Received Target Abort). This bit gets set whenTM1100 initiated a transaction that was aborted by thetarget. To reset this bit, write a ‘1’ to this bit position. Thisbit is set simultaneous with the RTA bit in the configura-tion space status register, but gets cleared independent-ly.
RMA (Received Master Abort). This bit gets set whenTM1100 initiated a transaction and aborts it. This usuallysignals a transaction to a non existent device. To resetthis bit, write a ‘1’ to this bit position. This bit is set simul-taneous with the RMA bit in the configuration space sta-tus register, but gets cleared independently.
TTE (Target Timer Expired). In normal operation, aread of a TM1100 data item is performed on retry basis -TM1100 tells the external master to retry, and meanwhileit fetches the data item across the highway. This bit getsset if an external master did not retry a read of a TM1100data item within 32768 PCI clocks. The requested data isdiscarded. To reset this bit, write a ‘1’ to this bit position.This is purely a software information bit. No software ac-tion is required when this condition occurs, but it may in-dicate a non-compliant or defective master on the bus.
10.7.5 BIU_CTL Register
The BIU_CTL register contains bits that control miscella-neous aspects of the PCI interface operation. Followingare descriptions of the fields.
SE (Swap Bytes Enable). This bit is initialized after re-set to zero, which causes the PCI interface to operate inits default big-endian mode. Writing a one to SE causesaccesses to MMIO registers over the PCI interface to bemade in little endian mode.
BO (Burst mode Off). This bit is initialized to zero, whichallows the PCI interface to support burst-mode writes asa target on the PCI bus. Setting this bit to one disablesburst-mode writes.
With burst mode enabled, the PCI interface buffers asmuch data as possible into r_buffer before issuing a dis-connect to the PCI initiator. With burst mode disabled,the PCI interface buffers only one data phase before is-suing a disconnect to the PCI initiator.
IntE (Interrupt Enables). The bits in the IntE field controlthe signalling of interrupts to the DSPCPU for PCI inter-face events. These events raise DSPCPU interrupt 16 ifenabled. Interrupt 16 must be set up as a level triggeredinterrupt. Table 10-14 lists the function of each IntE bit.
IntE is initially set to zeros (interrupts disabled).
Note that the error condition masked by bit 6 (see Sec-tion 10.7.4, “BIU_STATUS Register”) occurs when eithera config_cycle or an io_cycle is requested and a requestof either type is already in progress. That is, the secondrequest need not be of exactly the same type that is al-ready in progress.
Table 10-12. PCI MMIO Registers and Bus Cycles
Internal Cycle Registers Involved
mmio_cycle(MMIO register R/W)
All registers accessible by external PCI devices
mem_cycle(PCI-space memory R/W)
PCI_ADR,PCI_DATA
dma_cycle(Block data transfer)
SRC_ADR,DEST_ADR,DMA_CTL
IO_cycle(I/O register R/W)
IO_ADR,IO_DATA,IO_CTL
config_cycle(Configuration register R/W)
CONFIG_ADR,CONFIG_DATA,CONFIG_CTL
Table 10-13. PCI MMIO Register Accessibility
Register MMIO_BASE Offset
Accessibility
DSPCPU External Initiator
DRAM_BASE 0x10 0000 R/W R/W
MMIO_BASE 0x10 0400 R/W R/W
BIU_STATUS 0x10 3004 R/W R/W
BIU_CTL 0x10 3008 R/W R/W
PCI_ADR 0x10 300C R/W –/–
PCI_DATA 0x10 3010 R/W –/–
CONFIG_ADR 0x10 3014 R/W R/W
CONFIG_DATA 0x10 3018 R/W R/W
CONFIG_CTL 0x10 301C R/W R/W
IO_ADR 0x10 3020 R/W R/W
IO_DATA 0x10 3024 R/W R/W
IO_CTL 0x10 3028 R/W R/W
SRC_ADR 0x10 302C R/W R/W
DEST_ADR 0x10 3030 R/W R/W
DMA_CTL 0x10 3034 R/W R/W
INT_CTL 0x10 3038 R/W R/W
Table 10-12. PCI MMIO Registers and Bus Cycles
Internal Cycle Registers Involved
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IE (ICP DMA Enable). This bit is must be set to one to al-low the Image Coprocessor (ICP) to write pixel datathrough the PCI interface. If this bit is cleared to zero, theICP is not allowed to use the PCI interface. Programmingof ICP DMA is described in Section 13.6, “Operation andProgramming.”
HE (Host enable). This bit is initialized to zero, whichprevents the DSPCPU from serving as the host CPU inthe PCI system. If this bit is set to one, the Enable Mas-tering (EM) bit in the PCI Configuration register (see Sec-tion 10.6.3, “Command Register”) is also set to one(since TM1100 must be enabled to serve as a PCI businitiator to perform PCI configuration).
CR (PCI Clear Reset). This bit releases the DSPCPUfrom its reset state. The TM1100 device driver (executingon an external host CPU) sets this bit to one after it com-pletes TM1100’s configuration.
SR (PCI Set Reset). This bit forces the DSPCPU into itsreset state. Writing one to this bit resets the CPU; writingzero causes no action. The TM1100 device driver (exe-cuting on an external host CPU) can set this bit to resetthe DSPCPU. This form of reset resets only CPU andIcache. The Dcache is NOT reset, nor are any peripher-als.
RMD (Read Multiple Disable) . In default operatingmode, the RMD bit should be set to zero. In that case, theBIU uses “memory read multiple” PCI transactions forBIU DMA, and “memory read” PCI transactions forDSPCPU reads to PCI space. If the RMD bit is set, DMAtransactions are forced to also use the - less efficient -“memory read” transactions. Note that TM1000 onlyused “memory read” transactions.
10.7.6 PCI_ADR Register
The 30-bit PCI_ADR register is intended to be writtenonly by the data cache. PCI_ADR participates in the spe-cial two-cycle data-cache-to-PCI protocol. See Section10.7.7, “PCI_DATA Register,” for more information.
Only the DSPCPU can write to PCI_ADR. External PCIinitiators can neither read nor write this register.
DSPCPU software should not write to this register (bywriting to PCI_ADR in MMIO space). This register is in-tended only to support the special protocol between thedata cache and PCI bus. An unexpected write toPCI_ADR via MMIO space will not be prevented by hard-ware and may result in data corruption on the PCI bus.
10.7.7 PCI_DATA Register
The 32-bit PCI_DATA register is intended to be usedonly by the data cache. PCI_DATA participates in thespecial two-cycle data-cache-to-PCI protocol.
The PCI_DATA and PCI_ADR registers are used togeth-er by the data cache to perform a single data phase PCImemory-space read or write. A read operation is trig-gered when the data cache has written the transactionaddress into PCI_ADR and asserted the internal signalpci_read_operation (a direct internal connection be-tween the data cache and PCI interface). A write opera-tion is triggered when the data cache has written bothPCI_ADR and PCI_DATA with the signalpci_read_operation deasserted.
While the PCI interface is performing the PCI read orwrite, the DSPCPU is stalled waiting for the completionof the PCI transaction. When the PCI transaction is com-plete, the PCI interface asserts pci_ready (a direct inter-nal connection between the data cache and PCI inter-face). To finish a read operation, the data cache readsthe PCI_DATA register, forwards the data to theDSPCPU, and then unlocks the DSPCPU. To finish awrite, the data cache simply unlocks the DSPCPU.
Note that, if the DSPCPU attempts to access a non-exis-tent PCI address, a RMA condition occurs. In this case,the value in the PCI_DATA register is set to 0. Hence, theDSPCPU always reads non-existent PCI locations as ze-ro.
Normal MMIO write operations to PCI_DATA have no ef-fect. Reads return the register’s current value. ExternalPCI initiators can neither read nor write this register.
10.7.8 CONFIG_ADR Register
The CONFIG_ADR register is written by the DSPCPU toset up for a configuration cycle. When TM1100 is actingas the host CPU, it must configure devices on the PCIbus. The DSPCPU writes CONFIG_ADR to select a con-figuration register within a specific PCI device. See Sec-tion 10.7.10, “CONFIG_CTL Register,” for more infor-mation on initiating configuration cycles.
Following are descriptions of the fields of CONFIG_ADR.
BN (PCI Bus Number). The BN field (the two least-sig-nificant bits of CONFIG_ADR) selects one of four possi-ble PCI buses. A value of zero for BN means that the tar-geted device is on the PCI bus directly connected toTM1100 and that any PCI-to-PCI bridges should ignorethe configuration address. Any value for BN other thanzero means that the targeted device is on a PCI bus con-nected to a PCI-to-PCI bridge and that all devices direct-ly connected to TM1100’s local PCI bus should ignorethe configuration address.
RN (Register Number). The RN field (bits 2..7 ofCONFIG_ADR) is used to specify one of the 64 configu-ration words within the target device’s configurationspace.
FN (Function Number). The FN field (bits 8..10 ofCONFIG_ADR) is used to specify one of up to eight func-tions of the addressed PCI device.
Table 10-14. IntE Bit Functions
BIU_CTL Bit If Set to One, Interrupt DSPCPU When...
2 config_cycle done
3 io_cycle done
4 dma_cycle done
5 pci_dram write cycle done
6 second config_cycle or io_cycle requested
7 second dma_cycle requested
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Philips Semiconductors PCI Interface
DN (Device Number). The DN field (bits 11..31 ofCONFIG_ADR) is used to select the targeted PCI de-vice. Each bit corresponds to one of the 21 possible PCIdevices on a single PCI bus; i.e., each bit corresponds tothe idsel signal of one PCI device. Only one idsel sig-nal—and, therefore, only one DN bit—can be assertedduring a given configuration cycle.
10.7.9 CONFIG_DATA Register
The 32-bit CONFIG_DATA register is used by theDSPCPU to buffer data for a configuration cycle. WhenTM1100 is acting as the host CPU, it must configure thePCI bus and devices. The DSPCPU writes or readsCONFIG_DATA depending on whether it is performing awrite or read to a PCI device’s configuration space. SeeSection 10.7.10, “CONFIG_CTL Register,” for more in-formation on initiating configuration cycles.
10.7.10 CONFIG_CTL Register
The DSPCPU writes to CONFIG_CTL to trigger a config-uration read or write cycle on the PCI bus. A PCI config-uration read or write should not be performed during anongoing PCI I/O read or write.
The steps involved in a DSPCPU PCI configuration ac-cess are:
1. Wait until BIU_STATUS io_cycle.Busy and config_cycle.Busy are both de-asserted
2. Write to CONFIG_ADR as described above, and (in case of a write operation) write to CONFIG_DATA.
3. Write to CONFIG_CTL to start the read or write.This action sets config_cycle.Busy.
4. Wait (polling or interrupt based) until config_cycle.Done is asserted by the hardware.
5. Retrieve the requested data in CONFIG_DATA (in case of a read)
6. Clear config_cycle.Done by writing a ‘1’ to it.
Following are descriptions of the fields of CONFIG_CTLand a discussion of how a DSPCPU write toCONFIG_CTL triggers configuration cycles.
BE (Byte Enables). The BE field (the four least-signifi-cant bits of CONFIG_CTL) determines the state of PCI’sfour-line c/be# bus during the data phase of a configura-tion cycle. Since the c/be# bus signals are active low, azero in a BE field bit means “byte participates;” a one ina BE field bit means “byte does not participate.”Table 10-15 shows the correspondence between BE bitsand bytes on the PCI bus assuming little-endian byte or-der.
RW (Read/Write). The RW field (bit 4 of CONFIG_CTL)determines whether the configuration cycle will be a reador a write. Table 10-16 shows the interpretation of RW.
A write by the DSPCPU to the CONFIG_CTL registerstarts a configuration cycle on the PCI bus. TheCONFIG_DATA (for a write) and CONFIG_ADR regis-ters must be set up before writing to CONFIG_CTL.
During a configuration read, the PCI interface drives thePCI bus with the address from CONFIG_ADR and theBE field from CONFIG_CTL. The returned data is buff-ered in CONFIG_DATA. When the data is returned, thePCI interface will generate a DSPCPU interrupt if the ap-propriate IntE bit is set in BIU_CTL. Alternatively,DSPCPU software can poll the appropriate “done” statusbin in BIU_STATUS. Finally, DSPCPU software readsthe CONFIG_DATA register in MMIO space to accessthe data returned from the configuration cycle.
A write operation proceeds as for a read, except that PCIdata is driven from CONFIG_DATA during the transac-tion and no data is returned in CONFIG_DATA.
10.7.11 IO_ADR Register
The 32-bit IO_ADR register is written by the DSPCPU toset up for an access to a location in PCI I/O space. TheDSPCPU writes the address of the I/O register intoIO_ADR. See Section 10.7.13, “IO_CTL Register,” formore information on initiating I/O cycles.
10.7.12 IO_DATA Register
The 32-bit IO_DATA register is used by the DSPCPU toset up for an access to a location in PCI I/O space. TheDSPCPU writes or reads IO_DATA depending on wheth-er it is performing a write or read from IO space. SeeSection 10.7.13, “IO_CTL Register,” for more informa-tion on initiating I/O cycles.
10.7.13 IO_CTL Register
The DSPCPU writes to IO_CTL to trigger a read or writeaccess to PCI I/O space. The function of this register issimilar to that of CONFIG_CTL, and the protocol for an I/O cycle is similar to the configuration cycle protocol. APCI I/O read or write should not be performed during anongoing PCI configuration read or write.
The steps involved in a DSPCPU PCI I/O access are:
Table 10-15. BE Field Interpretation
BE Bit Interpretation
0 0 ⇒ byte 0 (LSB) participates1 ⇒ byte 0 (LSB) does not participate
1 0 ⇒ byte 1 participates1 ⇒ byte 1 does not participate
2 0 ⇒ byte 2 participates1 ⇒ byte 2 does not participate
3 0 ⇒ byte 3 (MSB) participates1 ⇒ byte 3 (MSB) does not participate
Table 10-16. RW Interpretation
RW Interpretation
0 Write
1 Read
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TM1100 Preliminary Data Book Philips Semiconductors
1. Wait until BIU_STATUS io_cycle.Busy and config_cycle.Busy are both de-asserted
2. Write IO address to IO_ADR, and (in case of a write operation) writedata to IO_DATA.
3. Write to IO_CTL to start the read or write.This action sets io_cycle.Busy.
4. Wait (polling or interrupt based) until io_cycle.Done is asserted by the hardware.
5. Retrieve the requested data in IO_DATA (in case of a read)
6. Clear io_cycle.Done by writing a ‘1’ to it.
Following are descriptions of the fields of IO_CTL and adiscussion of how a DSPCPU write to IO_CTL triggers I/O cycles.
BE (Byte Enables). The BE field (the four least-signifi-cant bits of IO_CTL) determines the state of PCI’s four-line c/be# bus during the data phase of an I/O cycle.Since the c/be# bus signals are active low, a zero in a BEfield bit means “byte participates;” a one in a BE field bitmeans “byte does not participate.” Table 10-15 showsthe correspondence between BE bits and bytes on thePCI bus assuming little-endian byte order.
RW (Read/Write). The RW field (bit 4 of IO_CTL) deter-mines whether the I/O cycle will be a read or a write.Table 10-16 shows the interpretation of RW (0 ⇒ write,1 ⇒ read).
A write by the DSPCPU to the IO_CTL register starts anI/O cycle on the PCI bus. The IO_DATA (for a write) andIO_ADR registers must be set up before writing toIO_CTL.
During an I/O read, the PCI interface drives the PCI buswith the address from IO_ADR and the BE field fromIO_CTL. The returned data is buffered in IO_DATA.When the data is returned, the PCI interface will gener-ate a DSPCPU interrupt if the appropriate IntE bit is setin BIU_CTL. Alternatively, DSPCPU software can pollthe appropriate “done” status bin in BIU_STATUS. Final-ly, DSPCPU software reads the IO_DATA register inMMIO space to access the data returned from the I/O cy-cle.
A write operation proceeds as for a read, except that PCIdata is driven from IO_DATA during the transaction andno data is returned in IO_DATA.
10.7.14 SRC_ADR Register
The 32-bit SRC_ADR register is used to set the sourceaddress for a block transfer DMA operation. The addressin SRC_ADR must be word (4 byte) aligned, i.e. the 2LSB’s have to be zero. The content of this register duringor after DMA is not defined, hence it can not be used totrack progress or verify completion of a DMA transaction.
10.7.15 DEST_ADR Register
The 32-bit DEST_ADR register is used to set the desti-nation address for a block transfer DMA operation. Theaddress is DEST_ADR must be word (4 byte) aligned,i.e. the 2 LSB’s have to be zero. The content of this reg-
ister during or after DMA is not defined, hence it can notbe used to track progress or verify completion of a DMAtransaction.
10.7.16 DMA_CTL Register
A write by the DSPCPU to the DMA_CTL register startsa DMA block transfer on the PCI bus. The SRC_ADRand DEST_ADR registers must be set up before writingto DMA_CTL.
The steps involved in a DMA transfer are:
1. Wait until BIU_STATUS dma_cycle.Busy is de-assert-ed
2. Write to SRC_ADR and DEST_ADR as described above.
3. Write to DMA_CTL to start the dma transaction.This action sets dma_cycle.Busy.
4. Wait (polling or interrupt based) until dma_cycle.Done is asserted by the hardware.
5. Clear dma_cycle.Done by writing a ‘1’ to it.
The fields of DMA_CTL are described below.
TL (Transfer Length). The TL field (bits 0..25 ofDMA_CTL) specifies the number of data bytes to betransferred during the DMA operation. It must be a mul-tiple of 4 bytes. The maximum length of a DMA operationis limited to 64M, the maximum amount of SDRAM sup-ported by TM1100. The content of this field during or af-ter a DMA transaction is not defined.
D (DMA Direction). The D field (bit 26 of DMA_CTL) de-termines the direction of data movement during the blocktransfer. Table 10-17 (shows the interpretation of the Dfield.
T (DMA Transaction Type). The T field (bit 27 ofDMA_CTL) determines the transaction type of a write, asdescribed below.
TM1100 generates memory write-and-invalidate PCItransactions if all conditions below are satisfied, other-wise it generates regular memory write transactions:
• The MWI bit in the Command Register is set.• The Cache Line Size register is set to 4,8 or 16 32-bit
words.• The DMA source address is 64 byte aligned.
Table 10-17. D Interpretation
D Data Movement Direction
0 SDRAM → PCI memory space (DMA write)
1 PCI memory space → SDRAM (DMA read)
Table 10-18. T interpretation
T DMA Write transaction type
0 memory write
1 memory write-and-invalidate
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Philips Semiconductors PCI Interface
• The DMA destination address is cache line sizealigned.
• The T bit is set
TM1100 generates “memory read multiple” PCI transac-tions for DMA reads, unless the RMD (Read Multiple Dis-able) bit is set in BIU_CTL, in which case the less effi-cient “memory read” transactions are used.
During a PCI → SDRAM block transfer, the PCI interfacedrives the PCI bus with the address from SRC_ADR. Thereturned data is buffered in r_buffer. The PCI interfacethen drives the address from DEST_ADR and the datafrom r_buffer to the SDRAM controller. SRC_ADR andDEST_ADR are incremented, the TL field in DMA_CTLis decremented, and this sequence repeats until TLreaches zero.
At the end of the PCI → SDRAM block transfer, the PCIinterface will generate a DSPCPU interrupt if the appro-priate IntE bit is set in BIU_CTL. Alternatively, DSPCPUsoftware can poll the appropriate “done” status bin inBIU_STATUS.
During an SDRAM → PCI block transfer, the PCI inter-face drives the address from SRC_ADR to the SDRAMcontroller. The returned data is buffered in w_buffer. ThePCI interface then drives the address from DEST_ADRand the data from w_buffer to the PCI bus. SRC_ADRand DEST_ADR are incremented, the TL field inDMA_CTL is decremented, and this sequence repeatsuntil TL reaches zero.
At the end of the SDRAM → PCI block transfer, the PCIinterface can generate a DSPCPU interrupt if the appro-priate IntE bit is set in BIU_CTL. Alternatively, DSPCPUsoftware can poll the appropriate “done” status bit inBIU_STATUS.
10.7.17 INT_CTL Register
The INT_CTL register contains three fields for setting,enabling, and sensing the four PCI interrupt lines.Table 10-19 shows the interpretation of the fields inINT_CTL.
INT (Interrupt bits). The INT field (bits 0..3 of INT_CTL)can force a PCI interrupt to be signalled.
IE (Interrupt Enable). The IE field (bits 4..7 of INT_CTL)enables TM1100 to drive PCI interrupt lines.
IS (Interrupt State). The IS field (bits 8..11 of INT_CTL)senses the state of the PCI interrupt lines.
Figure 10-9 shows a conceptual realization of the logicused to implement the control of each intx# pin.
See also Section 3.6, “TM1100 to Host Interrupts.”
10.8 PCI BUS PROTOCOL OVERVIEW
TM1100’s PCI interface can generate and respond toseveral types of PCI bus commands. Table 10-20 liststhe 12 possible commands and whether or not TM1100
Table 10-21 lists the 12 possible commands and wheth-er or not TM1100 can respond to them.
The basic transfer mechanism on the PCI bus is a burst,which consists of an address phase followed by one ormore data phases. In TM1100, the DSPCPU and ImageCoprocessor (ICP) are the only two units that can causeTM1100 to become a PCI-bus initiator; i.e., only theDSPCPU and ICP can access external resources.
Interrupt acknowledgeSpecial cycleDual addressMemory read line
INTx
oc PCI int x#
IEx
ISx
Figure 10-9. Conceptual realization of intx# pin con-trol logic.
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TM1100 Preliminary Data Book Philips Semiconductors
10.8.1 Single-Data-Phase Operations
When the DSPCPU reads or writes PC memory, the PCItransaction has only a single data phase. A typical sin-gle-data-phase read operation is illustrated inFigure 10-10. During the first clock period, the TM1100asserts the frame# signal to indicate that the transactionhas begun and that an address and command are stableon ad and c/be#, respectively.
TM1100 then releases the ad bus, deasserts frame#, as-serts irdy#, asserts byte enables on c/be#, and waits forthe target to claim the transaction by asserting devsel#.The target asserts trdy# to signal the master that the adbus contains stable data. The assertion of trdy# causesthe initiator (TM1100 in this case) to sample the ad busdata and deassert irdy# to complete the single-data-phase read transaction.
Figure 10-11 shows a typical single-data-phase write op-eration. The operation begins as with the read: TM1100asserts the frame# signal and drives the ad bus with thetarget address and drives the command onto the c/be#bus.
The operation continues when TM1100 deassertsframe#, asserts irdy#, and drives the byte enables as be-fore, but it also drives the data to be written on the adbus. The target device asserts devsel# to claim the trans-action. Eventually, the target asserts trdy# to signal thatit is sampling the data on the ad bus. TM1100 continues
to drive the data on the ad bus until after the target deas-serts trdy#, which completes the write operation.
10.8.2 Multi-Data-Phase Operations
As with the single-data-phase operations, DMA opera-tions begin with the assertion of frame# and valid ad-dress and command information. See Figure 10-12. Thetarget knows a burst is requested because frame# re-mains asserted when irdy# becomes asserted.
In the example timing of Figure 10-12, a fast device is re-ceiving the burst from TM1100. The target assertsdevsel# and trdy# simultaneously. The trdy# signal re-mains asserted while TM1100 sends a new word of dataon each PCI clock cycle. The burst operation shown is a16-word burst transfer. Since only the starting address issent by the initiator, both initiator and target must incre-ment source and destination addresses during the burst.
The initiator signals the end of the burst of data inFigure 10-12 when it deasserts frame# in clock 17. Thelast word (or partial word) of data is transferred in theclock cycle after frame# is deasserted. Finally, the targetacknowledges the last data phase by deasserting trdy#and devsel#.
Figure 10-13 illustrates back-to-back DMA burst datatransfers. The ICP is capable of exploiting the high band-width available with back-to-back DMA operations whenit is writing image data to a frame buffer on a PCI videocard.
The timing of Figure 10-13 assumes that the PCI bus isgranted to TM1100 until at least the beginning of the sec-ond DMA burst operation. For as long as bus ownershipis granted to TM1100 and the ICP has queued requestsfor data transfer, the PCI interface will perform back-to-back DMA operations. If the target eventually becomesunable to accept more data, it signals a disconnectTM1100’s PCI interface. The PCI interface rememberswhere the DMA burst was interrupted and attempts to re-start from that point after two bus clocks.
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Philips Semiconductors PCI Interface
10.9 LIMITATIONS
10.9.1 Bus Locking
The PCI interface does not implement lock#, sbo, andsbone pins. Consequently, it is possible for both theDSPCPU and external PCI initiators to write to a criticalmemory section simultaneously. Software must imple-ment policies to guarantee memory coherency.
10.9.2 No Expansion ROM
TM1100 does not implement the PCI expansion ROMcapability.
10.9.3 No Cacheline Wrap Address Sequence
The PCI interface does not implement the PCI cacheline-wrap address mode for external PCI initiators that ac-cess TM1100 SDRAM.
10.9.4 No Burst for I/O or Configuration Space
Only single-data-phase transactions to configuration andI/O spaces are supported. The byte-enable signals se-lect the byte(s) within the addressed word.
10.9.5 Word-Only MMIO Register Access
External initiators can access TM1100 MMIO registersonly as full words. The byte-enable signals have no ef-fect on the data transferred. External initiators must readand write all four bytes of MMIO registers.
pci_clk
frame#
ad
c/be#
irdy#
trdy#
devsel#
1 2 3 4 5 6 17
Address
Byte Enables
18
Command
Data 1 Data 2 Data 3 Data 4 Data 15 Data 16
Dat
a T
rans
fer
Dat
a T
rans
fer
Dat
a T
rans
fer
Dat
a T
rans
fer
Dat
a T
rans
fer
Dat
a T
rans
fer
Dat
a T
rans
fer
Figure 10-12. PCI burst write operation with 16 data phases.
pci_clk
frame#
ad
c/be#
irdy#
trdy#
devsel#
1 2 3 18 19 20
Address
Byte Enables
35
Byte EnablesCommand
Data 1 Data 15 Data 16 Data 17 Data 31 Data 32
36
Dat
a T
rans
fer
Dat
a T
rans
fer
Dat
a T
rans
fer
Dat
a T
rans
fer
Dat
a T
rans
fer
Dat
a T
rans
fer
Figure 10-13. Back-to-back PCI burst write operations with 16 data phases such as might be generated by the ICP when writing image data to a PCI-resident video frame buffer.
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TM1100 Preliminary Data Book Philips Semiconductors
10-18 PRELIMINARY INFORMATION File: pci.fm5, modified 7/23/99
SDRAM Memory System Chapter 11
by Eino Jacobs, Chris Nelson, Luis Lucas
11.1 TM1100 MAIN MEMORY OVERVIEW
TM1100 connects to its local memory system with a ded-icated memory bus as shown in Figure 11-1. This bus in-terfaces only with SDRAM (or SGRAM with its DSF pintied low), and TM1100 is the only master on this bus. Forup to four memory chips, the interface is glueless.
A variety of device types, speeds, and rank1 sizes aresupported, which allows a range of TM1100 systems tobe built. Table 11-1 summarizes the memory system fea-tures.
The interface provides all control and data signals withsufficient drive capacity for a glueless connection to a133-MHz memory system with up to four memory devic-es. Note that memory-system speed can be differentfrom TM1100 core speed; the ratio between the memorysystem clock and TM1100 core clock is programmable.
With current technology, TM1100 supports a glueless 8-MB memory system with four 2×1M×8 SDRAM chips(four devices with 2 banks of one million words, each 8bits wide) or 16MB with two 4x512Kx32. Larger memo-ries require a lower memory system clock frequency(though the TM1100 core clock can be higher), and thelargest memory arrays will require external buffers to in-crease drive capacity.
11.2 MAIN-MEMORY ADDRESS APERTURE
TM1100’s local main memory is just one of three aper-tures into the 4-GB address space of the DSPCPU:
• SDRAM (0.5 to 64 MB in size),• MMIO (2 MB in size), and• PCI (any address not in SDRAM or MMIO).
MMIO registers control the positions of the address-space apertures. The SDRAM aperture begins at the ab-solute address specified in the MMIO registerDRAM_BASE and extends upward to the address spec-ified in the DRAM_LIMIT register. If the SDRAM apertureoverlaps the memory hole, the memory hole is ig-
nored.The MMIO aperture begins at the address inMMIO_BASE, which defaults to 0xEFE00000 after pow-er-up, and extends upwards two megabytes. (See Chap-ter 3, “DSPCPU Architecture,” for a detailed discussion.)All addresses that fall outside these two apertures areassumed to be part of the PCI address aperture.
11.3 MEMORY DEVICES SUPPORTED
The devices and organizations supported can be config-ured as listed in Table 11-2. All devices must have aLVTTL, 3.3-V interface.
1. In this document, the term “rank” is used to refer to agroup of memory devices that are accessed together.Historically, the term “bank” has been used in this con-text; to avoid confusion, this document uses “bank” torefer to on-chip organization (SDRAM devices have twointernal banks) and “rank” to refer to off-chip, system-level organization.
Table 11-1. Memory System Features
Characteristic Comments
Data width 32 bits
Number of ranks Four chip-select signals support up to four ranks
Clock rate Up to 133 MHz SDRAM speed (program-mable ratio between TM1100 core clock and memory system clock)
Bandwidth 532 MB/s (@ 133 MHz)
Glueless interface • Up to four chips @ 133 MHz (e.g., 8 MB memory with 2×1M×8 SDRAM)
• Up to two chips @ 133 MHz (e.g., 16 MB memory with 4x512Kx32 SDRAM)
• More chips with slower clock and/or external buffers
Signal levels 3.3-V LVTTL
Table 11-2. Supported Rank Configurations
Device Size (Mbit) Device(s) Rank Size
2 2×64K×16 SDRAM 512 KB
4 2×128K×16 SDRAM 1 MB
8 2×128K×32 SGRAM 1 MB
16 2×256K×32 SGRAM 2 MB
2×512K×16 SDRAM 4 MB
2×1M×8 SDRAM 8 MB
2×2M×4 SDRAM 16 MB
64 4x512Kx32 SDRAM 8 MB
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TM1100 Preliminary Data Book Philips Semiconductors
11.3.1 SDRAM
TM1100 is designed to support synchronous DRAMchips directly. SDRAM has a fast, synchronous interfacethat permits burst transfers at a rate of one word perclock cycle. The memory inside an SDRAM device is di-vided into two banks, and the SDRAM implements inter-leaved bank access to sustain maximum bandwidth.
SDRAM devices implement a power down mechanismwith self-refresh. TM1100’s power management takesadvantage of this mechanism.
TM1100 supports only Jedec-compatible SDRAM withtwo internal banks of memory per device (Note:4×512K×32 SDRAM with 4 internal banks is an excep-tion see Section 11.16.1).
11.3.2 SGRAM
Synchronous graphics DRAM (SGRAM) can also beused in a TM1100 system. SGRAM has a 2×128K×32 or-ganization, and is essentially an SDRAM with some ad-ditional features for raster graphics functions. The devicetype is standardized by Jedec and offered by multipleDRAM vendors. SGRAM devices are packaged in a 100-pin QFP and are available in speed grades up to 133-MHz.
By tying the DSF input of an SGRAM low, the device op-erates like a standard 32-bit-wide SDRAM. Thus, tyingDSF low makes SGRAM compatible with TM1100’smemory interface.
11.4 MEMORY GRANULARITY AND SIZES
TM1100 supports a variety of memory sizes thanks to:
• The availability of many organizations of SDRAMdevices, and
• TM1100’s support for up to four memory ranks.
The minimum memory size is 512KB using two2×64K×16 SDRAM parts on the 32-bit data bus.
Up to four memory devices can be connected to TM1100without any glue logic and without sacrificing any perfor-mance. The maximum memory size with full perfor-
mance is 16MB using two 4×512K×32 SDRAMs on a 32-bit data bus.
Larger memories can be constructed using more devic-es, but the frequency of the memory interface must belowered to account for the extra propagation delay due tothe excessive loading on the interface signals (see Sec-tion 11.12, “Output Driver Capacity”). When a very largenumber of chips is connected (more than 16), it is advan-tageous to add external buffers to the address and con-trol signals.
The following rules apply to memory rank design:
• All devices in a rank must be of the same type.• All ranks must be a power of two in size.• All ranks must be equal size.
Table 11-3 lists some example memory system designs.Note that the 64-MB configuration requires external buff-ers. Note:
• Some of these configurations may not be economi-cally attractive due to the price premium for small-capacity devices.
• “Max. MHz” refers to the memory interface/SDRAMspeed, not the TM1100 core operating frequency.
11.5 MEMORY SYSTEM PROGRAMMING
Memory system parameters are determined by the con-tents of two configuration registers, MM_CONFIG andPLL_RATIOS. Table 11-4 describes the function ofthese registers, and Figure 11-2 shows their formats. Toensure compatibility with future devices, any undefinedMMIO bits should be ignored when read.
MM_CONFIG and PLL_RATIOS are loaded from theboot EEPROM, as described in Section 12.5, “DetailedEEPROM Contents.” During this boot process, the mem-ory interface is held in reset state. After the memory in-terface is released from reset, the contents of these reg-isters cannot be altered.
These registers are visible in MMIO space. They can beread, but writes have no effect.
Figure 11-1. TM1100 provides a high-performance memory interface for local main memory. The interface connects the internal highway bus to external SDRAM or SGRAM. The interface is glueless for an array of up to four devices.
TM1100Memory
Interface
Chip Selects#Address,
Clock Enables,RAS#, CAS#, WE#
Byte Enables[3:0]Clock
MatchOut
MatchInData[31:0]
CS#
Address, Control
DQM[3:0]CLK
DQ[31:0]
GNDPropagation Delay
Compensation Loop
22 Ω0 Ω
SDRAMMemoryArray
DataHighway
TM1100
On-ChipPeripherals
DSPCPU
0 pf
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Philips Semiconductors SDRAM Memory System
11.5.1 MM_CONFIG Register
The MM_CONFIG register tells the memory interfacehow to use the local DRAM memory. The fields in thisregister tell the interface the rank size and the refresh
rate of the memory. Table 11-6 summarizes the fieldfunctions.
REFRESH (Refresh interval). The 16-bit REFRESHfield specifies the number of memory-system clock cy-cles between refresh operations. The default value ofthis register is 1000 (0x03E8). See Section 11.10, “Re-fresh,” for more information.
Bit three of MM_CONFIG must be set to zero for normaloperation.
SIZE (Rank Size). The three-bit SIZE field specifies thesize of each rank of DRAM. Each rank must be the sizespecified by SIZE. The default is a rank size of 4MB. Re-fer to Table 11-5 for the interpretation of this field.
11.5.2 PLL_RATIOS Register
The PLL_RATIOS register controls the operation of theseparate memory-interface and CPU PLLs. Fields in thisregister determine if the PLLs are active and what in-put:output ratio each PLL should generate. Table 11-6summarizes the field functions. Figure 11-3 shows howthe PLLs are connected and how fields in thePLL_RATIOS register control them.
CR (CPU-to-memory PLL Ratio). The three-bit CR fieldselects one of five input-to-output clock ratios for theCPU PLL. The input clock is the memory system clock;the output clock determines TM1100’s core operatingfrequency. The default value is zero, which implies a 1:1CPU:memory ratio. See Table 11-6 for other encodings.
SR (Memory-to-external PLL Ratio). The one-bit SRfield selects one of two memory-to-external clock ratiosfor the memory interface PLL. The PLL input is TM1100’sexternal input clock TRI_CLKIN; the PLL output deter-mines the operating frequency of the memory interfaceand SDRAM devices. The default value is zero, whichimplies a 2:1 memory:external ratio. A value of one im-plies a 3:1 ratio.
CD (CPU PLL Disable). The one-bit CD field determineswhether or not the CPU PLL is turned on. The reset valueis one, which disables operation of the CPU PLL and dis-sipates almost no power. For normal operation the valueshould be zero, enabling the CPU PLL.
CB (CPU PLL Bypass). The one-bit CB field determineswhether the input or the output of the CPU PLL drives
Table 11-3. Example Memory Configurations
Size(MB) Ranks Rank Configurations Max.
MHzPeakMB/s
0.5 1 two 2×64K×16 SDRAM 133 532
1 1 one 2×128K×32 SGRAM 133 532
1 two 2×128K×16 SDRAM 133 532
2 1 one 2×256K×32 SDRAM 133 532
4 1 two 2×512K×16 SDRAM 133 532
8 1 four 2×1M×8 SDRAM 133 532
2 two 2×512K×16 SDRAMtwo 2×512K×16 SDRAM
133 532
1 one 4×512K×32 SDRAM 133 532
16 1 eight 2×2M×4 SDRAM 66 264
2 one 4×512K×32 SDRAMone 4×512K×32 SDRAM
133 532
24 3 one 4×512K×32 SDRAMone 4×512K×32 SDRAMone 4×512K×32 SDRAM
125 500
32 2 eight 2×2M×4 SDRAMeight 2×2M×4 SDRAM
50 200
4 one 4×512K×32 SDRAMone 4×512K×32 SDRAMone 4×512K×32 SDRAMone 4×512K×32 SDRAM
File: memsys.fm5, modified 7/24/99 PRELIMINARY INFORMATION 11-3
TM1100 Preliminary Data Book Philips Semiconductors
TM1100’s core logic. The default value is one, whichcauses the TM1100 core to be clocked by the input of theCPU PLL (i.e., the memory interface clock). A value of
zero causes normal operation, and the core is clocked bythe output of the CPU PLL.
Note that if both CB and SB are set to one (bypass theCPU PLL and bypass the SDRAM PLL), TM1100’s corelogic is effectively clocked at the external input frequen-cy.
Note: it is illegal to use the output of a disabled PLL. Forexample, it is illegal to have CD set to one while CB is setto zero.
SD (SDRAM PLL Disable). The one-bit SD field deter-mines whether or not the SDRAM PLL is turned on. Thedefault value is one, which disables the SDRAM PLL,and it dissipates almost no power. For normal operationthe value should be zero, enabling the SDRAM PLL.
SB (SDRAM PLL Bypass). The one-bit SB field deter-mines whether the input or the output of the SDRAM PLLdrives the memory interface and memory devices. Thedefault value is one, which causes the memory system tobe clocked by the input of the SDRAM PLL (TM1100’sexternal input clock). A value of zero causes normal op-eration, and the memory system is clocked by the outputof the SDRAM PLL.
11.6 MEMORY INTERFACE PIN LIST
The memory interface consists of 61 signal pins includ-ing clocks (but excluding power and ground pins).Table 11-7 lists the interface signal pins.
11.7 ADDRESS MAPPING
Table 11-8 shows how internal address bits from thedata highway bus (which connects all internal TM1100units) are mapped to main-memory address-bus pins(MM_A[11:0]). The mapping is determined by the state ofthe rank-size bits in the MM_CONFIG register.
The column “Rank Addr./H.Way Bits” specifies which in-ternal data-highway address bits select the preliminarySDRAM rank. The actual rank used is subject to the lim-itation implied by the relationship between SDRAM aper-ture size (described in Section 12.3.1) and the rank size.
Table 11-5. MM_CONFIG Fields
Field Function
REFRESH Refresh interval in memory clock cycles.Default value 1000 (0x03E8).
SIZE Memory rank size 0 Reserved
1 512KB
2 1MB
3 2MB
4 4MB
5 8MB
6 16MB
7 Reserved
Table 11-6. PLL_RATIOS Fields
Field Function
CR CPU:memory ratio 0 1:1
1 2:1
2 3:2
3 4:3
4 5:4
5–7 Reserved
SR Memory:external ratio 0 2:1
1 3:1
CD CPU PLL Disable 0 CPU PLL on
1 CPU PLL off
CB CPU PLL bypass 0 CPU ← PLL
1 CPU ← Memory
SD SDRAM PLL Disable 0 SDRAM PLL on
1 SDRAM PLL off
SB SDRAM PLL bypass 0 Memory ← PLL
1 Memory ← external
Figure 11-3. TM1100 memory and core PLL connections.
Memory System PLL DSPCPU PLL
CR
04 237 56
SD SB CD CB SR PLL_RATIOS Register
TM1100 CoreClock
TM1100
TRI_CLKIN
MM_CLK1MM_CLK0
External Clock Input
Memory System Clocks
11-4 PRELIMINARY INFORMATION File: memsys.fm5, modified 7/24/99
Philips Semiconductors SDRAM Memory System
The rank is selected via the chip select bits,MM_CS#[3:0].
The column “Row Address/H.Way Bits” specifies whichinternal data-highway address bits map to the SDRAMrow address. “Row Address/Pins” specifies which linesof TM1100’s MM_A address bus serve as the SDRAMrow address.
The column “Column Address/H.Way Bits” specifieswhich data-highway address bits map to the SDRAM col-umn address. “Column Address/Pins” specifies whichlines of TM1100’s MM_A address bus serve as theSDRAM column address.
MM_A[12] is only defined for a 8 MB rank size with4x512Kx32 SDRAMs. MM_A[12] contains then H.Waybit 11 (i.e. same behavior as pin MM_A[8]).
Bits 5–0 of the highway address are the offset within a64-byte block; these bits are all zero for an aligned blocktransfer. The table lists the mapping of bits 5–2 to identifyin which SDRAM positions the words of a block are locat-ed.
Bit 5 of the highway address is always mapped to theSDRAM internal bank select; thus, each SDRAM bankreceives half (32 bytes) of the block transfer.
Bits 4–2 of the highway address are the word offset in acache block. Bits 1–0 are the byte offset within a 32-bitword.
11.8 MEMORY INTERFACE AND SDRAM INITIALIZATION
Immediately after reset, the main-memory interface is ini-tialized by placing default values in the MM_CONFIGand PLL_RATIOS registers (see Section 11.5, “MemorySystem Programming”). During the subsequent hard-ware boot process, when TM1100 reads initial valuesfrom an external ROM, these registers can be set to dif-ferent values.
After TM1100 is released from the reset state, the mem-ory interface automatically executes 10 refresh opera-tions, then initializes the mode register in each SDRAMchip. Table 11-9 shows the settings in the SDRAM moderegister(s).
11.9 ON-CHIP SDRAM INTERLEAVING
The main-memory interface takes advantage of the on-chip interleaving of SDRAM devices. Interleaving allowsthe precharge, RAS, and CAS delays needed to readyone internal bank to be performed while useful datatransfer is occurring with the other internal bank. Thus,the overhead of preparing one bank is hidden duringdata movement to or from the other.
The benefit of on-chip interleaving is sustainable full-bandwidth data transfer (one word per clock cycle). Thetransition from one internal bank to the other happens on8-word boundaries; transferring 8 words gives the inac-tive bank time to prepare (perform precharge, RAS, andCAS) so that when the last word of the 8-word block inthe active bank has been transferred, the next word fromthe just-precharged bank is ready on the next cycle.
The seamless transitions between the two on-chip bankscan be sustained for a stream of contiguous addresseswith the same direction (read or write). That is, a streamof contiguous reads or contiguous writes can sustain fullbandwidth. If a write follows a read, then a small gap be-tween transfers is needed.
Each bank access is terminated with a read or write withautomatic precharge, making a separate prechargecommand before the next RAS unnecessary.
Interleaving is not improved by the use of 4 banks 64Mbit SDRAMs organized in x32.
Table 11-7. Memory Interface Signal Pins
Name Function I/O Active...
MM_CLK[1:0] Memory bus clock O High
MATCHOUT Clock propagation match-trace output
O High
MATCHIN Clock propagation match-trace input
I High
MM_CS#[3..0] Chip selects for the four memory ranks
O Low
MM_RAS# Row-address strobe O Low
MM_CAS# Column address strobe O Low
MM_WE# Write enable O Low
MM_A[12:0] Address O High
MM_CKE[1:0] Clock enable O High
MM_DQM[3:0] Byte enables for dq bus O High
MM_DQ[31:0] Bi-directional data bus I/O High
Table 11-8. Address Mapping Based on Rank Size
RankSize
RankAddr.
RowAddress
ColumnAddress
BankAddress
H.WayBits Pins H.Way
Bits Pins H.WayBits Pin H.Way
Bit
512 KB 20-19 8,6–0
18,17–11 7–0 10–6,
4–2 9
5
1 MB 21-20 8–0 19–11 7–0 10–6,4–2 9
2 MB 22-21 9–0 20–11 7–0 10–6,4–2 10
4 MB 23–22 10–0 21–11 7–0 10–6,4–2 11
8 MB 24-23 10–0 22–12 8–0 11–6,4–2 11
16 MB 25-24 10–0 23–13 9–0 12–6,4–2 11
Table 11-9. SDRAM Mode Register Settings
Parameter Value
Burst Length 4
Wrap type Interleaved
CAS latency 3
File: memsys.fm5, modified 7/24/99 PRELIMINARY INFORMATION 11-5
TM1100 Preliminary Data Book Philips Semiconductors
11.10 REFRESH
The main-memory interface performs SDRAM refreshcycles autonomously using the CAS-before-RAS (CBR)mechanism. SDRAMs have a 4K refresh interval: either4096 rows must be refreshed every 64 ms or 2048 rowsevery 32 ms.
The main-memory interface performs refresh at timed in-tervals: one CBR refresh command must be issued ev-ery 15.6 µSec. A counter in the main-memory interfacekeeps track of the number of SDRAM clock cycles be-tween refresh operations. This counter starts after theCBR operation has completed; this CBR operation take19 cycles. When the counter reaches a programmed lim-it, the next refresh operation is due, and the next-in-linedata transfer request from the data-highway is delayeduntil the CBR operation is executed.
All devices in the main-memory system are refreshed si-multaneously. The REFRESH field in the MM_CONFIGregister determines the number of memory-system clockcycles (as distinguished from TM1100 core clock cycles)between the CBR refresh operations. Table 11-10 liststhe number of memory-system clocks for typical SDRAMoperation speeds.
Each CBR refresh operation takes 19 SDRAM clock cy-cles. Thus, at 100-MHz, refresh consumes about 1.2% ofmaximum available SDRAM bandwidth (19 cycles out of1560). The bandwidth impact is slightly higher at lowerfrequencies.
11.11 POWER DOWN MODE
When TM1100 is put into power down mode to reducepower consumption, the main-memory interface re-sponds by putting the SDRAM devices into their powerdown mode. In this mode, the SDRAM devices retaintheir contents through self-refresh.
11.12 OUTPUT DRIVER CAPACITY
TM1100’s output driver circuits for the memory addressand control signals (output signals in Table 11-7), candrive up to four memory devices when the memory inter-face is operating at 133 MHz. If more devices are con-nected, then a lower SDRAM clock frequency must bechosen.
Table 11-11 lists the clock frequency as a function of thenumber of memory devices connected to unbufferedmemory interface signals.
Two identical outputs are provided for both the MM_CKE(clock-enable) and MM_CLK signals. Each MM_CKEand MM_CLK signal is capable of driving two SDRAMdevices at 133MHz, thus the total of four devices.
11.13 SIGNAL PROPAGATION DELAY COMPENSATION
The memory interface has two special pins, matchoutand matchin, that help the interface compensate for thepropagation delay through circuit-board traces to andfrom the external SDRAM devices. At high clock frequen-cies, e.g., 133 MHz, propagation delay becomes signifi-cant compared to the clock period, which is as small as7.5 ns.
Matchout and matchin are connected through a dedicat-ed trace on the circuit board. This trace forms a “matchloop” with an outgoing part and an incoming part. Theoutgoing part should match the clock trace from thememory interface to the SDRAM(s). The incoming partshould match the longest trace between the SDRAM(s)and the memory interface pins.
Since the memory interface uses the matchin signal tosample incoming data, the match-loop trace should esti-mate the round-trip propagation delay as closely as pos-sible. This can be achieved with careful circuit board lay-out and some passive components to estimatecapacitive loading.
A lumped capacitive load is attached to the middle of thematchout/matchin trace to represent the sum of theclock-input and data-line loads. The lumped load shouldaccount for the number of SDRAM devices attached tothe clock line. The memory interface provides two clockoutputs, each capable of driving one or two memory de-vices directly.
Finally, to avoid excessive ringing of the clock signals,series termination with a 22-Ohm resistor is advised atthe clock and matchout outputs when the memory inter-face is operating at 100 MHz or higher.
The phase delay of the memory clock with respect to theinternal sending and receiving clocks is adjusted insidethe memory interface to achieve reliable communicationand guarantee correct setup and hold times.
Figure 11-4 shows a conceptual circuit board layout.Two SDRAM devices share a single clock output. The
Table 11-10. Refresh Intervals
SDRAM Operation Speed Value For REFRESH Field(decimal)
66 MHz 1000
75 MHz 1140
83 MHz 1270
100 MHz 1540
125 MHz 1930
133 Mhz 2060
Table 11-11. Glueless Interface Limits for Address/Clocks
Memory Chips Maximum Clock Frequency
4 133 Mhz
6 80 MHz
8 66 MHz
16 50 MHz
11-6 PRELIMINARY INFORMATION File: memsys.fm5, modified 7/24/99
Philips Semiconductors SDRAM Memory System
clock and matchout signals have source-series termina-tion. The matchout/matchin trace has a lumped load es-timating two SDRAM clock input and data loads.
It is recommended to abandon the transmission lineMATCHOUT-MATCHIN for speed higher than 100 MHz.Instead, tie MATCHOUT to MATCHIN through a RC de-lay circuit with minimal wire-length. I.e. MATCHOUTfeeds a resistor R to MATCHIN. MATCHIN has a cap. Cto ground. Suitable values for R and C can be optimizedto get best performance out of a given board. Initially useR = 0 Ohm, C = 0 pF, i.e. no C and shorted R. This willwork fine, and the fact that a R and C site are on theboard allows future fine-tuning. Figure 11-10 shows anexample for a 16 MB memory system.
11.14 CIRCUIT BOARD DESIGN
TM1100 and its memory array form a high-speed digitalsystem. Even though only a small number of chips is in-volved, this digital system operates at frequencies highenough to make the analog characteristics of the con-nections between the chips significant. Consequently,the system designer must take care to ensure reliableoperation.
11.14.1 General Guidelines
• In general, TM1100 and its memory chips should beas close together as possible to minimize parasiticcapacitance. Close proximity is especially importantfor a 100-MHz or higher memory system.
• SIgnal traces between TM1100 and the memorychips should be matched in length as closely as pos-sible to minimize signal skew.
• The clock-signal trace(s) should be as short as pos-sible.
• Address and control-signal traces should also beshort, but their length is less critical than the clock’s.
• Data-signal traces should also be short, but theirlength is less critical than the clock’s, especially ifonly one or two ranks are connected.
• The length of the trace between matchout andmatchin should be as close as possible to the sum ofthe lengths of the longest clock and data traces.
11.14.2 Specific Guidelines
• The maximum length for a signal trace is 10 cm.• The maximum capacitive load is 30 pF per trace,
including loads.• The signal traces on the TM1100 circuit board must
be designed as 50-Ohm transmission lines.• At 100 MHz or higher, the memory chips should also
be soldered to the circuit board.• At most two SDRAM devices may be connected to
each MM_CLK signal at 133 MHz.
11.14.3 Termination
No termination is required for address, data, and controlsignals. Address and control signals are driven only byTM1100; the output impedance of the drivers is suffi-ciently matched to prevent excessive ringing. TM1100design assumes that the output drivers of SDRAM chips,when driving data lines, are also sufficiently impedancematched.
Series termination of the clock and matchout outputswith a 22-Ohm resister is advised when operating thememory system at 100-MHz or higher (see Section11.13, “Signal Propagation Delay Compensation”).
11.15 TIMING BUDGET
The glueless interface of the TM1100 main-memory in-terface makes the memory system simple and straight-forward from one point of view, but to ensure reliable op-eration at high clock rates, system designers must follow
Figure 11-4. Conceptual board layout. The match trace loop should be as close to the sum of the lengths of the clock and data traces as possible.
Add
ress
& Con
trol
CLK
DQ
[31:
0]
GND
22 Ω
22 Ω
Add
ress
&
Con
trol
CLK
DQ
[31:
0]
14 pF
SDRAMDevice
SDRAMDevice
TM1100Memory
Interface
Address,Clock Enables,
RAS#, CAS#, WE#Clock
MatchOut
MatchInData[31:0]
DataHighway
TM1100
On-ChipPeripherals
DSPCPU
File: memsys.fm5, modified 7/24/99 PRELIMINARY INFORMATION 11-7
TM1100 Preliminary Data Book Philips Semiconductors
the match-loop and board design guidelines (see Sec-tion 11.13, “Signal Propagation Delay Compensation,”and Section 11.14, “Circuit Board Design”).
The following A.C. timing specifications are provided tohelp the verification of a memory system design. The tim-ing parameters take into account the following:
• Corners in the fabrication process, temperature, andvoltage.
• Ground and VDD bounce.• Transmission-line reflections.• Stub mismatch.• Signal trace wire-length mismatch.• Imbalance in internal chip wiring.• Tester accuracy of ± 400 ps.
These timing specifications do not include any other un-correlated margin. Table 11-12 lists four general timingparameters for the memory bus assuming worst-case
conditions for a board designed in compliance with theguidelines of Section 11.14, “Circuit Board Design.”
SDRAM devices must meet the critical specifications list-ed in Table 11-13 to ensure reliable operation of a 100-MHz memory system. These values leave virtually nomargin for the critical timing parameters in a high-speedsystem.
Table 11-12. Memory-Bus Timing Parameters, Worst-Case Board Design for 100 MHz system
Timing Parameter Value
Max. output delay of data, address, and control; (referenced to SDRAM clock input)
6.6 ns
Min. output hold time of data, address, and control; (referenced to SDRAM clock input)
1.0 ns
Min. input setup time of data;(referenced to MatchIn)
0.8 ns
Min. input hold time of data;(referenced to MatchIn)
1.9 ns
Table 11-13. Required SDRAM Performance For 100-MHz Memory System
Timing Parameter Value
Max. output delay 9.0 ns
Min. output hold time 3.0 ns
Max. input setup time 3.0 ns
Max. input hold time 1.0 ns
11-8 PRELIMINARY INFORMATION File: memsys.fm5, modified 7/24/99
Philips Semiconductors SDRAM Memory System
11.16 EXAMPLE BLOCK DIAGRAMS
Figure 11-5, Figure 11-6, Figure 11-7, Figure 11-8, Figure 11-9, and Figure 11-10 illustrate some common memorysystem designs. Figure 11-5 and Figure 11-6 show a system with a single SGRAM chip; the others show a variety ofSDRAM-based systems.
Figure 11-5. Schematic of a 1-MB memory system consisting of one 2 ×128K×32 SGRAM.
GND
0 pF
DQ[31:0]
TM1100
DQM[3:0]
CLK
Address
Control
CS# DSF
2×128K×32SGRAM
MM
_CS
[3:0
]
RA
S, C
AS
, WE
#
MM
_A[1
1:0]
MM
_CLK
[1:0
]
MM
_DQ
[31:
0]
MM
_DQ
M[3
:0]
MA
TC
HO
UT
MA
TC
HIN
GND
MM_CS#[0]
MM_CLK[0]
0 Ω
22 Ω
File: memsys.fm5, modified 7/24/99 PRELIMINARY INFORMATION 11-9
TM1100 Preliminary Data Book Philips Semiconductors
Figure 11-6. Schematic of a 2-MB memory system consisting of one 2 ×256K×32 SGRAM.
GND
0 pF
DQ[31:0]
DQM[3:0]
CLK
Address
Control
CS#
2×256K×32SGRAM
MM
_CS
[3:0
]
RA
S, C
AS
, WE
#
MM
_A[1
1:0]
MM
_CLK
[1:0
]
MM
_DQ
[31:
0]
MM
_DQ
M[3
:0]
MA
TC
HO
UT
MA
TC
HIN
MM_CS#[0]
MM_CLK[0]
0 Ω
22 Ω
GND
DSF
TM1100
Figure 11-7. Schematic of a 4-MB memory system consisting of two 2 ×512K×16 SDRAM chips.
GND
0 pF
DQ[15:0]
UDQM
CLK
Address
Control LDQM
CS#
2×512K×16SDRAM
MM
_CS
[3:0
]
RA
S, C
AS
, WE
#
MM
_A[1
1:0]
MM
_CLK
[1:0
]
MM
_DQ
[31:
0]
MM
_DQ
M[3
:0]
MA
TC
HO
UT
MA
TC
HIN
MM_CS#[0]
MM_CLK[1]
MM_DQM[2]
MM_DQM[3]
MM_DQ[31:16]
DQ[15:0]
UDQM
CLK
Address
Control LDQM
CS#
2×512K×16SDRAM
MM_DQM[0]
MM_DQM[1]
MM_DQ[15:0]
MM_CS#[0]
MM_CLK[0]
22 Ω
0 Ω
TM1100
11-10 PRELIMINARY INFORMATION File: memsys.fm5, modified 7/24/99
Philips Semiconductors SDRAM Memory System
Figure 11-8. Schematic of an 8-MB memory system consisting of four 2 ×1M×8 SDRAM chips.
GND
0 pF
DQ[7:0]
DQM
CLK
Address
Control
CS#
2×1M×8SDRAM
MM
_CS
[3:0
]
RA
S, C
AS
, WE
#
MM
_A[1
1:0]
MM
_CLK
[1:0
]
MM
_DQ
[31:
0]
MM
_DQ
M[3
:0]
MA
TC
HO
UT
MA
TC
HIN
MM_CS#[0]
MM_CLK[1]
MM_DQM[1]
MM_DQM[3]
MM_DQ[31:24]
DQ[7:0]
DQM
CLK
Address
Control
CS#
2×1M×8SDRAM
MM_DQM[0]
MM_DQM[2]
MM_DQ[23:16]
MM_CS#[0]
MM_CLK[1]
DQ[7:0]
DQM
CLK
Address
Control
CS#
2×1M×8SDRAM
DQ[7:0]
DQM
CLK
Address
Control
CS#
2×1M×8SDRAM
MM_DQ[15:8]
MM_DQ[7:0]
MM_CS#[0]
MM_CS#[0]
MM_CLK[0]
MM_CLK[0]
0 Ω
22 Ω
TM1100
File: memsys.fm5, modified 7/24/99 PRELIMINARY INFORMATION 11-11
TM1100 Preliminary Data Book Philips Semiconductors
Figure 11-9. Schematic of an 8-MB memory system consisting of four 2 ×512K×16 SDRAM chips (two ranks)
GND
0 pF
DQ[15:0]
UDQM
CLK
Address
Control
CS#
2×512K×16SDRAM
MM
_CS
[3:0
]
RA
S, C
AS
, WE
#
MM
_A[1
1:0]
MM
_CLK
[1:0
]
MM
_DQ
[31:
0]
MM
_DQ
M[3
:0]
MA
TC
HO
UT
MA
TC
HIN
MM_CS#[1]
MM_CLK[1]
MM_DQM[3]
MM_DQM[3]
MM_DQ[31:16]
DQ[15:0]
UDQM
CLK
Address
Control
CS#
2×512K×16SDRAM
MM_DQM[1]
MM_DQM[1]
MM_DQ[15:0]
MM_CS#[1]
MM_CLK[1]
DQ[15:0]
UDQM
CLK
Address
Control
CS#
2×512K×16SDRAM
DQ[15:0]
UDQM
CLK
Address
Control
CS#
2×512K×16SDRAM
MM_DQ[31:16]
MM_DQ[15:0]
MM_CS#[0]
MM_CS#[0]
MM_CLK[0]
MM_CLK[0]
0 Ω
22 Ω
LDQMMM_DQM[0]
LDQMMM_DQM[2]
LDQMMM_DQM[2]
LDQMMM_DQM[0]
TM1100
11-12 PRELIMINARY INFORMATION File: memsys.fm5, modified 7/24/99
Philips Semiconductors SDRAM Memory System
11.16.1 64 Mbit support
TM1100 provides limited support for 64 Mbit devices: only 4 banks 64 Mbit devices organized in x32 are supported.Figure 11-10 shows detailed schematic for the connections between TM1100 and these SDRAM devices. Up to 4 chipsmay be connected resulting in a maximum of 32 MB system. Note that the method on how to connect one chip (i.e. 8Mbytes system) described in the TM1000 databook is still valid.
GND
0 pF
DQ[31:0]CLK
Address[10:0]
Control DQM[3:0]
CS#
4×512K×32SDRAM
MM
_CS
[1:0
]
MM
_RA
S#,
CA
S#,
WE
#, C
KE
MM
_A[1
0:0]
MM
_CLK
[1:0
]
MM
_DQ
[31:
0]
MM
_DQ
M[3
:0]
MA
TC
HO
UT
MA
TC
HIN
MM_CS#[0]
MM_CLK[1]
MM_DQM[3:0]
MM_DQ[31:0]
DQ[31:0]CLK
Control DQM[3:0]
CS#
MM_DQM[3:0]
MM_DQ[31:0]
MM_CS#[1]
MM_CLK[0]
22 Ω
0 Ω
TM1100
MM
_A[1
1]
4×512K×32SDRAM
BA[1:0]
Figure 11-10. Schematic of a 16 MB memory system consisting of two ranks of 4 ×512K×32 SDRAM chips.
BA[1:0]
MM
_A[1
2]
Address[10:0]
File: memsys.fm5, modified 7/24/99 PRELIMINARY INFORMATION 11-13
TM1100 Preliminary Data Book Philips Semiconductors
11-14 PRELIMINARY INFORMATION File: memsys.fm5, modified 7/24/99
System Boot Chapter 12
by Gert Slavenburg, Bob Bradfield, and Hani Salloum
12.1 NEW IN TM1100
A new bit in the boot EEPROM allows enabling of an in-ternal PCI_CLK clock source for low-cost standalonesystems
12.2 TM1100 BOOT SEQUENCE OVERVIEW
Before a TM1100 system can begin operating, the main-memory interface registers and on-chip clock ratio regis-ter must be configured. Since the DSPCPU cannot beginoperating until after these registers and circuits are ini-tialized, the DSPCPU cannot be relied upon to initializethese resources. Consequently, TM1100 needs an inde-pendent bootstrap facility for the low-level initialization.
TM1100 implements low-level system initialization bycombining a small block of on-chip system boot logic witha single external serial boot EEPROM connected to theI2C interface. See Figure 12-1. Serial EEPROMs with anI2C interface are slow but have the advantages of beingspace-efficient and inexpensive. The amount of informa-tion needed for initial system boot is small, so speed isnot a concern.
The TM1100 system boot block performs differently foreach of the two major types of TM1100 system. Themost significant bit of the tenth byte in the external EE-PROM determines the system boot procedure and mustmatch the system configuration.
In the first type of system, host-assisted bootstrappingtakes place. In this configuration, a TM1100 device is in-
tegrated into a system where some other processorserves as the host. For example, a TM1100 chip mightbe part of a PCI card in a standard personal computer(PC). In this case, the TM1100 system boot need onlyload enough information from the serial EEPROM to con-figure the on-chip timing circuits and main-memory inter-face; the host processor can perform all other TM1100setup chores.
In the second type of system, autonomous bootstrappingtakes place. In this configuration, a TM1100 deviceserves as the host (main) processor; consequently, theTM1100 system boot must perform more work. In addi-tion to configuring on-chip timing and the main-memoryinterface, the system boot must set the base addressesof the main-memory and MMIO address apertures andload into main memory a level 1 bootstrap program forthe DSPCPU.
Only the first ten bytes of the serial EEPROM are neededwhen TM1100 is not the host PCI processor; thus, suchsystems can use a very low-cost 128-byte EEPROM de-vice. When TM1100 serves as the system’s host proces-sor, the boot logic permits almost 2K bytes of storage forFigure 12-1. The system boot logic uses the I2C in-
terface to access a serial EEPROM that contains main-memory and system timin g information.
4.7K
Ω
TM1100
System Boot Block
I2C Interface SerialEEPROM
SCL
SDA
4.7K
Ω
Vdd
Table 12-1. System Boot Features
Characteristic Comments
Boot Configurations Supported
• Host assisted, e.g., TM1100 is a PCI slave in a standard PC.
• Autonomous, e.g., TM1100 is the host PCI processor.
ROM Device Types Supported
• Single standard I2C serial EEPROMs from 128 bytes to 2K bytes in size.
• EEPROMs connect via the tm1100’s built-in two-wire I2C inter-face.
• The use of EEPROMs with hard-ware Write Protect (WP) is recom-mended. A jumper on WP allows user control over in-system repro-gramming using the I2C interface.
• The EEPROM must respond to I2C device address 1010.
ROM size • From 128 bytes to 2K bytes (one device) for initial program load.
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the level 1 bootstrap DSPCPU program in a single eight-pin EEPROM device.
12.3 BOOT HARDWARE OPERATION
The TM1100 boot sequence begins with the assertion ofthe reset signal TRI_RESET#. After reset is de-asserted,only the system boot block, I2C, and PCI interfaces areallowed to operate. In particular, the DSPCPU and the in-ternal data highway bus will remain in the reset state untilthey are explicitly released during the boot procedure. Inautonomous boot, the system boot block is responsiblefor releasing the DSPCPU and highway from reset. Inhost-assisted boot, the boot logic releases the highwayfrom reset and the TM1100 software driver (which runson the host processor) releases the DSPCPU from reset.
The system boot block operation is illustrated in a flowchart shown in Figure 12-2.
12.3.1 Boot Procedure Common to Both Autonomous and Host-Assisted Bootstrap
There should be no other I2C master active from resetuntil boot EEPROM load completes. The system bootprocedure begins by loading a few critical pieces of infor-mation from the serial EEPROM. This part of the proce-dure is common to both autonomous and host-assistedbootstrapping. See Table 12-2 for a summary andTable 12-5 for full bit accurate EEPROM layout details.
The first byte of the EEPROM is read using a serial clockequal to BOOT_CLK/1000, which is guaranteed to beless than 100 kHz. After reading the first byte, which con-tains the actual BOOT_CLK rate as well as the EEPROMspeed capability, the boot block proceeds to read subse-quent bytes at the highest valid speed.
The number of lines in the EEPROM device should be 0in case of a 128 byte device and 1 for larger devices.
The SDRAM aperture size should be set to the smallestsize that is larger than or equal to the actual size ofSDRAM connected to tm1100. The SDRAM aperturesize information is forwarded to the PCI interface for usein host BIOS configuration, as described in Section12.4.2, “Stage 2: Host-System PCI Configuration.”
The BOOT_CLK speed bits should be set to match theclosest rounded up frequency of the external clock cir-cuit, i.e. for an external clock of 40 MHz or 50 MHz thevalue should be 10. This field, together with the EE-PROM maximum clock speed bit are used to decide thebest possible divider ratio for generation of the I2C clock,as shown in Table 12-3. In addition, the delay actions inFigure 12-2 are taken based on the specifiedBOOT_CLK value.
The EEPROM maximum clock speed bit is set to matchthe speed grade of the serial EEPROM device.
The test mode bit should always be set to 0. It is only setto one for factory ATE testing.
The Subsystem ID and Subsystem Vendor ID data hasno meaning to the TM1100 hardware; its meaning is en-
Table 12-2. Information Loaded During First Part of Bootstrapping Procedure
Information Size Interpretation
Number of lines in EEPROM device
1 bit 0 128 lines
1 256 or more lines
SDRAM aperture size 3 bits 000 1 MB
001 1 MB
010 2 MB
011 4 MB
100 8 MB
101 16 MB
110 32 MB
111 64 MB
BOOT_CLK speed 2 bits 00 100 MHz
01 75 MHz
10 50 MHz
11 33 MHz
I2C clock speed 1 bit 0 100 KHz
1 400 KHz
Test mode 1 bit 0 normal operation
1 rapid ATE testing
Subsystem ID 16 bits Value is copied to Sub-system ID register in PCI configuration space.
Subsystem Vendor ID 16 bits Value is copied to Sub-system Vendor ID regis-ter in PCI config space.
MM_CONFIG register initialization
20 bits Value is simply written to the MM_CONFIG regis-ter; see Section 11.5.1, “MM_CONFIG Register.”
PLL_RATIOS register initialization
8 bits Value is simply written to the PLL_RATIOS regis-ter; see Section 11.5.2, “PLL_RATIOS Register.”
Autonomous/host-assisted boot
1 bit 0 host-assisted
1 autonomous
Enable internal PCI_CLK
1 bit
0 PCI_CLK taken from outside
1 use on-chip XIO PCI_CLK clock generatorNote: MUST be set if no external PCI clock is supplied
Table 12-3I2C speed as a function of EEPROM byte 0
BOOT_CLKbits
EEPROMspeed bit
dividervalue
actual I2Cspeed
00 (100 MHz) 0 (100 kHz) 1008 99.2 kHz
00 1 (400 kHz) 256 390.6 kHz
01 (75 MHz) 0 (100 kHz) 752 99.7 kHz
01 1 (400 kHz) 192 390.6 kHz
10 (50 MHz) 0 (100 kHz) 512 97.6 kHz
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Philips Semiconductors System Boot
tirely software defined. The value is loaded by the sys-tem boot block from the EEPROM and published in thePCI configuration space register at offset 0x2C to pro-vide the 16 bit Subsystem ID and Subsystem Vendor IDvalues. These values are used by driver software to dis-tinguish the board vendor and product revision informa-tion for multiple board products based on the TM1100chip. Refer to Section 10.6.12, “Subsystem ID, Sub-system Vendor ID Register,” for more information on thechoice of values.
The MM_CONFIG and PLL_RATIOS registers controlthe hardware of the main-memory interface and TM1100on-chip clock circuits. These registers are described indetail in Section 11.5, “Memory System Programming.”The boot value should be set to reflect the exact capabil-ities of the actual SDRAM in the system.
The ‘enable internal PCI_CLK generator’ bit determinesthe PCI_CLK pin operating mode. If a ‘0’ is present in thisbit, PCI_CLK acts compatible with TM1000 and normalPCI operation, i.e. it is an input pin that takes PCI clockfrom the external world. If a ‘1’ is present in this bit, an on-chip clock divider in the XIO logic becomes the source ofPCI_CLK, and the PCI_CLK pin is configured as an out-put. In the latter case, the PCI_CLK frequency can beprogrammed to a divider of the TM1100 highway clockby setting the XIO_CTL register ‘Clock Frequency’ divid-er value. Refer to Chapter 21, “PCI-XIO External I/OBus.” Note: This bit must be set if no external PCI clockis supplied.
The autonomous/host-assisted boot bit determineswhether the system boot logic will continue reading moreinformation from the EEPROM or halt its operation so thehost can complete system initialization. After the infor-mation listed in Table 12-2 has been loaded into TM1100registers, an external PCI host processor can finish theinitialization of tm1100. If no external PCI host processoris present, the autonomous/host-assisted boot bit shouldbe set to one to allow the system boot logic to load theinformation described in the next section.
10 1 (400 kHz) 128 390.6 kHz
11 (33 MHz) 0 (100 kHz) 336 98.2 kHz
11 1 (400 kHz) 96 343.8 kHz
Table 12-3I2C speed as a function of EEPROM byte 0
BOOT_CLKbits
EEPROMspeed bit
dividervalue
actual I2Cspeed
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TRI_RESET#de-asserted
8-bit serial read:1 bit: EPROM capacity
3 bits: DRAM aperture size2 bits: TM1100 clock speed
1 bit: I2C clock rate1 bit: Test mode control
Write to EEPROMsize register
Write aperture size to DRAM_ROUND_SIZEsize register in PCI BIU
Write to TM1100 clock speed register
32-bit serial read
Write toSUBSYSTEM ID
registers in PCI BIU
Write 20 bits to MM_CONFIGregister in MMI
Write toPLL_RATIOSregister in MMI
Disable MMI_RESET
to activate highway
AutonomousBoot
YesNo
System boot halts(Host driver will complete
the boot procedure)
Save 11-bitbyte count
Write toMMIO space:MMIO_BASE
Write toMMIO space:DRAM_BASE
Write toMMIO space:
DRAM_CACHEABLE_LIMIT
Bytecount == 0 YesNo
Write to SDRAMWrite 32 bits of code onto highway
with all byte enables active.Then execute 15 dummy writes on
highway to meet MMI protocol.
Decrement byte count by four
Write to MMIO space:Disable CPU_RESET.
DSPCPU starts execution atDRAM_BASE in big-endian mode.
System boot halts
24-bit serial read
8-bit serial read
8-bit serial read
64-bit serial read
8-bit serial read
64-bit serial read
64-bit serial read
32-bit serial read
32-bit serial readWait 400 usec for
PLLs to lock
Wait ca. 0.6 msec forI2C to stabilize
Figure 12-2. Flow chart of system boot procedure for both host-assisted and autonomous configurations.
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12.3.2 Initial DSPCPU Program Load for Autonomous Bootstrap
In a system where TM1100 serves as the host CPU, thesystem boot block performs an autonomous boot proce-dure. For an autonomous boot, the system boot blockreads all the information described in Section 12.3.1,“Boot Procedure Common to Both Autonomous andHost-Assisted Bootstrap,” and then—because the au-tonomous boot bit is set—continues reading informationfrom the EEPROM. After this part of the system boot pro-cedure is done, the DSPCPU starts executing. SeeTable 12-4.
The DSPCPU bootstrap program byte count encodes thenumber of bytes of DSPCPU program code contained inthe EEPROM(s). This eleven-bit unsigned byte countcan encode up to 2048 bytes, which is also the maximumamount of EEPROM storage supported. The actualamount of EEPROM available for the DSPCPU boot-strap program is limited to 2000 bytes because the otherinformation consumes 47 bytes and the DSPCPU codemust be an integral number of 32-bit words.
Four pairs of 32-bit MMIO-register addresses and valuesfollow the bootstrap program byte count. Each addresstells the boot block where in the 32-bit DSPCPU addressspace to store the corresponding 32-bit value.
The first pair initializes the MMIO_BASE. TheMMIO_BASE sets the base address of the 2-MB MMIO-register address aperture within the DSPCPU 32-bit ad-dress space. All MMIO registers are addressed using anoffset that is relative to the value of MMIO_BASE. Forthis pair, the address is required to be 0xEFF00400 be-cause that is the default MMIO_BASE enforced whenTM1100 is reset. The new value for MMIO_BASE is en-coded in the corresponding value.
The DRAM_BASE address/value pair determine thebase address of the SDRAM address aperture within the32-bit DSPCPU address space. The address must beequal to 0x100000 plus the new value of MMIO_BASEset previously in the boot procedure. The DRAM_BASEvalue must be naturally aligned given the rounded DRAMaperture size, i.e. a 6 MByte DRAM aperture should starton a 8M address multiple.
The DRAM_LIMIT address/value pair determine the ex-tent of the SDRAM address aperture. The address mustbe equal to 0x100004 plus the new value ofMMIO_BASE set previously in the boot procedure. Thevalue in DRAM_LIMIT should be 1 higher than the ad-dress of the last valid byte of SDRAM memory, and mustbe a 64 kByte multiple.
The DRAM_CACHEABLE_LIMIT address/value pair de-termine the extent of the cacheable aperture of theSDRAM address space. The address must be equal to0x100008 plus the value of MMIO_BASE set previouslyin the boot procedure. The cacheable aperture alwaysbegins at the address value in DRAM_BASE; the valuein DRAM_CACHEABLE_LIMIT is one higher than theaddress of the last byte of cacheable SDRAM memory,and must be a 64 kByte multiple. It is safe to initially setthe value of DRAM_CACHEABLE_LIMIT equal to
DRAM_LIMIT. The RTOS can, if desired, change the val-ue later.
The next 32-bit value in boot EEPROM memory is a copyof the DRAM_BASE value encoded previously. The sys-tem boot hardware loads the DSPCPU bootstrap pro-gram into SDRAM starting at DRAM_BASE.
The bytes of the DSPCPU bootstrap program follow thecopy of the SDRAM_BASE value. The bootstrap pro-
Table 12-4. Information Loaded During Second Part of Bootstrapping Procedure for Autonomous Boot
Information Size Interpretation
DSPCPU bootstrap pro-gram byte count n
11 bits up to 500 32-bit words (2048 bytes less 47 header bytes)
MMIO_BASE address 32 bits Value must be 0xEFF00400
MMIO_BASE value 32 bits Value is simply written to 0xEFF00400 to determine new base address of 2-MB MMIO register aperture within 32-bit DSPCPU address space
DRAM_BASE address 32 bits MMIO_BASE + 0x100000
DRAM_BASE value 32-bits
Value is simply written to DRAM_BASE to determine base address of SDRAM aperture within 32-bit DSPCPU address space
DRAM_LIMIT address 32-bits
MMIO_BASE + 0x100004
DRAM_LIMIT value 32-bits
Value is simply written to DRAM_LIMIT to deter-mine limit address of SDRAM aperture within 32-bit DSPCPU address space
DRAM_CACHEABLE_LIMIIT address
32-bits
MMIO_BASE + 0x100008
DRAM_CACHEABLE_LIMIT value
32-bits
Value is simply written to DRAM_CACHEABLE_LIMIT to determine limit address of cacheable part of SDRAM aperture within 32-bit DSPCPU address space
DRAM_BASE value 32-bits
Copy of the DRAM_BASE; must be equal to value specified above
SDRAM code word 0 32-bits
First 32-bit word of initial DSPCPU bootstrap pro-gram
SDRAM code word 1 32-bits
Second 32-bit word of ini-tial DSPCPU bootstrap program
.
.
.
.
.
.
.
.
.
SDRAM code word n/4 32 bits Last 32-bit word of initial DSPCPU bootstrap pro-gram
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gram can consist of up to 500 32-bit words of DSPCPUinstructions. The byte count must be a multiple of four.Note that the bytes are stored in the EEPROM in a byteswapped order per group of 4 compared to SDRAM, asdetailed in Table 12-5.
After the entire DSPCPU bootstrap program is loadedinto SDRAM at DRAM_BASE, the system boot logic re-leases the DSPCPU from the reset state. At this point,the DSPCPU begins executing the bootstrap programstarting at DRAM_BASE and TM1100 is fully operation-al. At the same time, the boot logic releases the I2C in-terface.
12.4 HOST-ASSISTED BOOT DESCRIPTION
For a host-assisted bootstrap, the complete bootstrapprocess consists of three distinct stages, but the systemboot hardware performs only the first stage. The othertwo stages are the responsibility of the host system.
12.4.1 Stage 1: TM1100 System Boot Hardware
In the first stage, the TM1100 hardware must be initial-ized enough to allow the host system to query and ma-nipulate TM1100 resources. The system boot hardware,using the procedure described above in Section 12.3.1,“Boot Procedure Common to Both Autonomous andHost-Assisted Bootstrap,” initializes the Subsystem ID,Subsystem Vendor ID, MM_CONFIG, and PLL_RATIOSregisters, waits for the PLLs to lock, enables the internalhighway and main-memory interface (MMI), but leavesthe DSPCPU in the reset state. After this minimal initial-ization, the host system can finish the bootstrap process.
At the completion of stage 1, the TM1100 hardware isready to respond to PCI configuration space accesses,and the boot block has released the I2C interface.
12.4.2 Stage 2: Host-System PCI Configuration
Stage 2 is carried out either by the host-system PCIBIOS or by a combination of the BIOS and the host op-erating system (e.g., Windows 95). During this stage, thehost system configures all PCI-bus clients.
The PCI-bus configuration consists of querying the busclients to determine the following:
• The number of PCI base-address registers imple-mented by each client. For tm1100, the number ofPCI base-address registers is always two(MMIO_BASE and DRAM_BASE).
• The size of each aperture associated with the base-address registers. For tm1100, the size of the MMIOaperture is always 2 MB, while the size of theSDRAM aperture can be from 1 MB to 64 MB withthe constraint that the size must be a power of two(seven distinct sizes).
Using this information, the host system relocates eachaddress aperture to eliminate overlaps in the PCI ad-dress space. The host system accomplishes the reloca-tion by considering each apertures size and then writingan appropriate starting address to each base-addressregister. For tm1100, the base addresses of the MMIOand SDRAM apertures must be relocated in this way.Note that in the case of autonomous boot, this relocationis done statically by the system boot hardware when itsimply copies the values of MMIO_BASE andDRAM_BASE from the serial EEPROM into these regis-ters.
The steps of the PCI protocol for determining the size ofan address aperture are as follows (see Section 10.6.11,“Base Address Registers,” for a more complete discus-sion):
• The host writes a 32-bit word of all ones (0xffffffff) tothe base-address register.
• The host reads the base-address register immedi-ately after the write. The value returned will havezeros in all don’t-care bits and ones in all requiredaddress bits. The required address bits form a left-aligned (i.e., starting at the most-significant bit) con-tiguous field of ones.
• This left-aligned field of ones effectively specifies thesize of the address aperture by indicating the bits ofthe base-address register that are significant for relo-cation. That is, an address aperture of size 2n canonly begin on a 2n-byte-aligned boundary.
As an example, consider the case of the MMIO aperture.The host will perform the following steps during stage 2of the bootstrap process:
• Write 0xffffffff to MMIO_BASE.• Read from MMIO_BASE, which returns the value
0xffe00000. The host sees that this value has an 11-bit left-aligned field of ones, which indicates that theaperture can only be relocated on 2-MB boundaries;thus, the aperture size is 2 MB.
• Write a new value to MMIO_BASE with the top 11bits set to relocate the MMIO aperture to a 2-MBregion of PCI address space that does not conflictwith other PCI address apertures.
At the completion of stage 2, the TM1100 hardware isready to respond to host configuration space accesses,host MMIO accesses and host SDRAM aperture access-es. The DSPCPU is still in RESET state.
12.4.3 Stage 3: TM1100 Driver Executing on the Host
During the final stage of the bootstrap process, theTM1100 software driver executing on the host systemwill write to SDRAM a program for the DSPCPU, and setany MMIO registers as it sees fit. When the initial pro-gram load is complete, the driver releases the DSPCPUfrom its reset state by a write to the BIU_CTL registerwith the CR bit set. See Chapter 10, “PCI Interface.”Now, with the DSPCPU and host both running, theTM1100 bootstrap process is complete.
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12.5 DETAILED EEPROM CONTENTS
Table 12-5 shows the serial EEPROM contents neededfor an autonomous boot procedure. For the host-assist-
ed boot procedure, only the contents up to line nine areneeded.
Note that the 32-bit words in the serial EEPROM are notstored on 32-bit word-aligned addresses.
cpu PLL bypass cpu PLL disable sdram ratio cpu ratio[2:0]
9boot type
0: host assist.1: autonomous
enable inter-nal PCI_CLK — — — byte count [10:8]
10 byte count [7:0]
11121314
MMIO_BASE address [31:24] (must be 0xEF)MMIO_BASE address [23:16] (must be 0xF0)MMIO_BASE address [15:8] (must be 0x04)MMIO_BASE address [15:8] (must be 0x00)
15161718
MMIO_BASE value [31:24]MMIO_BASE value [23:16]MMIO_BASE value [15:8]MMIO_BASE value [7:0]
19202122
DRAM_BASE address [31:24] (must be byte 3 of MMIO_BASE + 0x100000)DRAM_BASE address [23:16] (must be byte 2 of MMIO_BASE + 0x100000)DRAM_BASE address [15:8] (must be byte 1 of MMIO_BASE + 0x100000)DRAM_BASE address [7:0] (must be byte 0 of MMIO_BASE + 0x100000)
23242526
DRAM_BASE value [31:24]DRAM_BASE value [23:16]DRAM_BASE value [15:8]DRAM_BASE value [7:0]
27282930
DRAM_LIMIT address [31:24] (must be byte 3 of MMIO_BASE + 0x100004)DRAM_LIMIT address [23:16] (must be byte 2 of MMIO_BASE + 0x100004)DRAM_LIMIT address [15:8] (must be byte 1 of MMIO_BASE + 0x100004)DRAM_LIMIT address [7:0] (must be byte 0 of MMIO_BASE + 0x100004)
31323334
DRAM_LIMIT value [31:24]DRAM_LIMIT value [23:16]DRAM_LIMIT value [15:8]DRAM_LIMIT value [7:0]
35363738
DRAM_CACHEABLE_LIMIT address [31:24] (must be byte 3 of MMIO_BASE + 0x100008)DRAM_CACHEABLE_LIMIT address [23:16] (must be byte 2 of MMIO_BASE + 0x100008)DRAM_CACHEABLE_LIMIT address [15:8] (must be byte 1 of MMIO_BASE + 0x100008)DRAM_CACHEABLE_LIMIT address [7:0] (must be byte 0 of MMIO_BASE + 0x100008)
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39404142
DRAM_CACHEABLE_LIMIT value [31:24]DRAM_CACHEABLE_LIMIT value [23:16]DRAM_CACHEABLE_LIMIT value [15:8]DRAM_CACHEABLE_LIMIT value [7:0]
43444546
repeat of DRAM_BASE value [31:24]repeat of DRAM_BASE value [23:16]repeat of DRAM_BASE value [15:8]repeat of DRAM_BASE value [7:0]
47484950
byte 0 of DSPCPU bootstrap program (stored at DRAM_BASE + 3)byte 1 of DSPCPU bootstrap program (stored at DRAM_BASE + 2)byte 2 of DSPCPU bootstrap program (stored at DRAM_BASE + 1)byte 3 of DSPCPU bootstrap program (stored at DRAM_BASE + 0)
.
.
.
.
.
.
j+47 byte j of DSPCPU bootstrap program (stored at DRAM_BASE + ((j div 4) + (3 – (j mod 4))))
.
.
.
.
.
.
(n–1)+47 last byte of DSPCPU bootstrap program (bits [7:0] of last 32-bit word, stored at DRAM_BASE + n – 4)
Table 12-5. Serial Boot EEPROM Contents
LineData Byte
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
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12.6 EEPROM ACCESS PROTOCOLS
Figure 12-3 shows the SDA (serial data) line protocolsfor three types of read accesses supported by I2C serialEEPROMs. A read from the address currently latched in-side the EEPROM can be for either a single byte or foran arbitrary series of sequential bytes. The mastermakes the choice by setting the ACK bit after a byte hasbeen transferred.
A random-access read is accomplished by performing adummy write, which overwrites the latched addressstored inside the EEPROM. Once the internal addresslatch is set to the desired value, one of the other two readprotocols can be used to read one or more bytes.
The boot logic inside TM1100 uses a single random readtransaction to location 0 of device address 1010000 fol-lowed by a sequential read extension to read all requiredEEPROM bytes in a single pass.
SDA Line Protocol:Random Read
START
Device Address
WRITE
WA7
WA6
WA5
WA4
WA3
WA2
WA1
WA0 1 0 1 0
A0
P1
P0
D7
D6
D5
D4
D3
D2
D1
D0
START
READ
STOP
ACK
ACK
ACK1 0 1 0
DA0
PA0
PA0
NO
ACK
Device Address
Dummy Write
1 0 1 0A0
P0
P0
START
READ
STOP
ACK
ACK
Device Address
D7
D6
D5
D4
D3
D2
D1
D0
NO
ACK
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
ACK
D7
D6
D5
D4
D3
D2
D1
D0
ACK
SDA Line Protocol:Sequential Read
Data n Data n+1 Data n+2 Data n+3
1 0 1 0A0
P0
P0
START
READ
ACK
NO
ACK
D7
D6
D5
D4
D3
D2
D1
D0
SDA Line Protocol:Current-Address Read
Data n
Device Address
STOP
Figure 12-3. EEPROM access methods. In the diagrams, a label is shown on top of a data bit window to in-dicate the SDA line is driven by the master (TM1100), and a label is shown on the bottom to indicate that the SDA line is driven by the EEPROM.
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Image Co-Processor Chapter 13
13.1 SUMMARY FUNCTIONALITY
The Image Co-Processor (ICP) connects to the TM1100on-chip data highway to perform SDRAM block read andwrite actions. It also connects to the PCI interface to al-low block write transactions across PCI.
The major functions of the Image Co-Processor are:
• Filter an image by reading the image from SDRAMand writing the image back to SDRAM, while apply-ing a user defined polyphase filter with optional up ordown scaling in horizontal direction.
• Filter an image by reading the image from SDRAMand writing the image back to SDRAM, while apply-ing a user defined polyphase filter with optional up ordown scaling in vertical direction.
• Filter an image and convert it from planar to RGB orYUV composite by reading the image from SDRAMand writing the image out to PCI bus memory (graph-ics card) or SDRAM, while performing horizontalscaling and conversion to one of a several RGB orYUV formats. The user can add optional bitmapmasking to selectively enable/disable pixel writes toPCI (to refresh only the exposed part of a video win-dow) and an optional image overlay with alpha blend-ing and optional chroma keying (PCI output only).
• Move an image by reading the image from SDRAMand writing it back to SDRAM.
All of the Image Co-Processor functions move and trans-form data from memory to memory or memory to the PCIbus. Hence, the DSPCPU can use the ICP in a time-sharing fashion to simultaneously achieve:
1. Vertical and horizontal resizing/subsampling on the stream of images from Video In.
2. Vertical and horizontal resizing/upsampling on the stream of images sent to Video Out.
3. Presentation of a collection of live video windows with programmable up and down scaling and arbitrary overlap configuration on PCI graphics cards.1
Full two dimensional scaling and filtering requires twopasses over the data: one to do horizontal scaling and fil-tering and one to do vertical scaling and filtering.
Figure 13-1 shows a block diagram of the TM1100 withthe Image Co-Processor (ICP). Figure 13-2 shows a
block diagram of the internal structure of the Image Co-Processor. The ICP contains a 5-tap filter, YUV to RGBconverter, an overlay and alpha blending unit, and anoutput formatter. These blocks communicate with eachother and communicate with the TM1100 SDRAM DataHighway through FIFOs. The FIFOs buffer the block datato and from the TM1100 SDRAM Data Highway. The ICPuses a microprogram controlled sequencer to control itsinternal timing. The program for this sequencer is in a ta-ble in SDRAM. The ICP reads the appropriate portionfrom the SDRAM each time the ICP is commanded toperform a function. Microprogram control simplifies andminimizes the ICP hardware and increases the flexibilityof the ICP to do additional tasks without adding hard-ware.
13.2 REQUIREMENTS
13.2.1 Functions
The major functions of the Image Co-Processor are:
1. Read an image from SDRAM and write the image back to SDRAM, while applying a user defined polyphase filter with optional up or down scaling in horizontal direction.
2. Read an image from SDRAM and write the image back to SDRAM, while applying a user defined polyphase filter with optional up or down scaling in vertical direction.
3. Read an image from SDRAM and write the image out to PCI bus memory (graphics card) or SDRAM, while performing horizontal scaling and conversion to one of a several RGB and YUV formats. The PCI output mode includes optional bitmap masking to selectively enable/disable pixel writes to PCI (to refresh only the exposed part of a video window) and optional RGB overlay with alpha blending and optional chroma key-ing.
13.2.2 Bandwidth
The bandwidth for the ICP can be estimated from theworst case image processing bandwidth. If the worstcase image is 1024 x 768 at 30 Hz in YUV 4:2:2 format,the pixel rate is 1024 x 768 x 30 = 23.59 megapixels persecond. For YUV 4:2:2 image coding at 2 bytes per pixel,this is 23.59 x 2 = 47.19 megabytes per second. The min-imum bandwidth for the ICP function is therefore 47.18megabytes per second, or approximately 50 megabytesper second.
1. Note that function 2 and 3 don’t normally occur simulta-neously, and if an application attempts both simulta-neously, some performance limitations are incurred.
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Video DMA In
Audio DMA In
Audio DMA Out
DSPCPU400 MIPS2.5 GOPS
I$
D$
I2C intf
ImageCo-Processor
TM1100MemoryController
PCI Master/Slave Interface
VLD Assist
Video Out
Digital
DMSDor Raw
Video
SerialDigitalAudio
JTAG
Clock
PCI Local Bus
SDRAM
SDRAMHighway
SSI
Camera
Figure 13-1. TM1100 Chip Block Diagram
FIFOBank
5-tapFilter
Microprogram Control Unit
To P
CI
Y
U
V
Overlay
Bit Mask
To SDRAM
Microcode
Ove
rlay
+
Alp
ha B
lend
ing
+
Chr
oma
Key
ing
YU
V =
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vers
ion
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B
it M
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Image Co-Processor
Overlay
Bit Mask
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TM
1100
SD
RA
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ata
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hway
Figure 13-2. Image Co-Processor Block Diagram
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Scaling and filtering of the two dimensional image re-quires two passes of the image data through the filter,one for vertical and one for horizontal. Scaling an imageand sending it to the PCI bus requires three transfers ofthe image over the SDRAM bus: one transfer to read theimage for vertical filtering, one transfer to write the fil-tered data back, and one transfer to read the image forhorizontal filtering and output to the PCI bus. This meansan average of SDRAM bus bandwidth of 3 x 50 = 150megabytes/second for the 1024 x 768 image case de-scribed above, assuming a scaling factor of 1.0. A largeror smaller scaling factor means that either the input oroutput image will be smaller than 1024 x 768. The band-widths required are determined by the larger of the twoimages, input or output. This is because all input pixelsmust be scanned to generate all the output pixels. Scal-ing and filtering the image back to the SDRAM requiresan additional transfer to write the horizontally filtered im-age back to SDRAM.
13.2.3 Image Size and Scaling
Image sizes in the TM1100 have a nominal range of 16x 16 to 1024 x 768. Sizes smaller than 16 x 16 are pos-sible, but are too small to be recognizable images. Imag-es larger than 1024 x 768 (up to 64K x 64K) are possiblebut cannot be processed in real time. They also requirelarger SDRAM size to support them. Scaling factors havea nominal range of 1/4 (down scaling by 4) to 4 (upscal-ing by 4). Larger up and down scaling factors are possi-ble, up to 1000 and beyond; however, very large upscal-ing factors result in a large magnification of a few pixels,and very large down scaling factors give only a few pixelsas a result.
13.3 INTERFACE
The Image Co-Processor block has no TM1100 externalpins. It interfaces internally to the SDRAM Data Highwayand the PCI output.
13.4 DATA FORMATS
The Image Co-Processor block accepts input and over-lay image data to generate output image data. The ICPaccommodates a variety of formats for the input, overlayand output data. These image data formats define the re-lationship between the Y, U and V or the R, G, and Bcomponents of the image as they are stored in memory.The ICP accepts input image data in planar format,where the Y, U and V components are in separate tablesin SDRAM. The various input image data formats differin the position of the U and V components relative to theY component and the amount of U and V data relative tothe Y data.
In all modes except the YUV to RGB conversion modes,each ICP operation processes one Y, U or V image com-ponent. Three separate commands are required to pro-cess all three components of an image. Since each com-ponent is scaled and filtered separately, the calling
software defines the image format and format conversionby how it scales each component.
In the YUV to RGB conversion to PCI output or SDRAMoutput mode, each output pixel is a combination of RGBor YUV components as defined by the output format. TheYUV input data and the RGB or YUV overlay data arecombined by the ICP hardware pixel by pixel to form theRGB or YUV output pixels. Because all three YUV com-ponents are simultaneously woven together to createeach output pixel, the ICP hardware must know the im-age data format in SDRAM, defined as how the compo-nents of the image data are to be found and combined.
In the YUV to RGB conversion mode, the ICP acceptsthe following input data formats: YUV 4:2:2 co-sited,YUV 4:2:2 interspersed and YUV 4:2:0. In the YUV toRGB conversion mode, the ICP also accepts imageoverlay data when PCI output is specified. The ICP ac-cepts image overlay data in several combined formats:RGB-24+α, RGB15+α and YUV 4:2:2+α. In this mode,the ICP generates RGB or YUV output data in severalRGB and YUV formats. These formats are compatiblewith a wide variety of PCI frame buffers.
13.4.1 Image Input Formats
The ICP image input formats define the relative positionsof the Y component and the U and V components of theinput image pixel data. There are three input formats tothe ICP: 4:2:2 co-sited, 4:2:2 interspersed, and 4:2:0 in-terspersed. The 4:2:2 formats have 2 U and 2 V pixels forevery 4 Y pixels, so the ratio of Y to U or V is 2:1. The4:2:0 format has 1 U and 1 V pixel for every 4 Y pixels,so the ratio of Y to U or V is 4:1. The input formats aregiven below. The input formats have a significant impacton the 2 dimensional scaling operation.
13.4.1.1 YUV 4:2:2 Co-Sited
In the YUV 4:2:2 co-sited format, the U and V pixels co-incide with the Y pixel on every other pixel, as shown inFigure 13-3.
13.4.1.2 YUV 4:2:2 Interspersed
In the YUV 4:2:2 interspersed format, the U and V pixelslie between the Y pixels on every other pixel of the hori-zontal line, as shown in Figure 13-4.
13.4.1.3 YUV 4:2:0 XY Interspersed
In the YUV 4:2:0 interspersed format, the U and V pixelslie between the Y pixels on every other pixel of the hori-zontal line, as shown in Figure 13-5.
13.4.1.4 YUV 4:1:1 Co-Sited
In the YUV 4:1:1 co-sited format, the U and V pixels co-incide with the Y pixel on every fourth pixel, as shown inFigure 13-6.
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Figure 13-3. 4:2:2 Co-Sited Input Format
Chrominance (U,V) samples
Luminancesamples
Figure 13-4. 4:2:2 Interspersed Input Format
Chrominance (U,V) samples
Luminancesamples
Figure 13-5. 4:2:0 XY Interspersed Input Format
Chrominance (U,V) samples
Luminancesamples
Figure 13-6. 525-60 YUV 4:1:1 Co-Sited Input Format
Chrominance (U,V) samples
Luminancesamples
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13.4.2 Image Overlay Formats
The ICP accepts image overlay data in three formats,RGB-24+α, RGB-15+α and YUV-4:2:2+α as shown inTable 13-1. The overlay image format must be the sametype as the output image format generated by the ICP forthe main image. If the output image is one of the RGBformats, the overlay must be one of the two RGB overlayformats, RGB-24-α and RGB-15+α. If the output imageformat is YUV, the overlay format must be in YUV-4:2:2+α format. The formats must be of the same typebecause the ICP does no conversion on the overlay da-ta.
In RGB-24+α, a full byte of alpha information is includedwith each pixel. In RGB-15+α, one bit of alpha is includedfor each pixel. The pixels are packed as 2 pixels perword, and the alpha bit is the most significant bit of eachpixel. In the same manner, the YUV-4:2:2+α formatpacks two pixels into one word, and it has one bit of alphafor each pixel. The least significant bit (LSB) of the U andV components supplies the alpha bit for the Y0 and Y1pixels, respectively. The alpha bit in these formats se-lects between two alpha values stored in the ICP, alpha1 and alpha 0. The alpha 1 and alpha 0 values are loadedfrom the parameter block when the ICP is started.
13.4.3 Alpha Blending Codes
Image overlay uses alpha blending, which combines theoverlay image with the main image according to the al-pha value. The alpha value is supplied by the alpha bytein RGB 24+α format and by the alpha registers, Alpha 0and Alpha 1 in the other formats. The alpha code formatis shown in Table 13-2.
13.4.4 Output Formats
The output formats are the RGB image formats sent tothe PCI interface or SDRAM. These formats are shownin Table 13-3. Note: B1 = Byte 1 of blue = [b7...b0]1.
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13.5 ALGORITHMS
13.5.1 Introduction
The ICP provides filtering, resizing (scaling) and YUV toRGB conversion of the source image. Filtering providesimage enhancement. Scaling generates a new imagethat is larger or smaller than the current image. YUV toRGB conversion is used to generate an RGB version ofthe image for output to an RGB format frame bufferthrough the PCI interface or to SDRAM.
The filtering, scaling and YUV to RGB conversion algo-rithms are discussed separately. The ICP uses these al-gorithms in two ways.
1. It provides one pass horizontal scaling with horizontal 5-tap filtering of Y, U, or V.
2. It provides one pass vertical scaling with vertical 5-tap filtering of Y, U, or V.
13.5.2 Filtering
The ICP provides high quality, 5-tap polyphase filtering,both horizontal and vertical. Horizontal and vertical filter-ing are done in separate passes as one dimensional fil-ters. Two dimensional filtering of the image requires twopasses of the one dimensional filters.
Multi-tap FIR Filtering
In multi-tap FIR filtering of an image, the new filter output(pixel) value is a weighted sum of adjacent pixels. Theweighting coefficients determine the type of filteringused. A 5-tap filter generates the new pixel value as aweighted sum of the current value and the two pixels oneither side (2 left and 2 right for horizontal filtering, 2above and 2 below for vertical).
A multi-tap FIR filter can be used to generate values fornew pixels that are displaced from the original (“center”)pixel in the same way as linear interpolation. Assumingthe new pixel location is shifted slightly to the right of thecenter pixel of the input image. Then a horizontal filtercan be used to estimate the new pixel value by weightingthe right pixel filter coefficients more heavily than the left,proportional to the relative position offset of the new pix-el. (In this sense, interpolation is a 2-tap filter.) This isshown in Figure 13-7. The ICP horizontal and vertical fil-ter operations use this method to combine scaling withfiltering.
Mirroring Pixels at the Start and End of a Line or Window
A line may start and/or end at the edge of the input im-age. In this case, the two start and/or end pixels neededfor the first and last pixels of the line, respectively, aremissing. The ICP uses pixel mirroring to solve this prob-lem. In pixel mirroring, the two available pixels are usedto substitute the two missing pixels. The first pixel, usescopies of the two pixels to the right as though they werethe two pixels to the left. Specifically, P+2 substitutes forP-2, and P+1 substitutes for P-1. The last pixel, usescopies of the two pixels to the left as though they werethe two pixels to the right. Since the left and right pixelsare now the same, this is called pixel mirroring.
There are five states of pixel mirroring: first output pixel,second output pixel, middle pixels, next to last output pix-el and last output pixel. The first output pixel uses pixelsnumbered (2,1,0,1,2). The second pixel uses (1,0,1,2,3).The middle pixels use (P-2, P-1, P, P+1, P+2). The nextto last pixel uses (N-3, N-2, N-1,N, N-1), where N is thenumber of the last input pixel. The last pixel uses (N-2,N-1, N, N-1, N-2).
In some cases of upscaling, one more input pixel may beneeded at the end of the line. That cannot be generatedby the mirror logic. In this case, the ICP uses a copy ofthe last output pixel as the best estimate of the requiredoutput pixel. The mirroring logic which detects the lastpixels in the input line also detects this case, and it cre-ates copies of the last pixel generated by preventing anyfurther scaling action (data shifting and scaling counterincrementing) once the end of the input line has beenreached.
13.5.3 Scaling
Scaling Overview
Resizing, or scaling the image means generating a newimage that is larger or smaller than the original. The newimage will have a larger or smaller number of pixels in thehorizontal and/or vertical directions than the original im-age. A larger image is scaling up (more new pixels); asmaller image is scaling down (fewer newer pixels). Asimple case is a 2:1 increase or decrease in size. A 2:1decrease could be done by throwing away every otherpixel (although this simple method results in poor imagequality). A 2:1 increase is more interesting. The new pix-els can be generated in between the old ones by:
Input Pixels
Output Pixels
Filter (uses 5 input pixels)
Interpolation (uses 2 input pixels)
Figure 13-7. Pixel Generation by Interpolation and Filtering
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1. Duplicating the original pixels2. Linear interpolation, where the new in-between pixels
are the weighted average of the adjacent input pixels3. Multi-tap filtering, where the new in-between pixels
are multi-pixel filtered version of the adjacent input pixels. This approach results in the best image.
The more general case is where the output image is notan integral multiple of sub-multiple of the input image,such as converting from 640 x 480 to 1024 x 768. In thiscase, the output pixels have differing positions relative tothe input pixels as you move in the horizontal or verticaldimensions. In converting from 640 to 1024, the first out-put pixel on a line corresponds to the first input pixel. Thesecond output pixel is at 640/1024 of the distance be-tween the first and second input pixels. The third outputpixel is at (2*640)/1024 of the distance = 1280/1024 = 1+256/1024 = 256/1024 of the distance between the sec-ond and third input pixels, etc. The output pixels shift withrespect to the input pixel grid as you move along the linein the horizontal or vertical dimensions. This is shown inFigure 13-8.
New pixels are generated by interpolation or filtering ofthe original pixels. Interpolation is the weighted averageof the input pixels adjacent to the output pixel. Filteringextends interpolation to include input pixels beyond theinput pair adjacent to the output pixel. The number of pix-els used to generate the output defines the filter type. In-terpolation is a 2-tap filter. A 4-tap filter would use the twopixels to the left and the two pixels to the right of the out-put pixel. A 5-tap filter identifies the single pixel nearestthe output as the center pixel, and uses this pixel plustwo to the left and two to the right to generate the output.
If the ratio of the output pixel count per line (in H or V) toinput pixel count per line is the ratio of small integers, youhave a repeating pattern in these relative positions of in-put to output pixel locations. For 640 to 1024, the ratio is8/5. The pattern repeats for every 8 output and every 5input pixels. If the ratio is not a ratio of small integers, thepattern will take a long time to repeat. The worst casewould be 640 to 641, for example. There would be no ex-act repetition for the whole line.
The interpolator or filter coefficients must be weightedaccording to the relative position of the new pixel relativeto the old pixels. The weighting factor is between 0.0 and1.0, corresponding to the relative position of the new pix-el with respect to the old pixel grid. With a repeating pat-tern, fewer weighting factors are needed, and thereforefewer coefficients in the linear interpolator or filter gener-
ating the new pixels, since you can reuse them each timethe pattern repeats. A filter with a repeating pattern iscalled polyphase, indicating a repeating pattern in thephase (offset position) of the output pixels relative to theinput pixels.
Generating the Output Pixels: Relating the Output Grid to the Input Grid
Scaling is a pixel transformation. You generate an arrayoutput pixels from an array of input pixels. The value ofeach pixel on the output pixel grid is calculated from thevalues of its adjacent pixels on the input grid. To findthese adjacent pixels, you overlay the output grid on theinput grid and align the starting pixels, X0Y0, of the twogrids. To identify the adjacent input pixels for a given out-put pixel, you divide the output pixel X (pixel numberalong the output line) and Y (pixel line number within win-dow) by their corresponding scaling factors:
Note that the resulting Xin and Yin values will be realnumbers, integers plus fractions. This is because theoutput pixels will usually fall between the input pixels.The fractional value indicates the fractional distance tothe next pixel. To calculate the output pixel value, youuse the value for the nearest pixel to the left and aboveand combine it with the value of the other adjacent pix-el(s). For example, horizontal interpolation uses thestarting pixel to the left interpolated with the next pixel tothe right, with the fractional value used to determine theweighting for the interpolation.
ICP Scaling Output Resolution
In the ICP, scaling is forced to have a repeating patternby limiting the resolution of the new pixel position to 1/32;the new position is forced to be at a location n/32 in Hand V relative to the position of the original pixel grid.This results in a worst case error of approximately 1.5%in amplitude relative to calculations using exact outputpixel positions. This is comparable to the errors causedby quantizing the amplitude of the pixels. The additionalquantization noise can be avoided by choosing an appro-priate scale factor which, when inverted, results in frac-tional values which are expressed in 32nd’s, such as the8/5 scaling factor in the 640 to 1024 example above. A
1 2 3 4 5 1
187654321
Input Pixels
Output Pixels
Figure 13-8. 640 to 1024 Upscaling Example
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diagram of the input to output pixel relationship and theoutput fractional X and Y subpixel offset is shown inFigure 13-9.
Output Scaling Calculation Method
The output pixel distance in H and V in the ICP is calcu-lated to high precision (16 bit fraction) even though theoutput resolution is fixed at 1/32 of the input grid. Eachoutput pixel’s location relative to the input pixel grid inmemory is given by:
X location of output pixel = X0 of input line + Output pixel number / X Scale Factor
Y location of output pixel = Y0 of input window + Output line number / Y Scale Factor
The X and Y locations may not be integer values, de-pending on the scale factor. The resulting X and Y pixellocations can be separated into an integer and a fraction-al part. The integer part of the X and Y location selectsthe pixel and line number closest to the output pixel, re-spectively. The fractional part gives the fractional dis-tance of the output pixel to the next X and Y input pixelvalues. These fractional parts are the dX and dY valuesshown in Figure 13-9.
The output pixel’s value can be calculated by interpola-tion between these two pixels, or by 5-tap filtering usingthe 5 nearest pixels rather than the 2 nearest pixels. In-terpolation or filtering uses the fractional position values,∆X and ∆Y, to select the appropriate filter coefficients. Inthe ICP, these values are limited to 5 bits for a resolutionof 1/32, even though the actual position value has muchhigher resolution. The ICP uses fractional values that arecentered around the center pixel with a range of -16/32to +15/32.
To perform scaling, you must generate the X and Y loca-tions of the output pixel relative to the input pixel grid, in-cluding both the integer part to locate the adjacent pixelsand the fractional part to choose the filter coefficientswhich generate the output value from the adjacent pixels.This could be done by generating the output pixel X andY numbers and dividing each by its associated scale fac-
tor. Since dividing is expensive in hardware and time, theICP effectively multiplies the X and Y pixel numbers bythe inverse of the X and Y scaling factors, respectively.The ICP does this by incrementing the X and Y input pix-el counters by X and Y increment values that are the in-verse of the X and Y scale factors, respectively. If you areat output pixel Xn, you have added the inverse of thescale factor to the X input location n times, equivalent tomultiplying n by the inverse of the scale factor.
The ICP uses a 16-bit integer and a16-bit fractional valuefor the X and Y increment values. This allows a fractionalvalue resolution of 1/64K. This high resolution of the cal-culated prevents an accumulation of error as you incre-ment along the line. Since you will add the increment val-ue 1024 times in a 1024 pixel line, any error in anindividual calculation will be multiplied by 1024.
Only the most significant 5 bits of the fractional value areused by the filter coefficient RAMs. However, the X andY Counters are incremented by the high resolution X andY increment values. The result of this truncation is aworst case error of approximately 1.5% in amplitude rel-ative to arbitrary pixel output positions.
The error caused by discrete (1/32) resolution can be re-duced to exactly zero if the output image size is adjustedto have a repeating pattern that fits on these 1/32 bound-aries. For zero error, this implies that the scaling factormust be of the form of B/A, where B (the output pixelcount factor) is a sub-multiple of 32 [i.e. 1, 2, 4, 8, 16, 32],and A (the input pixel count factor) is an integer deter-mined by the nearest acceptable scale factor for a givenB. In the 640 to 1024 conversion case, the B/A ratio was8/5, meeting this requirement.
The integer values, if accumulated, would be equal to thetotal number of input pixels when scaling is complete.The integer values for each pixel define the number ofpixels to read from memory and shift in to generate thenext output pixel. For example, a scaling factor of 1.0 willresult in one pixel shifted in for each output pixel gener-ated. Upscaling will have integer increment values ofless than one. This means that the integer value will 0 forsome pixels and 1 for others. For example, upscaling by2.0 will result in integer values of 1 half the time and 0 forthe other half, depending on the carry out from the frac-tional increment.
Pixel Shift Bypassing for Large Down Scaling
Down scaling will have integer increment values of great-er than one. In this case, the integer value indicates thenumber of pixels to read to get filter pixels for the nextoutput pixels. There are two ways to read and shift in thepixels in the down scaling case: shift all and shift bypass.In the shift all mode (the default mode) all five pixels areshifted for each input value read and shifted in. The shiftall mode uses the five input pixels nearest the output pix-el, independent of scaling factor. In the shift bypasscase, only the last pixel is shifted in. For example, in adown scaling of 10, nine pixels are read, and the 10thpixel is shifted in to the filter. The shift bypass mode isused for large down scaling, i.e. down scaling factors of2.0 or greater. The shift bypass mode is selected by set-ting the GETB bit in the parameter table. The shift by-
Figure 13-9. ICP 1/32 Output Resolution
1 2
Input Pixels
Output Pixels
dY
dX
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pass mode uses input pixels that are nearest the outputpixel and those nearest each of the four output pixels ad-jacent to the output pixel. The shift bypass mode alsoforces the coefficient RAM inputs to zero, since you areno longer interpolating between adjacent input pixels.
Using Scaling to Convert From YUV 4:2:0 to YUV 4:2:2
YUV information in the 4:2:0 format has the UV pixels off-set from the input grid in both X and Y. Also, the U and Vpixels are at 1/2 of the horizontal and 1/2 of the verticalfrequencies of the Y pixels. This means the UV pixelsmust be filtered and additionally scaled in both X and Yin order to line up with the output Y pixels even if no initialscaling is done. To generate 4:2:2 interspersed data, youvertically up scale U and V by a factor of 2 with a start off-set of -1/4 pixel. Upscaling by 2 generates the additionallines required, and starting with a -1/4 pixel offset (rela-tive to U, V space) moves the output up to the same lineas the Y pixels. To generate 4:2:2 co-sited, you then filterhorizontally with no scaling factor but with a start offset of-1/4 pixel, moving the output left 1/4 pixel.
13.5.4 YUV to RGB Conversion
In the ICP, YUV to RGB conversion is done by sequen-tially processing triplets of Y, U, and V pixel data to con-vert the pixels to an internal YUV 4:4:4 format and apply-ing the YUV to RGB conversion algorithm on the YUV4:4:4 pixels. The results of this conversion normally go tothe PCI bus but can also go back to SDRAM.
YUV to RGB conversion has two steps. First you get theY, U and a V pixel data to generate an RGB pixel at theoutput. Second, YUV to RGB conversion is done oncethe Y, U and V pixels are ready. YUV to RGB conversionuses the following algorithms:
R = Y + 1.375(V)= Y + (1 + 3/8)(V)G = Y - 0.34375(U) - 0.703125(V)
= Y - (11/32)(U) - (45/64)(V)B = Y + 1.734375(U)
= Y + (1 + 47/64)(U)
In CCIR601, the U and V values are offset by +128 by in-verting the most significant bit of the 8-bit byte. This is theway the U and V values are stored in SDRAM. The abovealgorithms assume that the U and V values are convert-ed back to normal signed two’s complement values by in-verting the MSB before being used.
13.5.5 Overlay and Alpha Blending
The ICP has the ability to add an overlay image to themain image when in the horizontal filter to RGB/YUVmode with PCI output. The overlay image is a user de-fined rectangle within the main image. When the overlayis active, each overlay pixel is combined with each mainimage pixel to generate the resulting pixel to be dis-played. Each pixel combination is controlled by an alphavalue which determines the proportions of overlay andmain image that contribute to the output pixel. The rela-tion is given by:
In the ICP, the alpha value range is limited by the hard-ware to five values: 0.0, 0.25, 0.50, 0.75, 1.0.
An alpha value is supplied for each overlay pixel. In theRGB 24+α overlay data format: the 8-bit alpha value iscontained within the overlay data. In all other overlaydata formats (RGB 15+α, etc.), an alpha bit in the overlaydata determines the alpha value. The alpha bit selectsbetween two 8-bit values, alpha 1 and alpha 0, suppliedby a pair of internal ICP registers. These registers areloaded from the parameter block when the ICP is started.When the alpha bit is one, alpha 1 value is used as thealpha value; when the alpha bit is zero, alpha 0 is usedas the alpha value. The two alpha registers allow trans-lucent images and backgrounds while being restricted toone bit per pixel for alpha selection.
Alpha blending has several uses.
1. Alpha can be used to disable portions of the overlay, called keying. When the alpha for a pixel is zero, there is no overlay. When the alpha is 1, the overlay is 100%, replacing the image. This allows the user to put an irregular shaped object in an image without show-ing the bounding rectangle of the overlay.
3. Using alpha at the edges of small images such as font characters increases their effective visual resolution.
Chroma Keying
The ICP also provides optional chroma keying. It is a re-stricted form of chroma keying, sometimes called colorkeying. When the overlay Y value is zero (an illegal valuein the YUV 4:2:2+α format) or the RGB values are allzero (RGB15+α format), the alpha value is forced to zeroand no overlay or blending occurs. This provides threelevels of overlay: no overlay, alpha zero and alpha one.This combination can be used to generate an irregularlyshaped menu (an oval shape, for example) which istranslucent (with an alpha value of 50%, for example)and containing opaque (alpha = 100%) letters. In agame, this could be a message written on a foggy back-ground in an oval window. The chroma keying providesthe definition of the oval shape, the alpha zero value de-fines the translucent foggy background and the alphaone value defines the opaque characters on the foggybackground.
Chroma keying in the ICP is intended for computer gen-erated or modified overlays. Chroma keying turns off theoverlay process for selected pixels by forcing an alphavalue of zero for those pixels. Chroma keyed pixels usespecial codes to identify them. These codes must becomputer generated in most cases. For example, theDSPCPU or other CPU would process an overlay imageand convert the overlay pixels to be turned off into chro-ma keyed pixels by changing the data for those pixels tothe chroma key code.
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The ICP does not have full chroma keying. Full chromakeying has adjustable threshold values for the pixel com-ponents. Adjustable thresholds allow the user to auto-matically select an overlay sub-image from a larger over-lay background, such as selecting an image of an actoragainst a bright blue background while inhibiting the bluebackground.
13.5.6 Dithering
Short output codes, such as RGB 8, have few bits for out-put value determination. RGB 8R has (2,3,3) bits for(R,G,B). The result is a coarse, patchy image if nothingis done to correct for the limited resolution. Dithering sig-nificantly improves the effective resolution of these imag-es. RGB 8 images with dithering look nearly as good asRGB 16, for example.
Dithering works by adding a random dithering value tothe pixel before it is truncated by the output formatter.The dither is added to the portion which will be truncated.The carry from this add will occasionally propagate intothe most significant portion of the pixel before truncation.The carry from the add thus “dithers” the displayed value.This is shown in Figure 13-10. In the example shown, arandom dither value is added to the original data beforetruncation. The dither value should have a range of fromapproximately 0 to 1 LSB of the truncated value. Thedither value should be symmetrical about 1/2 the LSB ofthe quantizing error of the truncation. In the exampleshown, the dither signal has values of (1/8, 3/8, 5/8, 7/8).This set of values has a range of approximately 0 to 1LSB, and it is symmetrical about 1/2 LSB.
In this example, the input signal has a value of 2.83.Without dithering, this value would be truncated to anoutput value of 2 in all cases. Averaging the un-ditheredsignal over four pixels still gives you a value of 2. By add-ing the dither signal, the output value is 2 or 3 dependingon the value of the added dither signal. Averaging overfour pixels, the average output value is 2.75, much closerto the input value than without the dither signal. The dith-er signal has significantly reduced the error when aver-aged over four pixels.
Two types of dithering are combined in the ICP: quadpixel and full image dithering. Quad pixel dithering, alsoknown as ordered dithering, adds one of four ditheringvalues to each pixel. The four dithering values corre-spond to four-pixel quads in the output image. The pixelsin each quad have fixed positions in the input image, sothe dither values are chosen on the bases of odd or evenline number and odd or even pixel number in the line.The dither values of (0/4, 3/4, 2/4, 1/4) are added by lineand pixel number: (even line & even pixel, even line &odd pixel, odd line & even pixel, odd line & odd pixel).This gives a four value ordered function for four adjacentpixels in the image. The (0,3,2,1) pattern is chosen spe-cifically to prevent pairs of high or low pixel values fromclustering. Spatial dithering provides a significant im-provement in effective resolution.
Full image dithering adds a random number to every pix-el of the image. The result is that the intensity and coloraccuracy increases as the size of the sample is enlarged.The random number has a long bit length to prevent re-peating patterns in the image. The random number canbe static or dynamic. In the static case, the random num-ber generator starts with a fixed seed at the start of theimage. The random number spatial pattern is fixed forthe image even though the image data may change fromframe to frame. In the dynamic case, the random numbergenerator runs continuously, and the dithering patternchanges from frame to frame.
The ICP adds full image dithering to the quad pixel dith-ering to provide the final dithering signal for each pixel.The quad pixel dither provides the two most significantbits of the dither signal, and the full image dither providesthe least significant 4-bits of the dither signal. The com-bined dither signal is 6 bits.
From 1 to 6 bits of dither signal are used, depending onthe output format. If fewer than 6 bits are needed, onlythe most significant bits (MSBs) of the dither signal areused. For example in the RGB8R output format, the Routput value is 3 bits in size. The output uses the 3 MSBsof the R input value and truncates the 5 LSBs. The ditherunit adds 5 bits of dither signal (the 5 MSBs) to the 5
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LSBs of the R input value before truncation, and the RGBformatter truncates the result after adding.
13.5.7 Implementation Overview: Horizontal Scaling and Filtering
Figure 13-11 shows a data flow block diagram of the ICPhorizontal scaling algorithm implementation. Blocks ofpixels are provided by the input block buffer. Each blockof pixels is transferred sequentially to the 5-tap filter. Thefilter does scaling and filtering of the data and puts the re-sulting pixels in the output buffer. Completed pixels in theoutput buffer are written back to SDRAM or to the PCIoutput. A bypass multiplexer allows to bypass the filterfor SDRAM to SDRAM block moves.
Input pixel access is controlled by the Y Counter. The YCounter selects the word and byte for the current pixel inthe Y FIFO buffer. The Y Increment register, Y LSB Reg-ister and the Y MSB Counter control the increment of theY Counter. If the Y MSB Counter contents are not zero,the Y Counter is incremented and the Y MSB register isdecremented until the Y MSB Counter is zero.
The Y MSB Counter is loaded with the integer portion ofthe results of the Y Counter Increment operation. YCounter Increment means adding the Y Increment frac-tion and integer values to the Y LSB register and Y MSBCounter, respectively. If there is no scaling (scaling fac-tor = 1.0), the Y Increment integer value will be 1, and theY Increment fractional value will be 0. Each Y Counter
Increment operation will increment the Y Counter by onein this case.
The Y Counter sequentially reads out horizontally in-dexed pixels to the filter. The Y Counter is incrementedonce (1.0 for no scaling) for each pixel. For a line of pix-els beginning with Xa and ending with Xb, the Y Counterreads pixels from the block buffer beginning with Xa-2and ending with Xb+2. The extra pixels are required bythe 5-tap filter, which uses a total of 5 pixels to generateeach output pixel, two pixels before and two pixels aftereach pixel. The horizontal filter uses the current outputfrom the block buffer and four delayed versions of it togenerate the filter output as the weighted sum of the cen-ter pixel plus the two on either side. (For the case wherethe scaling factor = 1.0, the LSBs are always zero.)
For up or down scaling, the Y Increment value is not 1.0,it is the inverse of the scaling factor (See “ICP ScalingOutput Resolution,” on page 13-7). For up scaling by afactor of 2.0, the effective Y increment value is 0.5, forexample. This means you generate two output pixels foreach input pixel. The Y Counter effectively increments as0.0, 0.5, 1.0, 1.5, 2.0, etc. The LSBs of the counter (i.e.the fractional part less than 1) in the Y LSB register areused by to the filter to generate the intermediate values.An LSB value of 0.5 means that the output pixel is halfway between Xn and Xn+1. The filter contains a set of 5filter parameter RAMs, one for each coefficient. The 5most significant LSBs from the counter select the filtercoefficients which will generate the correct value for the
SDRAM
To S
DR
AM
Y MSB Cntr
Pixel Clock
5 Stage Multipli-er-Accumulator
Y LSBs
Reg
Reg
Reg
Reg
Pix
el D
ata
a +2
RA
M
a +1
RA
M
a +0
RA
M
a -1
RA
M
a -2
RA
M
Z Counter
Mux
Bypass
Bypass
SDRAM
AddressBlock
Y Counter
Y Incr Fraction
Y LSB RegCarry Out
Filter Source Select
5-tap Filter
YUV Code Delay
Y Incr Integer
N Byte Incr
Figure 13-11. ICP Horizontal Scaling Data Flow Block Diagram
OutputBuffers 6,7Block FIFO
Buffers 0,1Block FIFO
viahighway
via
high
way
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TM1100 Preliminary Data Book Philips Semiconductors
output pixel at the relative offset from 0.0 indicated by theLSBs.
The Y Counter selects the next pixel from the input buff-er. A new pixel is clocked into the filter registers onlywhen the Y Counter contents change. The Y Countercontents change only when the Y MSB Counter is loadedwith a value greater than zero. Note that for Y incrementvalues less than 1.0 (up scaling), the change will becaused by carry increment from the Y LSBs, and a newpixel will not be clocked into the filter shift register on ev-ery Y clock.
For increment values of 2.0 or for values of 1.0 or greaterwith carry in (down scaling), multiple new pixels will beclocked into the filter shift register before the filter inputsare ready. The number of new bytes needed for the nextpixel is the sum of the Y Increment Integer value and thecarry out of the Y LSB adder. This result is loaded intothe Y MSB Counter. The filter clock is stalled until the in-puts are ready. The integer value of the increment -- in-cluding carry -- defines the number of new pixels to beclocked through the shift register before the filter inputsare ready for use.
In this discussion, the Y Counter LSBs form a 16-bit bi-nary number. The upper 5 bits of this 16-bit number forma 5-bit binary number between 0 and 31 representing afractional distance between Y pixels between 0/32 and32/31. If the new pixel relative distance is 31/32, it isnearest the right pixel of the two pixels it is in between,and the right 2 pixels will be more heavily weighted thanthe left 3.
The horizontal filter shown in Figure 13-11 is pipelined togenerate a pixel for every integer increment of the YCounter. The filter input is always 5 clocks ahead of itsoutput. The first stage generates the filter term an+2Xn+2using the data from the input block and the an+2 coeffi-cient from the coefficient RAM driven by the Y LSBs. Thesecond stage registers hold the data for Xn+1 and its cor-responding Y LSBs and generate an+1Xn+1. The laststage registers hold the data for Xn-2 and the Xn-2 LSBsand generate an-2Xn-2.
The LSB Register contents can change on every clock.In the 2:1 scaling example, the LSBs alternated between0.0 and 0.5. The LSB Counter represents each outputpixel’s x offset value from the input pixel grid. The LSBIncrement value is 16 bits long. The 5 upper bits go to thecoefficient RAMs, and the 11 lower bits provide precisionincrement of the LSB Counter for precision in represent-ing the scaling factor. The 11 lower bits of the LSB Incre-ment value added to the 11 lower bits of the LSB Counterdetermine when to increment the 5 LSBs that drive thecoefficient RAMs and when to clock a new Y pixel intothe filter.
13.5.7.1 Loading the Extra Pixels in the Filter
For a 5-tap filter, you need 4 more pixels input to the filterthan you generate at the filter output, two before the firstpixel and two after the last pixel. In the worst case of awindow that is exactly N blocks wide and starts at the firstpixel of the first block, you will need to read two extrablocks - one at each end of the window - in order to get
these 4 pixels! This is an unavoidable problem with amulti-tap filter. For an n-tap filter, you need n-1 extra pix-els. There are two ways to avoid this efficiency hit offetching extra blocks.
1. Move the window edges so they are not within 2 pixels of a 64 input pixel boundary.
2. Simulate the edge pixels, such as by mirroring the pair of pixels you have on the other side. This is the only solution to the problem of starting (or ending) at the edge of the image, where there are no pixels to the left (or right) of the image window.
The ICP uses automatic mirroring to supply these pixels.Mirroring is used in both horizontal and vertical filtermodes.
13.5.7.2 Mirroring Pixels at the Ends of a Line
A line may start and/or end at the edge of the input im-age. In this case, you are missing the two start and/orend pixels needed for the first and last pixels of the line,respectively. The start mirror uses the two pixels to theright of the first pixel, and the end mirror uses the two pix-els to the right of the last pixel. These pixels are suppliedby controlling the Y counter.
A mirror multiplexer in the 5-tap filter provides mirroringof one or two pixels at the filter inputs. This mirror multi-plexer is used for both horizontal and vertical filtering. Inhorizontal filtering, the first and last two pixels in the lineare mirrored. The mirror multiplexer is set to the appro-priate mirror code for the first and last two pixels in theline. The first two pixels are mirrored for the first two clockpulses, and the last two pixels are detected using the pix-el counter for the line.
Mirroring is optional, depending on whether the start orend of the line is on a window boundary. The DSPCPUor microprogram must detect this and enable start and/orend mirroring as required.
13.5.7.3 Horizontal Filter SDRAM Timing
Figure 13-13 shows a timing diagram for block data flowbetween the SDRAM and the filter for a scaling factor of1.0. The bus block reads and writes are one fourth of thefilter processing time because the filter processes data at100 mega pixels per second, and the SDRAM reads andwrites blocks of pixels at 400 megapixels per second.The SDRAM logic reads the next block while the currentblock is being processed. This also provides the two pix-els from the next block required to finish filtering the cur-rent block.
If the scaling factor is greater or less than 1.0. theSDRAM bus activity will be different. For scaling factorsgreater than 1.0, there will be fewer SDRAM reads forthe same number of writes generated by the filter. Forexample, a scale factor of 2.0 means that you need toread only half as many blocks to generate the samenumber of output blocks. For a scale factor less thanone, there will be more reads for the same number ofwrites. For a scale factor of 0.5, you need to read twoblocks for every block of output. If the scale factor is less
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than 1/3, you will spend more time reading and writingSDRAM than filtering.
13.5.8 Implementation Overview: Vertical Scaling and Filtering
Figure 13-14 shows a data flow block diagram of the ICPvertical scaling algorithm implementation. Blocks of pix-els are loaded sequentially into five input block buffers,one for each of the 5 terms of the 5-tap filter. Each blockof pixels is transferred sequentially to the 5-tap filter. Thefilter does scaling and filtering of the data and puts the re-sulting pixels in the output buffer. Completed pixels in theoutput buffer are written back to SDRAM.
In the vertical scaling case, five separate blocks of pixels,one for each line, are required because the pixels arestored in horizontal sequence in the SDRAM. The YCounter steps through the 64 horizontal pixels of the fiveinput blocks and writes the resulting pixels into the outputblock. Four of the five blocks are used on the next pass,so that one block of pixels in generates one block of pix-els out except for end conditions. The image is pro-cessed in 64-pixel columns. Since the image to be fil-tered will not generally start or end on a block boundary,the number of horizontal pixels for the first and last col-umns will be less than 64 in these cases. Also, the datain the columns must be aligned vertically. This results inthe requirement that the line to line address offset valuemust be a multiple of 64 bytes. Note that only the addressoffset value is modulo 64; the image to be filtered canstart and stop anywhere. Block alignment is not required.
Vertical scaling and filtering processes five 64-pixel inputline segments to generate one 64-pixel output segment.When input lines Yn-2 to Yn+2 have been processed to
generate one 64-pixel output segment for output line Yn,five new input segments are needed for the next outputline segment in the 64-pixel column, Yn+1. If the verticalscale factor is 1.0 (no scaling), line segments Yn-1 toYn+2 are reused, a new block for Yn+3 is loaded and theblock for line Yn-2 is discarded.
To load Yn+3, the MCU adds the Y offset value to theblock address (upper 26 bits) of the Y Counter, and theY Counter selects the next Y block to be read fromSDRAM. The Y Counter points to the line block addressfor last Y block loaded, and the Y offset value is the ad-dress difference between the start of one line and thestart of the next, X0Y0 to X0Y1. The line offset is alwaysan integral number of SDRAM blocks. The line offset val-ue must be added to the current line address to get thenext line address.
Up and down scaling use the U Counter and U Incrementvalue. The U Counter is used to detect how many linesmust be read (0 to 5) to generate the next output line andto generate the vertical offset fraction for the 5-tap filterfor output lines that fall between the input lines. The UCounter is set to its starting value (typically zero) at thestart of the column, and the U Increment value is addedto the U Counter for each output line segment generatedin the column. For a scaling factor of 1.0, the U Incrementvalue is 1.0, and each line processed will generate a re-quest for one block. If the scaling factor is 1/2, the incre-ment value will be two, corresponding to moving downtwo lines. In this case, twice the line offset is added to theY Counter value.
For up scaling by a factor of 2.0, the Y increment value is0.5. This means you generate two output lines for eachinput line. The U Counter increments as 0.0, 0.5, 1.0, 1.5,
Input Pixels: Y
Output Pixels: Y’
1 2 3 4 5 6
Y’=F(Y3,Y2,Y1,Y2,Y3)
Y’=F(Y2,Y1Y2,Y3,Y4)
Y’=F(Y1,Y2,Y3,Y4,Y5)
Y’=F(Y2,Y3,Y4,Y5,Y6)
Y’=F(Y3,Y4,Y5,Y6,Y5)
2N: Y’=F(Y4,Y5,Y6,Y5,Y4)
(3) (2) (5) (4)
Mirrored Pixels
Figure 13-12. Horizontal Pixel Mirroring
SDRAM Bus
Filter Action
Read X0 Write Xa Read X1
Filter X1 => Xb Filter X0 => Xa
Read X2 Write Xb
Filter X2 => Xc
Read X3
Figure 13-13. SDRAM and Horizontal Filter Block Timing
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TM1100 Preliminary Data Book Philips Semiconductors
2.0, etc. The LSBs of the U Counter (i.e. the fractionalpart less than 1) are passed along to the filter to generatethe intermediate values. An LSB value of 0.5 means thatthe output line is half way between Yn and Yn+1. The filtercontains a set of 5 filter parameter RAMs, one for eachcoefficient. The 5 most significant LSBs from the counterselect the filter coefficients which will generate the cor-rect value for the output pixel at the relative offset from0.0 indicated by the LSBs.
For down scaling, the increment factor will be greaterthan one. If the increment factor is 2.0, two new blockswill have to be loaded before starting the next vertical fil-ter pass. If the increment factor is 5 or greater, all fiveblocks will have to be loaded. The number of blocks to beloaded for the next line is equal to the integer incrementvalue plus carry out from the LSB portion of the UCounter increment.
Note that the LSB adder carry out is available before theU Counter has been updated. This allows you to use thecurrent U Counter value LSB bits for the filter coefficientswhile using the carry out for the next value to predict howmany blocks to fetch. The integer value from the U incre-ment value plus the carry in from the LSB portion of theIncrement adder is the number of blocks to be loaded.These blocks must be sequentially loaded (and notskipped) so that the filter has the necessary 5 adjacent
lines to perform the filtering. The contents of the integerportion of the U Counter (updated after the add) are notused.
You can only load one new block while the current line isbeing processed. If two or more blocks are needed toprocess the next line, you load one in overlap, wait untilthe current line is done and then load the rest of theblocks. The microprogram only has to make two deci-sions for the next line: is the increment value zero orgreater than zero, and if greater than zero, is it greaterthan five. If it is zero, do nothing: you will reuse all fiveblocks. If it is 1-4, load the next block. If it is five or more,calculate the address of the first block -- by adding Ntimes the address offset to the Y counter -- and fetch it.
When a new block is loaded and it is time to process thenext line, the block which was Yn+2 becomes Yn+1. TheY blocks, in effect, shift up one line as you scan down theimage. This shifting action is implemented by shifting theblock select codes in the Filter Source Select Register(FSSR). The FSSR contains six 3-bit register fields.These 3-bit fields are rotated by a shift command to theFSSR. The output of five of the FSSR fields go to the in-put multiplexer, which selects the next block combinationand sends it to the filter. The output of the sixth field is thefree block to be filled for the next line while the currentline is being processed. The select code is also the block
SDRAM
To S
DR
AM
Out
put B
uffe
rs 6
,7
Blo
ck F
IFOY Counter
Yn+2 Buffer
5-tap Filter
a +2
RA
M
a +1
RA
M
a +0
RA
M
a -1
RA
M
a -2
RA
M
Yn+1 Buffer
Yn+0 Buffer
Yn-1 Buffer
Yn-2 Buffer
U Incr Integer
U LSBs
U LSB Reg
U Incr Fraction
Z Counter
Filter Source Select 6 In x 5 OutMultiplexer
FSSR
Y L
ine
cloc
k
Line ClockCarry
Byte Index
Pixel Clock
Block Countto Microcode U MSB Cntr
Block Addressto SDRAM
OutputPixel clock
Figure 13-14. ICP Vertical Scaling Data Flow Block Diagram
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code (0 to 5), so the free block is identified by its blockcode in the FSSR. The FSSR codes for the six cases ofvertical filtering are shown in Table 13-4
13.5.8.1 Mirroring Lines at the Ends of an Image
A window may start and/or end at the edge of the inputimage. In this case, you are missing the two start and/orend lines needed for the first and last lines of the window,respectively. These pixels are supplied by the mirror mul-tiplexer at the 5-tap filter which mirrors the inputlines.The mirror multiplexer is controlled by the mirrorcounter and mirror end register in the same manner as inhorizontal filtering. The mirror register in vertical filteringis incremented by the output line counter. Mirroring isperformed on the first two and last two lines of the col-umn. Mirroring is optional, depending on whether thestart or end of the line is on a window boundary. TheDSPCPU or microprogram must detect this and enablestart and/or end mirroring as required.
13.5.8.2 Vertical Filter SDRAM Block Timing
Figure 13-15 shows a timing diagram for block data flowbetween the SDRAM and the filter for a scaling factor of1.0. The bus block reads and writes are one fourth of thefilter processing time because the filter processes data at100 mega pixels per second, and the SDRAM reads andwrites blocks of pixels at 400 megapixels per second(peak). The vertical filter starts by reading in the fiveblocks necessary to generate the next output block.While the current block is being processed, the nextblock is read from SDRAM to prepare for the next outputblock.
13.5.9 Horizontal Scaling and Filtering for RGB Output
Figure 13-16 shows a data flow block diagram of the ICPhorizontal scaling to RGB output algorithm implementa-tion. The six input block buffers are arranged as threeblock FIFOs, one each for a Y, U and V pixel streams.These three streams are sequentially filtered, pixel bypixel by the 5-tap filter to generate a scaled and filteredoutput sequence of Y, U, V, Y, U, V, etc. This YUVstream is fed to the YUV to RGB converter where it isconverted to one of several RGB output formats, blendedwith RGB overlay pixels supplied by the Overlay FIFOand masked by bit mask pixels from the bit mask block.The resulting scaled, filtered, converted, overlay blendedand masked RGB stream is sent to the PCI interface --typically to an RGB format frame buffer on the PCI bus -- or to the SDRAM.
The input pixel streams from the input FIFOs are trans-ferred sequentially to the 5-tap filter. Each stream has itsown set of four-stage delay registers used to performhorizontal filtering on the stream. A pair of 3-way multi-plexers switch the five filter data inputs and the 5-bit filtercoefficient select codes to the 5-tap filter. This set of mul-tiplexers is driven by the YUV Sequence counter, a 2-bitcounter that provides the YUV processing sequence.
Horizontal scaling and filtering for RGB output is per-formed in the same way as for ordinary filtering. The dif-ference is in the format of the output data (RGB), the se-quencing of the filtering to create the combined RGBoutput and the buffering of the YUV output data. In hori-zontal scaling and filtering from SDRAM to SDRAM,each Y, U and V component is filtered separately as acomplete image. In RGB output horizontal scaling and fil-tering, the image is processed as three interwovenstreams of all three YUV components.
In the RGB output mode, the ICP normally generatesRGB data and writes it into a frame buffer memory on theRGB bus or to the SDRAM. The frame buffer memoryformat is RGB with one R, one G and one B value perpixel. This could be called RGB 4:4:4. To generate thisimage, the ICP generates a YUV 4:4:4 image and con-verts it to RGB. This process is done one RGB outputpixel at a time. The ICP generates a U pixel and saves itin a register, generates a V pixel and saves it in a regis-ter, then generates a Y pixel for output. The YUV to RGBconverter combines each Y pixel as it is generated withthe previously stored U and V pixels to generate the RGBoutput data. This process is repeated until the whole im-age has been converted and sent to the PCI bus orSDRAM.
Table 13-4. FSSR Codes for Vertical Filtering.
Case Pn-2 Pn-1 Pn+0 Pn+1 Pn+2 IO Block
1 5 4 3 2 1 0
2 0 5 4 3 2 1
3 1 0 5 4 3 2
4 2 1 0 5 4 3
5 3 2 1 0 5 4
6 4 3 2 1 0 5
SDRAM Bus
Filter Action
Read Y5 Write Ya Read Y6
Filter Y3-6 => Yb Filter Y2-5 => Ya
Read Y7 Write Yb
Filter Y4-7 => Yc
Read Y8
Figure 13-15. SDRAM and Vertical Filter Block Timing
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TM1100 Preliminary Data Book Philips Semiconductors
13.5.9.1 YUV Sequence Counter in YUV 4:2:2 Output Mode
For RGB output formats, the YUV data must be scaled toYUV 4:4:4 format before conversion to RGB. The YUVdata in SDRAM is typically stored in YUV 4:2:2. Thismeans that the U and V data must be upscaled by 2 rel-ative to the Y data to generate the internal YUV 4:4:4 for-mat required for RGB conversion.
For the YUV 4:2:2 output code, the U and V data doesnot need to be up scaled to 4:4:4. You would be scalingup to YUV 4:4:4 only to decimate back to YUV 4:2:2. Inthe YUV 4:2:2 output case, you want to use the U and Vpixels twice. This is done by having a half-speed modefor the YUV Sequence Counter. In this mode, the se-quence is U0, V0, Y0, Y1, U2, V2, Y2, Y3, etc. The U and
V are not up scaled by 2 relative to the Y component forYUV 4:4:4 output, although they could be up scaled aspart of general up scaling of the image.
The YUV 4:2:2 Output mode also provides higher pro-cessing bandwidth relative to YUV 4:4:4 up scaling. Youare processing half as many U and V pixels. The outputpixel rate is one pixel per 20 nanoseconds for the YUV4:2:2 Output mode versus one pixel per 30 for conver-sion to YUV 4:4:4. This can be used to provide some pro-cessing performance improvement for very large imagesat the expense of some chroma quality.
13.5.9.2 PCI Output Block Timing
The ICP generates pixels to the PCI interface at a peakrate of 33 output megapixels per second in the RGB
To P
CI
5 Stage Multiplier-Accumulator
Y, U, V LSBs
Reg
a +2
RA
M
a +1
RA
M
a +0
RA
M
a -1
RA
M
a -2
RA
M
Y CounterY LSB Counter
Buffers 0,1Block FIFO
Filter Source Select
5-tap Filter
RegRegReg
Reg
U CounterU LSB Counter
Buffers 2,3Block FIFO
RegRegReg
Reg
V CounterV LSB Counter
Buffers 4,5Block FIFO
RegRegReg
OL Counter
B, BX Counter
Buffer 8Bit Mask
Buffers 6,7Overlay
FIFO
Mul
tiple
xer:
Y, U
, V S
elec
t
Mux
YU
V to
RG
B C
onve
rsio
n, F
orm
attin
g, A
lpha
Ble
ndin
g &
Bit
Mas
king
YUV
CounterSequence
PixelClock Y, U, V Data FIFO Clocks
Mirr
or M
ultip
lexe
r
Y Mirror CntrU Mirror CntrV Mirror Cntr
Mux
RGB to SDRAM case
RGB to PCI case
Figure 13-16. ICP Horizontal Scaling for RGB Output Data Flow Block Diagram
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mode and 50 megapixels per second in the YUV modeusing YUV sequencing. For one word per pixel outputcodes, such as RGB-24, this is a peak rate of 33 megawords or 132 megabytes per second in the RGB se-quencing mode. This is the same speed as the 132megabytes per second peak rate of the PCI interface. (At50 megapixels per second, the result would be 200megabytes/second.) The BIU control for the PCI inter-face has a FIFO for buffering data from the ICP, but thisbuffer is only 16 words deep. Therefore, the ICP will oc-casionally have to wait for the PCI to accept more data.In the PCI output mode, this stalls the ICP clock.
13.6 OPERATION AND PROGRAMMING
The ICP uses a combination of hardware and a Micro-program Control Unit (MCU) to implement its scaling, fil-tering and conversion functions. The microprogram is afactory supplied state machine that resides in SDRAM. Itis read each time the ICP executes an operation. Using
an SDRAM resident microprogram controlled state ma-chine minimizes hardware and provides flexibility in han-dling special conditions without additional hardware.
Important Note: You must set the ICP DMA Enable bit(IE) in the BIU_CTL register of the PCI interface for RGBoutput to PCI. This bit must be set before initiating RGBto PCI operations, or the ICP will stall waiting for the PCIto become ready. Refer to Section 10.7.5, “BIU_CTLRegister.”
13.6.1 ICP Register Model
The ICP is controlled by the DSPCPU through five MMIOregisters: the MicroProgram Counter (MPC), the MicroInstruction Register (MIR), the Data Pointer (DP), theData Register (DR) and the ICP Status register (SR), asshown in Figure 13-17. The MPC, DP and SR are usedin normal operations, and the MIR and DR are used intest and debug. Note that the MMIO registers shouldnever be written while the ICP is executing microcode, i.e
test the Busy bit in the SR register before writing any ICPMMIO register.
The MPC is the MCU instruction counter. It points to thenext microinstruction to be executed. The entry point inthe microprogram defines which ICP operation is to bedone.The DP points to the location in SDRAM of a tableof parameters used by the ICP to process the image da-ta, such as the image input and output start addresses,scaling factor, etc.
The SR has 13 active bits: Busy (B), Done (D), done In-terrupt Enable (IE), ACK_DONE (A), Little Endian (L),Step (S), Diagnostic (DG), Reset (R) , Priority Delay (PD,4 bits) and PWDN (Power down, P). Bits 12 .. 30 are re-served.
• Busy indicates the ICP is busy executing microcode.
• Done indicates that the previous requested functionis complete, and that the ICP clock is stopped.
• Done causes an interrupt to the DSPCPU whenInterrupt Enable is set.
• ACK_DONE clears Done and the correspondinginterrupt.
• Little Endian sets the highway endian swap multi-plexer to little endian mode for data on the SDRAMbus.
• Step causes the MCU to execute one microinstruc-tion. Step is used for diagnostics to step the ICPthrough its microinstructions one clock step at a time.Writing a one to Step sets Busy, which is reset at theend of execution of the next microinstruction.
• DG allows SDRAM operations in step mode. • R is a write-only bit that resets ICP internal registers.
MicroProgram Counter (MPC, ICP_MPC)
Data Pointer (DP, ICP_DP)
ICP Status (ICP_SR) D
1 031
31 0
BIE
2
MicroInstruction Register (MIR, ICP_MIR)
Data Register (DR, ICP_DR)
3
ALS
45
0x10 2400
0x10 2404
0x10 2408
0x10 2410
0x10 2414
MMIO Offsets
Priority Delay
12 11 6
DGR
78
Figure 13-17. ICP MMIO Registers
P
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• The PD field sets a timer for bus activity that definesthe minimum bus bandwidth available to the ICP.
• The PWDN bit indicates a selective power down ofthe ICP.
The ICP Status Register contains 20 read only statusbits. The upper 16 bits of the Status Register can containa 16-bit code returned by the microprogram upon com-pletion. Bits 15 through 12 are reserved for error flags.
Bit 31 has a special function as PWDN bit in TM1100only. It is reserved in future implementations. To use thisTM1100 feature the microprogram writes a 1 into PWDN.After the busy bit is removed the ICP will power down. Itis only powered up again by a hardware reset. See alsoChapter 20 for Power Management features. Note: thePWDN bit can only be written by the microprogram.
Important Note: You must set the ICP DMA Enable bit(IE) in the BIU_CTL register of the PCI interface for RGBoutput to PCI. This bit must be set before initiating RGBto PCI operations, or the ICP will stall waiting for the PCIto become ready. Refer to Section 10.7.5, “BIU_CTLRegister.”
13.6.2 ICP Operation
The DSPCPU commands the ICP to perform an opera-tion by loading the DP with a pointer to a parameterblock, loading the MPC with a microprogram start ad-dress and setting Busy in the SR. For example to causethe ICP to scale and filter an image, you set up a block ofSDRAM with the image and filter parameters, load theMPC with the starting address of the appropriate micro-program entry point in SDRAM, load the DP with the ad-dress of the parameter block, and set Busy in the SR bywriting a one to it. When the filter operation is complete,the ICP will set Done and issue an interrupt. TheDSPCPU clears the interrupt by writing a one toACK_DONE. Note: The interrupt should be set up as alevel triggered interrupt.
When the DSPCPU sets busy, the MCU begins readingthe microprogram from SDRAM. The microinstructionsare read in from SDRAM as required by the ICP, and in-ternal pre-fetching is used to eliminate delays. SettingBusy enables the MCU clock, the first block of microin-structions is automatically read in and the MCU beginsinstruction execution at the current address in the MPC.Clearing Busy stops the MCU clock. Busy can be clearedby hardware reset, by the MCU and by the DSPCPU.Hardware reset clears the Status register, including Busyand Done, and internal registers, such as the TCR.When the MCU completes a microprogram operation,the microprogram typically clears Busy and sets Done,causing an interrupt if IE is enabled.
The DSPCPU performs a software reset by clearing(writing a zero to) Busy and by writing a one to Reset.The DSPCPU can also set Done to force a hardware in-terrupt, if desired.
13.6.3 ICP Microprogram Set
The ICP comes with a factory generated microprogramset. This microprogram set implements the functions of
the ICP. The microprogram set includes the followingfunctions:
1. Loading the filter coefficient RAMs.2. Horizontal scaling and filtering from SDRAM to
SDRAM of an input image to an output image. The in-put and output images can be of any size and position that fits in SDRAM. The scaling factors are, in general, limited only by input and output image sizes.
3. Vertical scaling and filtering from SDRAM to SDRAM of an input image to an output image. The input and output images can be of any size and position that fits in SDRAM. The scaling factors are, in general, limited only by input and output image sizes.
4. Horizontal scaling, filtering and YUV to RGB conver-sion of an input image from SDRAM to an output im-age to PCI or SDRAM, with an alpha blended and chroma keyed RGB overlay and a bit mask. The input and output images can be of any size and position that fits in SDRAM and output to the PCI bus or SDRAM, The scaling factors are, in general, limited only by input and output image sizes.
The microprogram is supplied with the ICP as part of thedevice driver. The entry point in the microprogram de-fines which ICP operation is to be done. The entry pointsare given below in terms of word offsets from the begin-ning of the microprogram:
Offset Function
0 Load coefficients
1 Horizontal scaling and filtering
2 Vertical scaling and filtering
3 Horizontal scaling, filtering, YUV to RGB conversion, bit masking (PCI) and over-lay (PCI) with alpha blending and chroma keying
13.6.4 ICP Processing Time
The processing time for typical operations on typical pic-ture sizes has been measured.
During the measurements the CPU clock and SDRAMclock were set to 100MHz, PCI clock was 33MHz. Allmeasurement with PCI as pixel destination were donewith an Imagine 128 Series II graphics card, which nevercaused a slowdown of the ICP operation. The mother-board was a TRITON2 with SB82437UX andSB82371SB based Intel Pentium chipset. TheTM1100 arbiter was set to default settings. TM1100 la-tency timer was set to maximum value = 0xf8.
Overlay sizes were the same as picture sizes.
The results are tabulated below for three different casesof available memory bandwidth:
1. No other load to SDRAM, i.e. full SDRAM bandwidthavailable for ICP. See Table 13-5
2. SDRAM memory loaded to 95% of its bandwidth byDCACHE traffic from DSPCPU. Priority delay = 1, i.e.ICP did wait one block time before competing for memo-ry. See Table 13-6
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3. SDRAM memory loaded to 95% of its bandwidth byDCACHE traffic from DSPCPU. Priority delay = 16, i.e.ICP did wait 16 block times before competing for memo-ry. See Table 13-7
A load of 95% of the memory bandwidth is very rarelyfound in a real system.
So the results in these tables may be useful to estimateupper bounds for the computation time in a loaded sys-tem.
The priority delays were set to the minimum and maxi-mum possible values, so the computation time for otherpriority delay values should be somewhere in between.
A simple linear model of computation time has been fit-ted to the tabular data and to corresponding measure-ments with half the number of pixels per line.
It has been assumed that
processing time = (time per line start)* (number of lines)
+(time per pixel) * (number of pixels)
Table 13-8, Table 13-9, Table 13-10 give the time perline start and the time per pixel in this equation for thethree memory bandwidth cases.
The maximum deviation between measured time and fit-ted model is in the order of 10% in the range W = 180 ..1024, H = 240 .. 768. The deviation is much less in mostcases.
The values were found by least squares fit to the mea-sured data.
In some cases the cumulative time for line starts contrib-uted so little to the total computation time, that the valueper line start could only be determined relatively inaccu-rately. In other words the pixel time part then dominatedthe equation so much, that the line time part was negligi-ble, given the inaccuracies of the model.
Therefore the simple model is only thought to allow inter-polation for other picture sizes within the range W = 180..1024, H = 240 .. 768. Extrapolation to picture sizesmuch outside this range should not be attempted.
In some cases the real ICP performance may be muchbetter than that predicted by the model, due to irregularbehavior of the ICP.
For horizontal and vertical up/down-scaling operationsuse the larger W or H value occurring at input/output withthe H/V filter times table or model.
This will lead to overestimation of processing time by upto 20%.
Table 13-5. Measured processing time in ms - no other load to SDRAM
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13.6.5 Priority Delay and ICP Minimum Bus Bandwidth
The Priority Delay field in the Status register sets thetime the ICP will wait for SDRAM service before chang-ing from a low priority bus request to a high priority re-quest. The ICP normally requests SDRAM bus service atthe lowest priority level, since it is a background process-ing device. In some cases, service to the ICP could becontinuously delayed by other background devices, suchas the VLD processor or by high priority requests fromthe DSPCPU.
The PD field sets a timer on the currently active bus re-quest. The timer is loaded with the PD value and startedeach time a bus request is submitted. The timer is incre-mented once each block time, the time required to loadone block of 64 byte. If the timer reaches 16 before therequest is serviced, the ICP changes its bus request pri-ority from low to high.
The resulting time delay until the ICP changes to high pri-ority is
timer delay = (16 - PD)*(block time)
One block time is 16 clock times.
Table 13-8. Line start and pixel time for linear model, no other load on SDRAM
function t/linestart(µs)
t/pixel(ns)
horizontal filter, one component 1.1 11
horizontal filter, 3 components YUV 4:2:2 3.2 22
vertical filter, one component 0.2 29
vertical filter,3 components YUV 4:2:2 0.7 58
yuv to rgb8a,pci output 3.2 30
yuv to rgb15a,pci output 3.3 30
yuv to rgb24,pci output 3.7 34
yuv to rgb24a,pci output 5.3 40
yuv to rgb8a,sdram output 3.4 30
yuv to rgb15a,sdram output 3.3 31
yuv to rgb24,sdram output 3.1 33
yuv to rgb24a,sdram output 3.4 36
yuv to rgb8a,bitmask,pci output 2.5 32
yuv to rgb8a,rgbl15a overlay,pci output 3.8 32
yuv to rgb8a,rgbl24a overlay,pci output 4.0 39
yuv to rgb8a,yuv422a overlay,pci output 3.8 32
yuv to rgb8a,422sequencing,pci output 3.2 20
Table 13-9. Line start and pixel time for linear model, SDRAM loaded 95%, priority delay = 1
function t/linestart(µs)
t/pixel(ns)
horizontal filter, one component 0.9 20
horizontal filter,3 components YUV 4:2:2 2.8 40
vertical filter, one component 0.2 29
vertical filter,3 components YUV 4:2:2 0.7 58
yuv to rgb8a,pci output 3.8 30
yuv to rgb15a,pci output 3.8 30
yuv to rgb24,pci output 4.5 34
yuv to rgb24a,pci output 6.0 39
yuv to rgb8a,sdram output 4.3 31
yuv to rgb15a,sdram output 4.9 36
yuv to rgb24,sdram output 4.6 47
yuv to rgb24a,sdram output 5.0 53
yuv to rgb8a,bitmask,pci output 3.2 34
yuv to rgb8a,rgbl15a overlay,pci output 5.5 42
yuv to rgb8a,rgbl24a overlay,pci output 5.8 63
yuv to rgb8a,yuv422a overlay,pci output 5.5 42
yuv to rgb8a,422sequencing,pci output 4.9 21
Table 13-10. Line start and pixel time for linear model, SDRAM loaded 95%, priority delay = 16
function t/linestart(µs)
t/pixel(ns)
horizontal filter, one component 2.9 77
horizontal filter, 3 components YUV422 8.7 154
vertical filter, one component 0.4 87
vertical filter,3 components YUV 4:2:2 1.2 174
yuv to rgb8a,pci output 13.9 82
yuv to rgb15a,pci output 13.8 82
yuv to rgb24,pci output 13.7 82
yuv to rgb24a,pci output 14.0 82
yuv to rgb8a,sdram output 15.8 115
yuv to rgb15a,sdram output 18.5 151
yuv to rgb24,sdram output 17.5 187
yuv to rgb24a,sdram output 16.6 233
yuv to rgb8a,bitmask,pci output 14.3 91
yuv to rgb8a,rgbl15a overlay,pci output 20.7 153
yuv to rgb8a,rgbl24a overlay,pci output 21.6 232
yuv to rgb8a,yuv422a overlay,pci out-put
20.8 153
yuv to rgb8a,422sequencing,pci output 14.0 80
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Table 13-11 gives the delay in block times as a functionof the PD field.
The priority delay mechanism in interaction with the arbi-ter mechanism allows the user to allocate enough band-width for the ICP to do its processing in the requiredframe time. For details of the arbiter mechanism seeChapter 19.
13.6.6 ICP Parameter Tables
Each microprogram in the microprogram set has an as-sociated parameter table used by the ICP to process theimage data, such as the image input and output start ad-dresses, scaling factor, etc. The DP points to the locationin SDRAM of the first word of the parameter table. Theparameter table address must be word aligned. The pa-rameter table can be more than one SDRAM block (1632-bit words) long.
Note: In packed RGB24 to PCI operation the output ad-dress offset from the start of video memory must be amultiple of 6 bytes, i.e. on an even pixel boundary.
13.6.7 Load Coefficients
This routine loads the filter coefficient RAMs with coeffi-cient data in the parameter table. A total of 32 sets of five,10-bit coefficients are loaded. Each set of five coeffi-cients forms a 50-bit coefficient word. Two coefficientsare stored in each 32-bit word in SDRAM. three 32-bitwords are used for each set of five coefficients that forma coefficient word. The parameter table is 96 words (6SDRAM blocks) long. Each coefficient is stored as the 10least significant bits of each 16-bit halfword of the 32-bitword.
13.6.7.1 Parameter Table
The parameter table for the coefficient load function con-tains the coefficient data directly, as shown below. Theparameter table is 96 words long.
13.6.8 Horizontal Filter - SDRAM to SDRAM
This routine performs horizontal scaling and filtering ofone component (Y, U or V) of an N x M image from onelocation in SDRAM to another.
13.6.8.1 Algorithms
The routine reads image data from SDRAM using the Yaddress counter, scales and filters the data in the hori-zontal direction and writes it back to the SDRAM usingthe Z address counter. The 5-tap filter scales and filtersthe data. The LSB Increment value supplied by the pa-rameter table determines the scaling. The routine readsand writes a line at a time until the full image is trans-ferred. The filter mirrors the ends of each line to providethe extra pixels needed by the filter at the ends of eachline.
13.6.8.2 Parameter Table
The parameter table, shown in Table 13-13, supplies theinput and output starting addresses and offsets, the im-age height in lines and width in pixels, and the incrementvalue, which is derived from the scale factor.
The input and output addresses are the byte addressesof their respective tables. They need not be word or blockaligned.
The input and output line offsets define the difference inbytes from the address of the first pixel in the first line tothe address of the first pixel in the second line for their re-spective blocks. The line offset must be constant for alllines in each table. The line offset allows some space be-tween the end of one line and the start of the next line. Italso allows the ICP to scale and filter a subset of an ex-isting image, such as magnifying a portion of an image.There are no restrictions on line offset values other than
Table 13-11. ICP priority delay vs. PD Code
PDCode
Delayblock times
1111 1
1110 2
1101 3
1100 4
1011 5
1010 6
1001 7
1000 8
0111 9
0110 10
0101 11
0100 12
0011 13
0010 14
0001 15
0000 16
Table 13-12. Load Coefficients Parameter Table
Parameter Word
DescriptionUpper 2 bytes
Lower 2 bytes
a+2 a+1 RAM Coefficient word 0
a+0 a-1
a-2 0
a+2 a+1 RAM Coefficient word 1
a+0 a-1
a-2 0
a+2 a+1 RAM Coefficient word 31
a+0 a-1
a-2 0
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they must be 16-bit, two’s complement integer values.(Note that this allows negative offsets. You can use thisto flip an image vertically.)
The input and output image height and width values arethe height in lines and width in pixels per line for their re-spective images. The height and width are 16-bit positivebinary numbers between 0 and 64K-1.
The Integer increment and Fraction increment values arethe scaling parameters. The Integer value is a 16-bit in-teger, and the Fraction value is a positive binary fractionbetween 0 and 0.99999+. For up scaling (output imagebigger), the increment value is the inverse of the scalingvalue. If you are upscaling by a factor of 2.5, the incre-ment value will be the inverse of 2.50 = 0.40. The Integerincrement value will be 0 and the Fraction increment val-ue will be 0.40. For down scaling, the increment value isequal to the scaling value. If you are down scaling by 2.5(output image smaller), the Integer increment value willbe 2, and the Fraction increment value will be 0.500.
To perform scaling, the Integer and Fractional incrementvalues must be generated and placed in the parametertable. The simplest way to generate these values in com-mon computer languages such as C is as follows:
1. Generate the Increment Value as a floating point number = Input Width / Output Width
2. Multiply the Increment Value by 655363. Convert the result to a Long Integer (32 bits). The up-
per 16 bits of the Long integer will be the Integer in-crement value, and the lower 16 bits will be the Frac-tional value.
4. Store the 32-bit Long integer in the parameter table as the combined Integer and Fractional increment val-ues.
The Start Fraction defines the starting value in the scal-ing counter for each line. It is a 16-bit, two’s complementfractional value between -0.500 and 0.49999+. The StartFraction allows the input data to be offset by up to half apixel, referred to the input pixel grid. It is zero for Y andfor UV co-sited data, and is set to minus 0.25 (C000h) forinterspersed to co-sited conversion of U and V data. The
minus 0.25 value effectively shifts the U and V data to-ward the start of the line by 1/4 pixel, the amount requiredfor conversion.
13.6.8.3 Control Word Format
The Control word provides bit fields which affect the hor-izontal filtering operation. The format of the Control wordis as follows.
Bit Name Function
15 Bypass Bypass filter. Picks nearest input pixel and passes it to output unfiltered.
When Bypass is set & scale factor is 1.0, this results in an image block move
9 GETB Large down scaling bit. Picks nearest input pixels and then passes them to filter.
Equivalent to bypass + 5-tap filter of output pixels. LSB value = 0 for filter-ing.
The Bypass bit causes the data to bypass the 5-tap filter.The scaling operation selects the center pixel, and thispixel is passed to the filter output. No filtering or interpo-lation is provided. If the scaling factor is 1.0, the result isan image block move where the image is moved fromone part of SDRAM to another without modification. If thescaling factor is other than 1.0, the effective algorithm ispixel picking, where the input pixel nearest the outputpixel location is used as the output pixel.
The GETB bit is an optional bit for large (> 4) down scal-ing. When GETB is zero (normal operation), the 5-tap fil-ter receives the pixel nearest the output pixel as its cen-ter pixel plus the two adjacent input pixels on either sideof this pixel to form the five filter inputs. When GETB isset, the filter receives the pixel nearest the output pixelas its center pixel plus the two pixels nearest the adja-cent output pixels on either side of this pixel to form thefive filter inputs. The effective algorithm is pixel pickingplus 5-tap filtering of the result. GETB also forces thescaling LSB value to zero, since output pixels are being
Table 13-13. Horizontal Filter Parameter Table
Parameter WordDescription
Upper 2 bytes Lower 2 bytes
Input Image Start Address Start address of X0Y0 (byte address)
Y Counter Start Fraction
Input Image Line Offset
Starting value: may be 0.5, etc. for interspersed convert; Line offset from X0Y0 to X0Y1
Fraction increment Integer increment Increment value for Y = 1/scale factor
Input Image Height Input Image Width Height and width in input lines and pixels
Output Image Start Address Start address of X0Y0 (byte address)
Control Output Image Line Offset
Control bits; Line offset from X0Y0 to X0Y1
Output Image Height Output Image Width Height and width in output lines and pixels
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filtered and no interpolation is used. (See Section 13.5.2,“Filtering”) This is shown in Figure 13-18.
13.6.9 Vertical Filter - SDRAM to SDRAM
This routine performs vertical scaling and filtering of onecomponent (Y, U or V) of an N x M image from one loca-tion in SDRAM to another.
13.6.9.1 Algorithms
The routine reads image data from SDRAM using the Yaddress counter, scales and filters the data in the verticaldirection and writes it back to the SDRAM using the Z ad-dress counter. The 5-tap filter scales and filters the data.The U LSB register is used as the scaling coefficient reg-ister. The U LSB Increment value supplied by the param-eter table determines the scaling. Lines at the top andbottom of the image are mirrored to provide the extra linedata needed by the 5-tap filter.
The routine reads and writes data in 64-byte (oneSDRAM block) columns of pixels until the entire image istransferred. For each column, line segments of 64 pixels
are processed until the entire column has been pro-cessed. Each 64-pixel line segment generated requiresfive vertically adjacent 64-pixel line segments as input tothe 5-tap filter. The routine processes the image in pixelcolumns to eliminate redundant read of input pixel data:each new line segment typically requires reading onlyone new 64 byte line segment.
The routine processes data in 64-pixel blocks, corre-sponding to the input block buffer sizes. Five buffers areused in processing the current line segment, while thesixth buffer reads in the next line segment in overlap withcurrent processing.
13.6.9.2 Parameter Table
The parameter table, as shown in Figure 13-19, suppliesthe input and output starting addresses and offsets, theimage height in lines and width in pixels, and the scalefactor.
Figure 13-18. Normal vs. Large Down Scaling for Scale Factor = 5.0
Figure 13-19. Vertical Filter Parameter Table
Parameter WordDescription
Upper 2 bytes Lower 2 bytes
Input Image Start Address Start address of X0Y0 (byte address)
U Counter Start Fraction
Input Image Line Offset
Starting value: may be 0.5, etc. for interspersed convert;Line offset from X0Y0 to X0Y1
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The input and output addresses are the byte addressesof their respective tables. The output address needs tobe 64-byte aligned.
The input and output line offsets define the difference inbytes from the address of the first pixel in the first line tothe address of the first pixel in the second line for their re-spective blocks. The line offset must be constant for alllines in each table. The line offset allows some space be-tween the end of one line and the start of the next line. Italso allows the ICP to scale and filter a subset of an ex-isting image, such as magnifying a portion of an image.Offset values are 16-bit, two’s complement integer val-ues.
Vertical filtering has a restriction on input and output lineoffset values: they must be positive, and they must bemultiples of 64. Note that this only applies to the line-to-line spacing. Even with this restriction, input images maybe any height and any width and may start at any byteaddress. Also, image subsets of arbitrary height andwidth can be used. As long as the original image has aline offset which is a multiple of 64, all subsets of that im-age will also automatically have a line offset, which is amultiple of 64 - the same as the original image. All imag-es should have line offsets which are multiples of 64 asgood programming practice, even though this restrictiononly applies to vertical filtering. If an image does not havea multiple of 64 line offset, it can be converted to that byusing horizontal filtering in the image block move modewith the output offset value being a multiple of 64.
The input and output image height and width values arethe height in lines and width in pixels per line for their re-spective images. The height and width are 16-bit positivebinary numbers between 0 and 64K-1.
The Integer increment and Fraction increment values arethe scaling parameters. The Integer value is a 16-bit in-teger, and the Fraction value is a positive binary fractionbetween 0 and 0.99999+. For up scaling (output imagebigger), the increment value is the inverse of the scalingvalue. If you are upscaling by a factor of 2.5, the incre-ment value will be the inverse of 2.50 = 0.40. The Integerincrement value will be 0 and the Fraction increment val-ue will be 0.40. For down scaling, the increment value isequal to the scaling value. If you are down scaling by 2.5(output image smaller), the Integer increment value willbe 2, and the Fraction increment value will be 0.500.
To perform scaling, the Integer and Fractional incrementvalues must be generated and placed in the parameter
table. The simplest way to generate these values in com-mon computer languages such as C is as follows:
1. Generate the Increment Value as a floating point number = Input Height / Output Height
2. Multiply the Increment Value by 655363. Convert the result to a Long Integer (32 bits). The up-
per 16 bits of the Long integer will be the Integer in-crement value, and the lower 16 bits will be the Frac-tional value.
4. Store the 32-bit Long integer in the parameter table as the combined Integer and Fractional increment val-ues.
The Start Fraction defines the starting value in the scal-ing counter for each line. It is a 16-bit, two’s complementfractional value between -0.500 and 0.49999+. This val-ue is placed in the The Start Fraction allows the inputdata to be offset by up to half a line, referred to the inputpixel grid. It is set to zero for all conventional YUV inputdata.
13.6.9.3 Control Word Format
The Control word provides bit fields which affect the ver-tical filtering operation. The format of the Control word isas follows.
Bit Name Function
15 Bypass Bypass filter. Picks nearest input line and passes it to output unfiltered.
When Bypass is set & scale factor is 1.0, this results in an image block move
The Bypass bit causes the data to bypass the 5-tap filter.The scaling operation selects the center line, and thisline is passed to the filter output. No filtering or interpola-tion is provided. If the scaling factor is 1.0, the result is animage block move where the image is moved from onepart of SDRAM to another without modification. If thescaling factor is other than 1.0, the effective algorithm isline picking, where the input line nearest the output linelocation is used as the output line.
13.6.10 Horizontal Filter with RGB/YUV Conversion to PCI or SDRAM
This routine moves an N x M image in YUV 4:2:2, YUV4:2:0 or YUV 4:1:1 format from SDRAM to the PCI bus orto SDRAM. The image is scaled and filtered in the hori-
Fraction increment Integer increment Increment value for U = 1/scale factor
Input Image Height Input Image Width Height and width in input lines and pixels
Output Image Start Address Start address of X0Y0 (byte address)
Control Output Image Line Offset
Control Word; Line offset from X0Y0 to X0Y1
Output Image Height Output Image Width Height and width in output lines and pixels
Figure 13-19. Vertical Filter Parameter Table
Parameter WordDescription
Upper 2 bytes Lower 2 bytes
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zontal direction during the move. Optional bit maskingand/or RGB overlay may be used during the move whenPCI output is specified.
13.6.10.1 Algorithms
The routine reads image data from SDRAM using the Y,U, and V address counters, scales and filters the data inthe horizontal direction and writes it to the PCI interfaceor SDRAM. The 5-tap filter scales and filters the data.The LSB Increment value for each of the Y, U and V com-ponents supplied by the parameter table determines thescaling. Separate scaling factors allows YUV 4:2:2 inter-spersed to co-sited transformation as the data is beingfiltered. The scaled and filtered data is converted to RGBor YUV format before being sent to the PCI interface orto SDRAM. In the PCI output case, overlay data with al-pha blending and chroma keying can be added to theoutput image, and the output image can be gated by a bitmask before it is sent to the PCI interface.
The routine reads and writes a line at a time until the fullimage is transferred. The filter mirrors the ends of eachline to provide the extra pixels needed by the filter at theends of each line.
13.6.10.2 Parameter Table
The parameter table, as shown in Table 13-14, suppliesthe input and output starting addresses and offsets for Y,
U, V, OL, B and Z, the image height in lines and width inpixels, and the scale factors for each component.
The input and output addresses are the byte addressesof their respective tables. They need not be word or blockaligned. Note the following restriction: In packed RGB24to PCI operation the output address offset from the startof video memory must be a multiple of 6 bytes, i.e. on aneven pixel boundary.
The input and output line offsets define the difference inbytes from the address of the first pixel in the first line tothe address of the first pixel in the second line for their re-spective blocks. The line offset must be constant for alllines in each table. The line offset allows some space be-tween the end of one line and the start of the next line. Italso allows the ICP to scale and filter a subset of an ex-isting image, such as magnifying a portion of an image.There are no restrictions on line offset values other thanthey must be 16-bit, two’s complement integer values.(Note that this allows negative offsets. You can use thisto flip an image vertically.)
The input and output image height and width values arethe height in lines and width in pixels per line for their re-spective images. The height and width are 16-bit positivebinary numbers between 0 and 64K-1.
Table 13-14. Horizontal Filter to RGB Output Parameter Table
Parameter WordDescription
Upper 2 bytes Lower 2 bytes
Input Image Y Start Address Y Start address of X0Y0 (byte address)
Y Counter Start Fraction
Input Image Y Line Offset
Starting value: may be 0.5, etc. for interspersed convert;Y Line offset from X0Y0 to X0Y1
Y Fraction increment Y Integer increment Increment value for U = 1/scale factor
Y Input Image Height Y Input Image Width Y& Height and width in pixels
Input Image U Start Address U Start address of X0Y0 (byte address)
U Counter Start Fraction
Input Image U Line Offset
Starting value: may be 0.5, etc. for interspersed convert;U Line offset from X0Y0 to X0Y1
U Fraction increment U Integer increment Increment value for Y = 1/scale factor
U Input Image Height U Input Image Width U Height and width in pixels
Input Image V Start Address V Start address of X0Y0 (byte address)
V Counter Start Fraction
Input Image V Line Offset
Starting value: may be 0.5, etc. for interspersed convert;V Line offset from X0Y0 to X0Y1
V Fraction increment V Integer increment Increment value for V = 1/scale factor
V Input Image Height V Input Image Width V Height and width in pixels
Output Image Start Address Start address of X0Y0 (byte address)
Control Output Image Line Offset
Input & output formats & control bits; Line offset from X0Y0 to X0Y1
Output Image Height Output Image Width Height and width in output pixels
Bit Map Image Start Address Start address of X0Y0 (byte address)
0 Bit Map Image Line Offset
Line offset from X0Y0 to X0Y1
RGB Overlay Start Address Start address of X0Y0 (byte address)
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Philips Semiconductors Image Co-Processor
The Integer increment and Fraction increment values arethe scaling parameters. there is a separate scaling pa-rameter for each of the Y, U and V input components.The Integer value is a 16-bit integer, and the Fraction val-ue is a positive binary fraction between 0 and 0.99999+.For up scaling (output image bigger), the increment val-ue is the inverse of the scaling value. If you are upscalingby a factor of 2.5, the increment value will be the inverseof 2.50 = 0.40. The Integer increment value will be 0 andthe Fraction increment value will be 0.40. For down scal-ing, the increment value is equal to the scaling value. Ifyou are down scaling by 2.5 (output image smaller), theInteger increment value will be 2, and the Fraction incre-ment value will be 0.500.
To perform scaling, the Integer and Fractional incrementvalues must be generated and placed in the parametertable. The simplest way to generate these values in com-mon computer languages such as C is as follows:
1. Generate the Increment Value as a floating point number = Input Width / Output Width
2. Multiply the Increment Value by 655363. Convert the result to a Long Integer (32 bits). The up-
per 16 bits of the Long integer will be the Integer in-crement value, and the lower 16 bits will be the Frac-tional value.
4. Store the 32-bit Long integer in the parameter table as the combined Integer and Fractional increment val-ues.
For YUV 4:2:2 or YUV 4:2:0 input data and RGB outputdata, the scaling factor for U and V must be twice thescaling factor for Y, unless YUV4:2:2 sequencing is usedfor speed. In YUV 4:2:2 or YUV 4:2:0 data, the horizontalcomponents of U and V are half those of Y. The U and Vmust be upscaled by 2 to generate a YUV 4:4:4 formatinternally for YUV to RGB conversion. For YUV 4:1:1 in-put data, the U and V components must be upscaled bya factor of 4 to generate the required internal YUV 4:4:4format.
The Start Fraction defines the starting value in the scal-ing counter for each line. It is a 16-bit, two’s complementfractional value between -0.500 and 0.49999+. The StartFraction allows the input data to be offset by up to half apixel, referred to the input pixel grid. It is zero for Y andfor UV co-sited data, and is set to minus 0.25 (C000) forinterspersed to co-sited conversion of U and V data. Theminus 0.25 value effectively shifts the U and V data to-ward the start of the line by 1/4 pixel, the amount requiredfor conversion.
The Alpha 1 and Alpha 0 values are 8-bit fields within the16-bit Alpha field. These values are loaded into the Alpha1 and Alpha 0 registers, respectively, for use by RGB15+α and YUV 4:2:2+α overlay formats in alpha blend-ing.
The Overlay start and end pixels and lines define thestart and end pixels and lines within the output image forthe overlay. The first pixel of the overlay image will beblended with the pixel at the Overlay Start Pixel andOverlay Start Line in the output image.
13.6.10.3 Control Word Format
The Control word provides bit fields which affect the hor-izontal filtering operation. The format of the Control wordis as follows.
Bits Name Function
15 Bypass Normally set to 0 to enable filtering. Can be set to 1 to accomplish data move without filtering.
14 422SEQ 4:2:2 Sequence bit. Used with YUV 4:2:2 output
13 YUV420 YUV 4:2:0 input format
12 OEN Overlay enable. Valid only for PCI out-put
11 PCI PCI output enable. Otherwise SDRAM output
10 BEN Bit mask enable. Valid only for PCI output
9 GETB Large down scaling bit. Picks five input pixels nearest 5 output pixels and passes to filter.
Equivalent to filter bypass + 5-tap filter of output pixels. LSB value = 0 for fil-tering.
8 OLLE Overlay little endian enable
7-6 OFRM Overlay format
0 = RGB 24+α1 = RGB 15+α2 = YUV 4:2:2+α
5 CHK Chroma keying enable
4 LE RGB output little endian enable
3-0 RGB RGB Output Code
0 = YUV 4:2:2+α1 = YUV 4:2:2
2 = RGB 24+α
Alpha 1 & Alpha 0 Overlay Line Offset
Alpha 1 & Alpha 0 blend code for RGB15+α, etc.;Line offset from X0Y0 to X0Y1
Overlay End pixel Overlay Start Pixel Start and end pixels along line
Overlay End Line Overlay Start Line Start and end lines in frame
Table 13-14. Horizontal Filter to RGB Output Parameter Table
Parameter WordDescription
Upper 2 bytes Lower 2 bytes
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TM1100 Preliminary Data Book Philips Semiconductors
3 = RGB 24 packed
4 = RGB 8A (RGB 233)
5 = RGB 8R (RGB 332)
6 = RGB15+α7 = RGB 16
The 422SEQ bit controls the internal sequencing of theYUV to RGB operation. It is set to one when YUV 4:2:2output is selected. When 422SEQ is zero, normal RGBoutput is assumed. In this mode, the input is YUV 4:2:2or YUV 4:2:0, and the output is RGB. To generate theRGB output, the YUV 4:2:2 or YUV 4:2:0 input must beupscaled to YUV 4:4:4 before conversion to RGB. Thismeans the scaling factor for U and V must be twice thescaling factor for Y. The internal sequencing of the filterin this case is UVY, UVY, UVY to generate RGB, RGB,RGB. For YUV 4:2:2 output formats, no upscaling of Uand V is required. In this case, the 422SEQ bit is set toone, and the filter sequence is UVYY, UVYY, UVYY.
The 422SEQ bit can be set in RGB output mode to de-crease the processing time for the image at the expenseof color bandwidth and some corresponding decrease inpicture quality. If the 422SEQ bit is set for RGB output,the filter will perform the UVYY sequence. In this case,the U and V components are not upscaled by 2, and theYUV to RGB converter updates its U and V componentsevery other pixel. In the normal case (422SEQ=0), ittakes 6 clocks to generate two RGB pixels. In the422SEQ=1 case, it takes 4 clocks to generate two RGBpixels, reducing processing time by 33%.
The YUV420 bit indicates that the input data is in YUV4:2:0 format. In YUV 4:2:0 format, the U and V compo-nents are half the width and half the height of the Y data.YUV 4:2:0 data is normally converted to YUV 4:2:2 databy a separate vertical upscaling by a factor of 2.0 for bestquality. The YUV420 bit allows using YUV 4:2:0 data di-rectly but with some quality degradation. When YUV420is set, the ICP up scales the data vertically by line dupli-cation. Each U and V input line is used twice. The sepa-rate vertical scaling step is eliminated at the expense ofsome quality since the lines are simply duplicated ratherthan being fully scaled and filtered.
The OEN bit enables overlay. You set it to one if an over-lay is used, zero if not. Overlays are only valid for PCIoutput.
The PCI bit selects PCI as the output port for the ICP da-ta. A one selects PCI output; a zero selects SDRAM out-put.
The BEN bit enables bit masking. You set it to one if bitmasking is used, zero if not. Bit masking is only valid forPCI output.
The GETB bit is an optional bit for large (> 4) down scal-ing. When GETB is zero (normal operation), the 5-tap fil-ter receives the pixel nearest the output pixel as its cen-ter pixel plus the two adjacent input pixels on either sideof this pixel to form the five filter inputs. When GETB isset, the filter receives the pixel nearest the output pixelas its center pixel plus the two adjacent output pixels oneither side of this pixel to form the five filter inputs. Theeffective algorithm is pixel picking plus 5-tap filtering ofthe result. GETB also forces the scaling LSB value to ze-ro, since output pixels are being filtered and no interpo-lation is used.
The OFRM bit field selects the overlay data format, asshown in the Control word format list.
The CHK bit enables chroma keying. You set it to one ifchroma keying is used, zero if not.
The OLLE bit sets the endian-ness of the overlay data in-put. You set it to one if the overlay data is little-endian,zero if big endian. The OLLE bit is normally set to thesame value as the LE bit in the Status register.
The LE bit sets the endian-ness of the RGB/YUV outputdata. You set it to one if the output data is little-endian,zero if big endian. The LE bit is normally set to the samevalue as the LE bit in the Status register.
The RGB field defines the output data format, as shownin the Control word format list.
Important Note: You must set the ICP DMA Enable bit(IE) in the BIU_CTL register of the PCI interface for RGBoutput to PCI. This bit must be set before initiating RGBto PCI operations, or the ICP will stall waiting for the PCIto become ready.
13-28 PRELIMINARY INFORMATION File: icp.fm5, modified 7/26/99
Variable Length Decoder Chapter 14
by Gene Pinkston and Selliah Rathnam
14.1 VLD OVERVIEW
The VLD block Huffman decodes MPEG1 and MPEG2(Main Profile) video bitstreams[1-3]. This document de-scribes a programmers view of the VLD. The VLD readsan MPEG stream from main memory, decodes the bit-stream under the control of DSPCPU and outputs twodata streams. The output data streams contain: 1) mac-roblock header information and 2) the run length encod-ed DCT coefficients. The output data streams are storedin the main memory buffers.
The VLD unit, enabled by the DSPCPU, operates inde-pendently during the slice decoding process. The re-maining decoding of the MPEG stream is carried out bythe DSPCPU.
14.2 VLD OPERATION
The VLD can be initialized by the hardware or softwarereset operations. The hardware reset is provided by theexternal TRI_RESET# pin. The software reset is provid-
ed by one of the VLD commands. The DSPCPU controlsthe VLD through the VLD command register. There arefive commands supported by the VLD:
• Shift the bitstream by some number of bits (a maxi-mum of 15-bit shift)
• Search for the next start code• Reset the VLD• Parse some number of macroblocks• Flush VLD output buffers to main memory
The normal mode of operation will be for the DSPCPU torequest the VLD to parse some number of macroblocks.Once the VLD has begun parsing macroblocks it maystop for any one of the following reasons:
• The command was completed with no exceptions • A start code was detected• An error was encountered in the bitstream• The VLD input DMA completed and the VLD is
stalled waiting for more data
HWY_BUS
RD Buffer
Macroblock
DMA
ENGINE
Controlstatus
status
MMIO & CONF REGs
SHIFTER
start_code_ detector
mb_addr
mb_type
cbp
dmv &motion
dct_lum
dct_chr
dctcoef (0)
dctcoef (1)
escape_codes
VLD
FLOW
Control
Interrupt
Run-Level
Hdr WR FIFO
WR FIFO
Figure 14-1. VLD Block Diagram
64 Bytes
64 Bytes
64 Bytes
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• One of the VLD output DMAs has completed and theVLD is stalled because the output FIFO is full
The DSPCPU can be interrupted whenever the VLDhalts.
Consider the case in which the VLD has encountered astart code. At this point, the VLD will halt and set the sta-tus flag which indicates that a start code has been de-tected. This event will generate an interrupt to theDSPCPU (if corresponding interrupt is enabled). Uponentering the interrupt routine, the DSPCPU will read theVLD status register to determine the source of the inter-rupt. Once it has been determined that a start code hasbeen encountered, the CPU will read 8 bits from the VLDshift register to determine the type of start code that hasbeen encountered. If a slice start code has been encoun-tered, the DSPCPU will read from the shift register theslice quantization scale and any extra slice information.The slice quantization scale will then be written back tothe VLD quantizer-scale register. Before exiting the inter-rupt routine, the DSPCPU will clear the start code detect-ed status bit in the status register and issue a new com-mand to process the remaining macroblocks.
14.3 DECODING UP TO A SLICE
MPEG decoding up to the slice layer is carried out by theDSPCPU and the VLD. The VLD is controlled by the
DSPCPU for the decoding of all parameters up to theslice-start code. During this process, the DSPCPU readsfrom the VLD_SR register which contains the next 16 bitsof the bitstream. The DSPCPU also issues shift com-mands to the VLD in order to advance the contents of theshift register by the specified number of bits. TheDSPCPU may also command the VLD to advance to thenext start code. Refer Table 14-6 for the complete VLDcommands and their functions. Once at the slice layer,the VLD operates independently for the entire slice de-coding. The slice decoding starts once the DSPCPU is-sues a parse command.
14.4 VLD INPUT
Input to the VLD is controlled by the VLD input DMA en-gine. The input DMA engine is programmed by theDSPCPU to read from the main memory. The DSPCPUprograms this DMA engine by writing the address andthe length of the main memory buffer containing theMPEG stream. The address of the buffer is written to theVLD_BIT_ADR register. The length, in bytes, of the buff-er is written to the VLD_BIT_CNT register.
The VLD reads data from main memory into an internal64-byte FIFO. The VLD processing engine then readsdata from the FIFO as needed. Once this internal FIFOis empty the VLD reads more data from main memory.
Esc Count MBA Inc MB Type Mot Type DCT Type MV count MV Format DMV
MV Field Sel [0][0] Motion Code [0][0][1]Motion Residual [0][0][0] Motion Residual [0][0][1]Motion Code [0][0][0]
MV Field Sel [1][0] Motion Code [1][0][1]Motion Residual [1][0][0] Motion Residual [1][0][1]Motion Code [1][0][0]
MV Field Sel [0][1] Motion Code [0][1][1]Motion Residual [0][1][0] Motion Residual [0][1][1]Motion Code [0][1][0]
MV Field Sel [1][1] Motion Code [1][1][1]Motion Residual [1][1][0] Motion Residual [1][1][1]Motion Code [1][1][0]
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Philips Semiconductors Variable Length Decoder
The VLD_BIT_ADR and VLD_BIT_CNT registers areupdated after each read from main memory. The contentof the VLD_BIT_ADR register reflects the next addressfrom which the bitstream data will be fetched. The con-tent of the VLD_BIT_CNT register reflects the number ofbytes remaining to be read before the current transfer iscomplete. When the number of bytes remaining to beread from main memory becomes zero, a status flag isset and an interrupt can be generated to the DSPCPU.The DSPCPU will provide the new bitstream buffer ad-dress and the number of bytes in the bitstream buffer tothe VLD.
14.5 VLD OUTPUT
The VLD outputs two data streams which are writtenback to main memory by two output DMA engines.These DMA engines are programmed by the DSPCPU.One of the output streams contains macroblock headerinformation and the other contains run-length encodedDCT coefficients. Each DMA engine contains a 64-byteFIFO which is transferred to main memory once it is full.The main memory address and count for the macroblockheader output are contained in the VLD_MBH_ADR andVLD_MBH_CNT registers respectively. The main mem-ory address and count for the DCT coefficient output arecontained in the VLD_RL_ADR and VLD_RL_CNT reg-isters respectively. The counts for both the macroblockheader and coefficient data are expressed in terms of 32-bit (4 bytes) words.
14.5.1 Macroblock Header Output Data
For each MPEG2 macroblock parsed by the VLD, six 32-bit words of macroblock header information will be outputfrom the VLD. Figure 14-2 pictures the layout of the VLDoutput, while the fields are described in Table 14-1. Notethat these fields may or may not be valid depending uponthe MPEG2 video standard[2]. For example, motion vec-tors are not valid for intra coded macroblocks. Similarly,‘DCT Type’ is not valid for field pictures.
For each MPEG1 macroblock parsed by the VLD, four32-bit words of macroblock header information will beoutput from the VLD. Figure 14-3 pictures the layout ofthe VLD output, while the fields are described inTable 14-2. Note that these fields may or may not be val-id depending upon the MPEG1 video standard[1].
Table 14-1. References for the MPEG-2 Macroblock Header Data
Item Default value
References from MPEG-2 Video Standard, IS 13818-2
document
Esc Count 0 Section 6.2.5
MBA Inc - Section 6.2.5 and Table B-1
MB Type Unde-fined
Section 6.2.5.1 and Tables B-2, B-3, and B-4; Only 5 Msb bits from the tables are used
MotType Unde-fined
Section 6.2.5.1; Field or Frame motion type will be decided by the user
DCT Type Unde-fined
Section 6.2.5.1
MV Count Unde-fined
Tables 6-17 and 6-18. The MV Count value is one less than the value from the tables.
MV Format Unde-fined
Tables 6-17 and 6-18
DMV Unde-fined
Tables 6-17 and 6-17
MV Field Sel[0]0] to MV Field Sel[1][1]
Unde-fined
Section 6.2.5 and 6.2.5.2
Motion Code[0][0][0] to Motion Code[1][1][1]
Unde-fined
Section 6.2.5.2.1 and Table B-10
Motion Resid-ual[0][0][0] to Motion Resid-ual[1][1][1]
Unde-fined
Section 6.2.5.2.1; the corre-sponding rsize bits are extracted from the bitstream and stored as left justified; to get the final value shift the given number by 8 (corre-sponding rsize). The rsize val-ues are stored in VLD_PI register
dmvector[1] and dmvector[0]
Unde-fined
Section 6.2.5.2.1 and Table B-11; signed 2-bit integer from Table B11.
CBP - Section 6.2.5, 6.2.5.3 and Table B-9
Quant Scale - Section 6.2.5; 5-bit from bit-stream and use Table 7-6 to compute the quant scale value.
Table 14-2. References for the MPEG-1 Macroblock Header data
Item Default value
References from IS 11172-2 document
Esc Count 0 Section 2.4.3.6
MBA Inc - Section 2.4.3.6
MB Type Unde-fined
Section 2.4.3.6 and Tables B-2a to B2d
Motion Code[0][0][0] to Motion Code[0][1][1]
Unde-fined
Section 2.4.2.7 and Table B-4
Motion Resid-ual[0][0][0] to Motion Resid-ual[0][1][1]
Unde-fined
Section 2.4.2.7;the corre-sponding rsize bits are extracted from the bitstream and stored as left justified; to get the final value shift the given number by (8 - corre-sponding rsize). The rsize val-ues are stored in VLD_PI register.
CBP - Section 2.4.3.6 and Table B-3
Quant Scale - Section 2.4.2.7
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14.5.2 Run-Level Output Data
The DCT coefficients associated with the macroblock areoutput to a separate memory area and each DCT coeffi-cient is represented as one 32-bit quantity (16 bits of runand 16 bits of level). For intra blocks, the DC term is ex-pressed as 16 bits of DC size and a 16-bit value whosemost significant bits (the number of bits used for DC levelis determined by DC size) represent the DC level. Eachblock of DCT coefficients is terminated by a run value of0xff.
14.6 VLD TIME SHARING
The TM1100 VLD is targeted for a single bitstream de-code and there is no provision to decode more than onebitstream by using the VLD in time multiplexed mode.However internal development has shown that up to 4 si-multaneous MPEG1 bitstreams can be decoded. Proce-dure is out of the topic of this data-book and can beasked through the customer support.
14.7 MMIO REGISTERS
To ensure compatibility with future devices, any unde-fined MMIO bits should be ignored when read, and writ-ten as zeroes.
14.7.1 VLD Status (VLD_STATUS)
This register contains current status information which ismost pertinent to the normal operation of an MPEG videodecode application. VLD status description is detailed inTable 14-3 and pictured in Figure 14-4. Default value (af-ter hardware reset) is 0.
Interrupts can be enabled for any of the defined statusbits (see following VLD_IMASK description). Acknowl-edgment of the interrupt is done by writing a one to thecorresponding bit in VLD_STATUS register. Writing aone to the bits one through five clears the correspondingbits. However bit 0 (COMMAND_DONE) is cleared onlyby issuing a new command. Writing a one to bit 0 of thestatus register will result in undefined behavior of theVLD. Note that several status bits may be asserted si-multaneously. Thus it is recommended to use level trig-gered interrupts (see Section 3.5.3.6 on page 3-11) andcarefully acknowledge the interrupt.
14.7.2 VLD Interrupt Enable (VLD_IMASK)
This register allows the DSPCPU to control the initiationof the interrupt for the corresponding bits in the VLD Sta-tus Register. Writing a one into any of the definedVLD_IMASK bits enables the interrupt for the corre-sponding bit in the status register (VLD_STATUS). De-fault value (after hardware reset) is 0.
Figure 14-3. MPEG1 Macroblock Header Output Format
w1
w2
w3
w0
MB
1M
B2
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Philips Semiconductors Variable Length Decoder
14.7.3 VLD Control (VLD_CTL)
The VLD_CTL register has one bit in order to operate theVLD unit in Little-endian(1) or Big-endian(0) mode. De-fault value (after hardware reset) is 0.
14.8 VLD DMA REGISTERS
There are one input DMA engine and two output DMAengines in the VLD block. Each of the three DMA en-gines (or channels) for the VLD is controlled by twoMMIO registers. The address register always containsthe address of the next SDRAM transaction. The countregister always indicates the amount of data to be trans-ferred to or from main memory. A DMA completes whenits count reaches zero. Once a DMA count register be-comes zero, a bit is set in the status register and the
DSPCPU can be interrupted. The DSPCPU sets a non-zero value to a DMA count register to initiate a new DMAtransaction. The input count register always containsnumber of bytes to be fetched from the main memory.The output count registers always contain the number ofwords (4 bytes) to be written to the main memory.
Note that both of the DMA output engines write only to64-byte aligned addresses and they always write 64bytes. When flushing the DMA output FIFOs there maynot be 64 bytes of valid data at the time the flush com-mand is received. In this case, 64 bytes are still written tothe main memory. The valid bytes can be determinedfrom the count register value before issuing the flushcommand. The valid data always resides in the first Nbytes while the last 64-N bytes will contain random dataand should be ignored.
14.8.1 DMA Input
The bitstream input to the VLD is controlled byVLD_BIT_ADR and VLD_BIT_CNT MMIO registers.VLD_BIT_ADR contains the main memory address forthe next read from the main memory to the VLD inputFIFO. VLD_BIT_CNT register contains the number ofbytes remaining to be read before the current DMA iscompleted.
The VLD input address is byte aligned.
14.8.2 Macroblock Header Output DMA
The macroblock header output of the VLD is controlledby VLD_MBH_ADR and VLD_MBH_CNT registers.VLD_MBH_ADR contains the address of the next writeof macroblock header data to the main memory.VLD_MBH_CNT contains the remaining number ofwords (4 bytes) to write before the current DMA expires.
The macroblock header output address is 64-bytealigned.
14.8.3 Run-Level Output DMA
The run-level output of the VLD is controlled byVLD_RL_ADR and VLD_RL_CNT. VLD_RL_ADR con-tains the address of the next write of macroblock headerdata to the main memory. VLD_RL_CNT contains thenumber of 4-byte writes remaining before the currentDMA expires.
The run-level buffer address is 64-byte aligned.
Table 14-3. VLD_STATUS register
Name Size (bits) Description
COMMAND_DONE 1 Indicates successful comple-tion of current command
STARTCODE 1 VLD encountered 0x000001 while executing parse or next start code command
ERROR 1 VLD encountered an illegal Huffman code or an unex-pected start code
DMA_IN_DONE 1 DMA transfer of given SDRAM buffer has completed and VLD is stalled waiting on more main memory input data; DSPCPU is responsible to provide the new main memory buffer to VLD
MBH_OUT_DONE 1 Macroblock Header DMA transfer has completed
RL_OUT_DONE 1 Run-level DMA transfer has completed
Table 14-4. VLD Control (R/W)
Name Size (bits) Description
Reserved 1
Little Endian 1 Forces VLD to operate in Little Endian Mode when set to 1.
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Figure 14-4. VLD MMIO Registers Layout.
31 0371115192327
MMIO_baseoffset:
VLD_COMMAND (r/w)0x10 2800
VLD_STATUS (r)0x10 2810
RL_OUT_DONE
MBH_OUT_DONE
DMA_IN_DONE
ERRORSTARTCODE
COMMAND_DONE
VLD_CTL (r/w)0x10 2818
COMMAND COUNT
31 0371115192327
31 0371115192327
31 0371115192327
VLD_SR (r)0x10 2804
31 0371115192327
31 0371115192327
31 0371115192327
VALUE
VLD_QS (r/w)0x10 2808
VLD_PI (r/w)0x10 280C
QS
VBRS HBRS VFRS HFRS
MPEG2CONCEAL_MV
INTRA_VLC
FPFD
PICT_STRUC
PICT_TYPE
VLD_RL_CNT (r/w)0x10 283031 0371115192327
VLD_BIT_ADR (r/w)0x10 281C
VLD_BIT_CNT (r/w)0x10 282031 0371115192327
VLD_MBH_ADR (r/w)0x10 282431 0371115192327
VLD_MBH_CNT (r/w)0x10 282831 0371115192327
VLD_RL_ADR (r/w)0x10 282C31 0371115192327
LITTLE_ENDIAN
BIT_ADR
MBH_ADR
RL_ADR
BIT_CNT
RL_CNT
MBH_CNT
VLD_IMASK (r/w)0x10 2814 Int. Enables
0 0 0 0 0 0
0 0 0 0 0 0
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14.9 VLD OPERATIONAL REGISTERS
14.9.1 VLD Command (VLD_COMMAND)
This register indicates the next action to be taken by theVLD. Some commands have an associated count whichresides in the least significant 8 bits of this register.There are currently five commands recognized by theVLD block:
• Shift the bitstream by “count” bits (“count” must beless than or equal to 15)
• Parse “count” un-skipped macroblocks• Search for the next start code• Reset the VLD• Flush the VLD output buffers
The DSPCPU must wait for the VLD to halt before thenext command can be issued. Note that there are sever-al ways in which a command may complete. Only a suc-
cessful completion is indicated by theCOMMAND_DONE bit in the status register. A commandmay complete unsuccessfully if a start code or an error isencountered before the requested number of items hasbeen processed. Note also that expiration of a DMAcount does not constitute completion of a command.When a DMA count expires the VLD is stalled as it waitsfor a new DMA to be initiated. It is not halted. Default val-ue (after hardware reset) is 0. VLD_COMMAND fieldsare described in Table 14-5 and the different commandsexplained in Table 14-6.
Table 14-5. VLD Command Register
Name Size (bits) Description
COUNT 8 Count for current command
COMMAND 4 VLD command to be exe-cuted
Table 14-6. VLD Commands
Command Field coding
Flags Set after Completion of the
Command Description
Shift the bit-stream by “count” bits
1 COMMAND_DONEorDMA_IN_DONE
VLD shifts the number of bits in its internal shift register. The shift register value is available in the VLD_SR register. The DMA_IN_DONE flag will be set when VLD runs out of data from input FIFO.The flag is reset by issuing the new command.
Search for the next start code
3 STARTCODEor COMMAND_DONEorDMA_IN_DONE
VLD search for a start code. The search code has 0x000001 prefix and an addi-tional 8-bit value.The DMA_IN_DONE flag will be set when VLD runs out of data from input FIFO.The STARTCODE detected flag is reset by writing a ‘1’ value to the flag.The COMMAND_DONE flag is reset by issuing the new command.
Reset the VLD 4 None Refer section 14.12 for more details
Parse for a given number of mac-roblocks
2 COMMAND_DONEorSTARTCODEorERRORorDMA_IN_DONE
VLD parses for a given number of un-skipped macroblocks and the associated run-level values. COUNT field will indicate the remaining macroblocks to parse. Note that this number is slightly inaccurate since a parsed macroblock can still be in internal 64-byte FIFO.If VLD encounters a start code, the parsing action will be terminated and VLD sets only the STARTCODE detected flag. If VLD parses the given number of un-skipped macroblocks without encountering a start code, VLD will set the COMMAND_DONE flag.The ERROR flag will be set when VLD encounters an error while parsing the bit-stream.The DMA_IN_DONE flag will be set when VLD runs out of data from input FIFO.The STARTCODE detected flag is reset by writing a ‘1’ value to the flag.The COMMAND_DONE flag is reset by issuing the new command.
Flush the VLD output buffer
8 COMMAND_DONE VLD flushes the remaining macroblock header data and the remaining run-level data to the main memory. The highway byte-enables will be used in order to write only the valid data to the main memory. Only the valid word count values written to the main memory will be subtracted from the VLD_MBH_CNT and the VLD_RL_CNT registers.
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14.9.2 VLD Shift Register (VLD_SR)
This read only register is a shadow of the VLD’s opera-tional shift register and it allows the DSPCPU to accessthe bitstream through the VLD. Bits 0 through 15 are thecurrent contents of the VLD shift register. Bits 16 to 31are RESERVED and should be treated as undefined bythe programmer.
14.9.3 VLD Quantizer Scale (VLD_QS)
This 5-bit register contains the quantization scale code(from the slice header) to be output by the VLD until it isoverridden by a macroblock quantizer scale code. Thequantizer scale code is part of the macroblock headeroutput.
14.9.4 VLD Picture Info (VLD_PI)
This 32-bit register contains the picture layer informationnecessary for the VLD to parse the macroblocks withinthat picture. Again, the values for each of these fields aredetermined by the appropriate standard (MPEG [1-3]).
14.10 ERROR HANDLING
Upon encountering a bitstream error the VLD will set thebitstream-error flag (ERROR) in the VLD_STATUS reg-ister and interrupt the DSPCPU, if the interrupt is en-
abled. Note that if a start code is present (in the VLD shiftregister) when an error is detected, then both the startcode and the error bits will be set. A separate flush com-mand is required to flush any valid data in the run-leveland macroblock header output buffers.
The DSPCPU de-asserts the ERROR flags by writing a‘1’ to the ERROR flag.
14.11 INTERRUPT
The interrupt source number for the VLD is 14 and itshould be set in level sensitive mode (see Section3.5.3.6 on page 3-11).
14.12 RESET
The VLD block is reset by a hardware reset or a softwarereset. The hardware reset signal is generated from theexternal pin TRI_RESET#. The software reset is initiatedby writing a ‘Reset VLD’ command in theVLD_COMMAND register. Refer Table 14-8 for the de-tails on the software reset procedure.
14.13 ENDIAN-NESS
VLD supports little-endian and big-endian modes of op-erations. Refer to Appendix C for the endian-ness spec-ification of the VLD input and output data.
14.14 REFERENCES
[1] ISO/IEC IS 13818-2, International Standard (1994),MPEG-2 Video.
[2] ISO/IEC IS 11172-2, International Standard (1992),MPEG-1 Video.
[3] MPEG Video Compression Standard, by Joan L.Mitchell, William B. Pennebaker, Chad E. Fogg, Didier J.LeGall; ITP publication.
Table 14-7. VLD Picture Info Register (r/w)
Name Size(bits) Description
PICT_TYPE (picture type)
2 I, P, or B picture
PICT_STRUC (picture structure)
2 field or frame picture
FPFD (frame predic-tion frame dct)
1 specifies that this picture uses only frame prediction and frame dct
INTRA_VLC 1 Use DCT table zero or one
CONCEAL_MV 1 concealment vectors present in the bitstream
reserved 6 Reserved for future expan-sion
MPEG2 mode 1 switches VLD between mpeg1 and mpeg2 decod-ing. Value ‘1’ means mpeg2 mode
reserved 2 reserved
HFRS (horizontal for-ward rsize)
4 size of residual motion vec-tor
VFRS (vertical forward rsize)
4 size of residual motion vec-tor
HBRS (horizontal back-ward rsize)
4 size of residual motion vec-tor
VBRS (vertical back-ward rsize)
4 size of residual motion vec-tor
Table 14-8. Software Reset Procedure
Cycle no. Action Remarks
i DSPCPU issues the ‘Reset the VLD’ command by writ-ing the required value in the VLD_COMMAND register.
i to j VLD will complete the pend-ing, if any, highway transac-tions.
Any highway transac-tions, once started, will not be aborted in the middle
j+1 VLD will perform the full reset.
All status and control registers are reset and all the buffers are made empty.MMIO Registers initial-ized to zero includes VLD_STATUS.
14-8 PRELIMINARY INFORMATION File: vld.fm5, modified 7/26/99
I2C Interface Chapter 15
by Essam Abu-ghoush, Robert Nichols
15.1 I2C OVERVIEW
TM1100 includes an I2C interface which can be used tocontrol many different multimedia devices such as:
• DMSDs - Digital Multi-Standard Decoders• DENCs - Digital Encoders• Digital Cameras• I2C - Parallel I/O expanders
The key features of the I2C interface are:
• Supports I2C single master mode• I2C data rate up to 400 kbits/sec• Support for the 7-bit addressing option of the I2C
specification• Provisions for full software use of I2C interface pins
for implementing software I2C or similar protocols
Note that the I2C pins are also used to load the initial bootparameters and/or code from a serial EEPROM as de-scribed in Section 12, “System Boot”. The boot logic isonly active upon TM1100 hardware reset, and quiescentafterwards.
A typical system using the I2C interface is presented inFigure 15-1. The TM1100 is connected as a master to aseries of slave devices through SCL and SDA. Note thatthe bus has one pullup resistor for each of the clock anddata lines. The pullup should be to a voltage no higherthan VREF_PERIPH.
15.2 NEW IN TM1100
The following are the main I2C differences from TM1000:
• The SEX bit is removed. Endian-ness is fixed.• The I2C clock rate is closer to 100/400 kHz
• The GDI bit now correctly indicates write-completion• Clock stretching is always enabled.
15.3 EXTERNAL INTERFACE
The I2C external interface is composed of two signals asshown in Table 15-1.
15.4 I2C REGISTER SET
The I2C user interface consists of four registers visible tothe programmer. The registers are mapped into theMMIO address space and are fully accessible to the pro-grammer. Figure 15-2 shows the I2C register set. To en-sure compatibility with future devices, any undefinedMMIO bits should be ignored when read, and written aszeroes.
15.4.1 IIC_AR Register
The IIC_AR is the I2C address register and is used in bothmaster receive and transmit modes. This register is writ-ten with the address(es) of the I2C slave device and thebytecount for transmit/receive. Table 15-2 lists the bit-field definitions for the IIC_AR register.
ADDRESS must be programmed to contain the 7 bits ofthe desired slave address
The DIRECTION bitfield controls read/write operation onthe I2C interface. The bit definition is:
• DIRECTION = 0 –> I2C write
Figure 15-1. Typical I 2C System Implementation
SCL
SDA
TM1100SlaveI2C
SlaveI2C
+ VREF_PERIPH
Rp Rp
Table 15-1. I2C External Interface
Signal Type Description
IIC_SDA I/O I2C serial data
IIC_SCL O I2C clock
Table 15-2. IIC_AR Register
Bits Field Name Definition
31:25 ADDRESS 7-bit slave device address.
24 DIRECTION Read/Write control bit
23:16 reserved must be written to ‘0’
15:8 COUNT Byte count of requested transfer
7:0 reserved Read as ‘0’
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• DIRECTION = 1 –> I2C read
The COUNT field must contain the desired bytecount forthe current transfer. The COUNT field will decrement byone for each data byte transferred across I2C. The re-maining bytecount for the current transfer can be readfrom the COUNT field at any time. Note that theDSPCPU must refrain from re-writing the IIC_AR registeruntil the current transfer completes to avoid corruptingthe bytecount or address fields.
Note: For writes, the byte count decrements before thebyte is actually transferred over the I2C bus. However,the last byte is saved in an internal register and theDSPCPU can write a new word when COUNT = 0.
15.4.2 IIC_DR Register
The IIC_DR register contains the actual data transferredduring I2C operation. For a master transmit operation,data transfer will be initiated when data is written to thisregister. Transmission will begin with the transfer of theaddress byte in the IIC_AR register followed by the databytes that were written to the IIC_DR register, byte3 firstand byte0 last. The I2C interface will interrupt for more
transmit data to be written to the IIC_DR until the transferbytecount COUNT in the IIC_AR register is reached.
In master receive operation, one or more data bytes re-ceived are placed in the IIC_DR register by the I2C inter-face. Data bytes received are loaded into the IIC_DRregister starting with byte3, then byte2, byte1 and byte0.:
The number of bytes the DSPCPU requests for a transferis written into the COUNT bitfield of the IIC_AR register.The transfer completes when the I2C interface receivesthe number of bytes indicated by the COUNT bitfield ofthe IIC_AR register.
15.4.3 IIC_SR Register
The I2C status register contains status information re-garding the transfer in progress and the nature of inter-rupts associated with I2C operation.
The IIC_SR register is read only and is intended as theprimary source of status regarding current I2C operation.The IIC_SR register must be used in conjunction with theIIC_CR register. The interrupt sources of the IIC_SR reg-ister are individually enabled by writing to the appropriateenable bit in the IIC_CR register. The bitfield definitions
Figure 15-2. I 2C Registers
MMIO_baseoffset:
IIC_AR (r/w)0x10 3400037111519232731
COUNT
IIC_DR (r/w)0x10 3404037111519232731
IIC_SR (r/o)0x10 3408037111519232731
reserved
DIRECTION
ADDRESS
BYTE3 BYTE2 BYTE1 BYTE0
reservdDIRECTION
STATE
SDNACKISANACKI
FIGDI
GD_IENF_IEN
SDNACK_IENSANACK_IEN
IIC_CR (r/w)0x10 340C037111519232731
CLRFICLRGDI
CLRSANACKICLRSDNACKI
ENABLE
RBC
SDA_STATSCL_STAT
SW_MODE_ENSDA_OUTSCL_OUT
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of the IIC_SR register are presented in Table 15-3. TheIIC_SR provides four sources of interrupts. Note: the in-terrupt should be set up as level triggered interrupt.
• GDI interrupt — The GDI bit together with the FI bitsprovide status about I2C transfer completion. Theinterpretation of GDI/FI bit combinations are differentdepending on whether the I2C interface is in mastertransmit or master receive mode. Refer to Table 15-4and Table 15-6 for GDI/FI interpretation
• FI interrupt — See GDI bit definition and GDI/FItransmit and receive definitions in Table 15-4 andTable 15-6.
• SANACKI interrupt — This interrupt flag bit indicatesthat a slave address was transmitted but no slave onthe I2C bus acknowledges the address to claim thetransaction. This is an error condition. Once the I2Cinterface has set this interrupt flag, the interface isidle. The DSPCPU should clear this interrupt flag bywriting a ‘1’ to IIC_CR.CLRSANACKI before re-attempting this transfer or starting another I2C trans-fer.
• SDNACKI interrupt — This interrupt flag bit indicatesthat an addressed slave receiver device has refusedto acknowledge the current byte of data for an ongo-ing transfer. This is an error condition. Once the I2Cinterface has set this interrupt flag, the interface is
idle. The DSPCPU should clear this interrupt flag bywriting a ‘1’ to IIC_CR.CLRSDNACKI before retryingthis transfer or starting another.
The SDA_STAT and SCL_STAT bits indicate the currentstate of the SDA and SCL signals. The STATE field indi-cates the microactivity of the I2C interface. The field val-ues and their meanings are presented in Table 15-5 TheDIRECTION status bit indicates if the I2C interface is intransmit or receive mode.
• if DIRECTION = 0 then I2C is a transmitter.• if DIRECTION = 1 then I2C is a receiver.
The RBC bitfield indicates the remaining bytecount for anI2C transfer in progress. The IIC_SR.RBC bitfield servesas a read-only “shadow register” for the IIC_AR.COUNTbitfield. During I2C transfer, the RBC bitfield will reflectthe remaining bytecount. To avoid corrupting an I2C
Table 15-3. IIC_SR Register
Bits Field Name Definition
31 GDI Good Data Interrupt. This is the nor-mal transfer complete interrupt flag.This interrupt may be asserted without the IIC_SR.FI interrupt bit at the end of an I2C transfer or after master abort of an I2C transfer.
30 FI Full Interrupt. This interrupt indicates the condition of the IIC_DR register dependent upon whether the I2C inter-face is in receive or transmit mode.
29 SANACKI Slave Address No Acknowledge Inter-rupt.
28 SDNACKI Slave Data No Acknowledge Interrupt.
27 SDA_STAT This bit is used to examine the state of the external I2C SDA data pin. Bit polarity is:1 = SDA pad is low0 = SDA pad floated high
26 SCL_STAT This bit is used to examine the state of the external I2C SCL clock pin. Bit polarity is: 1 = SCL pad is low0 = SCL pad floated high
25:23 STATE The STATE field indicates the microac-tivity of the I2C bus.
22 DIRECTION Direction of current data transfer.
21 Reserved Read as ‘0’
15:8 RBC Remaining Byte Count.
7:0 Reserved Read as ‘0’
Table 15-4. Master Transmit Mode GDI/FI Status
GDI FI Description
0 0 Message is not complete. The IIC_DR is not empty. No interrupt.
0 1 Message is not complete. The IIC_DR is empty and the requested transmit byte count is not equal to 0. The DSPCPU must write additional bytes of the current transfer to the IIC_DR regis-ter.
1 X Message transmission has completed. The IIC_DR is empty. The byte transmit count = 0.
Table 15-5. STATE field values
STATE Meaning
000 I2C Interface is idle.
001 RESERVED FOR FUTURE USE
010 IDLE (MSG is done, awaiting clear GDI to go to 000 state)
011 Address phase is being processed
100 BYTE3 (first byte) is being processed
101 BYTE2 is being processed
110 BYTE1 is being processed
111 BYTE0 (last) is being processed
Table 15-6. Master Receive GDI/FI Conditions
GDI FI Description
0 0 Message is not complete. IIC_DR is not full. No interrupt.
0 1 IIC_DR contains received data and needs to be read serviced. More data bytes are expected since the receive byte count is not equal to 0.
1 X The transfer has been completed and the receive byte count is equal to 0. 0 to 4 valid bytes are in the IIC_DR register awaiting read servicing by the DSPCPU.
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transfer, the DSPCPU must refrain from writing to theIIC_AR.COUNT bitfield until a message is complete.Completion is indicated by the RBC bitfield decrementingto zero.
15.4.4 IIC_CR Register
The I2C control register contains control information re-quired for enabling I2C transfers. This register is used toenable and clear interrupt sources which normally occurduring I2C operation. The four interrupt sources de-scribed in the section on the IIC_SR register are enabledand cleared through the IIC_CR register. The enable bit-fields are:
• GD_IEN — Enable for normal transfer completeinterrupt.
• F_IEN — Enable for IIC_DR data service requestinterrupt.
• SANACK_IEN — Enable for slave address notacknowledged interrupt. This is an error interrupt.
• SDNACK_IEN — Enable for slave data not acknowl-edged interrupt. An addressed slave receiver hasrefused to accept the last byte transmitted to it. Thisis handled as an error interrupt.
In addition to the interrupt enable bits, the IIC_CR con-tains interrupt clear bits associated with each of the inter-rupt sources in the IIC_SR register. These IIC_CR inter-rupt clear bits are defined as:
• CLRGDI — Clear bit for the GDI interrupt in theIIC_SR register. Writing a ‘1’ to this bit clears the GDIinterrupt.
• CLRFI — Clear bit for the FI interrupt in the IIC_SRregister. Writing a ‘1’ to this bit clears the FI interrupt.
• CLRSANACKI — Clear bit for the SANACKI interruptin the IIC_SR register. Writing a ‘1’ to this bit clearsthe SANACKI interrupt.
• CLRSDNACKI — Clear bit for the SDNACKI interruptin the IIC_SR register. Writing a ‘1’ to this bit clearsthe SDNACKI interrupt.
The remaining bitfield of the IIC_CR register is:
• ENABLE — Master enable for I2C serial interface.ENABLE must be set equal to ‘1’ to transfer any bitsfrom the I2C interface block. Writing a ‘0’ to theENABLE bit effectively resets the entire I2C interface,including all status and interrupt flag bits. A transferin progress is aborted and the byte currently trans-ferred is lost.Note: For writes, Reserved1, 2, 3 and 4 bitfieldsMUST always be written with ‘0’s.
15.5 I2C SOFTWARE OPERATION MODE
I2C software operation mode is intended for use by soft-ware I2C or similar algorithm implementations. In thiscase, the SCL and SDA pins are fully controlled and ob-served by software, and the hardware I2C interface isdisconnected from the SCL and SDA pins. Refer toFigure 15-3 for a clarification of the principles involved.Software mode is by default disabled after boot. Soft-ware mode is enabled by writing a ‘1’ to
Table 15-7. IIC_CR Register
Bits Field Name Definition
31 GD_IEN Enable for normal transfer complete interrupt
30 F_IEN Enable for IIC_DR data service request interrupt.
29 SANACK_IEN Enable for slave address not acknowledged interrupt.
28 SDNACK_IEN Enable for slave data not acknowl-edged interrupt. An addressed slave receiver has refused to accept the last byte transmitted to it.
27:26 Reserved1 Always write ‘0’s to these bits. (See Note1)
25 CLRGDI Clear bit for the GDI interrupt in the IIC_SR register. Writing a ‘1’ to this bit clears the GDI interrupt.
24 CLRFI Clear bit for the FI interrupt in the IIC_SR register. Writing a ‘1’ to this bit clears the FI interrupt.
23 CLRSANACKI Clear bit for the SANACKI interrupt in the IIC_SR register. Writing a ‘1’ to this bit clears the SANACKI interrupt.
22 CLRSDNACKI Clear bit for the SDNACKI interrupt in the IIC_SR register. Writing a ‘1’ to this bit clears the SDNACKI inter-rupt.
21:6 Reserved2 Always write ‘0’s to these bits. (See Note1)
10 SW_MODE_EN 0 (power-on/reset default) - Normal I2C hardware operating mode..1 - Enable software operating mode. The I2C pins are entirely controlled by user writes to the ‘sda_out’ and ‘scl_out’ register bits.
7 SDA_OUT Enabled by sw_mode_en. This bit is used by sw to manually control the external i2c SDA data pin. Bit polar-ity is:1 = SDA pad pulled low0 = SDA pad left open drain
6 SCL_OUT Enabled by sw_mode_en. This bit is used by sw to manually control the external i2c SCL clock pin. Bit polar-ity is:1 = SCL pad pulled low0 = SCL pad left open drain
5:2 Reserved3 Always write ‘0’s to these bits. (See Note1)
1 Reserved4 Always write ‘0’s to these bits. (See Note1)
0 ENABLE I2C serial interface enable
Table 15-7. IIC_CR Register (Continued)
Bits Field Name Definition
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IIC_CR.SW_MODE_EN. At that point, the SCL and SDApins can be controlled by the IIC_CR SDA_OUT andSCL_OUT bits. Writing a ‘1’ to either bit causes the cor-responding pin to become active, i.e. be pulled low. TheSDA and SCL lines are open-collector outputs, and canhence also be pulled low by external devices. The actualpin state can be observed by software by examiningIIC_SR SDA_STAT and SCL_STAT bits. A 1 in theseMMIO bits indicates that the corresponding pin is cur-rently pulled low.
By appropriate software, possibly using a timer interrupt,full I2C functionality can be implemented using thismechanism.
15.6 I2C HARDWARE OPERATION MODE
Hardware operation of I2C is the default mode after boot.The TM1100 I2C hardware interface operates in one oftwo modes:
1. Master-Transmitter (to write data to a slave)2. Master-Receiver (to read data from a slave)
As a master, the I2C logic will generate all the serial clockpulses and the START and STOP bus conditions. TheSTART and STOP bus conditions are shown inFigure 15-4. A transfer is ended with a STOP conditionor a repeated START condition. Since a repeated
START condition is also the beginning of the next serialtransfer, the I2C bus will not be released.
Note: The I2C interface on TM1100 will operate as amaster ONLY!
The number of bytes transferred between the STARTand STOP conditions from transmitter to receiver is notlimited. Each data byte of 8 bits is followed by one ac-knowledge bit. The transmitter releases the SDA linewhich will pull-up to a HIGH level during the acknowl-edge bit time. The receiver acknowledges by pulling thedata line LOW during this acknowledge period. The mas-ter must always generate the SCL transitions for the ac-knowledge bit time.
Two types of data transfers are supported by theTM1100 I2C interface:
SCL
SDA
hardware
DATAHIWAY
open drain
scl_stat
scl_outI2C
D Q
sda_stat
sda_out
tribuf
tribuf
sw_mode_en
sw_mode_en
buf
open drain
buf
D Q
Figure 15-3. I 2C software mode only logic
SDA
SCL S P
START STOP
Figure 15-4. START and STOP Conditions on I 2C
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• Data transfer from a master transmitter to a slavereceiver, also called a WRITE operation. The firstbyte transmitted by the master is the slave address.Then the desired number of data bytes follow. Theslave receiver returns an acknowledge bit after eachbyte. The master terminates the transaction by aSTOP after the last byte.
• Data transfer from slave transmitter to masterreceiver, also called a READ operation.The first byte(the slave address), is transmitted by the master andacknowledged by the slave. The selected slave trans-mits successive data bytes which are each acknowl-edged by the master, except the last byte desired bythe master, for which the master generates a ‘not-ack’ condition. This causes the slave to terminatebyte transmission. The slave transmitter then mustrelease the bus so that the master may generate aSTOP condition.
The type of transaction is indicated by the LSbit of the ad-dress byte. Data transfer from a master transmitter to aslave receiver is called a WRITE. It is signified by a ‘0’ inthe LSbit of the address byte. Data transfer from a slavetransmitter to a master receiver is called a READ. It issignified by a ‘1’ in the LSBit of the address byte.
Example steps for successful programming of the I2C in-terface on TM1100 are outlined as follows for both readsand writes. Enable the I2C interface prior to attemptingany accesses to external I2C devices.
To enable the interface:
• Set bit IIC_CR.ENABLE (0x10340c) = 1
For write addressing mode:
i) On entry, clear any possible I2C interrupt sources bywriting IIC_CR bits [25:22] = ‘1111’. (Note that program-mers must mask and enable high level interrupt sourcesthrough the VIC facility in the DSPCPU. See the appro-priate TM1100 databook chapter).
ii) Enable desired I2C interrupt sources by settingIIC_CR[31:28] bits appropriately.
iii) Simultaneously load IIC_AR[31:25] with 7-bit slaveaddress, IIC_AR.DIRECTION = 0 and IIC_AR[15:8] withthe appropriate bytecount for the transfer.
iv) Load IIC_DR[31:0] with data for the write. Note thatwriting this register triggers the transfer across the I2Cbus.Up to 4 bytes will be transferred after writing, depen-dent on bytecount in IIC_AR[8:15.Transfers of more
than 4 bytes have to be done by breaking them down intoa sequence of 4-byte transfers and a last transfer whichmay be less than 4 bytes. This is done by repeatedly re-loading the register until the bytecount is fulfilled. Trans-fer is done high byte first, proceeding to low byte.
v) Detect I2C resulting condition code in IIC_SR[31:28]and respond - OR - Detect I2C high level interrupt and re-spond. (Note that this last step is dependent upon sys-tem software requirements).
vi) If transfer count is not yet fulfilled, clear GDI and FIbits and proceed with step iv) until all data is written.
For read addressing mode:
i) On entry, clear any possible I2C interrupt sources bywriting IIC_CR bits [25:22] = ‘1111’. (Note that program-mers must mask and enable high level interrupt sourcesthrough the VIC facility in the DSPCPU. See the appro-priate databook chapter).
ii) Enable desired I2C interrupt sources by settingIIC_CR[31:28] bits appropriately.
iii) Simultaneously load IIC_AR[31:25] with 7-bit slaveaddress, IIC_AR.DIRECTION = 1 and IIC_AR[15:8] withthe appropriate bytecount for the transfer. Note that writ-ing this register triggers the read across the I2C bus.
iv) Detect I2C resulting condition in IIC_SR[31:28] andrespond - OR - Detect I2C interrupt and respond. (Notethat this last step is dependent upon system software re-quirements.)
v) Clear GDI and FI bits and read the contents of IIC_DR.Up to 4 bytes will be available in IIC_DR, fever if the re-maining bytecount was less than 4. Bytes are stored highbyte first, proceeding to low byte.
vi) Proceed with step iv) until all data is read, i.e byte-count is fulfilled.
15.6.1 Slave NAK
If a slave device does not generate an ACK where re-quired, this is considered a NAK. Upon receipt of a NAKafter transmitting a device address or data byte, the mas-ter takes the following actions:
• the I2C state becomes IDLE (STATE = 000)• a STOP condition is issued on the bus• no more data is sent
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15.7 I2C CLOCK RATE GENERATION
The I2C hardware block diagram is shown in Figure 15-5below. In hardware operating mode, the IIC__SCL exter-nal clock is derived by division from the BOOT_CLK pinon tm1100. The BOOT_CLK pin is normally connected toTRI_CLKIN. The IIC__SCL clock divider value is deter-mined at boot time, and cannot be changed thereafter.The value chosen depends on the first byte read from theEEPROM, as described in Section 12.3.1, “Boot Proce-dure Common to Both Autonomous and Host-AssistedBootstrap.”
The TM1100 I2C block is able to “stretch” the SCL clockin response to slaves that need to slow down byte trans-fer. This mechanism of slowing SCL in response to aslave is called “clock stretching.” This clock stretching isaccomplished by the slave by holding the SCL line “low”
after completion of a byte transfer and acknowledge se-quence. Clock stretching is always enabled.
Table 15-8. I2C speed and EEPROM byte 0
BOOT_CLKbits
EEPROMspeed bit
dividervalue
actual I2Cspeed
00 (100 MHz) 0 (100 kHz) 1008 99.2 kHz
00 1 (400 kHz) 256 390.6 kHz
01 (75 MHz) 0 (100 kHz) 752 99.7 kHz
01 1 (400 kHz) 192 390.6 kHz
10 (50 MHz) 0 (100 kHz) 512 97.6 kHz
10 1 (400 kHz) 128 390.6 kHz
11 (33 MHz) 0 (100 kHz) 336 98.2 kHz
11 1 (400 kHz) 96 343.8 kHz
Figure 15-5. I 2C block diagram
Boot S/Mand Logic
ResetLogic
I2C ClockGen Prog
PAD
I2CI/F
S/M
Serializer/DeserializerPAD
n
0 1
0 1
PAD
AddrRegister
DataRegister
Boot AddressBoot Data
cpu-arstTRI_RESET#
controls controls
cpu-arst
IIC_SCL
PAD
BOOTCLKIN
ATE(eeprom image
Byte0,bit0)
IIC_SDA
controls
I2C lowlevel S/M
controls
boot addr
cpu-arstboot_sclk
sclk
BootData
IIC_AR reg
IIC_DR reg
I
sclk
.
. 4
sync
Data Hiway
File: i2c.fm5, modified 7/25/99 PRELIMINARY INFORMATION 15-7
TM1100 Preliminary Data Book Philips Semiconductors
15-8 PRELIMINARY INFORMATION File: i2c.fm5, modified 7/25/99
Synchronous Serial Interface Chapter 16
16.1 SYNCHRONOUS SERIAL INTERFACE OVERVIEW
The TM1100 synchronous serial interface (SSI) unit in-terfaces to an off-chip modem analog front end (MAFE)subsystem, Network Terminator, ADC/DAC or Codecthrough a flexible bit-serial connection. The hardwareperforms full-duplex serialization/deserialization of a bitstream from any of these devices. Any such front end de-vice connected must support Transmitting, Receiving ofdata, and initialization via a synchronous serial interface.
Since the communication algorithm is implemented insoftware by the TM1100 DSPCPU and the analog inter-face is off chip, a wide variety of modem, network and/orFAX protocols may be supported.
The synchronous serial Interface hardware includes:
• A 16-bit receive shift register (RxSR), synchronizedby an external receive frame synchronization pulse(SSI_RxFSX) and clocked by an external clock(RxCLK).
• A 32-bit MMIO receive data register (SSI_RxDR) toprovide data access from the DSPCPU.
• 32 entry deep,16-bit wide receive buffer (RxFIFO), tobuffer between the receive shift register (RxSR) andMMIO receive data register (SSI_RxDR).
• A 16-bit transmit shift register (TxSR), synchronizedby an external or internal transmit frame synchroni-zation pulse and clocked by an external clock (eitherSSI_IO1 or SSI_RxCLK).
• A 32-bit MMIO transmit data register (SSI_TxDR) totransmit data from the DSPCPU.
• 30 entry deep, 16-bit wide transmit buffer (TxFIFO),to buffer between the MMIO transmit data register(SSI_TxDR) and transmit shift register (TxSR).
• Transmit frame sync pulse generation logic.• Control and status logic.• Interrupt generation logic.
The SSI unit is not a hiway bus master. All I/O is complet-ed through DSPCPU MMIO cycles. FIFO’s are used toincrease allowable interrupt response time and decreaseinterrupt rate.
16.2 INTERFACE
The external interface consists of the 6 pins described in
16.3 BLOCK DIAGRAM
The main block diagram of the SSI unit is illustrated inFigure 16-1.
The I/O block is used for control of the I/O pins and forselecting the transmit clock and transmit frame synchro-nization signals.
The Frame Synchronization block can be used for gen-erating an internal synchronization signal derived fromreceive clock input (SSI_RxCLK) or from an IO pin(SSI_IO1).
The SSI Transmit block buffers and transmits the bits us-ing the generated frame synchronization signal (TxFSX)and the transmit clock. The transmit clock is either the re-ceive clock or the clock present on SSI_IO1.
The SSI Receive block receives and buffers the bits onthe SSI_RxDATA line, using the receive clock(SSI_RxCLK) and the receive frame synchronization sig-nal (SSI_RxFSX).
Each of the blocks will be described in detail in the nextsubsections.
Table 16-1. Synchronous Serial Interface Pins
Name Type Description
SSI_RxCLK IN-5 Serial interface clock signal. Pro-vided by an external communica-tion device.
SSI_RxFSX IN-5 Frame synchronization reference signal. Provided by an external communication device.
SSI_RxDATA IN-5 Receive serial data signal. Pro-vided by the receive channel of an external communication device.
SSI_TxDATA OUT Transmit serial data signal output.
SSI_IO1 I/O-5 This pin can function as Transmit clock input or as general purpose I/O pin.
SSI_IO2 I/O-5 This pin can function as Transmit Frame synchronization signal input or output, or as general purpose I/O pin.
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TM1100 Preliminary Data Book Philips Semiconductors
16.3.1 General Purpose I/O
Figure 16-2 illustrates the functionality of the generalpurpose I/O pins. The SSI_IO1 and SSI_IO2 externalpins may be used as general purpose I/O by proper con-figuration of the SSI_CTL register, or they may be usedas transmit clock input and as transmit framing signal in-put or output. The SSI_CTL.IO1 and SSI_CTL.IO2 ModeSelect fields control the direction and functionality ofthese two pins.
A hardware reset or a software reset of the transmitterthrough SSI_CTL.TXR command sets the SSI_CTL.IO1and SSI_CTL.O2 fields to 11b, a conflict-free initial pinstate.Table 16-2 shows the effect of SSI_CTL.IO1 on pinSSI_IO1, Table 16-3 shows the effect of SSI_CTL.IO2on SSI_IO2. Note: If SSI_IO1 is not selected as transmitclock input, the transmit clock is taken from the receiveclock signal instead. If SSI_IO2 is not selected as trans-mit framing signal input or output, the transmit framingsignal is taken from the receive framing signal instead.
SSI_RxCLK
TxFSX
SSI_RxFSX
Frame SynchronizationBlock
Figure 16-1. The SSI interface block diagram
SSI_IO2
SSI_IO1I/O Control
Block
SSI TransmitBlock
TxCLK
SSI_TxDATA
SSI ReceiveBlock
SSI_RxDATA
IO1[1:0]=00
RIO1
WIO1
Figure 16-2. I/O Block Diagram
internal TxFSX
2:1MUX
IO2[1:0] = 00
WIO2IO2[1:0] = 00
SSI_IO2
RIO2IO2[0] = 0
IO2[0] = 1
SSI_IO1
IO1[1:0]=01
SSI_RxFSX TxFSX
SSI_IO2
2:1MUX
IO2[1:0] = 11
2:1MUX
IO2[1:0] = 10
internal TxFSXIO2[1:0] = 10
IO2[1:0] = 11
TxCLK2:1MUX
IO1[1:0]=10
IO1[1:0]=10SSI_IO1
SSI_RxCLK
16-2 PRELIMINARY INFORMATION File: ssi.fm5, modified 7/24/99
Philips Semiconductors Synchronous Serial Interface
16.3.2 Frame Synchronization.
The internal frame synchronization logic is illustrated inFigure 16-3. An internal Frame Synchronization signal
(TxFSX) is being generated from the transmit or receiveclock selected by SSI_CTL.IO1. The Clock is divided bythe word length (16) and a Frame Rate Divider which iscontrolled by the FSS[3:0] bits in the SSI_CTL register.FMS determines the Frame Mode operation, whether theframe sync pulse is word-length or bit-length. The trans-
mit framing signal is selected dependent onSSI_CTL.IO2, as shown in Table 16-4.
16.3.3 SSI Transmit.
The Transmitter control block diagram is illustrated inFigure 16-4. The transmitter clock can be selected fromtwo sources, i.e. SSI_IO1 or SSI_RxCLK by program-ming IO1[1:0] bits in the SSI_CTL register (seeFigure 16-2). A transfer takes place on either the rising orfalling edge of the clock, which can be configured withSSI_CTL.TCP.
The transmitter has a 30 entry deep, 16-bit transmitbuffer that buffers the data between the 32-bitSSI_TXDR register and the 16-bit transmit shift register
(TxSR).
The TxSR is a 16-bit transmit shift register. TxSR can beconfigured to shift out MSB or LSB first withSSI_CTL.TSD.
A detailed description of the configuration of the transmit-ter can be found in the SSI_CTL and SSI_CSR registerdescription (16.10.1 and 16.10.2)
SSI_TxDR is a 32-bit MMIO transmit register.
16.3.4 SSI Receive.
The receiver control block diagram is illustrated inFigure 16-5. The receiver clock, frame synchronizationand data signal are always taken from the external pins.
The receiver has a 32 entry deep, 16-bit receive bufferthat buffers the data between the 16-bit receive shift reg-ister (RxSR) and the 32-bit SSI_RXDATA register.
The input pin SSI_RxDATA provides serial shift in datato the RxSR. The RxSR is a 16-bit receive shift register.RxSR can be configured to shift in from MSB or LSB firstusing SSI_CTL.RSD. A transfer takes place on either therising or falling edge of the receiver clock, which can beconfigured with the SSI_CTL.RCP.
A detailed description of the configuration of the receivercan be found in the SSI_CTL and SSI_CSR register de-scription (16.10.1 and 16.10.2)
Table 16-2 Effect of SSI_CTL.IO1 on SSI_IO1
IO1[0:1] Function of SSI_IO1
00 general purpose output with positive logic polarity, reflecting the value in SSI_CTL.WIO1
01 general purpose input, with optional change detector function. The input state can be read from SSI_CSR.RIO1. The change detector is clocked by the highway bus. The change detector may optionally generate an interrupt, under the control of CDE bit of SSI_CTL.
10 Transmit clock (TxCLK) input11 tri-state, input signal value ignored
Table 16-3 Effect of SSI_CTL.IO2 on SSI_IO2
IO2[0:1] Function of SSI_IO2
00 General purpose output with positive logic polarity, reflecting the value in SSI_CTL.WIO2
01 General purpose input. The input state canbe read in from SSI_CSR.RIO2. No changedetector is provided for this pin.
10 Internal transmit framing signal (TxFSX) out-put.
Table 16-4. Effect of SSI_CTL.IO2 on transmit framing signal
IO2[0:1] Source of transmit framing signal
00 taken from RxFSX
01 taken from RxFSX
10 internally generated
11 taken from SSI_IO2 pin
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TM1100 Preliminary Data Book Philips Semiconductors
SSI_RxDR is a 32-bit MMIO receive data register.
Due to the possibility of speculative reading of theSSI_RxDR the read itself can not be implemented to ac-knowledge the data as a side effect. For this reason anexplicit acknowledge mechanism is provided by theSSI_RxACK register.
The SSI_RxACK is a 1-bit MMIO register that is used tosignal the SSI receiver state machine that a word hasbeen successfully read from the SSI_RxDR.
Writing a ‘1’ to this register initiates updating of the inter-nal state. Writing a zero has no effect.
The register cannot be read, its effect may be observedin the WAR field of the SSI_CSR.
The status fields of the SSI_CSR will update within 1highway clock cycle after writing to the SSI_RXACK reg-ister.
Figure 16-4. The Sync Serial Interface Transmit Block Diagram
TxSR SSI_TXDR
SSI_RxCLK
SSI_RxFSXSSI_RxDATA
ReceiveShift Reg 64-byte Receive Buffer
ReceiveData Reg
Receive Control Logic
ReceiveControl Reg
ReceiveStatus Reg
Figure 16-5. The Sync Serial Interface Receive Block Diagram
RxSR SSI_RXDR
16-4 PRELIMINARY INFORMATION File: ssi.fm5, modified 7/24/99
Philips Semiconductors Synchronous Serial Interface
16.4 SSI TRANSMIT OPERATION
16.4.1 Setup SSI_CTL
Write the SSI_CTL to reset and enable the transmitter. Itis required to reset both the transmitter and receiver si-multaneously. This will set all registers and internal logicthe same as after a power-up reset. The recommendedprocedure is to set up all transmitter related control bitsbefore performing a TXE assert. In particular, fields TCP,RSD, IO1, IO2, FMS, FSP, MOD and TMS should NOTbe changed after enabling the transmitter until after thenext transmitter reset.
The TxCLK is taken from the SSI_IO1 pin or from the re-ceive clock, dependent on SSI_CTL.IO1. The direction ofshift in the TxSR and the clock edge to shift on must alsobe configured in SSI_CTL. If the DSPCPU does not pollthe SSI status registers, it should enable the transmitterinterrupt and set the ILS field by writing to the SSI_CTLto allow interrupt driven servicing of the SSI. Note thatboth transmit and receive use the same ILS field. Set theframing controls, slot size, and mode required accordingto the external communication circuit’s requirements bywriting the SSI_CTL. Finally, set the interrupt level to re-spond to empty levels in the TxFIFO. Note that the Rxand Tx machines share the framing and clock divide con-trols. They cannot be set to different values for Rx andTx.
If the RxCLK used to derive the TxCLK needs a divide bytwo, this is done by setting SSI_CSR.CD2.
16.4.2 Operation Details
The transmit state machine will wait for transmit data tobe written to the SSI_TxDR register. (see alsoFigure 16-6) As soon as SSI_TxDR is written, it will be
propagated through two entries of the TxFIFO (TxFIFOis 16-bit and SSI_TxDR is 32-bit) and transferred to Tx-SR, synchronized to TxFSX. The order of transferring thetwo 16-bit parts in the 32-bit SSI_TxDR can be config-ured by the endian bit SSI_CTL.EMS. Data will beginshifting out of TxSR, one bit for each active edge of theTxCLK, from either bit 15 (MSB first SSI_CTL setting) orfrom bit 0 (LSB first) until TxSR is empty. For endian con-trol and shift direction see also subsection 16.8. Whenthe shift register is empty, the transmit state machine willload the value from the next available TxFIFO locationand begin shifting out that data. The transmission contin-ues until the transmit state machine is disabled or reset.
If the last available TxFIFO has not been updated at theappropriate time to reload TxSR, the last transmittedframe is retransmitted and a transmit underrun error is in-dicated in the transmitter status SSI_CSR.TUE
16.4.3 Interrupt and Status
The refill status of the SSI_TxDR register is stored inSSI_CSR. As the transmit state machine loads a TxFIFOregister to the TxSR, it sets the associated status bits.The SSI will generate an internal interrupt when the num-ber of empty words in the TxFIFO rises above the levelset by SSI_CSR.ILS. If the transmit state machine at-tempts to read a TxFIFO while the last available TxFIFOhas not been updated, it will set the transmit underrun bit.This can cause a protocol error in the transmission.
The number of available word buffers (SSI_CSR.WAW)and transmitter data register empty (SSI_CSR.TDE) in-formation is updated automatically by the SSI block.
... ... ... ... 7 6 5 4 3 2 1 0
TxS
R
32-b
it M
MIO
Reg
30-depth of 16-bit buffer
16-bit
SSI_TxDATA
29 28 27 ...
rd_ptr
FromHiway
wr_ptr
SSI_TxDR
Figure 16-6. The Transmit Buffer operation.
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TM1100 Preliminary Data Book Philips Semiconductors
16.5 SSI RECEIVE OPERATION
16.5.1 Setup SSI_CTL
Write the SSI_CTL to reset and enable the receiver. It isrequired to reset both the transmitter and receiver simul-taneously. This will set all registers and internal logic thesame as after a power-up reset. The recommended pro-cedure is to set up all receiver related control bits beforeperforming a RXE assert. In particular, fields TCP, RSD,IO1, IO2, FMS, FSP, MOD and TMS should NOT bechanged after enabling the receiver until after the nextreceiver reset.
The direction of shift in the RxSR, mode, and the clockedge polarity must also be configured in SSI_CTL. Setthe framing controls according to the external communi-cation circuit’s requirements. Note that the Rx and Txmachines share the framing and clock divide controls.
If the DSPCPU does not poll the SSI status registers, itshould enable the receiver interrupt and set the ILS fieldby writing to the SSI_CTL to allow interrupt driven servic-ing of the SSI receiver. Note that both transmit and re-ceive use the same ILS field.
If the RxCLK is double the frequency of the data rate onthe SSI bus, SSI_CSR.CD2 can be used to divide the re-ceive clock by two.
16.5.2 Operation Details
The receive state machine will begin shiftingSSI_RxDATA into the RxSR on the first active edge ofSSI_RxCLK received after the receiver is enabled (seealso Figure 16-7). When full, the RxSR is parallel trans-ferred to the first available RxFIFO entry and possiblySSI_RxDR. Reception continues and when RxSR is fullagain, a parallel load of the next available RxFIFO entryfrom RxSR is accomplished. This continues until the re-ceiver is disabled or reset. If the receive state machinemust transfer RxSR into one of the RxFIFO entries andnone of the RxFIFO entries is available, the value will belost and the receive overrun bit will be set.
16.5.3 Interrupt and Status
The status of the RxFIFO is visible in SSI_CSR, i.e. num-ber of 32-bit words available for read (WAR), number ofwords available for read is more than ILS (RDF). As thereceive state machine loads RxFIFO from the RxSR, itsets the associated status bit. The SSI will generate aninternal interrupt when the number of full entries inRxFIFO is more then SSI_CTL.ILS. If the receive statemachine attempts to load RxFIFO while none of theRxFIFO entries is available, it will set the receive overrunbit and generate an interrupt.
Due to the possibility of speculative reading of theSSI_RxDR, the DSPCPU must explicitly indicate a suc-cessful read of SSI_RxDR by writing a one in the LSB tothe SSI_RxACK register. The status fields of theSSI_CSR will update within 1 highway clock cycle aftercompletion of writing to SSI_RXACK register.
16.6 FRAME TIMING
The frame timing can be controlled by the FSS and VSSfield in the SSI_CTL register.
The FSS[3:0] bits control the divide ratio for the program-mable frame rate divider used to generate the framesync pulses. The valid value ranges from 1 to 16 slots of16 bit each, e.g. a value of 5 indicates that a frame con-tains 5 slots of 16 bits each. Note: the value 16 is accom-plished by storing a 0 in this field. If a codec is connectedwhich generates 6 slots and the SSI block is pro-grammed to 5 slots a framing error is indicated inSSI_CSR.FES, and if TIE or RIE is enabled, an interruptis generated.
For an example of a frame timing diagram seeFigure 16-11 and Figure 16-12.
The VSS[3:0] bits control the number of valid slots in theframe, starting from slot 1, e.g. if set to 4 and FSS set to5, slots 1, 2, 3 and 4 in the frame contain valid data fromthe FIFO of the transmitter and slot 5 will contain non-val-
4 5 6 7 ... ... ... ... ... 29 30 31
RxS
R
32-b
it M
MIO
Reg
32-depth of 16-bit buffer
16-bit
SSI_RxDATA
0 1 2 3
rd_ptr wr_ptr
ToHiway
SSI_RxDR
Figure 16-7. The Receive Buffer operation.
16-6 PRELIMINARY INFORMATION File: ssi.fm5, modified 7/24/99
Philips Semiconductors Synchronous Serial Interface
id data. The receiver will only accept data in slot 1, 2, 3and 4.
16.7 INTERRUPT GENERATION.
Depending on the settings of the TIE, RIE and CDE bitsin the SSI_CTL register the SSI unit can generate inter-
rupts. This is best illustrated by Figure 16-8. Note:RXFES and TXFES are the internal receive and transmitframing error conditions. When an SSI interrupt is detect-ed, the interrupt service routine should check all statusbits.The interrupts should be set up as level triggered in-terrupts.
16.8 16-BIT ENDIAN-NESS AND SHIFT DIRECTION.
The SSI unit supports both access orders for the 16-bithalves of a machine word. In addition the shift directioncan be controlled to select MSB or LSB shifting first. TheSSI_CTL.EMS bit controls the 16-bit endian mode, andthe TSD and RSD bits control transmit and receive shiftdirection.
When EMS is set, the first data word received in a framewill be transferred to bit 15-0 of the SSI_RxDR, the sec-ond word will be transferred to bits 31-16 of theSSI_RxDR. EMS = ‘0’ reverses the order of the halves of
SSI_RxDR. Likewise in the transmitter, when EMS is set,the first data word transmitted in a frame will be bits 15-0 of SSI_TxDR, the second word transferred will be bits31-16 of SSI_TxDR.
TSD and RSD control the shift direction of transmit andreceive shift registers (TxSR and RxSR). Transmit data istransmitted MSB first when TSD is zero or LSB first oth-erwise. Receive data is received MSB first when RSDequals zero, LSB first otherwise.
For an example of the transmit operation seeFigure 16-9. Receive works the same, only that data isshifted in.
Figure 16-8. Interrupt generation logic.
TUEandorTDE
TXFES
TIE
ROEandorRDF
RIE
or SSI interrupt
CDE & CDS
RXFES
Figure 16-9. 16-bit endian and shift direction operation.
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TM1100 Preliminary Data Book Philips Semiconductors
16.9 SSI TEST MODES
The SSI unit has two test modes which can be controlledby setting SSI_CSR.TMS. A remote and a local loopbacktestmode are supported (see also Table 16-9).
16.9.1 Remote Loopback
This test mode allows a remote transmitter to test itself,the intervening transmission media and its associated re-ceiver. In this mode, the data received on SSI_RxDATApin is buffered and transmitted on SSI_TxDATA pin. Thedata is not transferred to SSI_TxDR/TxFIFO and theDSPCPU is never interrupted. The transmitter is clockedby SSI_RxCLK pin with a combinatorial clock delay.
16.9.2 Local Loopback
This test mode allows the DSPCPU to run local checksof the SSI. Data written to the TxFIFO is serialized and
passed to the receiver via an internal serial connection.The receiver deserializes the data and passes it to theRxFIFO register. Interrupts will be generated if enabled.During local loopback mode, the data on theSSI_RxDATA pin is ignored and the SSI_TxDATA pin istristated. An external CLK must be provided during localloopback mode or no transmission or reception will oc-cur.
16.10 MMIO REGISTERS
The MMIO Control and Status registers are shown inFigure 16-10. The register fields are described inTable 16-5, Table 16-6, Table 16-7, Table 16-8 andTable 16-9. To ensure compatibility with future devices,any undefined MMIO bits should be ignored when read,and written as zeroes.
SSI_CTL (r/w)0x10 2C0031 0
MMIO_BASEoffset:
SSI_TXDR (w/o)0x10 2C10
SSI_RXDR (r/o)0x10 2C20
SSI_RXACK (w/o)0x10 2C24
371115192327
TXDATA
RXDATA
SSI_CSR (r/w)0x10 2C04 WAW
FMSFSP
MODEMS
TDERDF
TUE
RIO1RIO2
037111519
31 0371115192327
FESCDS
ROE
TXRRXR
TXE
TSDRSD
TCPRCP
RXE
IO1 IO2
WIO1WIO2
TIERIE
FSS VSS ILS
WAR31 2327
CTUESROE
CFESCCDS
TMS
CDECD2
SLP
reset: 0x00f00000
reset: 0x0000f000
RX_ACK
Figure 16-10. SSI MMIO registers.
16-8 PRELIMINARY INFORMATION File: ssi.fm5, modified 7/24/99
Philips Semiconductors Synchronous Serial Interface
16.10.1 SSI Control Register (SSI_CTL)
SSI_CTL is a 32-bit read/write control register is used to direct the operation of the SSI. The value of this register aftera hardware reset is 0x00F00000.
Table 16-5. SSI Control Register (SSI_CTL) Fields.
Field Description
TXR Transmitter Software Reset (Bit 31). Setting TXR performs the same functions as a hardware reset. Resets all transmitter functions. A transmission in progress is interrupted and the data remaining in the TxSR is lost. The TxFIFO pointers are reset and the data contained will not be transmitted, but the data in the SSI_TxDR and/or TxFIFO is not explicitly deleted. The transmitter status and interrupts are all cleared. This is an action bit. This bit always reads ‘0’. Writing a ‘1’ in combination with writing a ‘1‘ in the RXR field will initiate a reset for the SSI module. Note: always set together with RXR, as a separate transmitter or receiver reset is not implemented.
RXR SSI_CTL Receiver Software Reset (Bit 30). Setting RXR performs the same functions as a hardware reset. Resets all receiver functions. A reception in progress is interrupted and the data collected in the RxSR is lost. The RxFIFO pointers are reset and the SSI will not generate an interrupt to DSPCPU to retrieve data in the SSI_RxDR and/or RxFIFO. The data in the SSI_RxDR and/or RxFIFO is not explicitly deleted. The receiver status and interrupts are all cleared.This is an action bit.This bit always reads ‘0’. Writing a ‘1’ in combination with writing a ‘1‘ in the TXR field will initiate a reset for the SSI module. Note: always set together with TXR, as a separate transmitter or receiver reset is not implemented.
TXE Transmitter Enable (Bit 29). TXE enables the operation of the transmit shift register state machine. When TXE is setand a frame sync is detected, the transmit state machine of the SSI is begins transmission of the frame. When TXEis cleared, the transmitter will be disabled after completing transmission of data currently in the TxSR. The serial out-put (SSI_TxDATA) is three-stated, and any data present in SSI_TxDR and/or TxFIFO will not be transmitted (i.e., datacan be written to SSI_TxDR with TXE cleared; TDE can be cleared, but data will not be transferred to the TxSR).
Status fields updated by the Transmit state machine are not updated or reset when an active transmitter is disabled.
RXE Receive Enable (Bit 28). When RXE is set, the receive state machine of the SSI is enabled. When this bit is cleared,the receiver will be disabled by inhibiting data transfer into SSI_RxDR and/or RxFIFO. If data is being received whilethis bit is cleared, the remainder of that 16-bit word will be shifted in and transferred to the SSI RxFIFO and/orSSI_RxDR.
Status fields updated by the Receive state machine are not updated or reset when an active receiver is disabled.
TCP Transmit Clock Polarity (Bit 27). The TCP bit value should only be changed when the transmitter is disabled. TCPcontrols on which edge of TxCLK data is output.. TCP=0 causes data to be output at rising edge of TxCLK, TCP=1causes data to be output at falling edge of TxCLK.
RCP Receive Clock Polarity (Bit 26). RCP controls which edge of RxCLK samples data. This bit causes the data to besampled at rising edge when RCP equals one or falling edge when RCP equals zero.
TSD Transmit Shift Direction (Bit 25). TSD controls the shift direction of transmit shift register (TxSR). Transmit data istransmitted MSB first when TSD is zero or LSB first otherwise. The operation of this bit is explained in more detail insection 16.8.
RSD Receive Shift Direction (Bit 24). The RSD bit value should only be changed when the receiver is disabled. RSD con-trols the shift direction of receive shift register (RxSR). Receive data is received MSB first when RSD equals zero,LSB first otherwise. The operation of this bit is explained in more detail in section 16.8.
IO1 Mode Select SSI_IO1 pin (Bit 23-22). The IO1 field value should only be changed when the transmitter and receiverare disabled. The IO1[1:0] bits are used to select the function of SSI_IO1 pin. The function may be selected as listedin table Table 16-6.
IO2 Mode Select SSI_IO2 pin (Bit 21-20). The IO2 field value should only be changed when the transmitter and receiverare disabled. The IO2[1:0] bits are used to select the function of SSI_IO2 pin. The function may be selected accordingto Table 16-7
WIO1 Write IO1 (Bit 19). Value written here appears on the SSI_IO1 pin when this pin is configured to be a general purposeoutput.
WIO2 Write IO2 (Bit 18). Value written here appears on the SSI_IO2 pin when this pin is configured to be a general purposeoutput.
TIE Transmit Interrupt Enable (Bit 17). Enables interrupt by the TDE flag in the SSI status register (transmit needs refill)Also enables interrupt the TUE (transmitter underrun error) and TXFES (transmit framing error)
RIE Receive Interrupt Enable (Bit 16). When RIE is set, the DSPCPU will be interrupted when RDF in the SSI status reg-ister is set (receive is complete). It will also be interrupted on ROE (receiver overrun error), and on RXFES (receiveframing error).
FSS Frame Size Select (Bits 15-12). The FSS[3:0] bits control the divide ratio for the programmable frame rate dividerused to generate the frame sync pulses. The valid setup value ranges from 1 to 16 slot(s). The value 16 is accom-plished by storing a 0 in this field.
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VSS Valid Slot Size (Bit 11-8). The VSS[3:0] bits control the valid slot size starting from slot 1 for different modem analogfront end devices. The valid setup value ranges from 1 to 16 slot(s). The value 16 is accomplished by storing a 0 inthis field.
FMS Frame Sync Mode Select (Bit 7). The FMS bit value should only be changed when the transmitter and receiver aredisabled. FMS selects the type of frame sync to be recognized by both Rx and Tx. When FMS equals one, framesync is word-length bit clock. When this bit equals zero, frame sync is one-bit clock.
FSP Frame Sync Polarity (Bit 6). The FSP bit value should only be changed when the transmitter and receiver are dis-abled. FSP controls which edge of frame sync is the active edge for both Rx and Tx. This bit causes frame signal tobe active at rising edge when FSP equals zero, or falling edge when FSP equals one.
MOD Mode Select (Bit 5). The MOD bit value should only be changed when the transmitter and receiver are disabled. MODselects the operational mode of the SSI for ISDN functionality. When MOD is set, the SSI is configured as a U-inter-face for ISDN NT. Otherwise, set to ‘0’. Setting MOD bit and CD2 it supports the MC145574 and MC145572 ISDNinterface transceivers.
EMS Endian Mode Select (Bit 4). EMS selects the big- or little-endian mode operation. Both these modes are explainedin more detail in section 16.8.
ILS Interrupt Level Select (Bit 3-0). Set the point where an interrupt is generated for normal data buffer servicing. Thenumber is ranging from 1 to 15 of 32-bit word(s). This field controls interrupt level of both transmit and receive func-tions.
Table 16-5. SSI Control Register (SSI_CTL) Fields.
Field Description
Table 16-6. IO1 Mode Select
Bit Mode
00 General Purpose Output: Configures the SSI_IO1 pin as a general purpose output. The pin follows the state of the WIO1 field of the SSI_CTL.
01 General Purpose Input: Change detector may be used. Value can be read in from RIO1 field of the SSI_CSR.
10 Enable External TxCLK: Allows for use of an externally generated TxCLK. The clock is provided via the TxCLK pin. All general purpose I/O functions are unavailable.
11 Disable: Pin is not used. Output buffer is tristated and the input is ignored. (RESET default)
Table 16-7. IO2 Mode Select
Bit Mode
00 General Purpose Output: Configures the SSI_IO2 pin as a general purpose output. The pin follows the state of the WIO2 field of the SSI_CTL.
01 General Purpose Input: Value can be read in from RIO2 field of the SSI_CSR.
10 Frame Signal TxFSX (Output): Output the frame signal generated by the internal frame signal generation logic.
11 Frame Signal TxFSX (Input): Allows for use of an externally generated TxFSX. The frame sync signal is provided via TxFSX pin. All general purpose I/O functions are unavailable. (RESET default)
16-10 PRELIMINARY INFORMATION File: ssi.fm5, modified 7/24/99
Philips Semiconductors Synchronous Serial Interface
16.10.2 SSI Control/Status Register (SSI_CSR)
SSI_CSR is a 32-bit read/write register to control the SSI unit and to show the current status of the SSI module. Thedefault value after hardware reset is 0x0000F000.
TMS Test Mode Select (Bit 31-30). The TMS field value should only be changed when the transmitter and receiver are dis-abled. See Table 16-9.
CDE Change Detector Enable (Bit 29). CDE enables the change detector function on the SSI_IO1 pin. When CDE is set,the DSPCPU will be interrupted when CDS in the SSI status register is set. When CDE is cleared, this interrupt isdisabled. However, the CDS bit will always indicate the change detector condition.
When the change detector is enabled, the CLK samples SSI_IO1. The CDS bit will be set for either a ‘0’ –> ‘1’ or a ‘1’–> ‘0’ change between the current value and the stored value.
CD2 RXCLK Divider (Bit 28). When CD2 equals one, the internal RxCLK is divided by two. In the divide by 2 mode, theclock edge that samples the Frame Sync Pulse asserted will resync the RxCLK divider to be a data capture edge.Data samples will occur every other clock thereafter until the end of the valid slots in the frame.
SLP Sleepless (Bit 27). When set, this bit allows the SSI to ignore the global power down signal. If cleared, assertion ofthe global power down signal will cause the SSI transmitter will finish transmission of the current 16-bit word, thenenter a state similar to transmitter disabled, (SSI_CTL.TXE = ’0’).
In the receiver, a 16-bit word currently being transmitted to RxSR will complete reception and be transferred to theRxFIFO. The receiver will then enter a state similar to receiver disabled, (SSI_CTL.RXE = ‘0’).
CTUE Clear Transmitter Underrun Error (Bit 21). A control bit written by the DSPCPU to indicate that the transmitter underrunerror flag should be cleared. This is an action bit. Writing a ‘1’ clears SSI_CSR.TUE. The bit always reads ‘0’.
CROE Clear Receiver Overrun Error (Bit 20). A control bit written by the DSPCPU to indicate that the receiver overrun errorflag should be cleared. This is an action bit. Writing a ‘1’ clears SSI_CSR.TOE. The bit always reads ‘0’.
CFES Clear Framing Error Status (Bit 19). A control bit written by the DSPCPU to indicate that the receiver’s framing errorflag should be cleared. This is an action bit. Writing a ‘1’ clears SSI_CSR.FES. The bit always reads ‘0’.
CCDS Clear Change Detector Status (Bit 18). A control bit written by the DSPCPU to indicate that the change detector statuson IO1 flag should be cleared. This is an action bit. Writing a ‘1’ clears SSI_CSR.CDS. The bit always reads ‘0’.
WAW Word buffers Available for Write (Bit 15-12). The WAW[3:0] bits provide the number of 32-bit words available for writein the transmit buffer (TxFIFO). The SSI can store 15 words in the transmit FIFO. When the FIFO is empty, WAW hasthe value 15. When the FIFO is full, WAW has the value 0 and the SSI will ignore any further attempts to add wordsto the FIFO. Note: The fill routine should check that WAW is nonzero, before writing data.
WAR Word buffers Available for Read (Bit 11-8). The WAR[3:0] bits provide the number of 32-bit word available for read inthe receive buffer (RxFIFO). The SSI can store 16 words in the receive FIFO. However, the maximum value indicatedby the WAR register is 15 (because it’s a 4 bit register field). When the FIFO is empty, WAR has the value 0. Whenthe FIFO is full, WAR has the value 15 and the SSI will generate an overrun error if more data is received.
TDE Transmit Data register Empty (Bit 7). In normal operation, this bit will be set when the number of empty words in theTxFIFO is greater than SSI_CTL.ILS. If SSI_CTL.TIE is set, the SSI will generate an interrupt. When set, it indicatesthat the SSI_TxDR/TxFIFO registers require DSPCPU service for refilling after normal transmission. As the DSPCPUrefills the TxFIFO during the interrupt service routine, this bit will be cleared by the SSI when the number of emptyslots drops below the Interrupt Level Select value, SSI_CTL.ILS.
RDF Receive Data register Full (Bit 6). In normal operation, this bit will be set when the number of words in the RxFIFO isgreater than SSI_CTL.ILS. If SSI_CTL.RIE is set, the SSI will generate an interrupt. When set, this bit indicates thatnormal received data resides in SSI_RxDR register and RxFIFO buffer for reading. DSPCPU must service the RxFIFObefore a receiver overrun occurs.
TUE Transmitter Underrun Error (Bit 5). No current data was available from the TxFIFO when a load of the TxSR wasscheduled. The transmitted message may have been corrupted. Generates interrupt if enabled by TIE.
ROE Receive Overrun Error (Bit 4). Receive data has been received with no RxFIFO slot to store it. These bits have beenlost and the message stream is incomplete. Generates an interrupt if enabled by RIE.
FES Frame Error (Bit 3). A frame sync pulse has been detected where not expected or did not occur as expected duringtransmit or receive. Received data may be invalid. Transmit data have been sent out of sync. Receive frame errorRXFES generates an interrupt if enabled by RIE. Transmit frame error TXFES generates an interrupt if enabled by TIE
CDS Change Detector Status (Bit 2). The input change detector on SSI_IO1 pin has detected a change in state.
RIO1 Read IO1 (bit 1). RIO1 reflects the value on the SSI_IO1 pin.
RIO2 Read IO2 (bit 2). RIO2 reflects the value on the SSI_IO2 pin.
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TM1100 Preliminary Data Book Philips Semiconductors
16.11 TIMING DIAGRAMS
Figure 16-11 and Figure 16-12 illustrate the timing of thedata signals and the frame timing.
Table 16-9. Test Mode Select
Bit Mode
0X Normal Operation.
10 Remote Loopback Test: Direct connection of receiver serial data to transmitter serial data. Transmitter is clocked with RxCLK. No data loaded to the SSI_RxDR register or RxFIFO buffer and no interrupt of the DSPCPU is generated. Useful to allow remote device to test the communication medium and our Rx and Tx front ends.
11 Local Loopback Test: Feedback is after SSI_TxDR and SSI_RxDR register and serializer/deserializer. Allows DSPCPU to test the bulk of the Rx and Tx circuits. During Local Loopback Test an external clock on SSI_RXCLK should be present, this signal is used to clock the SSI unit.
16-12 PRELIMINARY INFORMATION File: ssi.fm5, modified 7/24/99
JTAG Functional Specification Chapter 17
by Renga Sundararajan, Hans Bouwmeester and Frank Bouwman
17.1 OVERVIEW
The IEEE 1149.1 (JTAG) standard can be used for vari-ous goals including testing connections between inte-grated circuits on board level, control over testing the in-ternal structures of the integrated circuits, and monitoringand communicating with a running system.
The JTAG standard defines on-chip test logic, four or fivededicated pins collectively called the Test Access Port(TAP) and a TAP controller.
The JTAG standard defines instructions that must al-ways be implemented by a TAP controller, in order toguarantee correct behavior on board level. Apart frommandatory instructions, the standard also allows userdefined and private instructions. In TM1100 user definedand private instructions exist for debug purposes and forproduction test. For debug there is communication be-tween a debug monitor running on the TM1100-DSPCPU and a debugger front-end running on a hostcomputer. This will be explained in chapter Section 17.3
17.2 TEST ACCESS PORT (TAP)
The Test Access Port includes three or four dedicated in-put pins and one output pin:
• TCK (Test Clock)• TMS (Test Mode Select)• TDI (Test Data In)• TRST (Test Reset, optional!)• TDO (Test Data Out)
TRST is not present on TM1100.
TCK provides the clock for test logic required by the stan-dard. TCK is asynchronous to the system clock. Storedstate devices in JTAG controller must retain their stateindefinitely when TCK is stopped at 0 or 1.
The signal received at TMS is decoded by the TAP con-troller to control test functions. The test logic is requiredto sample TMS at the rising edge of TCK.
Serial test instructions and test data are received at TDI.The TDI signal is required to be sampled at the risingedge of TCK. When test data is shifted from TDI to TDO,the data must appear without inversion at TDO after anumber of rising and falling edges of TCK determined bythe length of the instruction or test data register selected.
TDO is the serial output for test instructions and datafrom he TAP controller. Changes in the state of TDOmust occur at the falling edge of TCK. This is because
devices connected to TDO are required to sample TDOat the rising edge of TCK. The TDO driver must be in aninactive state (i.e., TDO line HIghZ) except when thescanning of data is in progress.
17.2.1 TAP Controller
The TAP controller is a finite state machine and it syn-chronously responds to changes in TCK and TMS sig-nals. The TAP instructions and data are serially scannedinto the TAP controller’s instruction and data registers viathe common input line TDI. The TMS signal tells the TAPcontroller to select either the TAP instruction register ora TAP data registers as the destination for serial inputfrom the common line TDI. An instruction scanned intothe instruction register selects a data register to be con-nected between TDI and TDO and hence to be the des-tination for serial data input.
The TAP controller’s state changes are determined bythe TMS signal. The states are used for scanning in/outTAP instruction and data, updating instruction, and dataregisters, and for executing instructions.
The controller’s state diagram (Figure 17-1) shows sep-arate states for “capture”, “shift” and “update” of data andinstructions. The reason is to leave the contents of a dataregister or an instruction register undisturbed until serialscan in is finished and the update state is entered. Byseparating the shift and update states, the contents of aregister (by that we mean the parallel stage) is not affect-ed during scan in/out.
The TAP controller must be in Test Logic Reset state af-ter power-up. It remains in that state as long as TMS isheld at 1. The controller transitions to Run-Test/Idle statefrom Test Logic Reset state when TMS = 0. The Run-Test/Idle state is an idle state of the controller in betweenscanning in/out an instruction/data register. The “Run-Test” part of the name refers to start of built-in tests. The“Idle” part of the name refers to all other cases. Note thatthere are two similar sub-structures in the state diagram,one for scanning in an instruction and another for scan-ning in data. To scan in/out a data register, one has toscan in an instruction first.
An instruction or data register must have at least twostages, the shift register stage and the parallel input/out-put stage. When an n-bit data register is to be “read”, theregister is selected by an instruction, the registers con-tents are “captured” first (loaded in parallel into shift reg-ister stage), n bits are shifted in and at the same time nbits are shifted out, and finally the register is “updated”with the new n bits shifted in.
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Note that when a register is scanned, its old value is shift-ed out of TDO and the new value shifted in via TDI is writ-ten to the register at the update state. Hence, scan in/outinvolve the same steps. This also means that reading aregister via JTAG destroys its contents unless otherwisestated. We can specify some registers as read-only viaJTAG so that when the controller transitions to updatestate for the read-only register, the update has no effect.Some times, we need read-write registers (for example,control registers used for handshake) which must beread non-destructively. In such cases, the value shiftedin determines whether the old value is “remembered” orsomething else happens.
17.2.2 TM1100 JTAG Instruction Set
TM1100 uses a 5 bit instruction register. The unspecifiedopcodes are private and their effects are undefined.Table 17-1 lists the JTAG instructions.
The JTAG instructions EXTEST, SAMPLE/PRELOAD,and BYPASS are standard instructions and are not dis-cussed here. The MACRO, BURNIN and PASS_C_S in-structions are used during hardware test mode, and arealso not discussed here. All other instructions are dis-cussed in Section 17.3
17.3 USING JTAG FOR TM1100 DEBUG
Figure 17-2 shows an overview of the JTAG access pathfrom a host machine to a target TriMedia system and asimplified block diagram of the TriMedia processor. TheJTAG Interface Module shown separately in the diagrammay be a PC add-on card such as PC-1149.1/100FBoundary Scan Controller Board from Corelis Inc or asimilar module connected to a PC serial or parallel port.The JTAG interface module is necessary only for TriMe-dia systems that are not plugged into a PC. For PC-host-ed TriMedia systems, the host based debugger front-endcan communicate with the target resident debug monitorvia the PCI bus.
The enhancements to the standard functionality of JTAGtest logic provides a handshake mechanism for transfer-
ring data to and from a TriMedia processor’s MMIO reg-isters reserved for this purpose, for posting an interrupt,and for resetting processor state. The actual interpreta-tion of the contents of the MMIO registers is determinedby a software protocol used by the debug monitor run-ning on TriMedia processor and the debug front-end run-ning on a host machine.
The communication between a host computer and a tar-get TriMedia system via JTAG requires, at a high level ofabstraction, the following components.
• A Host computer with a serial or parallel inter-face. The host computer transfers data to and from theJTAG interface module, preferably in word-parallelfashion. Also needed is JTAG interface device driversoftware to access and modify the registers of theJTAG interface module.
• A JTAG interface module (hardware) that asyn-chronously transfers data to and from the hostcomputer. The interface module synchronously transfers data toand from the JTAG TAP on a TriMedia processor,supplies the test clock TCK and other signals to theJTAG controller on TriMedia. The interface modulemay be a PC plug-in board. This module may transfer data from and to the hostcomputer in bit-serial or word-parallel fashion. Ittransfers data from and to the JTAG registers on aTriMedia processor in bit-serial fashion in accordancewith the IEEE 1149.1 standard. The JTAG interface
11110 MACRO Hardware test mode select
01010 BURNIN Private
01110 PASS_C_S Private
Table 17-1. JTAG instruction encoding
Encoding Instruction name Action
Host MachineJTAG Interface
JTAG board Connector
Serial or ParallelConnection
JTAG TAP (TCK, TMS, TDI, TDO)
MainMemory(SDRAM)DSP
CPUMMI
I$
D$
JTAG controller
MMIO
Scan Chain connecting possiblyother chips on board
TriMedia Board
Figure 17-2. TriMedia System with JTAG Test Access
DATA Highway
Module(such as a PC)
May be a PC plug-in board
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module connects to a 4 pin JTAG connector on a Tri-Media board which provides a path to the JTAG pinson a TriMedia processor. It is the responsibility of theinterface module to scan data in and out of the TriMe-dia processor into its internal buffers and make themavailable to the host computer.
• A JTAG controller on the TriMedia processorwhich provides a bridge between the externalJTAG TAP and the internal system. The controller transfers data from/to the TAP to/fromits scannable registers asynchronous to the internalsystem clock. A monitor running on a TriMedia pro-cessor and the debugger front-end running on a hostcomputer exchange data via JTAG by reading/writingthe MMIO registers reserved for this purpose, includ-ing a control register used for the handshake.
17.3.1 JTAG Instruction and Data Registers .
TM1100 has two JTAG data registers and one JTAGcontrol register (see Figure 17-3) in MMIO space and anumber a JTAG instructions to manipulate those regis-ters. Table 17-2 lists the MMIO addresses of the JTAGdata and control registers. The addresses are offsetsfrom MMIO_BASE. All references to instruction and dataregisters below are JTAG instructions and data registersand not TriMedia instruction or data registers.
• Two 32-bit data registers, JTAG_DATA_IN andJTAG_DATA_OUT in MMIO space. Both can beconnected in between TDI and TDO like the standardBypass and Boundary Scan registers of JTAG (notshown in Figure 17-3).The JTAG_DATA_IN register can be read or written tovia the JTAG port. The JTAG_DATA_OUT register isread-only via the JTAG port, so that scanning outJTAG_DATA_OUT is non-destructive.
The JTAG_DATA_IN and JTAG_DATA_OUT are read-able/writable from the TriMedia processor via theusual load/store operations.
• An 8-bit control register JTAG_CTRL in MMIOspace. The JTAG_CTRL register is used for hand-shake between a debug monitor running on a TriMe-dia and a debugger front-end running on a host.JTAG_CTRL.ofull = 1 means that JTAG_DATA_OUThas valid data to be scanned out. On power-on resetof the TriMedia Processor, JTAG_CTRL.ofull = 0.JTAG_CTRL.ofull is both readable and writable viaJTAG tap. Writing 0 to JTAG_CTRL.ofull via JTAG isa ‘remember’ operation, i.e., JTAG_CTRL.ofullretains its previous state. Writing 1 toJTAG_CTRL.ofull via JTAG is a ‘clear’ operation, i.e.,JTAG_CTRL.ofull becomes 0. JTAG_CTRL.ifull = 0 means that the JTAG_DATA_INregister is empty. JTAG_CTRL.ifull = 1 means thatJTAG_DATA_IN has valid data and the debug monitorhas not yet copied it to its private area. On power-onreset of the TriMedia processor, JTAG_CTRL.ifull = 0.JTAG_CTRL.ifull is readable and writable via JTAG.Writing 0 to JTAG_CTRL.ifull via JTAG is a ‘remem-ber’ operation, i.e., JTAG_CTRL.ifull retains it previ-ous state. Writing 1 to JTAG_CTRL.ifull posts aninterrupt on hardware line 18. The peripheral blocks on a TriMedia processor mayenter a “power down” state to reduce power con-sumption. The JTAG_CTRL.sleepless bit determinesif the JTAG block participates in a power down state.In the power-on RESET state, JTAG_CTRL.sleep-less bit is 1 meaning the JTAG block does not powerdown. It can be read and written to by the TriMediaprocessor via load/store operations and by thedebugger front-end running on a host by scan in/out.
• Two virtual registers, JTAG_IFULL_IN andJTAG_OFULL_OUT. The first virtual registerJTAG_IFULL_IN connects the registersJTAG_CTRL.ifull and JTAG_DATA_IN in series. Like-wise, the virtual register JTAG_OFULL_OUT con-nects JTAG_CTRL.ofull and JTAG_DATA_OUT inseries. The reason for the virtual registers is to shorten thetime for scanning the JTAG_DATA_IN andJTAG_DATA_OUT registers. Without virtual registers,
Table 17-2. MMIO Register Assignments
MMIO Offset JTAG Register
0x 10 3800 JTAG_DATA_IN
0x 10 3804 JTAG_DATA_OUT
0x 10 3808 JTAG_CTRL
To
TDO
JTAG_DATA_IN
JTAG_DATA_OUT
JTAG_CTRL
from
TDI
01
ifull ofullUnused Bits
7
031
31 0
Figure 17-3. Additional JTAG data registers and control register
2SleeplessBit
3
17-4 PRELIMINARY INFORMATION File: jtag.fm5, modified 7/25/99
we must scan in an instruction to selectJTAG_DATA_IN, scan in data, scan an instruction toselect JTAG_CTRL register and finally scan in thecontrol register. With virtual register, we can scan inan instruction to select JTAG_IFULL_IN and thenscan in both control and data bits. Similar savingscan be achieved for scan out using virtual registers.
• Five JTAG instructions.• Five instructions SEL_DATA_IN, SEL_DATA_OUT,
SEL_IFULL_IN, SEL_OFULL_OUT, andSEL_JTAG_CTRL for selecting the registers to beconnected between TDI and TDO for serial input/output.
• An instruction RESET for resetting the TriMediaprocessor to power on state.
• In the capture-IR state of the TAP controller, the least2 significant bits (bits 0 and 1) of the shift registerstage must be loaded with the ‘01’ as required in thestandard. The standard allows the remaining bits ofthe IR shift stage to be loaded with design specificdata. The bits 2, 3 and 4 of the IR shift stage areloaded with bits 0, 1 and 2 of the JTAG_CTRL regis-ter. This means that shifting in any instruction allowsthe 3 least significant bits of the JTAG_CTRL registerto be inspected. This reduces the polling overheadfor data transfer.
Race ConditionsSince the JTAG data registers live in MMIO space andare accessible by both the TriMedia processor and theJTAG controller at the same time, race conditions mustnot exist either in hardware or in software. The followingcommunication protocol uses a handshake mechanismto avoid software race conditions.
17.3.2 JTAG Communication Protocol
The following describes the handshake mechanism fortransferring data via JTAG.
• Transfer from debug front-end to debug monitorThe debugger front-end running on a host transfersdata to a debug monitor via JTAG_DATA_IN register.It must poll JTAG_CTRL.ifull bit to check ifJTAG_DATA_IN register can be written to. If theJTAG_CTRL.ifull bit is clear, the front-end may scandata into JTAG_DATA_IFULL_IN register. Note thatdata and control bits may be shifted in withSEL_IFULL_IN instruction and the bit shifted intoJTAG_CTRL.ifull register must be 1. This action trig-gers an interrupt. The debug monitor must copy thedata from JTAG_DATA_IN register into its privatearea when servicing the interrupt and then clear
JTAG_CTRL.ifull bit thus allowing JTAG interfacemodule to write to JTAG_DATA_IN register the nextpiece of data.
• Transfer from monitor to front-endThe monitor running on TriMedia must check ifJTAG_CTRL.ofull is clear and if so, it can write datato JTAG_DATA_OUT. After that, the monitor must setthe JTAG_CTRL.ofull bit. The debugger front-endpolls the JTAG_CTRL.ofull bit. When that bit is set, itcan scan out JTAG_DATA_OUT register and clearJTAG_CTRL.ofull bit. Since JTAG_DATA_OUT isread-only via JTAG, the update action at the end ofscan out has no effect on JTAG_DATA_OUT. TheJTAG_CTRL.ofull bit, however, must be cleared byshifting in the value 1.
• Controller StatesIn the power-on reset state, JTAG_CTRL.ifull andJTAG_CTRL.ofull must be cleared by the JTAG con-troller.
17.3.3 Example Data Transfer Via JTAG
Scanning in a 5-bit instruction will take 12 TCK cyclesfrom the Run-Test/Idle state - 4 cycles to reach Shift-IRstate, 5 cycles for actual shifting in, 1 cycle to exit1-IRstate, 1 cycle to Update-IR state, and 1 cycle back toRun-Test/Idle state. Likewise, scanning in a 32 bit dataregister will take 38 TCK cycles and transferring an 8-bitJTAG_CTRL data register will take 14 TCK cycles fromIdle state. However, if a data transfer follows instructiontransfer, then the transition to DR scan stage can bedone without going through Idle state, saving 1 cycle.
17.3.3.1 Transfer of Data to TriMedia Via JTAG
Poll control register to check if input buffer is empty or notand scan in data when it is empty and set the ifull controlbit to 1 triggering an interrupt. Note that scanning in anyinstruction automatically scans out the 3 least significantbits (including ifull and ofull bits) of JTAG_CTRL register.
Table 17-3. Transfer of Data in via JTAG
Action Number of TCK cycles
IR shift in SEL_IFULL_IN instruction 12
While JTAG_CTRL.ifull = 1, scan in SEL_IFULL_IN instruction
11+
DR scan 33 bits of register JTAG_IFULL_IN 38
TOTAL 61+ cycles
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17.3.3.2 Transfer of Data from TriMedia Via JTAG
Poll control register to check if output buffer is full or notand scan out data when it is full and clear the ofull controlbit. Note that scanning in any instruction automaticallyscans out the 3 least significant bits (including ifull andofull bits) of JTAG_CTRL register.
Note that the above timings do not include the over-heads of the JTAG driver software driving the JTAG in-terface module plugged into a PC.
17.3.4 JTAG Interface Module
It is expected that the interface module will be a program-mable JTAG interface module, one end of which is con-nected to a JTAG tap and the other end is connected toa host computer via a serial line or parallel line orplugged in to a PC. It is up to the JTAG driver softwareon a host computer to program the JTAG interface mod-ule via the serial/parallel interface for transferring data to/from the target. The transfer rates will depend on the in-terface module.
Table 17-4. Transfer of Data out via JTAG
Action Number of TCK cycles
IR shift in SEL_OFULL_OUT instruction 12
While JTAG_CTRL.ofull = 0, scan in SEL_OFULL_OUT instruction
11+
DR scan 33 bits of register JTAG_OFULL_OUT 38
TOTAL 61+ cycles
17-6 PRELIMINARY INFORMATION File: jtag.fm5, modified 7/25/99
On-Chip Semaphore Assist Device Chapter 18
TM1100 has a simple MP semaphore assist device. It isan 32 bits register, accessible through MMIO by eitherthe local TM1100 CPU or by any other CPU on PCIthrough the aperture made available on PCI. The sema-phore “SEM” is located at MMIO offset 0x10 0500.
The operation is as follows: each master in the systemconstructs a personal nonzero 12 bit ID (see below). Toobtain the global semaphore, a master does the follow-ing action:
write ID to SEM (use 32 bit store, with ID in 12 LSB)retrieve SEM (use 32 bit load, it returns 0x00000nnn)if (SEM = ID) “performs a short critical section action” write 0 to SEMelse “try again later, or loop back to write”
18.1 SEM DEVICE SPECIFICATION
SEM is a 32 bits MMIO location. The 12 LSB consist ofstorage flip-flops with surrounding logic, the 20 MSB's al-ways return a zero when read.
SEM is RESET to zero by powerup reset.
When SEM is written to, the storage flip-flops behave asfollows:
if (cur_content == 0) new_content = write_value;else if (write_value == 0) new_content = 0;/* ELSE NO ACTION ! */
18.2 CONSTRUCTING A 12-BIT ID
A TM1100 processor can construct a personal, nonzero12 bit ID in a variety of ways. Below are some sugges-tions.
PCI configspace PERSONALITY entry. Each TM1100receives a 16 bits PERSONALITY value from the EE-PROM during boot. This PERSONALITY register is lo-cated at offset 0x40 in configuration space. In a MP sys-tem, some of the bits of PERSONALITY can beindividualized for each CPU involved, giving it a unique
2/3/4 bit ID, as needed given the max. number of CPU'sin the design.
In the case of a host-assisted boot of TM1100, the PCIBIOS assigns a unique MMIO_base and DRAM_base toeach and every TM1100. In particular, the 11 MSB's ofeach MMIO_base are unique, since each MMIO apertureis 2 MByte in size. These bits can be used as a person-ality ID. Use bit 11 (MSB) equal '1' to guarantee a nonze-ro ID#.
18.3 WHICH SEM TO USE
Each TM1100 in the system adds a SEM device to themix. The intended use is to treat one of these SEM de-vices as THE master semaphore in the system. Manymethods can be used to determine which SEM is masterSEM. Some examples below:
Each DSPCPU can use PCI configurationspace access-es to determine which other TM1100's are present in thesystem. Then, the TM1100 with the lowest PERSONAL-ITY number, or the lowest MMIO_base is chosen as theTM1100 containing the master semaphore.
18.4 USAGE NOTES
To avoid contention on the master SEM device, it shouldonly be used for inter-processor semaphores. Processesrunning on a single CPU can use regular memory to im-plement synchronization primitives.
The critical section associated with SEM should be keptas short as possible. Preferably, SEM should only beused as the basis to make multiple memory resident sim-ple semaphores. In this case, the non-cacheable DRAMarea of each TM1100 can be used to implement thesemaphore datastructures efficiently.
As described here, SEM does not guarantee starvation-free access to critical resources. Claiming of SEM ispurely stochastical. This should work fine as long asSEM is not overloaded. Utmost care should be taken inSEM access frequency and duration of the basic criticalsections to keep the load conditions reasonable.
00000000000000000000
31 12 11 0
SEM0x10 0500
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18-2 PRELIMINARY INFORMATION File: sem.fm5, modified 7/23/99
Arbiter Chapter 19
by Eino Jacobs, Luis Lucas, Chris Nelson, Allan Tzeng, Gert Slavenburg
19.1 ARBITER FEATURES
The TM1100 internal highway bus conveys all the mem-ory and MMIO traffic. The peripherals, also called devic-es or units, described along this data-book are connect-ed to this internal highway bus. Accesses to the bus arecontrolled by a central arbiter. Figure 2-1 on page 2-1pictures the whole system where the arbiter is embeddedin the main memory interface block. The traffic includesthe memory requests issued by most of the on-chip de-vices as well as the MMIO transactions that are issuedby the DSPCPU or by the PCI block and responded to bythe peripherals.
The arbiter has been designed in order to make TM1100a true real-time system by providing a highly programma-ble allocation scheme of the bus. The primary character-istics are:
• round robin arbitration• hierarchical organization• programmable allocation of highway bandwidth• dual priorities with priority raising mechanism
These features are explained in the next sections of thischapter. Arbiter programming is done through two MMIOregisters:
• ARB_RAISE• ARB_BW_CTL
The default values (after hardware RESET) stored inthese two MMIO registers are suitable for most of the ap-plications.
If these default settings introduce violations of real-timeconstraints in units like VI, VO, AI and AO (each of theseunits have a Highway Bandwidth Error detection mecha-nism) then ARB_BW_CTL register should be pro-grammed to 0x090A9. This setting gives almost maxi-mum priority to real-time units but may slow down theCPU.
Fine tuning of the arbiter settings is described in the fol-lowing sections.
19.2 DUAL PRIORITIES WITH PRIORITY RAISING MECHANISM
The best CPU performance is obtained if cache missescan take priority over peripheral requests on the high-way.
However, peripherals need to have a maximum guaran-teed latency that is low enough to satisfy the real timeconstraints of I/O units.
TM1100 provides this feature with the following priorityraising mechanism.
Device requests can have 2 priorities: low priority andhigh priority. Within each class there is fair, round-robinarbitration (Section 19.3). Requests with high prioritytake precedence over requests with low priority.
Devices can indicate the priority of their requests to below or high.
A device may initially post a request with low priority. If itdoes not get serviced within a particular waiting time,then the device can raise the priority of the request tohigh priority. This can be done when the worst case la-tency at high priority approaches the real time constraintof the device. Thus, the device uses only spare band-width without slowing down the CPU unless real timeconstraints require it to claim high priority.
In TM1100, only the ICP unit has its own priority raisinglogic (i.e. it controls the low to high transition of the re-quest). Refer to Chapter 13, “Image Co-Processor,” formore information.
Priority raising for VLD, PCI, VI and VO units (devices) ishandled by the arbiter central priority raising mechanism.The central priority raising mechanism settings are con-trolled from the DSPCPU with the ARB_RAISE MMIOregister (see Table 19-1). The delay is the amount oftime for which the arbiter handles the request at low pri-ority.
The delay is defined by a 5-bit field (dedicated per unit).Delay is counted in CPU clock cycles. The granularity ofthe delay is 16 cycles, so the maximum time spent at lowpriority for each request can be programmed from 0 to496 cycles, inclusive, in steps of 16 cycles.
The default value for the entire ARB_RAISE register is 0.This causes all requests from VLD, PCI, VI and VO to be
Table 19-1. ARB_RAISE register layout
Offset Name Bits Fields
0x10010C ARB_RAISE 19:15 VLD_delay[4:0]
14:10 PCI_delay[4:0]
9:5 VI_delay[4:0]
4:0 VO_delay[4:0]
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TM1100 Preliminary Data Book Philips Semiconductors
handled as high-priority requests until the ARB_RAISEregister contents has been changed for the applicationrequirements.
Corner-case note: There is some risk in setting the delayhigh, then lowering it, as the last request submitted withthe high delay might violate the latency constraints of thenew real-time domain.
However this should not happen since this registershould be set before the application starts.
The other devices (AI, AO and BTI (Boot Block)) and theCPU will always have their requests considered as highpriority.
High priority for the CPU will give maximum possible per-formance.
AO and AI requests are happening at very low rate.Hence, the probability that they take time away from theCPU is negligible.
19.3 ROUND ROBIN ARBITRATION
In addition to the dual priority mechanism a round-robinarbitration is used to schedule the requests that have thesame priority.
The purpose is to ensure, for every device with a high pri-ority request, a maximum latency for gaining access tothe highway and/or a minimum share of the availablebandwidth.
Round-robin arbitration ensures that no starvation of re-quests can occur and therefore requests with real-timeconstraints can be handled in time.
The round robin arbitration algorithm is as follows.
Requests are granted according to a dynamic priority list.Whenever a device gets a request granted it will bemoved to the last position in the priority list and anotherdevice will be moved to the first position in the priority list.Priorities are rotated. A device with a waiting request willeventually reach the first place in the priority list.
As an example, Figure 19-1 shows a state diagram of anarbitration state machine with 2 requesters. The nodes Aand B indicate states A and B. In state A requester A hasownership of the highway, in state B requester B hasownership. The arc from state A to state B indicates thatif the current state is state A and a request from request-er B is asserted, then a transition to state B occurs, i.e.ownership of the highway passes from requester A to re-quester B.
When in a particular state none of the arcs leaving fromthat node has its condition fulfilled, then the state ma-chine remains in the same state.
When both requester A and B have requests asserted,then ownership of the highway switches between A andB, creating fair allocation of ownership.
Figure 19-2 pictures a state diagram that allocates fairarbitration with 3 requesters.
19.3.1 Weighted Round Robin Arbitration
Not all devices need to have equal latency and band-width. It is preferred to allocate bandwidth to units ac-cording to their needs. This is achieved with weightedround-robin and can be illustrated in the following exam-ples.
Figure 19-3 pictures a state machine with two requestersA and B with double weight given to requester A. Thereare now 2 states A1 and A2 where requester A has own-ership of the highway. When both A and B requests areasserted, then requester A will have twice as often own-ership of the highway than requester B.
A B
Figure 19-1. State diagram of round robin arbitra-tor with 2 requesters.
B
A
A B
Figure 19-2. State diagram of round robin arbitra-tor with 3 requesters.
A&~C
B
C
AC
B&~AC&~B
A1 B
Figure 19-3. State diagram of round robin arbitra-tor with 2 requesters; A has double weight.
B&~A
A
A2
A
B
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Philips Semiconductors Arbiter
The example in Figure 19-4 shows a state machine with3 requesters, in which double weight is given to request-er A.
Such state machines can become very complex andcannot be implemented for a large system like TM1100with 9 requesters. Hierarchy or arbitration levels areused to overcome this problem.
19.3.2 Arbitration Levels
The arbitration is split into multiple levels of hierarchy.Each level of hierarchy has an independent arbitrationstate machine. At the bottom of the hierarchy, the arbitra-tion is performed between a group of devices. Whicheverof these devices “wins” is passed to the next level of hi-erarchy, where the selected device competes with otherdevices at that level for highway access.This is contin-ued until the highest level of arbitration.
By splitting arbitration into multiple levels it is easy tosupport a large number of highway devices while thecomplexity of the arbitration state machines at each levelof hierarchy remains modest.
A1 B
Figure 19-4. State diagram of round robin arbitra-tor with 3 requesters; A has double weight.
B
A2C
A
C
A
B&~A
C&~AA&~B
A&~C
B&
~C
&~
A
C&
~B
&~
A
L1 arbitration
L6 arbitration
L5 arbitration
L4 arbitration
L3 arbitration
L2 arbitration
Cache priority-based arbitration
vo_req
icp_reqhicp_reql
vi_req
pci_req
vld_req ai_req ao_req
bti_mmio_reqbti_req
pci_mmio_req
ic_req
dc_req
dc_mmio_req
dc_req_pref
1/2/3 1/2/3
1/3/5 1/3/5/7
1/3/5/7 1/3/5
1/2 1/3/5
1/3/5 1/2
1 1 11 11 1 2
Figure 19-5. Arbitration architecture
dvdd_req
1
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TM1100 Preliminary Data Book Philips Semiconductors
Hierarchy makes it also easy and natural to allocate busbandwidth or latency to a group of devices. Most band-width or latency demanding devices are located at thetop of the hierarchy while the less demanding are at thebottom of the hierarchy and get a small amount of overallbandwidth.
19.4 ARBITER ARCHITECTURE
In addition to the dual priority mechanism described inSection 19.2, TM1100 supports an arbitration architec-ture made of 6 fixed levels of hierarchy. This is combinedwith a programmable weighted round robin algorithm perlevel, as pictured in Figure 19-5.
The weights can be adjusted by software, to allocatebandwidth and latency depending on application require-ments.
Within a level of hierarchy the devices can have equalweights, giving them an equal share of bandwidth or they
can have different weights, giving them an unequal shareof the bandwidth for that level.
The arbitration weights at each level are described inTable 19-3 and illustrated in Figure 19-5.
Table 19-2 presents the minimum bandwidth allocationat Level 1 between the DSPCPU and the peripherals (thelevel 2) according to the different weight values that canbe programmed. Note that programming a weight of 3/3or 2/2 instead of 1/1 is legal and results in the same allo-cation.
Note: The different types of requests from the DSPCPUcaches are arbitrated amongst each other, resulting in asingle CPU request to the arbiter. So does the PCI unit.
The weight programming is done by setting the MMIOregister ARB_BW_CTL. Register offset as well as fielddescription and coding is provided in Table 19-4.
The hardware RESET value of ARB_BW_CTL is 0, re-sulting in a weight of 1 for all requests.
Note that each media processor application needs tocarefully review its arbiter settings.
Table 19-2. Minimum Bandwidth Allocation Between CPU Caches and Peripheral Units.
weight of CPU and caches
weight of level 2
bandwidthat level 1
bandwidthat level 2
3 1 75% 25%
2 1 67% 33%
3 2 60% 40%
1 1 50% 50%
2 3 40% 60%
1 2 33% 67%
1 3 25% 75%
Table 19-3. Arbitration Weights at Each Level
Level Arbitration Weights
level 1: CPU MMIO, Dcache, Icache are arbitrated with fixed priorities between each other and together have a programmable weight of 1, 2 or 3.Level 2 has a programmable weight of 1, 2 or 3.
level 2: Video Out has a programmable weight of 1, 3 or 5.Level 3 has a programmable weight of 1, 3, 5 or 7.
level 3: The ICP has a programmable weight of 1,3,5 or 7. Level 4 has a programmable weight of 1,3 or 5.
level 4 The Video In has a programmable weight of 1 or 2.Level 5 has a programmable weight of 1,3 or 5.
level 5: The PCI unit has a programmable weight of 1,3 or 5.Level 6 has a programmable weight of 1 or 2.
level 6: Level 6 contains several lower bandwidth and/or latency tolerant devices. The VLD has a weight of 2. Audio In, Audio Out, DVDD and the boot block (only active during booting) have a weight of 1.
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19.5 ARBITER PROGRAMMING
The TM1100 arbiter accepts programmable bandwidthweights to directly control the percentage of bandwidthallocated to each unit in the worst case, in which all band-width is used.
If not all bandwidth is used, then all units eventually gettheir desired bandwidth (as the bus becomes free) re-gardless of the weights .
However, the weights still matter to indirectly guaranteeeach unit a worst-case latency, which is important for thereal-time behavior.
TM1100 units come in two flavors.
The first flavor is units which have hard real-time con-straints, i.e. Video Out (VO), Video In (VI), Audio Out(AO) and Audio In (AI). To assure multimedia functional-ity, these units must be able to acquire the bus within afixed amount of time in order to fill or empty a buffer be-fore it over- or underflows.
The second flavor includes the CPU, PCI, ICP, VLD andDVDD. These units can absorb long latencies, but per-formance is enhanced (there are fewer stall cycles orwaiting cycles) if latency is short. The bandwidth require-ment is usually known and depends on the application. Itis especially well known for ICP and VLD or DVDD thathave a fixed bandwidth in multimedia applications.
For the TM1100 DSPCPU, latency is of prime impor-tance. CPU performance reduces as average latency in-creases. The design of the arbiter guarantees that theDSPCPU gets all unused bus bandwidth with lowest pos-sible latency. Optimal operation is achieved if the arbiteris set in such a way that the DSPCPU has the best pos-sible latency given the required latency and bandwidth ofunits active in the application.
To pick programmable weights and priority raising delaysthen, the following procedure is recommended:
1. Try to keep CPU weight as high as possible through the remaining steps.
2. Pick weights sufficient to guarantee latency to hard real-time peripherals (see Section 19.5.1).
3. Pick weights for remaining peripherals in order to give enough bandwidth to each (see Section 19.5.2). Step 2 above has priority, because bandwidth can be ac-quired as the bus becomes free and because the hard real-time units use a known amount of bandwidth.
4. If latency and bandwidth slack remains, increase pri-ority raise delays in order to improve average CPU la-tency.
19.5.1 Analysis of Latency
In the following, ceil(X) is the least integral value greaterthan or equal to X.
Latency is defined in each real-time unit chapter throughthis data-book. Refer to the related sections to find outthe latency requirement according to the mode and clockspeed at which the device is operating.
This latency value has to be larger than the maximum la-tency Lx (in nanoseconds) guaranteed by the arbiter.
For a device x the arbiter guarantees a latency of:
Lx = Lx,sc * (SDRAM cycle time in ns)
where
Lx,sc = (Dx * T) + E + ceil(Dx * T / Kd) * K + ceil(16*Rx/C)
is the latency in SDRAM clock cycles.
Latency in CPU clock cycles is defined by:
Lx,cc = ceil(Lx,sc * C)
The symbols are defined as follows:
T = 20 cycles (transaction length, assuming worst casepattern alternating reads and writes).
E = 10 cycles (extra delay in case the first transactionmade by the CPU requires a different bank order to sat-isfy the critical word first.
K = 19 cycles (refresh transaction length).
Kd is the programmed refresh interval (see Section 11.10on page 11-6).
C is the CPU/SDRAM ratio (i.e. 5/4, 4/3, 3/2, 2/1 or 1 asexplained in Section 11.5.2 on page 11-3).
Rx is the priority raise delay of unit x as stored in MMIOregister ARB_RAISE (see Section 19.2).
Rx = 0 for units other than VO, VI, PCI or VLD.
Dx is the worst case number of requests that the arbiterallows before the request from device x goes through.
Dx includes the transaction from device x (the unit whichneeds the data) as well as the internal implementationdelays that occur in the transaction.
Dx is derived from the arbiter settings as follows:
If CPU/SDRAM ratio is 5/4 (for example memory fre-quency is 80 MHz and CPU frequency is 100 MHz), re-fresh interval Kd is 1220 cycles, and Rx is 2, then themaximum latency for VO is:
Note: Average latency is normally much lower than worstcase latency, because rarely many devices issue re-quests at exactly the same time (but this is assumedwhen evaluating the maximum latency).
Note: All real-time units have a special exception notifi-cation flag that is raised if an overflow or underflow oc-curs while operating.
Note: To compute the latency Lx when a unit is not en-abled, its weight has to be set to 0 in the D2,3,4,5,6 equa-tions and in DAI,AO,VLD for AI, AO or VLD.
These equations are not accurate for all the weights, butgive an upper bound of the worst case (which is usuallytoo pessimistic).
A much more accurate number could be found by simu-lating the arbiter, e.g. if the settings are: CPUweight=1,L2weight=2, VOweight=1 and L3weight=1, then
DVO = ceil[(1 + 1) / 1] * ceil[(1 + 2) / 2]
giving 4 requests. But actually the worst case grant re-quests order is: CPU, L3, VO - resulting in 3 requestsonly.
19.5.2 Analysis of Bandwidth
In the following, ceil(x) means the least integral valuegreater than or equal to x.
Minimum allocated bandwidth, Bx for a device x, by thearbiter is defined as follows:
Bx = (Mcycles - Kk) * S / [T * Ex + (16 * Rx / C)]
Where
Mcycles is the total amount of SDRAM cycles available ina period P in which the bandwidth is computed. For ex-ample, if the period is 1 second and SDRAM runs at 80MHz then Mcycles is 80,000,000.
Kk is the amount of SDRAM cycles used by the refreshduring the same period P.
resulting in 26.23 million bytes per second which corre-sponds to 25.01 MB/s.
Note: In order to compute the latency Bx when a unit isnot enabled its weight has to be considered as 0 in theE2,3,4,5,6 equations and in EAI,AO,VLD for AI, AO orVLD.
The maximum amount of requests Ax for device x al-lowed during Mcycles period is:
Ax = floor(Bx / S)
Where floor(X) is the greatest integral value less than orequal to X.
Note: This number does not take into account the worstcase pattern for request acknowledgment. Thus if the pe-riod is too small Ax is not accurate.
19.6 EXTENDED BEHAVIOR ANALYSIS
The following sections try to give a more accurate behav-ior of the TM1100 arbitration system.
19.6.1 Extended Bandwidth Analysis
The minimum bandwidth allocation derived from the ar-biter settings is accurate if one of the two following con-ditions are true:
• The units emit requests all the time (i.e. do back-to-back requests).
• After a request has been acknowledged, the unitemits a new request before the new arbitration point.The arbitration is decided around every 16 cycles.This time depends on the direction of the transac-tions (read/write).
In TM1100 the only unit able to almost sustain back-to-back requests is the data cache. The other units will posta request and wait for the data before the next request isposted. This behavior makes the bandwidth computa-tion:
• almost accurate if the unit is down in the arbiter hier-archy (true if the units placed above are enabled).
• rather inaccurate if large weights are used for a unit.
Since no back-to-back requests are implemented theworst case is that a unit can only get one request out of
three if all the others are asking. This limits the use oflarge weights for other units than the data cache.
However some units might be able to catch one requestout of two. This depends on the way requests interleave,since the arbitration point is dependent on the type of therequest (read or write) as well as on the CPU ratio.
This makes it almost impossible to describe the behaviorprecisely.
The exact bandwidth necessary for units like VO, VI, AOor AI (see dedicated sections in each correspondingchapter) are well known. If the arbiter settings allocatemore bandwidth for these units than they can use, theextra bandwidth can be used by the units that are locatedbelow these units (VO, VI) or at the same level (AO andAI) in the arbiter hierarchy.
As an example, with the default settings, VO gets 25% ofthe available bandwidth and the CPU gets 50%. If theSDRAM clock speed is 100 MHz, then 100 MB/s are al-located to VO. If VO runs at 27 MHz (NTSC or PALmode), then VO will not use all this allocated bandwidth.Thus any of the units that are below VO can potentiallyuse the remaining allocated bandwidth.
In other words - even if only 10% are allocated to one unitlike the CPU, PCI or the ICP, it may use more.
19.6.2 Extended Latency Analysis
Some units (VO and VI) have a latency/bandwidth re-quirement and their behavior needs to be simulated in or-der to find out the correct settings. For example the re-quirement for VO (in image mode 4:2:2 or 4:2:0 withoutup scaling, overlay disabled) is:
• During 128 VO clock cycles, VO block needs to have 2 requests acked ([2 Ys, one U and one V]/2).
The default value 0 for ARB_BW_CTL leads to a bus al-location of 50% for CPU, 25% for VO and 25% for L3blocks.
The worst case arbitration for VO is then: CPU L3 CPUVO, CPU L3 CPU VO to which the refresh (K), internaldelays (T) and E for the first CPU request need to beadded.
The first VO request will require 129 SDRAM cycles(DVO = 5 or from the worst case pattern 19 + 10 + 20 + 4* 20).
The arbitration pattern shows that the following requestwill require (in the worst case) an extra 4 * 20 SDRAM cy-cles. Thus VO clock speed cannot be greater than61.24% (128 / [129 + 80]) of the SDRAM clock speed.
By changing the settings to 33% for the CPU, 33% for VOand 33% for L3 blocks (i.e. CPUweight = 1, L2weight = 2,VOweight = 1, L3weight = 1), the new SDRAM/VO clockpercentage becomes 75.74% (128 / [109 + 60]) corre-sponding to a worst case arbitration pattern of CPU L3VO, CPU L3 VO.
Before changing the settings the minimum SDRAMspeed to run VO at 74.25 MHz (High Definition speed)was 122 MHz. After the new allocation 100 MHz is fine.Note that here DVO remains equal to 5.
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When VO is running in image mode 4:2:2 or 4:2:0 withoutupscaling and overlay enabled, the requirements be-come:
• During the first 64 VO clock cycles at least onerequest must be acked (the OL (overlay) data).
• During 128 VO clock cycles, VO block requires to have 4 requests acked ([4 OLs, two Ys one V andone U]/2).
If the settings are 33% for the CPU, 33% for VO and 33%for L3 blocks then the worst case arbitration pattern isCPU L3 VO, CPU L3 VO, etc.
The first requirement limits the VO/SDRAM ratio to
(64 / [19 + 10 + 20 + 3 * 20]) = 58.7%.
The second requirement gives a VO/SDRAM ratio of44.29% (128 / [19 + 10 + 20 + 3 * 20 + 3 * 20 * 3]).
Thus if VO clock speed is supposed to be 54MHz (pro-gressive scan) the SDRAM has to run at least at 122MHz.
By setting the arbiter to 25% for the CPU, 37.5% for VOand 37.5% for VI (CPUweight = 1, L2weight = 3, VOweight =1, L3weight = 1, assuming only VO and VI are enabled)the arbitration pattern becomes CPU VI VO VI CPU VOVI VO CPU VI VO.
Now both VI and VO are able to catch one request out oftwo, thanks to the read / write overlap. This leads to aVO/SDRAM ratio of 47.5% or a 113 MHz SDRAM.
19.6.3 Raising Priority
If VO is running at 27 MHz (NTSC or PAL) without over-lay and CPUweight is set to 3 while all the other weightsare set to 1, then the worst case latency derived from19.5.1 for VO is:
If the SDRAM is running at 80 MHz and since the latencyfor VO is one request in 64 VO clock cycles (there is noback to back request and the requirement is two re-
quests in 128 VO clocks), this gives a maximum latencyfor VO of floor(64 / (27 / 80)) = 189 SDRAM cycles.
This means that VO requests can remain at low priorityfor 189 - 169 = 20 SDRAM cycles.
If the CPU clock speed is 100 MHz (ratio is 5 / 4) then theARB_RAISE register can be programmed to
floor(20 * (5 / 4) / 16) = 1.
VO requests will stay at low priority for 16 cycles allowingslightly better average CPU performance.
19.6.4 Conclusion
There is no obvious way to set the best weights for laten-cy or bandwidth allocation since the behavior of eachblock cannot be easily described with equations.
Practical results obtained by running applicationsshowed that once the arbiter is weighted to meet laten-cies the remaining weight settings do not allow much im-provement.
The best way to tune the weights is by experiment, run-ning the application.
The only accurate computation is the maximum worstcase latency, which ensures that the hard real-time unitswork properly.
This computation gives an upper bound and can be toopessimistic - but it still gives the right order of magnitude.Refer to Table 19-5 for the recommended allocationmethod.
Table 19-5. Recommended Allocation Method
Video In allocate required latency
Video Out allocate required latency
Audio In allocate required latency
Audio Out allocate required latency
ICP allocate bandwidth
PCI allocate bandwidth
VLD allocate bandwidth/latency
DVDD allocate bandwidth/latency
19-8 PRELIMINARY INFORMATION File: arb.fm5, modified 7/23/99
Power Management Chapter 20
by Eino Jacobs
20.1 OVERVIEW
TM1100 supports power management in two ways:
• It has a ‘power down’ mode in which most clocks onthe chip are shut down and the SDRAM main mem-ory is brought into low-power self-refresh mode.
• It has mechanisms to shut off certain blocks com-pletely if not used by an application.
20.2 BLOCK SHUT-OFF
This feature is new in TM1100. It allows to separatelyshut off the Enhanced Video-Out (EVO) and Image Co-Processor (ICP) facilities, in case they are not used.
The EVO can be separately powered down by writing a1 to EVO_CTL.PWDN. (This is bit 7 of EVO_CTL). TheEVO block only powers up again after this operation, if aRESET is performed.
Note: This feature is only present in TM1100, but notguaranteed in future implementations of the architecture.The bit EVO_CTL.PWDN is reserved in future implemen-tations.
The ICP can be separately powered down by settingICP_STATUS.PWDN via microcode. (This is bit 31 ofICP_STATUS. Direct MMIO write does not work for thatpurpose). Once the BUSY bit gets deasserted, the ICPpowers down. The ICP block only powers up again afterthis operation, if a RESET is performed.
Note: This feature is only present in TM1100, but notguaranteed in future implementations of the architec-ture.The bit ICP_STATUS.PWDN is reserved in futureimplementations.
20.3 ENTERING AND EXITING POWER DOWN MODE
Power management is software controlled and is initiat-ed by writing to the MMIO register POWER_DOWN. Dur-ing execution of this MMIO operation the system is pow-ered down without completing the MMIO operation. Onlywhen the system wakes up from power down mode, theMMIO operation is completed. This means that duringthe execution of a program on the DSPCPU the momentof power down is defined exactly: any instruction beforethe instruction that contains the MMIO operation is com-pleted before entering power down mode. The instruc-tion containing the MMIO operation and all subsequent
instructions are completed after wake up from powerdown mode.
Wake-up from power down mode is effected by receivingan interrupt (any interrupt) that passes the acceptancecriteria of the interrupt controller.
There is also wake-up from power down if a peripheralunit asserts a memory request signal on the highway.
During power down mode the whole chip is powereddown, except the PLLs, the interrupt logic, the timers, thewake-up logic in the MMI and any logic in the peripheralunits and PCI bus interface that is not participating in thepower down.
20.4 POWER DOWN OF PERIPHERALS
The peripherals participate in global power down. Thiscan be a programmable option for selected peripherals.These selected peripherals have a programmable MMIOcontrol bit, the SLEEPLESS bit, that can be used to pre-vent it from participating in the global power down mode.By default every peripheral unit must participate in powerdown.
The following peripherals have the SLEEPLESS bit: vid-eo-in, video-out, audio-in, audio-out, SSI, JTAG.
The following peripherals do not have the SLEEPLESSbit and always participate in power down: VLD, boot/I2Cand ICP.
The following peripherals do not participate in globalpower down, although they must still power themselvesdown when they are inactive: VIC, PCI.
When a peripheral does not participate in global powerdown, it can still do regular main memory traffic. Everytime a peripheral unit asserts the highway request signal,the MMI will initiate a wake-up sequence. The CPU mustexecute software that initiates a new power down of thesystem. This software can be the wait-loop of the RTOS.
Programmer’s note: Since the system is waked up eachtime there is a transaction on the highway, it may be in-teresting to make a software loop that does the activationof the POWER_DOWN mode. Then the activation is con-ditional, and most of the time, done using a global vari-able usually set by a handler. It becomes then mandatoryto be sure that there are no interruptible jumps betweenthe time the value of the global variable is fetched andcompared by the DSPCU and the time the conditionalwrite to the MMIO is performed (it is the classical sema-phore or test and set issue). Thus it is recommended to
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TM1100 Preliminary Data Book Philips Semiconductors
use a separate function with the address of the variableas a parameter and this function needs to be compiledspecifically without interruptible jumps.
The wake-up from power down mode takes approxi-mately 20 SDRAM clock cycles. This amount of time isadded to the worst case latency for memory requestscompared to the situation when the system is not in pow-er down mode.
20.5 DETAILED SEQUENCE OF EVENTS
The sequence of events to power down TM1100 is as fol-lows:
• Issue a MMIO write to the POWER_DOWN register• The main memory interface waits till the completion
of the current main memory transfer, if there is onestill busy.
• The MMI brings SDRAM into the self refresh state,goes into a wait state and asserts the global signalglobal_power_down.
• All units that participate in the power down, respondto the global_power_down signal by disabling theirclocks.
• Only the PLL, interrupt controller, timers, wake-uplogic, the PCI bus interface and any peripherals, thathave their SLEEPLESS bit control bit set, continue tobe clocked. Also the SDRAM clock continues.
• An interrupt is detected by the interrupt controller or aunit that didn’t participate in the power downrequests a memory transfer.
• The MMI deasserts the global_power_down signal,activating all blocks on the chip.
• The MMI recovers SDRAM from self-refresh.• The MMI causes completion of the MMIO operation
that initiated the power down sequence.• When software takes an interruptible branch opera-
tion, the interrupt that caused the wake_up will beserviced (if the wake-up was initiated by an interrupt).
20.6 MMIO REGISTER POWER_DOWN
The register POWER_DOWN has an offset 0x100108 inthe MMIO aperture.
The register POWER_DOWN is without content. Writingto this register has the side-effect to power down thechip. Reading from this register returns an undefined val-ue and has no side-effect.
20-2 PRELIMINARY INFORMATION File: power.fm5, modified 7/23/99
PCI-XIO External I/O Bus Chapter 21
By David Wyland
21.1 SUMMARY FUNCTIONALITY
The TM1100 PCI-XIO Bus allows glueless connection toPCI peripherals, 8-bit microprocessor peripherals and 8-bit memory devices. All these device types can be inter-mixed in a single TM1100 system.
The PCI-XIO Bus provides the following features:
• All PCI 2.1 features (32-bit, 33 MHz)• Simple non-multiplexed 8-bit data, 24-bit address
XIO bus with control signals for 68K and x86 styledevices
• Glueless connection to ROM, EPROM, flashEEPROM, UARTs, SRAM, etc.
• Programmable internal or external bus clock source• 0-7 programmable wait states for XIO devices• Support for single byte read, single byte write, DMA
read or DMA write• The 16 MBytes of XIO device space is visible as 16
MWords (64 MBytes) in the DSPCPU memory map
21.1.1 Description
The XIO logic that implements the protocol for 8-bit de-vices appears as a on-chip PCI target device to the restof the TM1100. It only responds when it is addressed bythe TM1100 as initiator, and never responds to externalPCI masters. When it is addressed by the TM1100 as aninitiator, it responds to the TM1100 PCI BIU as a normalslave device, activating PCI_DEVSEL#.
The XIO logic serves as a bridge between the PCI busand XIO devices such as ROMs, flash EPROMs and I/Odevice chips. The TM1100 addresses XIO devices onthe PCI-XIO bus in the same way as registers or memoryin any other PCI slave device. The XIO logic supplies thePCI_TRDY# signals to the PCI bus and also supplies thechip-select, read, write and data-strobe signals to XIOdevices attached to the PCI-XIO Bus. A conceptual onlyblock diagram of the PCI-XIO Bus is shown inFigure 21-2. The real hardware uses the PCI_AD[0:30]signals and PCI_C/BE#[0:3] signals for both PCI andXIO devices, as shown in Figure 21-3.
The XIO logic is activated when the Enable bit in theXIO_CTL register is asserted and whenever the TM1100as initiator addresses the PCI-XIO Bus address range,as defined by a 6-bit Address field in the XIO Bus ControlRegister. This 6-bit field defines the 6 most significantbits of the XIO Bus address space. When the TM1100sends out an address as an initiator, the upper 6 bits of
the address are compared with this field. If they match,the PCI-XIO bus logic is activated. The PCI_INTB# out-put is asserted to indicate that the PCI-XIO Bus is active.It becomes active at PCI data phase time. When XIO isenabled, the PCI_INTB# signal becomes dedicated asXIO bus chip-select, and turns from an open-drain outputinto a normal logic output. PCI_INTB# serves as a globalchip select for all XIO Bus chips. When XIO is disabled,PCI_INTB# is available for PCI specific use or as a gen-eral purpose software I/O pin, with open-drain behavioras in TM1000.
The Address field bits in the XIO Bus Control registerserve as a base address register in PCI terms. The XIOBus Control register is not a PCI configuration register. Itdoes not need to be a PCI configuration register becausethe PCI-XIO Bus can only be addressed by the TM1100.It will not respond to requests by any other external PCIdevice.
When the XIO-PCI Bus controller logic is activated, itgenerates PCI_DEVSEL# as a response to the PCI bus.When PCI_IRDY# has been received from the BIU, it as-serts an external PCI_INTB# signal as the global chip se-lect. It also reconfigures the PCI address/data pins for 8-bit byte transfers. When the PCI-XIO Bus is active, thelower 24 bits of the external 32-bit PCI bus are used tooutput a 24-bit address for all transfers, read or write.The upper 8 bits of the external PCI bus are unchangedand transfer data normally. This is shown in Figure 21-3.
The 24-bit address on the XIO Bus pins is the word ad-dress for the PCI transfer, which is the lower 26 bits ofthe PCI transfer address with the two least significant bitsignored. One word is transferred to or from the PCI busfor each byte read or written on the XIO bus. In writes tothe XIO bus, a 32-bit word is transferred from the PCIBIU to the XIO Bus controller, but the lower 24 bits andthe PCI byte enables are ignored. In reads from the PCIbus, a 32-bit word is transferred from the XIO Bus con-troller to the PCI BIU with the data in the upper 8 bits andthe 24-bit address in the lower 24 bits. Note that the 24-bit address returned in a read is the lower 26 bits of thePCI transfer address with the two least significant bitstruncated. For example, a PCI transfer address of 44hexadecimal would return a value of 11 hexadecimal asthe lower 24 bits of the 32-bit data in a read. The 24-bitXIO Bus address is generated by an address counter inthe XIO Bus controller. This counter is loaded with thePCI word address at PCI frame time at the start of thePCI transfer and is incremented for each PCI word trans-ferred.
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TM1100 Preliminary Data Book Philips Semiconductors
The XIO Bus does not generate parity during XIO Buswrite transfers nor check parity during XIO Bus readtransfers. This allows the XIO Bus to interface to stan-dard 8-bit devices without having to add parity generateand check logic. While the XIO Bus is active, the XIO Buslogic inhibits parity checking and drives the PCI Parityand Parity Error pins so that they do not float.
Word transfer is used to transfer the bytes to and fromthe PCI bus for hardware simplicity. The primary intend-ed use of the PCI-XIO Bus is for slow devices ROMs,flash EPROMs and I/O. Because the PCI-XIO bus is somuch slower than the TM1100, there is time available forthe TM1100 to pack and unpack the words. In the caseof ROMs and flash EPROMs, the data is typically com-
pressed, requiring the TM1100 CPU to both unpack anddecompress the data.
The PCI-XIO Bus Controller logic reconfigures the byteenables as control signals for the attached XIO Bus chipsduring XIO Bus transfers. It also drives the PCI_TRDY#signal to the PCI Bus for each transfer. The PCI Bus byteenables are reconfigured to generate XIO Bus timing sig-nals: Read (IORD), Write (IOWR) and Data Strobe (DS).These signals allow glueless interface of ROM, flashEPROM, 68K and x86 devices to the XIO Bus. For a sin-gle device, the PCI_INTB# line is used as the global chipenable. If more than one device is to be added, an exter-nal decoder, such as a 74FCT138, can be used to de-code the upper bits of the 24-bit transfer address, with
Audio In
Audio Out
DSPCPU400 MIPS
2.5 GOPS
I$
D$
I2C Interface
ImageCo Processor
TM1100MMI
PCI and External I/O (PCI-XIO) Bus Interface
VLD Assist
Video Out
Digital
DMSDor RawVideo
SerialDigitalAudio
JTAG
XIO BusPCI - XIO Bus AD[31:0]
SDRAM: 32-bit data
SDRAMHighway
Synchronous
Video In
GluelessFlashEPROM I/F
XIOI/O Device
PCII/O Device
Clock
Camera
I2C Bus
CCIR 601DigitalVideo Out
V.34 Modem
ControlsPCI BusControls
Serial I/F
Figure 21-1. Partial TM1100 Chip Block Diagram
21-2 PRELIMINARY INFORMATION File: pci-xio.fm5, modified 7/26/99
Philips Semiconductors PCI-XIO External I/O Bus
the PCI_INTB# line used as a global chip enable to thedecoder.
The PCI-XIO Bus controller has a wait state generator toprovide timing for slow devices. The wait state generatorallows adding up to 7 wait states for slow chip accessand write times. The wait state generator logic generatesthe PCI_TRDY# signal to the PCI bus.
The XIO Bus controller contains a clock generator forstand-alone systems. The PCI-XIO Bus uses the PCIclock. This clock is normally supplied by a PCI Bus cen-tral resource outside the TM1100 chip. In stand-alone orlow-cost systems, the internal clock generator can beused. The internal clock generator divides the TM1100highway clock by a 5-bit number in a prescaler. This al-lows setting bus clocks from 4 MHz to 66 MHz in a 133MHz system. The internal clock generator programmingis described in Section 21.5, “XIO_CTL MMIO Register.”
21.2 BLOCK DIAGRAM
Figure 21-2 shows a conceptual only block diagram ofthe PCI-XIO Bus as a slave device on the PCI Bus. The
XIO Bus Controller generates an XIO Bus, which is an 8-bit bus with a 24-bit address. Devices attached to theXIO Bus appear as memory locations in the 16 megabyteaddress space of the XIO Bus.
Figure 21-3 shows an implementation block diagram ofthe PCI_XIO Bus. To conserve pins, the XIO Bus Con-troller uses the PCI I/O pins as XIO Bus pins during XIOBus data transfers. It reconfigures the 32 PCI address/data pins as 8 XIO Bus data pins and 24 XIO Bus ad-dress pins, and it reconfigures the byte enable pins asXIO Bus timing signals. By changing the functions of thepins during the transfer, 36 pins are saved which wouldotherwise be required to drive the XIO Bus devices. Byreconfiguring the PCI pins only during the data phase ofthe XIO Bus transfers, the PCI-XIO bus retains its PCIBus compatibility.
Figure 21-4 shows a more detailed block diagram of thePCI-XIO Bus controller.
TM
1100
SD
RA
M D
ata
Hig
hway
PCIBus
InterfaceUnit (BIU)
PCI Bus
XIO BusControllerPCI Device
PCIDevice
PCIDevice
PCIHost
ROMx86Device
TM1100
8-bit data + 24-bit AddrsXIO Bus
Figure 21-2. PCI-XIO Bus Device CONCEPTUAL ONLY Block Diagram
for address & data, these use the same pins/wires
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TM1100 Preliminary Data Book Philips Semiconductors
TM
1100
SD
RA
M D
ata
Hig
hway PCI
Bus InterfaceUnit (BIU)
PCI Bus
XIO BusControllerPCI Device
PCIDevice
PCIDevice
PCIHost
ROM x86Deviceetc.
TM1100
Mux
PCI_INTB#
PCI_INTB# = XIO Bus Active As Target
PCI_AD[23:0]
PCI_AD[31:24] PCI_AD[31:24]
PCI_AD[31:0] PCI_AD[31:0] PCI_AD[31:0]
XIO Bus
Figure 21-3. PCI-XIO Bus Device Implementation Block Diagram
TM
1100
SD
RA
M D
ata
Hig
hway
XIO Config Reg Clock
Bus Timing
PCIBus
Interface
PCI_AD[31:24]
PCI_C/BE0#: IORD#
PCI_CLK
PCI-XIO BusPCI-XIO Bus Controller
Unit (BIU)
=
Mux
Data Out [31:24]
Data In [31:0]
Data Out [23:0]
Address [23:0]
PCI_AD[23:00]
Address [31:24]
PCI_INTA#, INTC#, INTD#
PCI_C/BE1#: IOWR#C/BE
TRDY
XIO Controls+ Wait States
PCI_INTB# = Chip Enable
PCI Controls: Frame, etc.
PCI_TRDY#
PCI_DEVSEL#
OR
OR
DEVSEL
PCI_REQ#PCI_GNT#
Tie REQ to GNT for stand alone (no host) case
TM1100 Initiator
PCI_C/BE2#: DS#PCI_C/BE3#
Figure 21-4. PCI-XIO Bus Interface Controller Block Diagram
21-4 PRELIMINARY INFORMATION File: pci-xio.fm5, modified 7/26/99
Philips Semiconductors PCI-XIO External I/O Bus
21.3 DATA FORMATS
The data transfer formats for the PCI-XIO bus are shownin Figure 21-5. The 8-bit data field is the data transferred
to or from the PCI-XIO Bus. The read address is the 24-bit address on the PCI-XIO Bus address lines when theread transfer takes place.
21.4 INTERFACE
21.4.1 PCI-XIO Bus Interface Design
The PCI-XIO Bus can accommodate a variety of differentdevices and bus protocols. The following are examplesof devices interfaced to the PCI-XIO Bus
Data Read Address
UnusedData
Read: XIO Bus to PCI
Write: PCI to XIO Bus
31 24 23 0
31 24 23 0
Figure 21-5. PCI-XIO Bus Data Formats
Table 21-1. PCI-XIO Bus Signal Definitions
TM1100 PCI Signal Pins I/O PCI Function XIO Function
PCI_INTB# 1 O PCI-XIO Bus Enable = XIO Bus Active As Target Device
PCI_CLK 1 I/O 33 MHz PCI Clock: can optionally be generated by TM1100 on board osc
PCI_FRAME# 1 I/O PCI Address/Command Strobe + Transfer In Progress
PCI_DEVSEL# 1 I/O Device Select Valid Asserted by TM1100 = XIO Active
PCI_IRDY# 1 I/O Initiator Ready = Transfer In Progress
PCI_TRDY# 1 I/O Target Ready Asserted by TM1100 = XIO Transfer Timing
PCI_STOP# 1 I/O Target Requests Stop of Transaction
PCI_IDSEL# 1 I Chip Select for PCI Config Writes
PCI_REQ# 1 O TM1100 Requesting PCI Bus
PCI_GNT# 1 I TM1100 Is Granted PCI Bus
PCI_PERR# 1 I Parity Error to TM1100
PCI_SERR 1 O System Error from TM1100
PCI_INTA# 1 I/O General Purpose I/O
PCI_INTB# 1 I/O General Purpose I/O XIO Bus Active = Global Chip Select
PCI_INTC# 1 I/O General Purpose I/O
PCI_INTD# 1 I/O General Purpose I/O
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TM1100 Preliminary Data Book Philips Semiconductors
21.4.1.1 Flash EEPROM
Figure 21-6 shows an 8-bit flash EEPROM interfaced tothe PCI-XIO Bus. Examples of these devices are the Mi-cron MT28F200C1 and the AMD 29LV400.
21.4.1.2 68K Bus I/O Device
Figure 21-7 shows a 68K bus I/O device interfaced to thePCI-XIO Bus. Example devices are the Motorola
MC68HC681 DUART and the MC68HC901 Multi-Func-tion Peripheral.
21.4.1.3 x86/ISA Bus I/O Device
Figure 21-8 shows an x86 or ISA bus I/O device inter-faced to the PCI-XIO Bus. An example device is the Intel82091 Advanced Integrated Peripheral (AIP).
AddressPCI_AD[16:0]
Write EnablePCI_C/BE1#: IOWR#
Output EnablePCI_C/BE0#: IORD#
Chip SelectPCI_INTB#
Data PCI_AD[31:24]
128Kx8 EEPROM
Figure 21-6. 8-bit Flash EEPROM Interface
AddressPCI_AD[23:0]
R/W#PCI_C/BE1#: IOWR#
DS#PCI_C/BE2: DS#
Chip SelectPCI_INTB#
Data PCI_AD[31:24]
68K Bus Device
CLKPCI_CLK
Figure 21-7. 8-bit 68K Bus Device Interface
AddressPCI_AD[23:0]
I/O Read EnablePCI_C/BE0#: IORD#
I/O Write EnablePCI_C/BE1#: IOWR#
Chip SelectPCI_INTB#
Data PCI_AD[31:24]
x86 or ISA Bus Device
BALEPCI_CLK
Figure 21-8. 8-bit x86 / ISA Bus Device Interface
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Philips Semiconductors PCI-XIO External I/O Bus
21.4.1.4 Multiple Flash EEPROM
Figure 21-9 shows two 8-bit flash EEPROMs interfacedto the PCI-XIO Bus. A 74FCT138 logic chip decodes up-per bits PCI_AD[19-17] of the XIO bus address to gener-ate the chip selects for the two EEPROMs. These bitsdecode the address space into blocks of 128K bytes.The address range of each enable is shown on the en-
able lines. Six spare chip selects are available for attach-ing up to six more EEPROMs or to attach other devices.The 74FCT138 provides both decode of the address bitsand the AND function for the PCI_INTB# global chip en-able signal so that only one EEPROM chip enable signalis active at global chip enable time.
21.5 XIO_CTL MMIO REGISTER
The PCI-XIO Bus Controller has one programmer visibleMMIO register: XIO_CTL. Its format is shown inTable 21-2. To ensure compatibility with future devices,any undefined MMIO bits should be ignored when read,and written as zeroes.
21.5.1 PCI_CLK Bus Clock Frequency
PCI_CLK, the clock for the PCI and PCI-XIO bus can besupplied externally or internally. This is determined atboot time, by the ‘enable internal PCI_CLK generator’ bit,bit 6 of byte 9 in the boot EEPROM. Refer toSection 12.2. If a ‘0’ is present in this bit, PCI_CLK actscompatible with TM1000 and normal PCI operation, i.e.PCI_CLK is an input pin that takes the PCI clock from theexternal world. If a ‘1’ is present in this bit, an on-chipclock divider in the XIO logic becomes the source ofPCI_CLK, and the PCI_CLK pin is configured as an out-put. In the latter case, the PCI_CLK frequency can be
programmed to a divider of the TM1100 highway clockby setting the XIO_CTL register ‘Clock Frequency’ divid-er value.
A table of PCI-XIO Bus Clock frequencies versus Clockfield values is shown in Table 21-3. Note that thePCI_CLK operating frequency should be set to observe
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TM1100 Preliminary Data Book Philips Semiconductors
the frequency limits given in the AC/DC timing character-ization data for TM1100. Odd values of ‘Clock Frequen-cy’ are recommended, resulting in an even divider, whichgenerates a 50% duty cycle PCI_CLK.
21.5.2 Wait State Generator
The XIO Bus controller has an automatic wait state gen-erator to allow for read and write cycle times of deviceson the XIO bus.
21.6 PCI-XIO BUS TIMING
The timing for the PCI-XIO bus is shown below: Note thatthe ‘fat’ lines indicate active drive by TM1100. Thin linesindicate areas where the TM1100 is not actively driving(in these areas, pull-up resistors retain the signal high forcontrol signals, PCI_AD lines are left floating).Figure 21-10 shows the timing for a single byte readtransfer. Figure 21-11 shows the timing for a single byteread transfer with wait states. Figure 21-14 shows thetiming for a DMA burst read transfer of 2 bytes, andFigure 21-16 shows the timing for a DMA burst writetransfer of 2 bytes. The DMA burst transfers are shownat maximum rate, with zero wait states. DMA burst trans-fers with wait states insert wait states between the trans-fers. In the read case, the IORD# enable and DS# areextended by the wait states. In the write case, the IO-WR# enable and DS# are delayed by the wait states.
Table 21-3. PCI_CLK Frequencies for 133.0 MHz TM1100 Highway Clock
Clock Frequency(use odd values)
TM1100Clocks
PCI-XIO Clock Period, ns
Frequency, MHz
0 illegal illegal illegal
1 2 15 66.5
2 3 22.5 44.33
3 4 30 33.25
... ... ... ...
30 31 233 4.29
31 32 241 4.16
Table 21-4. Wait State Generator Codes
Code Wait States
0 0
1 1
2 2
... ...
7 7
PCI_CLK
PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_DEVSEL#
Frame TimeBus Turnaround
XIO Transfer
Figure 21-10. PCI-XIO Bus Timing: Single Byte Read, 0 wait states
& Address Setup
PCI_AD[23:0]: ADDR XIO AddrsPCI Address
PCI_AD[31:24]: DATA Read DataPCI Address
PCI_INTB#/CE#
PCI_C/BE2#/DS# PCI Command
PCI_C/BE1#/IOWR# PCI Command
PCI_C/BE0#/IORD# PCI Command
Read Sample Point
Bus Idle
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Philips Semiconductors PCI-XIO External I/O Bus
PCI_CLK
PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_DEVSEL#
Frame TimeBus Turnaround
Wait (k times)
Figure 21-11. PCI-XIO Bus Timing: Single Byte Read, 1 or more wait states
& Address Setup
PCI_AD[23:0]: ADDR XIO AddrsPCI Address
PCI_AD[31:24]: DATA Read DataPCI Address
PCI_INTB#/CE#
PCI_C/BE2#/DS# PCI Command
PCI_C/BE1#/IOWR# PCI Command
PCI_C/BE0#/IORD# PCI Command
Read Sample Point
XIO transfer
PCI_CLK
PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_DEVSEL#
Frame Time Write Cycle Data hold time
Figure 21-12. PCI-XIO Bus Timing: Single Byte Write, 0 wait states
PCI_AD[23:0]: ADDR XIO AddrsPCI Address
PCI_AD[31:24]: DATA PCI Address
PCI_INTB#/CE#
PCI_C/BE2#/DS# PCI Command
PCI_C/BE1#/IOWR# PCI Command
PCI_C/BE0#/IORD# PCI Command
Bus Idle
XIO Data
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PCI_CLK
PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_DEVSEL#
Frame Time
Figure 21-13. PCI-XIO Bus Timing: Single Byte Write, 1 or more wait states
Write cycle
PCI_AD[23:0]: ADDR XIO AddrsPCI Address
PCI_AD[31:24]: DATA PCI Address
PCI_INTB#/CE#
PCI_C/BE2#/DS# PCI Command
PCI_C/BE1#/IOWR# PCI Command
PCI_C/BE0#/IORD# PCI Command
Data Hold time
XIO Data
Wait (k) Bus Idle
PCI_CLK
PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_DEVSEL#
Frame TimeBus Turnaround
XIO Data 1
Figure 21-14. PCI-XIO Bus Timing: DMA Burst Read, 2 bytes, 0 wait states
& Address Setup
PCI_AD[23:0]: ADDR XIO Addrs 1PCI Address
PCI_AD[31:24]: DATA Read Data 2PCI Address
PCI_INTB#/CE#
PCI_C/BE2#/DS# PCI Command
PCI_C/BE1#/IOWR# PCI Command
PCI_C/BE0#/IORD# PCI Command
Read Sample Points
XIO Data 2 Bus Idle
XIO Addrs 2
Read Data 1
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Philips Semiconductors PCI-XIO External I/O Bus
PCI_CLK
PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_DEVSEL#
Figure 21-15. PCI-XIO Bus Timing: DMA Burst Read, 2 bytes, 1 or more wait states
PCI_AD[23:0]: ADDR XIO Addrs 1PCI Addr
PCI_AD[31:24]: DATA PCI Addr
PCI_INTB#/CE#
PCI_C/BE2#/DS# PCI Com
PCI_C/BE1#/IOWR# PCI Com
PCI_C/BE0#/IORD# PCI Com
Read Sample Points
Read Data 1
wait(k) data 1 wait(k) data 2
XIO Addrs 2
Read Data 2
Frame Turn
PCI_CLK
PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_DEVSEL#
Figure 21-16. PCI-XIO Bus Timing: DMA Burst Write, 2 bytes, 1 or more wait states
PCI_AD[23:0]: ADDR PCI Addr
PCI_AD[31:24]: DATA PCI Addr
PCI_INTB#/CE#
PCI_C/BE2#/DS# PCI Com
PCI_C/BE1#/IOWR# PCI Com
PCI_C/BE0#/IORD# PCI Com
wait(k) hold data2 wait(k)
XIO Addrs 1
Frame data1
XIO Addrs 2
hold idle
XIO Data1 XIO Data 2
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21.7 PCI-XIO BUS CONTROLLER OPERATION AND PROGRAMMING
The PCI-XIO Bus is a PCI target device. All valid PCItransfers with TM1100 as the initiator are allowed, includ-ing single word and DMA transfers. When data is readfrom the PCI-XIO Bus, it reads as a 32-bit word with the8 bits of data as the most significant byte and the 24-bitXIO Bus transfer address as the least significant bytes.When data is written to the PCI-XIO Bus, it is written asa word, but only the most significant byte of the data istransferred to the bus. The lower 24 bits are ignored asthey are replaced by the lower 24 bits of the transfer ad-dress before being placed on the bus.
Before the PCI-XIO Bus can be used, the PCI-XIO BusControl Register must be set up. This register must beloaded with the base address for the PCI-XIO bus andthe control fields for clock frequency, wait states pertransfer and PCI-XIO Bus enable.
To read a single byte to a PCI-XIO Bus device, first de-fine the 24-bit address for the device. This might be theaddress in an EPROM for the desired byte. Multiply thisdevice address by four to convert it to a word addressand add the XIO Bus base address. The combined ad-dress is the PCI transfer address. Use this address asthe transfer address for a single word DSPCPU load.Table 21-5 shows examples of this address conversion.At the completion of the load, the data received will con-sist of 8 bits of data and the 24-bit device address. Towrite a byte, use the same transfer address and write aword to this address with the desired data as the mostsignificant byte of the word written.
To transfer data between the XIO-PCI bus and theSDRAM using the PCI DMA capability, set the
PCI_SRC_ADR or the PCI_DEST_ADR register to thePCI-XIO Bus transfer address, depending on the direc-tion of the transfer. The PCI-XIO Bus transfer address isfour times the starting address as seen on the PCI-XIOBus address pins plus the PCI-XIO Bus controller baseaddress. This is the starting address for the PCI-XIO Bustransfer. Set the other address, destination or source, tothe desired starting address in SDRAM. Set thePCI_DMA_CTL register for the desired direction and setthe transfer count to the four times number of PCI-XIOBus bytes to be transferred. The transfer count is fourtimes the PCI-XIO Bus bytes to be transferred becausethe PCI-XIO Bus transfers one word to or from the PCIbus for each byte transferred to or from devices on thePCI-XIO Bus.
Word transfer is used to transfer the bytes to and fromthe PCI bus for hardware simplicity. Additional hardwarecould be added to pack and unpack bytes, but this is anunnecessary complication given the speed of the PCI-XIO Bus relative to the speed of the TM1100 bus andCPU. The primary intended use of the PCI-XIO Bus is forROMs, flash EPROMs and I/O devices. Because thePCI-XIO bus is so much slower than the TM1100, there
PCI_CLK
PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_DEVSEL#
Figure 21-17. PCI-XIO Bus Timing: DMA Burst Write, 2 bytes, 0 wait states
PCI_AD[23:0]: ADDR PCI Addr
PCI_AD[31:24]: DATA PCI Addr
PCI_INTB#/CE#
PCI_C/BE2#/DS# PCI Com
PCI_C/BE1#/IOWR# PCI Com
PCI_C/BE0#/IORD# PCI Com
hold data 2 hold bus idle
XIO Addrs 1
Frame data1
XIO Addrs 2
XIO Data 1 XIO Data 2
Table 21-5. PCI to XIO Bus Address Conversion Examples
XIO Bus Addressin Hex
PCI Word Addressin Hex
XIO-PCI Base
Addressin Hex
PCI Transfer Addressin Hex
11 44 5800 0000 5800 0044
0123 048C 5800 0000 5800 048C
11 0012 44 0048 5800 0000 5844 0048
21-12 PRELIMINARY INFORMATION File: pci-xio.fm5, modified 7/26/99
Philips Semiconductors PCI-XIO External I/O Bus
is time available for the TM1100 to pack and unpack thewords. At three PCI-XIO bus wait states, at least 120nanoseconds are required for each byte transferred. Thiscorresponds to 12 CPU instructions at 100 MHz. The
CPU may need to process each byte of data anyway. Inthe case of ROMs and flash EPROMs, the data is typi-cally compressed, requiring the TM1100 CPU to both un-pack and decompress the data.
File: pci-xio.fm5, modified 7/26/99 PRELIMINARY INFORMATION 21-13
TM1100 Preliminary Data Book Philips Semiconductors
21-14 PRELIMINARY INFORMATION File: pci-xio.fm5, modified 7/26/99
DSPCPU Operations for TM1100 Appendix A
by Gert Slavenburg, Marcel Janssens
A.1 ALPHABETIC OPERATION LIST
The following table lists the complete operation set of TM1100’s DSPCPU. Note that this is not an instruction list; aDSPCPU instruction contains from one to five of these operations.A alloc ............................3
H h_dspiabs .................66h_dspidualabs ..........67h_iabs.......................68h_st16d.....................69h_st32d.....................70h_st8d.......................71hicycles.....................72
L ld32.........................128ld32d.......................129ld32r .......................130ld32x.......................131lsl ............................132lsli ...........................133lsr............................134lsri...........................135
M mergedual16lsb......136mergelsb.................137mergemsb ..............138
N nop .........................139P pack16lsb ...............140
R rdstatus...................152rdtag .......................153readdpc ..................154readpcsw ................155readspc...................156rol ...........................157roli...........................158
S sex16......................159sex8........................160st16.........................161st16d.......................162st32.........................163st32d.......................164st8...........................165st8d.........................166
ATTRIBUTESFunction unit dmemspecOperation code 213Number of operands 1Modifier -Modifier range -Latency - Issue slots 5
DESCRIPTIONThe alloc operation is a pseudo operation transformed by the scheduler into an allocd(0) with the same arguments.
(Note: pseudo operations cannot be used in assembly files.)The alloc operation allocate a cache block with the address computed from [(rsrc1 + 0) & cache_block_mask] and sets
the status of this cache block as valid. No data is fetched from main memory for this operation. The allocated cacheblock data is undefined after this operation. It is the responsibility of the programmer to update the allocated cacheblock by store operations.
Refer to the ‘cache architecture’ section for details on the cache block size.The alloc operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the execution
of the alloc operation. If the LSB of rguard is 1, alloc operation is executed; otherwise, it is not executed.
EXAMPLES
Initial Values Operation Result
r10 = 0xabcd, cache_block_size = 0x40
alloc r10 Allocates a cache block for the address space from 0xabc0 to 0x0xabff without fetching the data from main memory; The data in this address space is undefined.
r10 = 0xabcd, r11 = 0,cache_block_size = 0x40
IF r11 alloc r10 since guard is false, alloc operation is not executed
r10 = 0xac0f, r11 = 1,cache_block_size = 0x40
IF r11 alloc r10 Allocates a cache block for the address space from 0xac00 to 0xac3f without fetching the data from main memory; the data in this address space is undefined.
SEE ALSOallocd allocr allocx
alloc
TM1100 Preliminary Data Book Philips Semiconductors
A-4 PRELIMINARY INFORMATION File: ops.fm5, modified 7/23/99
ATTRIBUTESFunction unit dmemspecOperation code 213Number of operands 1Modifier 7 bitsModifier range -255..252 by 4Latency - Issue slots 5
DESCRIPTIONThe allocd operation allocate a cache block with the address computed from [(rsrc1 + d) & cache_block_mask] and
sets the status of this cache block as valid. No data is fetched from main memory for this operation. The allocatedcache block data is undefined after this operation. It is the responsibility of the programmer to update the allocatedcache block by store operations.
Refer to the ‘cache architecture’ section for details on the cache block size.The allocd operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
execution of the allocd operation. If the LSB of rguard is 1, allocd operation is executed; otherwise, it is not executed.
EXAMPLES
Initial Values Operation Result
r10 = 0xabcd, cache_block_size = 0x40
allocd(0x32) r10 Allocates a cache block for the address space from 0xabc0 to 0x0xabff without fetching the data from main memory; The data in this address space is undefined.
r10 = 0xabcd, r11 = 0,cache_block_size = 0x40
IF r11 allocd(0x32) r10 since guard is false, allocd operation is not executed
r10 = 0xabff, r11 = 1,cache_block_size = 0x40
IF r11 allocd(0x4) r10 Allocates a cache block for the address space from 0xac00 to 0xac3f without fetching the data from main memory; the data in this address space is undefined.
SEE ALSOallocr allocx
Philips Semiconductors DSPCPU Operations for TM1100
File: ops.fm5, modified 7/23/99 PRELIMINARY INFORMATION A-5
ATTRIBUTESFunction unit dmemspecOperation code 214Number of operands 2Modifier NoModifier range -Latency -Issue slots 5
DESCRIPTIONThe allocr operation allocate a cache block with the address computed from [(rsrc1 + rscr2) & cache_block_mask] and
sets the status of this cache block as valid. No data is fetched from main memory for this operation. The allocatedcache block data is undefined after this operation. It is the responsibility of the programmer to update the allocatedcache block by store operations.
Refer to the ‘cache architecture’ section for details on the cache block size.The allocr operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
execution of the allocr operation. If the LSB of rguard is 1, allocr operation is executed; otherwise, it is not executed.
EXAMPLES
Initial Values Operation Result
r10 = 0xabcd, r12 = 0x32cache_block_size = 0x40
allocr r10 r12 Allocates a cache block for the address space from 0xabc0 to 0xabff without fetching the data from main memory; The data in this address space is undefined.
IF r11 allocr r10 r12 Allocates a cache block for the address space from 0xac00 to 0xac3f without fetching the data from main memory; the data in this address space is undefined.
SEE ALSOallocd allocx
allocr
TM1100 Preliminary Data Book Philips Semiconductors
A-6 PRELIMINARY INFORMATION File: ops.fm5, modified 7/23/99
ATTRIBUTESFunction unit dmemspecOperation code 215Number of operands 2Modifier NoModifier range -Latency -Issue slots 5
DESCRIPTIONThe allocx operation allocate a cache block with the address computed from [(rsrc1 + 4 x rscr2) & cache_block_mask]
and sets the status of this cache block as valid. No data is fetched from main memory for this operation. The allocatedcache block data is undefined after this operation. It is the responsibility of the programmer to update the allocatedcache block by store operations.
Refer to the ‘cache architecture’ section for details on the cache block size.The allocx operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
execution of the allocx operation. If the LSB of rguard is 1, allocx operation is executed; otherwise, it is not executed.
EXAMPLES
Initial Values Operation Result
r10 = 0xabcd, r12 = 0xccache_block_size = 0x40
allocx r10 r12 Allocates a cache block for the address space from 0xabc0 to 0x0xabff without fetching the data from main memory; The data in this address space is undefined.
IF r11 allocx r10 r12 Allocates a cache block for the address space from 0xac00 to 0xac3f without fetching the data from main memory; the data in this address space is undefined.
SEE ALSOallocd allocr
Philips Semiconductors DSPCPU Operations for TM1100
File: ops.fm5, modified 7/23/99 PRELIMINARY INFORMATION A-7
Arithmetic shift left
SYNTAX[ IF r guard ] asl r src1 r src2 → r dest
FUNCTIONif rguard then
n ← rsrc2<4:0>rdest<31:n> ← rsrc1<31–n:0>rdest<n–1:0> ← 0if rsrc2<31:5> != 0
rdest <- 0
ATTRIBUTESFunction unit shifterOperation code 19Number of operands 2Modifier NoModifier range —Latency 1Issue slots 1, 2
DESCRIPTIONAs shown below, the asl operation takes two arguments, rsrc1 and rsrc2. Rsrc2 specify an unsigned shift amount,
and rdest is set to rsrc1 arithmetically shifted left by this amount. If the rsrc2<31:5> value is not zero, then take this asa shift by 32 or more bits. Zeros are shifted into the LSBs of rdest while the MSBs shifted out of rsrc1 are lost.
The asl operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is unchanged.
EXAMPLES
Initial Values Operation Result
r60 = 0x20, r30 = 3 asl r60 r30 → r90 r90 ← 0x100
r10 = 0, r60 = 0x20, r30 = 3 IF r10 asl r60 r30 → r100 no change, since guard is false
r20 = 1, r60 = 0x20, r30 = 3 IF r20 asl r60 r30 → r110 r110 ← 0x100
TM1100 Preliminary Data Book Philips Semiconductors
A-8 PRELIMINARY INFORMATION File: ops.fm5, modified 7/23/99
asli Arithmetic shift left immediate
SYNTAX[ IF r guard ] asli( n) r src1 → r dest
FUNCTIONif rguard then
rdest<31:n> ← rsrc1<31–n:0>rdest<n–1:0> ← 0
ATTRIBUTESFunction unit shifterOperation code 11Number of operands 1Modifier 7 bitsModifier range 0..31Latency 1Issue slots 1, 2
DESCRIPTIONAs shown below, the asli operation takes a single argument in rsrc1 and an immediate modifier n and produces a
result in rdest equal to rsrc1 arithmetically shifted left by n bits. The value of n must be between 0 and 31, inclusive.Zeros are shifted into the LSBs of rdest while the MSBs shifted out of rsrc1 are lost.
The asli operations optionally take a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is unchanged.
EXAMPLES
Initial Values Operation Result
r60 = 0x20 asli(3) r60 → r90 r90 ← 0x100
r10 = 0, r60 = 0x20 IF r10 asli(3) r60 → r100 no change, since guard is false
Philips Semiconductors DSPCPU Operations for TM1100
File: ops.fm5, modified 7/23/99 PRELIMINARY INFORMATION A-9
Arithmetic shift right
SYNTAX[ IF r guard ] asr r src1 r src2 → r dest
FUNCTIONif rguard then
n ← rsrc2<4:0>rdest<31:31–n> ← rsrc1<31>rdest<30–n:0> ← rsrc1<30:n>if rsrc2<31:5> != 0
rdest <- rsrc1<31>
ATTRIBUTESFunction unit shifterOperation code 18Number of operands 2Modifier NoModifier range —Latency 1Issue slots 1, 2
DESCRIPTIONAs shown below, the asr operation takes two arguments, rsrc1 and rsrc2. Rsrc2 specifies an unsigned shift
amount, and rsrc1 is arithmetically shifted right by this amount. If the rsrc2<31:5> value is not zero, then take this as ashift by 32 or more bits. The MSB (sign bit) of rsrc1 is replicated as needed to fill vacated bits from the left.
The asr operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is unchanged.
ATTRIBUTESFunction unit shifterOperation code 10Number of operands 1Modifier 7 bitsModifier range 0..31Latency 1Issue slots 1, 2
DESCRIPTIONAs shown below, the asri operation takes a single argument in rsrc1 and an immediate modifier n and produces a
result in rdest that is equal to rsrc1 arithmetically shifted right by n bits. The value of n must be between 0 and 31,inclusive. The MSB (sign bit) of rsrc1 is replicated as needed to fill vacated bits from the left.
The asri operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is unchanged.
Philips Semiconductors DSPCPU Operations for TM1100
File: ops.fm5, modified 7/23/99 PRELIMINARY INFORMATION A-11
Bitwise logical AND
SYNTAX[ IF r guard ] bitand r src1 r src2 → r dest
FUNCTIONif rguard then
rdest ← rsrc1 & rsrc2
ATTRIBUTESFunction unit aluOperation code 16Number of operands 2Modifier NoModifier range —Latency 1Issue slots 1, 2, 3, 4, 5
DESCRIPTIONThe bitand operation computes the bitwise, logical AND of the first and second arguments, rsrc1 and rsrc2. The
result is stored in the destination register, rdest.The bitand operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
TM1100 Preliminary Data Book Philips Semiconductors
A-12 PRELIMINARY INFORMATION File: ops.fm5, modified 7/23/99
bitandinv Bitwise logical AND NOT
SYNTAX[ IF r guard ] bitandinv r src1 r src2 → r dest
FUNCTIONif rguard then
rdest ← rsrc1 & ~rsrc2
ATTRIBUTESFunction unit aluOperation code 49Number of operands 2Modifier NoModifier range —Latency 1Issue slots 1, 2, 3, 4, 5
DESCRIPTIONThe bitandinv operation computes the bitwise, logical AND of the first argument, rsrc1, with the 1’s complement
of the second argument, rsrc2. The result is stored in the destination register, rdest.The bitandinv operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
Philips Semiconductors DSPCPU Operations for TM1100
File: ops.fm5, modified 7/23/99 PRELIMINARY INFORMATION A-13
Bitwise logical NOT
SYNTAX[ IF r guard ] bitinv r src1 → r dest
FUNCTIONif rguard then
rdest ← ~rsrc1
ATTRIBUTESFunction unit aluOperation code 50Number of operands 1Modifier NoModifier range —Latency 1Issue slots 1, 2, 3, 4, 5
DESCRIPTIONThe bitinv operation computes the bitwise, logical NOT of the argument rsrc1 and writes the result into rdest.The bitinv operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
TM1100 Preliminary Data Book Philips Semiconductors
A-14 PRELIMINARY INFORMATION File: ops.fm5, modified 7/23/99
bitor Bitwise logical OR
SYNTAX[ IF r guard ] bitor r src1 r src2 → r dest
FUNCTIONif rguard then
rdest ← rsrc1 | rsrc2
ATTRIBUTESFunction unit aluOperation code 17Number of operands 2Modifier NoModifier range —Latency 1Issue slots 1, 2, 3, 4, 5
DESCRIPTIONThe bitor operation computes the bitwise, logical OR of the first and second arguments, rsrc1 and rsrc2. The
result is stored in the destination register, rdest.The bitor operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
Philips Semiconductors DSPCPU Operations for TM1100
File: ops.fm5, modified 7/23/99 PRELIMINARY INFORMATION A-15
Bitwise logical exclusive-OR
SYNTAX[ IF r guard ] bitxor r src1 r src2 → r dest
FUNCTIONif rguard then
rdest ← rsrc1 ⊕ rsrc2
ATTRIBUTESFunction unit aluOperation code 48Number of operands 2Modifier NoModifier range —Latency 1Issue slots 1, 2, 3, 4, 5
DESCRIPTIONThe bitxor operation computes the bitwise, logical exclusive-OR of the first and second arguments, rsrc1 and
rsrc2. The result is stored in the destination register, rdest.The bitxor operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
TM1100 Preliminary Data Book Philips Semiconductors
A-16 PRELIMINARY INFORMATION File: ops.fm5, modified 7/23/99
borrow Compute borrow bit from unsigned subtractpseudo-op for ugtr
SYNTAX[ IF r guard ] borrow r src1 r src2 → r dest
FUNCTIONif rguard then
if rsrc1 < rsrc2 thenrdest ← 1
elserdest ← 0
ATTRIBUTESFunction unit aluOperation code 33Number of operands 2Modifier NoModifier range —Latency 1Issue slots 1, 2, 3, 4, 5
DESCRIPTIONThe borrow operation is a pseudo operation transformed by the scheduler into an ugtr with reversed arguments.
(Note: pseudo operations cannot be used in assembly source files.)The borrow operation computes the unsigned difference of the first and second arguments, rsrc1–rsrc2. If the
difference generates a borrow (if rsrc2 > rsrc1), 1 is stored in the destination register, rdest; otherwise, rdest is set to 0.The borrow operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
Philips Semiconductors DSPCPU Operations for TM1100
File: ops.fm5, modified 7/23/99 PRELIMINARY INFORMATION A-17
Compute carry bit from unsigned add
SYNTAX[ IF r guard ] carry r src1 r src2 → r dest
FUNCTIONif rguard then
if (rsrc1+rsrc2) < 232 thenrdest ← 0
elserdest ← 1
ATTRIBUTESFunction unit aluOperation code 45Number of operands 2Modifier NoModifier range —Latency 1Issue slots 1, 2, 3, 4, 5
DESCRIPTIONThe carry operation computes the unsigned sum of the first and second arguments, rsrc1+rsrc2. If the sum
generates a carry (if the sum is greater than 232-1), 1 is stored in the destination register, rdest; otherwise, rdest is setto 0.
The carry operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
TM1100 Preliminary Data Book Philips Semiconductors
A-18 PRELIMINARY INFORMATION File: ops.fm5, modified 7/23/99
curcycles Read current clock cycle counter, least-significant word
SYNTAX[ IF r guard ] curcycles → r dest
FUNCTIONif rguard then
rdest ← CCCOUNT<31:0>
ATTRIBUTESFunction unit fcompOperation code 162Number of operands 0Modifier NoModifier range —Latency 1Issue slots 3
DESCRIPTIONRefer to Section 3.1.5, “CCCOUNT—Clock Cycle Counter” for a description of the CCCOUNT operation. The
curcycles operation copies the current low 32 bits of the master Clock Cycle Counter (CCCOUNT) to thedestination register, rdest.. The master CCCOUNT increments on all cycles (processor-stall and non-stall) ifPCSW.CS = 1; otherwise, the counter increments only on non-stall cycles.
The curcycles operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
Philips Semiconductors DSPCPU Operations for TM1100
File: ops.fm5, modified 7/23/99 PRELIMINARY INFORMATION A-19
Read clock cycle counter, least-significant word
SYNTAX[ IF r guard ] cycles → r dest
FUNCTIONif rguard then
rdest ← CCCOUNT<31:0>
ATTRIBUTESFunction unit fcompOperation code 154Number of operands 0Modifier NoModifier range —Latency 1Issue slots 3
DESCRIPTIONRefer to Section 3.1.5, “CCCOUNT—Clock Cycle Counter” for a description of the CCCOUNT operation. The
cycles operation copies the low 32 bits of the slave register of Clock Cycle Counter (CCCOUNT) to the destinationregister, rdest. The contents of the master counter are transferred to the slave CCCOUNT register only on asuccessful interruptible jump and on processor reset. Thus, if cycles and hicycles are executed withoutintervening interruptible jumps, the operation pair is guaranteed to be a coherent sample of the master clock-cyclecounter. The master counter increments on all cycles (processor-stall and non-stall) if PCSW.CS = 1; otherwise, thecounter increments only on non-stall cycles.
The cycles operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
ATTRIBUTESFunction unit dmemspecOperation code 205Number of operands 1Modifier 7 bitsModifier range –256..252 by 4Latency 3Issue slots 5
DESCRIPTIONThe dcb operation causes a block in the data cache to be copied back to main memory if the block is marked dirty
and valid, and the block’s dirty bit is reset. The target block of dcb is the block in the data cache that contains the byteaddressed by rsrc1 + d. The d value is an opcode modifier, must be in the range –256 to 252 inclusive, and must be amultiple of 4.
A valid copy of the target block remains in the cache. Stall cycles are taken as necessary to complete the copy-backoperation. If the target block is not dirty or if the block is not in the cache, dcb has no effect and no stall cycles aretaken.
dcb has no effect on blocks that are in the non-cacheable SDRAM aperture. dcb does not change the replacementstatus of data-cache blocks.
dcb ensures coherency between caches and main memory by discarding all pending prefetch operations and bycausing all non-empty copyback buffers to be emptied to main memory.
The dcb operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls if theoperation is carried out or not.If the LSB of rguard is 1, the operation is carried out; otherwise,it is not carried out.
EXAMPLES
Initial Values Operation Result
dcb(0) r30r10 = 0 IF r10 dcb(4) r40 no change and no stall cycles, since
guard is falser20 = 1 IF r20 dcb(8) r50
SEE ALSOdinvalid
dcb
Philips Semiconductors DSPCPU Operations for TM1100
File: ops.fm5, modified 7/23/99 PRELIMINARY INFORMATION A-21
ATTRIBUTESFunction unit dmemspecOperation code 206Number of operands 1Modifier 7 bitsModifier range –256..252 by 4Latency 3Issue slots 5
DESCRIPTIONThe dinvalid operation resets the valid and dirty bit of a block in the data cache. Regardless of the block’s dirty
bit, the block is not written back to main memory. The target block of dinvalid is the block in the data cache thatcontains the byte addressed by rsrc1 + d. The d value is an opcode modifier, must be in the range –256 to 252inclusive, and must be a multiple of 4.
Stall cycles are taken as necessary to complete the invalidate operation. If the target block is not in the cache,dinvalid has no effect and no stall cycles are taken.
dinvalid has no effect on blocks that are in the non-cacheable SDRAM aperture. dinvalid does clear thevalid bits of locked blocks. dinvalid does not change the replacement status of data-cache blocks.
dinvalid ensures coherency between caches and main memory by discarding all pending prefetch operationsand by causing all non-empty copyback buffers to be emptied to main memory.
The dinvalid operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls if theoperation is carried out or not. If the LSB of rguard is 1, the operation is carried out; otherwise, it is not carried out.
EXAMPLES
Initial Values Operation Result
dinvalid(0) r30r10 = 0 IF r10 dinvalid(4) r40 no change and no stall cycles, since
guard is falser20 = 1 IF r20 dinvalid(8) r50
SEE ALSOdcb
dinvalid
TM1100 Preliminary Data Book Philips Semiconductors
A-22 PRELIMINARY INFORMATION File: ops.fm5, modified 7/23/99
Clipped signed absolute valuepseudo-op for h_dspiabs
SYNTAX[ IF r guard ] dspiabs r src1 → r dest
FUNCTIONif rguard then
if rsrc1 >= 0 thenrdest ← rsrc1
else if rsrc1 = 0x80000000 thenrdest ← 0x7fffffff
elserdest ← –rsrc1
ATTRIBUTESFunction unit dspaluOperation code 65Number of operands 1Modifier NoModifier range —Latency 2Issue slots 1, 3
DESCRIPTIONThe dspiabs operation is a pseudo operation transformed by the scheduler into an h_dspiabs with a constant
first argument zero and second argument equal to the dspiabs argument. (Note: pseudo operations cannot be usedin assembly source files.)
The dspiabs operation computes the absolute value of rsrc1, clips the result into the range [231–1..0] (or[0x7fffffff..0]), and stores the clipped value into rdest. All values are signed integers.
The dspiabs operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
SEE ALSOh_dspiabs h_dspidualabs dspiadd dspimul dspisub dspuadd dspumul dspusub
dspiabs
Philips Semiconductors DSPCPU Operations for TM1100
File: ops.fm5, modified 7/23/99 PRELIMINARY INFORMATION A-23
Clipped signed add
SYNTAX[ IF r guard ] dspiadd r src1 r src2 → r dest
FUNCTIONif rguard then
temp ← sign_ext32to64(rsrc1) + sign_ext32to64(rsrc2)if temp < 0xffffffff80000000 then
rdest ← 0x80000000else if temp > 0x000000007fffffff then
rdest ← 0x7fffffffelse
rdest ← temp
ATTRIBUTESFunction unit dspaluOperation code 66Number of operands 2Modifier NoModifier range —Latency 2Issue slots 1, 3
DESCRIPTIONAs shown below, the dspiadd operation computes the sum rsrc1+rsrc2, clips the result into the 32-bit signed
range [231–1..–231] (or [0x7fffffff..0x80000000]), and stores the clipped value into rdest. All values are signed integers.
The dspiadd operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
SEE ALSOdspiabs dspimul dspisub dspuadd dspumul dspusub
dspiadd
TM1100 Preliminary Data Book Philips Semiconductors
A-24 PRELIMINARY INFORMATION File: ops.fm5, modified 7/23/99
Dual clipped absolute value of signed 16-bithalfwords
pseudo-op for h_dspidualabs
SYNTAX[ IF r guard ] dspidualabs r src1 → r dest
FUNCTIONif rguard then
temp1 ← sign_ext16to32(rsrc1<15:0>)temp2 ← sign_ext16to32(rsrc1<31:16>)if temp1 = 0xffff8000 then temp1 ← 0x7fffif temp2 = 0xffff8000 then temp2 ← 0x7fffif temp1 < 0 then temp1 ← –temp1if temp2 < 0 then temp2 ← –temp2rdest<31:16> ← temp2<15:0>rdest<15:0> ← temp1<15:0>
ATTRIBUTESFunction unit dspaluOperation code 72Number of operands 1Modifier NoModifier range —Latency 2Issue slots 1, 3
DESCRIPTIONThe dspidualabs operation is a pseudo operation transformed by the scheduler into an h_dspidualabs with
a constant zero as first argument and the dspidualabs argument as second argument. (Note: pseudo operationscannot be used in assembly source files.)
The dspidualabs operation performs two 16-bit clipped, signed absolute value computations separately on thehigh and low 16-bit halfwords of rsrc1. Both absolute values are clipped into the range [0x0..0x7fff] and written into thecorresponding halfwords of rdest. All values are signed 16-bit integers.
The dspidualabs operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controlsthe modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
ATTRIBUTESFunction unit dspaluOperation code 70Number of operands 2Modifier NoModifier range —Latency 2Issue slots 1, 3
DESCRIPTIONAs shown below, the dspidualadd operation computes two 16-bit clipped, signed sums separately on the two
pairs of high and low 16-bit halfwords of rsrc1 and rsrc2. Both sums are clipped into the range [215–1..–215] (or[0x7fff..0x8000]) and written into the corresponding halfwords of rdest. All values are signed 16-bit integers.
The dspidualadd operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controlsthe modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
ATTRIBUTESFunction unit dspmulOperation code 95Number of operands 2Modifier NoModifier range —Latency 3Issue slots 2, 3
DESCRIPTIONAs shown below, the dspidualmul operation computes two 16-bit clipped, signed products separately on the two
pairs of high and low 16-bit halfwords of rsrc1 and rsrc2. Both products are clipped into the range [215–1..–215] (or[0x7fff..0x8000]) and written into the corresponding halfwords of rdest. All values are signed 16-bit integers.
The dspidualmul operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controlsthe modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
ATTRIBUTESFunction unit dspaluOperation code 71Number of operands 2Modifier NoModifier range —Latency 2Issue slots 1, 3
DESCRIPTIONAs shown below, the dspidualsub operation computes two 16-bit clipped, signed differences separately on the
two pairs of high and low 16-bit halfwords of rsrc1 and rsrc2. Both differences are clipped into the range [215–1..–215](or [0x7fff..0x8000]) and written into the corresponding halfwords of rdest. All values are signed 16-bit integers.
The dspidualsub operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controlsthe modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
TM1100 Preliminary Data Book Philips Semiconductors
A-28 PRELIMINARY INFORMATION File: ops.fm5, modified 7/23/99
Clipped signed multiply
SYNTAX[ IF r guard ] dspimul r src1 r src2 → r dest
FUNCTIONif rguard then
temp ← sign_ext32to64(rsrc1) × sign_ext32to64(rsrc2)if temp < 0xffffffff80000000 then
rdest ← 0x80000000else if temp > 0x000000007fffffff then
rdest ← 0x7fffffffelse
rdest ← temp<31:0>
ATTRIBUTESFunction unit ifmulOperation code 141Number of operands 2Modifier NoModifier range —Latency 3Issue slots 2, 3
DESCRIPTIONAs shown below, the dspimul operation computes the product rsrc1×rsrc2, clips the result into the 32-bit range
[231–1..–231] (or [0x7fffffff..0x80000000]), and stores the clipped value into rdest. All values are signed integers.
The dspimul operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
SEE ALSOdspiabs dspiadd dspisub dspuadd dspumul dspusub
dspimul
Philips Semiconductors DSPCPU Operations for TM1100
File: ops.fm5, modified 7/23/99 PRELIMINARY INFORMATION A-29
Clipped signed subtract
SYNTAX[ IF r guard ] dspisub r src1 r src2 → r dest
FUNCTIONif rguard then
temp ← sign_ext32to64(rsrc1) – sign_ext32to64(rsrc2)if temp < 0xfffffffff80000000 then
rdest ← 0x80000000else if temp > 0x000000007fffffff then
rdest ← 0x7fffffffelse
rdest ← temp<31:0>
ATTRIBUTESFunction unit dspaluOperation code 68Number of operands 2Modifier NoModifier range —Latency 2Issue slots 1, 3
DESCRIPTIONAs shown below, the dspisub operation computes the difference rsrc1–rsrc2, clips the result into the 32-bit range
[231–1..–231] (or [0x7fffffff..0x80000000]), and stores the clipped value into rdest. All values are signed integers.
The dspisub operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
SEE ALSOdspiabs dspiadd dspimul dspuadd dspumul dspusub
dspisub
TM1100 Preliminary Data Book Philips Semiconductors
A-30 PRELIMINARY INFORMATION File: ops.fm5, modified 7/23/99
Clipped unsigned add
SYNTAX[ IF r guard ] dspuadd r src1 r src2 → r dest
FUNCTIONif rguard then
temp ← zero_ext32to64(rsrc1) + zero_ext32to64(rsrc2)if (unsigned)temp > 0x00000000ffffffff then
rdest ← 0xffffffffelse
rdest ← temp<31:0>
ATTRIBUTESFunction unit dspaluOperation code 67Number of operands 2Modifier NoModifier range —Latency 2Issue slots 1, 3
DESCRIPTIONAs shown below, the dspuadd operation computes unsigned sum rsrc1+rsrc2, clips the result into the unsigned
range [232–1..0] (or [0xffffffff..0]), and stores the clipped value into rdest.
The dspuadd operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
SEE ALSOdspiabs dspiadd dspimul dspisub dspumul dspusub
dspuadd
Philips Semiconductors DSPCPU Operations for TM1100
File: ops.fm5, modified 7/23/99 PRELIMINARY INFORMATION A-31
Clipped unsigned multiply
SYNTAX[ IF r guard ] dspumul r src1 r src2 → r dest
OPERATIONif rguard then
temp ← zero_ext32to64(rsrc1) × zero_ext32to64(rsrc2)if (unsigned)temp > 0x00000000ffffffff then
rdest ← 0xffffffffelse
rdest ← temp<31:0>
ATTRIBUTESFunction unit ifmulOperation code 142Number of operands 2Modifier NoModifier range —Latency 3Issue slots 2, 3
DESCRIPTIONAs shown below, the dspumul operation computes unsigned product rsrc1×rsrc2, clips the result into the unsigned
range [232–1..0] (or [0xffffffff..0]), and stores the clipped value into rdest.
The dspumul operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
SEE ALSOdspiabs dspiadd dspisub dspuadd dspumul dspusub
dspumul
TM1100 Preliminary Data Book Philips Semiconductors
A-32 PRELIMINARY INFORMATION File: ops.fm5, modified 7/23/99
Quad clipped add of unsigned/signed bytes
SYNTAX[ IF r guard ] dspuquadaddui r src1 r src2 → r dest
FUNCTIONif rguard then
for (i ← 0, m ← 31, n ← 24; i < 4; i ← i + 1, m ← m – 8, n ← n – 8) temp ← zero_ext8to32(rsrc1<m:n>) + sign_ext8to32(rsrc2<m:n>)if temp < 0 then
rdest<m:n> ← 0else if temp > 0xff then
rdest<m:n> ← 0xffelse rdest<m:n> ← temp<7:0>
ATTRIBUTESFunction unit dspaluOperation code 78Number of operands 2Modifier NoModifier range —Latency 2Issue slots 1, 3
DESCRIPTIONAs shown below, the dspuquadaddui operation computes four separate sums of the four pairs of corresponding
8-bit bytes of rsrc1 and rsrc2. The bytes in rsrc1 are considered unsigned values; the bytes in rsrc2 are consideredsigned. The four sums are clipped into the unsigned range [255..0] (or [0xff..0]); thus, the final byte sums areunsigned. All computations are performed without loss of precision.
The dspuquadaddui operation optionally takes a guard, specified in rguard. If a guard is present, its LSBcontrols the modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is notchanged.
unsigned unsigned unsigned unsigned signed signed signed signed
signed signed signed signed
unsigned unsigned unsigned unsigned
Clip to [255..0] Clip to [255..0] Clip to [255..0]
SEE ALSOdspidualadd
dspuquadaddui
Philips Semiconductors DSPCPU Operations for TM1100
File: ops.fm5, modified 7/23/99 PRELIMINARY INFORMATION A-33
Clipped unsigned subtract
SYNTAX[ IF r guard ] dspusub r src1 r src2 → r dest
FUNCTIONif rguard then
temp ← zero_ext32to64(rsrc1) – zero_ext32to64(rsrc2)if (signed)temp < 0 then
rdest ← 0else
rdest ← temp<31:0>
ATTRIBUTESFunction unit dspaluOperation code 69Number of operands 2Modifier NoModifier range —Latency 2Issue slots 1, 3
DESCRIPTIONAs shown below, the dspusub operation computes unsigned difference rsrc1–rsrc2, clips the result into the
unsigned range [232–1..0] (or [0xffffffff..0]), and stores the clipped value into rdest.
The dspusub operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
ATTRIBUTESFunction unit shifterOperation code 102Number of operands 2Modifier NoModifier range -Latency 1Issue slots 1,2
DESCRIPTIONThe argument rsrc1 contains two 16-bit signed integers, rsrc1<31:16> and rsrc1<15:0>. Rsrc2 specifies an
unsigned shift amount, and the two 16-bit integers shifted right by this amount. The sign bits rsrc1<31> and rsrc1<15>are replicated as needed within each 16-bit value from the left. If the rsrc2<31:4> value is not zero, then take this as ashift by 16 or more, i.e. extend the sign bit into either result. Note that the behavior for rsrc2 > 15 differs from the asrbehavior.
The dualasr operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
ATTRIBUTESFunction unit dspaluOperation code 82Number of operands 2Modifier NoModifier range -Latency 2Issue slots 1,3
DESCRIPTIONThe argument rsrc1 contains two signed16-bit integers, rsrc1<31:16> and rsrc1<15:0>. Each integer value is clipped
into the signed integer range (-rsrc2 -1) to rsrc2. The value in rsrc2 contains an unsigned integer and must have thevalue between 0 and 0x7fff inclusive.
The dualiclipi operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
ATTRIBUTESFunction unit dspaluOperation code 83Number of operands 2Modifier NoModifier range -Latency 2Issue slots 1,3
DESCRIPTIONThe argument rsrc1 contains two 16-bit signed integers, rsrc1<31:16> and rsrc1<15:0>. Each integer value is
clipped into the unsigned integer range 0 to rsrc2. The value in rsrc2 contains an unsigned integer and must have thevalue between 0 and 0xffff inclusive.
The dualuclipi operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
Philips Semiconductors DSPCPU Operations for TM1100
File: ops.fm5, modified 7/23/99 PRELIMINARY INFORMATION A-37
Floating-point absolute value
SYNTAX[ IF r guard ] fabsval r src1 → r dest
FUNCTIONif rguard then
if (float)rsrc1 < 0 thenrdest ← –(float)rsrc1
elserdest ← (float)rsrc1
ATTRIBUTESFunction unit faluOperation code 115Number of operands 1Modifier NoModifier range —Latency 3Issue slots 1, 4
DESCRIPTIONThe fabsval operation computes the absolute value of the argument rsrc1 and stores the result into rdest. All
values are in IEEE single-precision floating-point format. If an argument is denormalized, zero is substituted for theargument before computing the absolute value, and the IFZ flag in the PCSW is set. If fabsval causes an IEEEexception, the corresponding exception flags in the PCSW are set. The PCSW exception flags are sticky: the flags canbe set as a side-effect of any floating-point operation but can only be reset by an explicit writepcsw operation. Theupdate of the PCSW exception flags occurs at the same time as rdest is written. If any other floating-point computeoperations update the PCSW at the same time, the net result in each exception flag is the logical OR of allsimultaneous updates ORed with the existing PCSW value for that exception flag.
The fabsvalflags operation computes the exception flags that would result from an individual fabsval .The fabsval operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest and the exception flags in PCSW are written;otherwise, rdest is not changed and the operation does not affect the exception flags in PCSW.
IF r10 fabsval r55 → r115 no change, since guard is false
r20 = 1,r55 = 0xff7fffff (–3.402823466e+38)
IF r20 fabsval r55 → r120 r120 ← 0x7f7fffff (3.402823466e+38)
SEE ALSOiabs dspiabs dspidualabs
fabsvalflags readpcsw writepcsw
fabsval
TM1100 Preliminary Data Book Philips Semiconductors
A-38 PRELIMINARY INFORMATION File: ops.fm5, modified 7/23/99
IEEE status flags from floating-point absolutevalue
SYNTAX[ IF r guard ] fabsvalflags r src1 → r dest
FUNCTIONif rguard then
rdest ← ieee_flags(abs_val((float)rsrc1))
ATTRIBUTESFunction unit faluOperation code 116Number of operands 1Modifier NoModifier range —Latency 3Issue slots 1, 4
DESCRIPTIONThe fabsvalflags operation computes the IEEE exceptions that would result from computing the absolute
value of rsrc1 and writes a bit vector representing the exception flags into rdest. The argument value is in IEEE single-precision floating-point format; the result is an integer bit vector. The bit vector stored in rdest has the same format asthe IEEE exception bits in the PCSW. The exception flags in PCSW are left unchanged by this operation. If rsrc1 isdenormalized, the IFZ bit in the result is set.
The fabsvalflags operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controlsthe modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
IF r10 fabsvalflags r55 → r115 no change, since guard is false
r20 = 1,r55 = 0xff7fffff (–3.402823466e+38)
IF r20 fabsvalflags r55 → r120 r120 ← 0x0
OFZ IFZ INV OVF UNF INX DBZ
0123456731
0 0
SEE ALSOfabsval faddflags readpcsw
fabsvalflags
Philips Semiconductors DSPCPU Operations for TM1100
File: ops.fm5, modified 7/23/99 PRELIMINARY INFORMATION A-39
Floating-point add
SYNTAX[ IF r guard ] fadd r src1 r src2 → r dest
FUNCTIONif rguard then
rdest ← (float)rsrc1 + (float)rsrc2
ATTRIBUTESFunction unit faluOperation code 22Number of operands 2Modifier NoModifier range —Latency 3Issue slots 1, 4
DESCRIPTIONThe fadd operation computes the sum rsrc1+rsrc2 and stores the result into rdest. All values are in IEEE single-
precision floating-point format. Rounding is according to the IEEE rounding mode bits in PCSW. If an argument isdenormalized, zero is substituted for the argument before computing the sum, and the IFZ flag in the PCSW is set. Ifthe result is denormalized, the result is set to zero instead, and the OFZ flag in the PCSW is set. If fadd causes anIEEE exception, the corresponding exception flags in the PCSW are set. The PCSW exception flags are sticky: theflags can be set as a side-effect of any floating-point operation but can only be reset by an explicit writepcswoperation. The update of the PCSW exception flags occurs at the same time as rdest is written. If any other floating-point compute operations update the PCSW at the same time, the net result in each exception flag is the logical OR ofall simultaneous updates ORed with the existing PCSW value for that exception flag.
The faddflags operation computes the exception flags that would result from an individual fadd .The fadd operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest and the exception flags in PCSW are written;otherwise, rdest is not changed and the operation does not affect the exception flags in PCSW.
TM1100 Preliminary Data Book Philips Semiconductors
A-40 PRELIMINARY INFORMATION File: ops.fm5, modified 7/23/99
IEEE status flags from floating-point add
SYNTAX[ IF r guard ] faddflags r src1 r src2 → r dest
FUNCTIONif rguard then
rdest ← ieee_flags((float)rsrc1 + (float)rsrc2)
ATTRIBUTESFunction unit faluOperation code 112Number of operands 2Modifier NoModifier range —Latency 3Issue slots 1, 4
DESCRIPTIONThe faddflags operation computes the IEEE exceptions that would result from computing the sum rsrc1+rsrc2
and stores a bit vector representing the exception flags into rdest. The argument values are in IEEE single-precisionfloating-point format; the result is an integer bit vector. The bit vector stored in rdest has the same format as the IEEEexception bits in the PCSW. The exception flags in PCSW are left unchanged by this operation. Rounding is accordingto the IEEE rounding mode bits in PCSW. If an argument is denormalized, zero is substituted before computing thesum, and the IFZ bit in the result is set. If the sum would be denormalized, the OFZ bit in the result is set.
The faddflags operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
Philips Semiconductors DSPCPU Operations for TM1100
File: ops.fm5, modified 7/23/99 PRELIMINARY INFORMATION A-41
Floating-point divide
SYNTAX[ IF r guard ] fdiv r src1 r src2 → r dest
FUNCTIONif rguard then
rdest ← (float)rsrc1 / (float)rsrc2
ATTRIBUTESFunction unit ftoughOperation code 108Number of operands 2Modifier NoModifier range —Latency 17Recovery 16Issue slots 2
DESCRIPTIONThe fdiv operation computes the quotient rsrc1÷rsrc2 and stores the result into rdest. All values are in IEEE
single-precision floating-point format. Rounding is according to the IEEE rounding mode bits in PCSW. If an argumentis denormalized, zero is substituted for the argument before computing the quotient, and the IFZ flag in the PCSW isset. If the result is denormalized, the result is set to zero instead, and the OFZ flag in the PCSW is set. If fdivcauses an IEEE exception, the corresponding exception flags in the PCSW are set. The PCSW exception flags aresticky: the flags can be set as a side-effect of any floating-point operation but can only be reset by an explicitwritepcsw operation. The update of the PCSW exception flags occurs at the same time as rdest is written. If anyother floating-point compute operations update the PCSW at the same time, the net result in each exception flag is thelogical OR of all simultaneous updates ORed with the existing PCSW value for that exception flag.
The fdivflags operation computes the exception flags that would result from an individual fdiv .The fdiv operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest and the exception flags in PCSW are written;otherwise, rdest is not changed and the operation does not affect the exception flags in PCSW.
fdiv r75 r76 → r126 r126 ← 0x7f800000 (+INF), DBZ flag set
SEE ALSOfdivflags readpcsw
writepcsw
fdiv
TM1100 Preliminary Data Book Philips Semiconductors
A-42 PRELIMINARY INFORMATION File: ops.fm5, modified 7/23/99
IEEE status flags from floating-point divide
SYNTAX[ IF r guard ] fdivflags r src1 r src2 → r dest
FUNCTIONif rguard then
rdest ← ieee_flags((float)rsrc1 / (float)rsrc2)
ATTRIBUTESFunction unit ftoughOperation code 109Number of operands 2Modifier NoModifier range —Latency 17Recovery 16Issue slots 2
DESCRIPTIONThe fdivflags operation computes the IEEE exceptions that would result from computing the quotient
rsrc1÷rsrc2 and stores a bit vector representing the exception flags into rdest. The argument values are in IEEEsingle-precision floating-point format; the result is an integer bit vector. The bit vector stored in rdest has the sameformat as the IEEE exception bits in the PCSW. The exception flags in PCSW are left unchanged by this operation.Rounding is according to the IEEE rounding mode bits in PCSW. If an argument is denormalized, zero is substitutedbefore computing the quotient, and the IFZ bit in the result is set. If the quotient would be denormalized, the OFZ bit inthe result is set.
The fdivflags operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
Philips Semiconductors DSPCPU Operations for TM1100
File: ops.fm5, modified 7/23/99 PRELIMINARY INFORMATION A-43
Floating-point compare equal
SYNTAX[ IF r guard ] feql r src1 r src2 → r dest
FUNCTIONif rguard then
if (float)rsrc1 = (float)rsrc2 thenrdest ← 1
elserdest ← 0
ATTRIBUTESFunction unit fcompOperation code 148Number of operands 2Modifier NoModifier range —Latency 1Issue slots 3
DESCRIPTIONThe feql operation sets the destination register, rdest, to 1 if the first argument, rsrc1, is equal to the second
argument, rsrc2; otherwise, rdest is set to 0. The arguments are treated as IEEE single-precision floating-point values;the result is an integer. If an argument is denormalized, zero is substituted for the argument before computing thecomparison, and the IFZ flag in the PCSW is set. If feql causes an IEEE exception, the corresponding exceptionflags in the PCSW are set. The PCSW exception flags are sticky: the flags can be set as a side-effect of any floating-point operation but can only be reset by an explicit writepcsw operation. The update of the PCSW exception flagsoccurs at the same time as rdest is written. If any other floating-point compute operations update the PCSW at thesame time, the net result in each exception flag is the logical OR of all simultaneous updates ORed with the existingPCSW value for that exception flag.
The feqlflags operation computes the exception flags that would result from an individual feql .The feql operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest and the exception flags in PCSW are written;otherwise, rdest is not changed and the operation does not affect the exception flags in PCSW.
TM1100 Preliminary Data Book Philips Semiconductors
A-44 PRELIMINARY INFORMATION File: ops.fm5, modified 7/23/99
IEEE status flags from floating-point compareequal
SYNTAX[ IF r guard ] feqlflags r src1 r src2 → r dest
FUNCTIONif rguard then
rdest ← ieee_flags((float)rsrc1 = (float)rsrc2)
ATTRIBUTESFunction unit fcompOperation code 149Number of operands 2Modifier NoModifier range —Latency 1Issue slots 3
DESCRIPTIONThe feqlflags operation computes the IEEE exceptions that would result from computing the comparison
rsrc1=rsrc2 and stores a bit vector representing the exception flags into rdest. The argument values are in IEEEsingle-precision floating-point format; the result is an integer bit vector. The bit vector stored in rdest has the sameformat as the IEEE exception bits in the PCSW. The exception flags in PCSW are left unchanged by this operation. Ifan argument is denormalized, zero is substituted before computing the comparison, and the IFZ bit in the result is set.
The feqlflags operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
Philips Semiconductors DSPCPU Operations for TM1100
File: ops.fm5, modified 7/23/99 PRELIMINARY INFORMATION A-45
Floating-point compare greater or equal
SYNTAX[ IF r guard ] fgeq r src1 r src2 → r dest
FUNCTIONif rguard then
if (float)rsrc1 >= (float)rsrc2 thenrdest ← 1
elserdest ← 0
ATTRIBUTESFunction unit fcompOperation code 146Number of operands 2Modifier NoModifier range —Latency 1Issue slots 3
DESCRIPTIONThe fgeq operation sets the destination register, rdest, to 1 if the first argument, rsrc1, is greater than or equal to
the second argument, rsrc2; otherwise, rdest is set to 0. The arguments are treated as IEEE single-precision floating-point values; the result is an integer. If an argument is denormalized, zero is substituted for the argument beforecomputing the comparison, and the IFZ flag in the PCSW is set. If fgeq causes an IEEE exception, thecorresponding exception flags in the PCSW are set. The PCSW exception flags are sticky: the flags can be set as aside-effect of any floating-point operation but can only be reset by an explicit writepcsw operation. The update ofthe PCSW exception flags occurs at the same time as rdest is written. If any other floating-point compute operationsupdate the PCSW at the same time, the net result in each exception flag is the logical OR of all simultaneous updatesORed with the existing PCSW value for that exception flag.
The fgeqflags operation computes the exception flags that would result from an individual fgeq .The fgeq operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest and the exception flags in PCSW are written;otherwise, rdest is not changed and the operation does not affect the exception flags in PCSW.
TM1100 Preliminary Data Book Philips Semiconductors
A-46 PRELIMINARY INFORMATION File: ops.fm5, modified 7/23/99
IEEE status flags from floating-point comparegreater or equal
SYNTAX[ IF r guard ] fgeqflags r src1 r src2 → r dest
FUNCTIONif rguard then
rdest ← ieee_flags((float)rsrc1 >= (float)rsrc2)
ATTRIBUTESFunction unit fcompOperation code 147Number of operands 2Modifier NoModifier range —Latency 1Issue slots 3
DESCRIPTIONThe fgeqflags operation computes the IEEE exceptions that would result from computing the comparison
rsrc1>=rsrc2 and stores a bit vector representing the exception flags into rdest. The argument values are in IEEEsingle-precision floating-point format; the result is an integer bit vector. The bit vector stored in rdest has the sameformat as the IEEE exception bits in the PCSW. The exception flags in PCSW are left unchanged by this operation. Ifan argument is denormalized, zero is substituted before computing the comparison, and the IFZ bit in the result is set.
The fgeqflags operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
Philips Semiconductors DSPCPU Operations for TM1100
File: ops.fm5, modified 7/23/99 PRELIMINARY INFORMATION A-47
Floating-point compare greater
SYNTAX[ IF r guard ] fgtr r src1 r src2 → r dest
FUNCTIONif rguard then
if (float)rsrc1 > (float)rsrc2 thenrdest ← 1
elserdest ← 0
ATTRIBUTESFunction unit fcompOperation code 144Number of operands 2Modifier NoModifier range —Latency 1Issue slots 3
DESCRIPTIONThe fgtr operation sets the destination register, rdest, to 1 if the first argument, rsrc1, is greater than the second
argument, rsrc2; otherwise, rdest is set to 0. The arguments are treated as IEEE single-precision floating-point values;the result is an integer. If an argument is denormalized, zero is substituted for the argument before computing thecomparison, and the IFZ flag in the PCSW is set. If fgtr causes an IEEE exception, the corresponding exceptionflags in the PCSW are set. The PCSW exception flags are sticky: the flags can be set as a side-effect of any floating-point operation but can only be reset by an explicit writepcsw operation. The update of the PCSW exception flagsoccurs at the same time as rdest is written. If any other floating-point compute operations update the PCSW at thesame time, the net result in each exception flag is the logical OR of all simultaneous updates ORed with the existingPCSW value for that exception flag.
The fgtrflags operation computes the exception flags that would result from an individual fgtr .The fgtr operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest and the exception flags in PCSW are written;otherwise, rdest is not changed and the operation does not affect the exception flags in PCSW.
TM1100 Preliminary Data Book Philips Semiconductors
A-48 PRELIMINARY INFORMATION File: ops.fm5, modified 7/23/99
IEEE status flags from floating-point comparegreater
SYNTAX[ IF r guard ] fgtrflags r src1 r src2 → r dest
FUNCTIONif rguard then
rdest ← ieee_flags((float)rsrc1 > (float)rsrc2)
ATTRIBUTESFunction unit fcompOperation code 145Number of operands 2Modifier NoModifier range —Latency 1Issue slots 3
DESCRIPTIONThe fgtrflags operation computes the IEEE exceptions that would result from computing the comparison
rsrc1>rsrc2 and stores a bit vector representing the exception flags into rdest. The argument values are in IEEEsingle-precision floating-point format; the result is an integer bit vector. The bit vector stored in rdest has the sameformat as the IEEE exception bits in the PCSW. The exception flags in PCSW are left unchanged by this operation. Ifan argument is denormalized, zero is substituted before computing the comparison, and the IFZ bit in the result is set.
The fgtrflags operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
Philips Semiconductors DSPCPU Operations for TM1100
File: ops.fm5, modified 7/23/99 PRELIMINARY INFORMATION A-49
Floating-point compare less-than or equalpseudo-op for fgeq
SYNTAX[ IF r guard ] fleq r src1 r src2 → r dest
FUNCTIONif rguard then
if (float)rsrc1 <= (float)rsrc2 thenrdest ← 1
elserdest ← 0
ATTRIBUTESFunction unit fcompOperation code 146Number of operands 2Modifier NoModifier range —Latency 1Issue slots 3
DESCRIPTIONThe fleq operation is a pseudo operation transformed by the scheduler into an fgeq with the arguments
exchanged (fleq ’s rsrc1 is fgeq ’s rsrc2 and vice versa). (Note: pseudo operations cannot be used in assemblysource files.)
The fleq operation sets the destination register, rdest, to 1 if the first argument, rsrc1, is less than or equal to thesecond argument, rsrc2; otherwise, rdest is set to 0. The arguments are treated as IEEE single-precision floating-pointvalues; the result is an integer. If an argument is denormalized, zero is substituted for the argument before computingthe comparison, and the IFZ flag in the PCSW is set. If fleq causes an IEEE exception, the corresponding exceptionflags in the PCSW are set. The PCSW exception flags are sticky: the flags can be set as a side-effect of any floating-point operation but can only be reset by an explicit writepcsw operation. The update of the PCSW exception flagsoccurs at the same time as rdest is written. If any other floating-point compute operations update the PCSW at thesame time, the net result in each exception flag is the logical OR of all simultaneous updates ORed with the existingPCSW value for that exception flag.
The fleqflags operation computes the exception flags that would result from an individual fleq .The fleq operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest and the exception flags in PCSW are written;otherwise, rdest is not changed and the operation does not affect the exception flags in PCSW.
TM1100 Preliminary Data Book Philips Semiconductors
A-50 PRELIMINARY INFORMATION File: ops.fm5, modified 7/23/99
IEEE status flags from floating-point compareless-than or equalpseudo-op for fgeqflags
SYNTAX[ IF r guard ] fleqflags r src1 r src2 → r dest
FUNCTIONif rguard then
rdest ← ieee_flags((float)rsrc1 <= (float)rsrc2)
ATTRIBUTESFunction unit fcompOperation code 147Number of operands 2Modifier NoModifier range —Latency 1Issue slots 3
DESCRIPTIONThe fleqflags operation is a pseudo operation transformed by the scheduler into an fgeqflags with the
arguments exchanged (fleqflags ’s rsrc1 is fgeqflags ’s rsrc2 and vice versa). (Note: pseudo operationscannot be used in assembly source files.)
The fleqflags operation computes the IEEE exceptions that would result from computing the comparisonrsrc1<=rsrc2 and stores a bit vector representing the exception flags into rdest. The argument values are in IEEEsingle-precision floating-point format; the result is an integer bit vector. The bit vector stored in rdest has the sameformat as the IEEE exception bits in the PCSW. The exception flags in PCSW are left unchanged by this operation. Ifan argument is denormalized, zero is substituted before computing the comparison, and the IFZ bit in the result is set.
The fleqflags operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
Philips Semiconductors DSPCPU Operations for TM1100
File: ops.fm5, modified 7/23/99 PRELIMINARY INFORMATION A-51
Floating-point compare less-thanpseudo-op for fgtr
SYNTAX[ IF r guard ] fles r src1 r src2 → r dest
FUNCTIONif rguard then
if (float)rsrc1 < (float)rsrc2 thenrdest ← 1
elserdest ← 0
ATTRIBUTESFunction unit fcompOperation code 144Number of operands 2Modifier NoModifier range —Latency 1Issue slots 3
DESCRIPTIONThe fles operation is a pseudo operation transformed by the scheduler into an fgtr with the arguments
exchanged (fles ’s rsrc1 is fgtr ’s rsrc2 and vice versa). (Note: pseudo operations cannot be used in assemblysource files.)
The fles operation sets the destination register, rdest, to 1 if the first argument, rsrc1, is less than the secondargument, rsrc2; otherwise, rdest is set to 0. The arguments are treated as IEEE single-precision floating-point values;the result is an integer. If an argument is denormalized, zero is substituted for the argument before computing thecomparison, and the IFZ flag in the PCSW is set. If fles causes an IEEE exception, the corresponding exceptionflags in the PCSW are set. The PCSW exception flags are sticky: the flags can be set as a side-effect of any floating-point operation but can only be reset by an explicit writepcsw operation. The update of the PCSW exception flagsoccurs at the same time as rdest is written. If any other floating-point compute operations update the PCSW at thesame time, the net result in each exception flag is the logical OR of all simultaneous updates ORed with the existingPCSW value for that exception flag.
The flesflags operation computes the exception flags that would result from an individual fles .The fles operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest and the exception flags in PCSW are written;otherwise, rdest is not changed and the operation does not affect the exception flags in PCSW.
TM1100 Preliminary Data Book Philips Semiconductors
A-52 PRELIMINARY INFORMATION File: ops.fm5, modified 7/23/99
IEEE status flags from floating-point compareless-than
pseudo-op for fgtrflags
SYNTAX[ IF r guard ] flesflags r src1 r src2 → r dest
FUNCTIONif rguard then
rdest ← ieee_flags((float)rsrc1 < (float)rsrc2)
ATTRIBUTESFunction unit fcompOperation code 145Number of operands 2Modifier NoModifier range —Latency 1Issue slots 3
DESCRIPTIONThe flesflags operation is a pseudo operation transformed by the scheduler into an fgtrflags with the
arguments exchanged (flesflags ’s rsrc1 is fgtrflags ’s rsrc2 and vice versa). (Note: pseudo operationscannot be used in assembly source files.)
The flesflags operation computes the IEEE exceptions that would result from computing the comparisonrsrc1<rsrc2 and stores a bit vector representing the exception flags into rdest. The argument values are in IEEEsingle-precision floating-point format; the result is an integer bit vector. The bit vector stored in rdest has the sameformat as the IEEE exception bits in the PCSW. The exception flags in PCSW are left unchanged by this operation. Ifan argument is denormalized, zero is substituted before computing the comparison, and the IFZ bit in the result is set.
The flesflags operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
Philips Semiconductors DSPCPU Operations for TM1100
File: ops.fm5, modified 7/23/99 PRELIMINARY INFORMATION A-53
Floating-point multiply
SYNTAX[ IF r guard ] fmul r src1 r src2 → r dest
FUNCTIONif rguard then
rdest ← (float)rsrc1 × (float)rsrc2
ATTRIBUTESFunction unit ifmulOperation code 28Number of operands 2Modifier NoModifier range —Latency 3Issue slots 2, 3
DESCRIPTIONThe fmul operation computes the product rsrc1×rsrc2 and stores the result into rdest. All values are in IEEE single-
precision floating-point format. Rounding is according to the IEEE rounding mode bits in PCSW. If an argument isdenormalized, zero is substituted for the argument before computing the product, and the IFZ flag in the PCSW is set.If the result is denormalized, the result is set to zero instead, and the OFZ flag in the PCSW is set. If fmul causes anIEEE exception, the corresponding exception flags in the PCSW are set. The PCSW exception flags are sticky: theflags can be set as a side-effect of any floating-point operation but can only be reset by an explicit writepcswoperation. The update of the PCSW exception flags occurs at the same time as rdest is written. If any other floating-point compute operations update the PCSW at the same time, the net result in each exception flag is the logical OR ofall simultaneous updates ORed with the existing PCSW value for that exception flag.
The fmulflags operation computes the exception flags that would result from an individual fmul .The fmul operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest and the exception flags in PCSW are written;otherwise, rdest is not changed and the operation does not affect the exception flags in PCSW.
r80 = 0x00800000 (1.763241526e–38) fmul r80 r80 → r125 r125 ← 0, UNF, INX flag set
SEE ALSOimul umul dspimul
dspidualmul fmulflags readpcsw writepcsw
fmul
TM1100 Preliminary Data Book Philips Semiconductors
A-54 PRELIMINARY INFORMATION File: ops.fm5, modified 7/23/99
IEEE status flags from floating-point multiply
SYNTAX[ IF r guard ] fmulflags r src1 r src2 → r dest
FUNCTIONif rguard then
rdest ← ieee_flags((float)rsrc1 × (float)rsrc2)
ATTRIBUTESFunction unit ifmulOperation code 143Number of operands 2Modifier NoModifier range —Latency 3Issue slots 2, 3
DESCRIPTIONThe fmulflags operation computes the IEEE exceptions that would result from computing the product
rsrc1×rsrc2 and stores a bit vector representing the exception flags into rdest. The argument values are in IEEEsingle-precision floating-point format; the result is an integer bit vector. The bit vector stored in rdest has the sameformat as the IEEE exception bits in the PCSW. The exception flags in PCSW are left unchanged by this operation.Rounding is according to the IEEE rounding mode bits in PCSW. If an argument is denormalized, zero is substitutedbefore computing the product, and the IFZ bit in the result is set. If the product would be denormalized, the OFZ bit inthe result is set.
The fmulflags operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
Philips Semiconductors DSPCPU Operations for TM1100
File: ops.fm5, modified 7/23/99 PRELIMINARY INFORMATION A-55
Floating-point compare not equal
SYNTAX[ IF r guard ] fneq r src1 r src2 → r dest
FUNCTIONif rguard then
if (float)rsrc1 != (float)rsrc2 thenrdest ← 1
elserdest ← 0
ATTRIBUTESFunction unit fcompOperation code 150Number of operands 2Modifier NoModifier range —Latency 1Issue slots 3
DESCRIPTIONThe fneq operation sets the destination register, rdest, to 1 if the first argument, rsrc1, is not equal to the second
argument, rsrc2; otherwise, rdest is set to 0. The arguments are treated as IEEE single-precision floating-point values;the result is an integer. If an argument is denormalized, zero is substituted for the argument before computing thecomparison, and the IFZ flag in the PCSW is set. If fneq causes an IEEE exception, the corresponding exceptionflags in the PCSW are set. The PCSW exception flags are sticky: the flags can be set as a side-effect of any floating-point operation but can only be reset by an explicit writepcsw operation. The update of the PCSW exception flagsoccurs at the same time as rdest is written. If any other floating-point compute operations update the PCSW at thesame time, the net result in each exception flag is the logical OR of all simultaneous updates ORed with the existingPCSW value for that exception flag.
The fneqflags operation computes the exception flags that would result from an individual fneq .The fneq operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest and the exception flags in PCSW are written;otherwise, rdest is not changed and the operation does not affect the exception flags in PCSW.
TM1100 Preliminary Data Book Philips Semiconductors
A-56 PRELIMINARY INFORMATION File: ops.fm5, modified 7/23/99
IEEE status flags from floating-point comparenot equal
SYNTAX[ IF r guard ] fneqflags r src1 r src2 → r dest
FUNCTIONif rguard then
rdest ← ieee_flags((float)rsrc1 != (float)rsrc2)
ATTRIBUTESFunction unit fcompOperation code 151Number of operands 2Modifier NoModifier range —Latency 1Issue slots 3
DESCRIPTIONThe fneqflags operation computes the IEEE exceptions that would result from computing the comparison
rsrc1!=rsrc2 and stores a bit vector representing the exception flags into rdest. The argument values are in IEEEsingle-precision floating-point format; the result is an integer bit vector. The bit vector stored in rdest has the sameformat as the IEEE exception bits in the PCSW. The exception flags in PCSW are left unchanged by this operation. Ifan argument is denormalized, zero is substituted before computing the comparison, and the IFZ bit in the result is set.
The fneqflags operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
Philips Semiconductors DSPCPU Operations for TM1100
File: ops.fm5, modified 7/23/99 PRELIMINARY INFORMATION A-57
Sign of floating-point value
SYNTAX[ IF r guard ] fsign r src1 → r dest
FUNCTIONif rguard then
if (float)rsrc1 = 0.0 thenrdest ← 0
else if (float)rsrc1 < 0.0 thenrdest ← 0xffffffff
elserdest ← 1
ATTRIBUTESFunction unit fcompOperation code 152Number of operands 1Modifier NoModifier range —Latency 1Issue slots 3
DESCRIPTIONThe fsign operation sets the destination register, rdest, to either 0, 1, or –1 depending on the sign of the argument
in rsrc1. rdest is set to 0 if rsrc1 is equal to zero, to 1 if rsrc1 is positive, or to –1 if rsrc1 is negative. The argument istreated as an IEEE single-precision floating-point value; the result is an integer. If the argument is denormalized, zerois substituted before computing the comparison, and the IFZ flag in the PCSW is set; thus, the result of fsign for adenormalized argument is 0. If fsign causes an IEEE exception, the corresponding exception flags in the PCSWare set. The PCSW exception flags are sticky: the flags can be set as a side-effect of any floating-point operation butcan only be reset by an explicit writepcsw operation. The update of the PCSW exception flags occurs at the sametime as rdest is written. If any other floating-point compute operations update the PCSW at the same time, the netresult in each exception flag is the logical OR of all simultaneous updates ORed with the existing PCSW value for thatexception flag.
The fsignflags operation computes the exception flags that would result from an individual fsign .The fsign operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest and the exception flags in PCSW are written;otherwise, rdest is not changed and the operation does not affect the exception flags in PCSW.
TM1100 Preliminary Data Book Philips Semiconductors
A-58 PRELIMINARY INFORMATION File: ops.fm5, modified 7/23/99
IEEE status flags from floating-point sign
SYNTAX[ IF r guard ] fsignflags r src1 → r dest
FUNCTIONif rguard then
rdest ← ieee_flags(sign((float)rsrc1))
ATTRIBUTESFunction unit fcompOperation code 153Number of operands 1Modifier NoModifier range —Latency 1Issue slots 3
DESCRIPTIONThe fsignflags operation computes the IEEE exceptions that would result from computing the sign of rsrc1 and
stores a bit vector representing the exception flags into rdest. The argument value is in IEEE single-precision floating-point format; the result is an integer bit vector. The bit vector stored in rdest has the same format as the IEEEexception bits in the PCSW. The exception flags in PCSW are left unchanged by this operation. If the argument isdenormalized, zero is substituted before computing the sign, and the IFZ bit in the result is set.
The fsignflags operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
Philips Semiconductors DSPCPU Operations for TM1100
File: ops.fm5, modified 7/23/99 PRELIMINARY INFORMATION A-59
Floating-point square root
SYNTAX[ IF r guard ] fsqrt r src1 → r dest
FUNCTIONif rguard then
rdest ← square_root(rsrc1)
ATTRIBUTESFunction unit ftoughOperation code 110Number of operands 1Modifier NoModifier range —Latency 17Recovery 16Issue slots 2
DESCRIPTIONThe fsqrt operation computes the squareroot of rsrc1 and stores the result into rdest. All values are in IEEE
single-precision floating-point format. Rounding is according to the IEEE rounding mode bits in PCSW. If an argumentis denormalized, zero is substituted for the argument before computing the squareroot, and the IFZ flag in the PCSWis set. If the result is denormalized, the result is set to zero instead, and the OFZ flag in the PCSW is set. If fsqrtcauses an IEEE exception, the corresponding exception flags in the PCSW are set. The PCSW exception flags aresticky: the flags can be set as a side-effect of any floating-point operation but can only be reset by an explicitwritepcsw operation. The update of the PCSW exception flags occurs at the same time as rdest is written. If anyother floating-point compute operations update the PCSW at the same time, the net result in each exception flag is thelogical OR of all simultaneous updates ORed with the existing PCSW value for that exception flag.
The fsqrtflags operation computes the exception flags that would result from an individual fsqrt .The fsqrt operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest and the exception flags in PCSW are written;otherwise, rdest is not changed and the operation does not affect the exception flags in PCSW.
EXAMPLES
Initial Values Operation Result
r60 = 0xc0400000 (–3.0) fsqrt r60 → r90 r90 ← 0xffffffff (QNaN), INV flag set
r40 = 0x40400000 (3.0) fsqrt r40 → r95 r95 ← 0x3fddb3d7 (1.732051), INX flag set
r10 = 0, r40 = 0x40400000 (3.0) IF r10 fsqrt r40 → r100 no change, since guard is false
r20 = 1, r40 = 0x40400000 (3.0) IF r20 fsqrt r40 → r110 r110 ← 0x3fddb3d7 (1.732051), INX flag set
r82 = 0x00c00000 (1.763241526e–38) fsqrt r82 → r112 r112 ← 0x201cc471 (1.32787105e-19), INX flag set
r70 = 0x7f7fffff (3.402823466e+38) fsqrt r70 → r120 r120 ← 0x5f7fffff (1.8446743e19), INX flag set
r80 = 0x00400000 (5.877471754e-39) fsqrt r80 → r125 r125 ← 0, IFZ flag set
SEE ALSOfsqrtflags readpcsw
writepcsw
fsqrt
TM1100 Preliminary Data Book Philips Semiconductors
A-60 PRELIMINARY INFORMATION File: ops.fm5, modified 7/23/99
IEEE status flags from floating-point square root
SYNTAX[ IF r guard ] fsqrtflags r src1 → r dest
FUNCTIONif rguard then
rdest ← ieee_flags(square_root((float)rsrc1))
ATTRIBUTESFunction unit ftoughOperation code 111Number of operands 1Modifier NoModifier range —Latency 17Recovery 16Issue slots 2
DESCRIPTIONThe fsqrtflags operation computes the IEEE exceptions that would result from computing the squareroot of
rsrc1 and stores a bit vector representing the exception flags into rdest. The argument value is in IEEE single-precision floating-point format; the result is an integer bit vector. The bit vector stored in rdest has the same format asthe IEEE exception bits in the PCSW. The exception flags in PCSW are left unchanged by this operation. Rounding isaccording to the IEEE rounding mode bits in PCSW. If the argument is denormalized, zero is substituted beforecomputing the squareroot, and the IFZ bit in the result is set. If the result is denormalized, and the OFZ flag in thePCSW is set.
The fsqrtflags operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
Philips Semiconductors DSPCPU Operations for TM1100
File: ops.fm5, modified 7/23/99 PRELIMINARY INFORMATION A-61
Floating-point subtract
SYNTAX[ IF r guard ] fsub r src1 r src2 → r dest
FUNCTIONif rguard then
rdest ← (float)rsrc1 – (float)rsrc2
ATTRIBUTESFunction unit faluOperation code 113Number of operands 2Modifier NoModifier range —Latency 3Issue slots 1, 4
DESCRIPTIONThe fsub operation computes the difference rsrc1–rsrc2 and writes the result into rdest. All values are in IEEE
single-precision floating-point format. Rounding is according to the IEEE rounding mode bits in PCSW. If an argumentis denormalized, zero is substituted for the argument before computing the difference, and the IFZ flag in the PCSW isset. If the result is denormalized, the result is set to zero instead, and the OFZ flag in the PCSW is set. If fsubcauses an IEEE exception, the corresponding exception flags in the PCSW are set. The PCSW exception flags aresticky: the flags can be set as a side-effect of any floating-point operation but can only be reset by an explicitwritepcsw operation. The update of the PCSW exception flags occurs at the same time as rdest is written. If anyother floating-point compute operations update the PCSW at the same time, the net result in each exception flag is thelogical OR of all simultaneous updates ORed with the existing PCSW value for that exception flag.
The fsubflags operation computes the exception flags that would result from an individual fsub .The fsub operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest and the exception flags in PCSW are written;otherwise, rdest is not changed and the operation does not affect the exception flags in PCSW.
TM1100 Preliminary Data Book Philips Semiconductors
A-62 PRELIMINARY INFORMATION File: ops.fm5, modified 7/23/99
IEEE status flags from floating-point subtract
SYNTAX[ IF r guard ] fsubflags r src1 r src2 → r dest
FUNCTIONif rguard then
rdest ← ieee_flags((float)rsrc1 – (float)rsrc2)
ATTRIBUTESFunction unit faluOperation code 114Number of operands 2Modifier NoModifier range —Latency 3Issue slots 1, 4
DESCRIPTIONThe fsubflags operation computes the IEEE exceptions that would result from computing the difference rsrc1–
rsrc2 and writes a bit vector representing the exception flags into rdest. The argument values are in IEEE single-precision floating-point format; the result is an integer bit vector. The bit vector stored in rdest has the same format asthe IEEE exception bits in the PCSW. The exception flags in PCSW are left unchanged by this operation. Rounding isaccording to the IEEE rounding mode bits in PCSW. If an argument is denormalized, zero is substituted beforecomputing the difference, and the IFZ bit in the result is set. If the difference would be denormalized, the OFZ bit in theresult is set.
The fsubflags operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
ATTRIBUTESFunction unit shifterOperation code 99Number of operands 2Modifier NoModifier range —Latency 1Issue slots 1, 2
DESCRIPTIONAs shown below, the funshift1 operation effectively shifts left by one byte the 64-bit concatenation of rsrc1 and
rsrc2 and writes the most-significant 32 bits of the shifted result to rdest.
The funshift1 operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
ATTRIBUTESFunction unit shifterOperation code 100Number of operands 2Modifier NoModifier range —Latency 1Issue slots 1, 2
DESCRIPTIONAs shown below, the funshift2 operation effectively shifts left by two bytes the 64-bit concatenation of rsrc1 and
rsrc2 and writes the most-significant 32 bits of the shifted result to rdest.
The funshift2 operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
ATTRIBUTESFunction unit shifterOperation code 101Number of operands 2Modifier NoModifier range —Latency 1Issue slots 1, 2
DESCRIPTIONAs shown below, the funshift3 operation effectively shifts left by three bytes the 64-bit concatenation of rsrc1
and rsrc2 and writes the most-significant 32 bits of the shifted result to rdest.
The funshift3 operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
IF r10 funshift3 r40 r30 → r60 no change, since guard is false
r20 = 1, r40 = 0x11223344,r30 = 0xaabbccdd
IF r20 funshift3 r40 r30 → r70 r70 ← 0x44aabbcc
07123
rsrc107123
rsrc2
07123
rdest
SEE ALSOfunshift1 funshift2 rol
funshift3
TM1100 Preliminary Data Book Philips Semiconductors
A-66 PRELIMINARY INFORMATION File: ops.fm5, modified 7/23/99
Clipped signed absolute value
SYNTAX[ IF r guard ] h_dspiabs r0 r src2 → r dest
FUNCTIONif rguard then
if rsrc2 >= 0 thenrdest ← rsrc2
else if rsrc2 = 0x80000000 thenrdest ← 0x7fffffff
elserdest ← –rsrc2
ATTRIBUTESFunction unit dspaluOperation code 65Number of operands 2Modifier NoModifier range —Latency 2Issue slots 1, 3
DESCRIPTIONThe h_dspiabs operation computes the absolute value of rsrc2, clips the result into the range [0x0..0x7fffffff], and
stores the clipped value into rdest. All values are signed integers. This operation requires a zero as first argument. Theprogrammer is advised to use the unary pseudo operation dspiabs instead.
The h_dspiabs operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
Philips Semiconductors DSPCPU Operations for TM1100
File: ops.fm5, modified 7/23/99 PRELIMINARY INFORMATION A-67
Dual clipped absolute value of signed 16-bit halfwords
SYNTAX[ IF r guard ] h_dspidualabs r0 rsrc2 → r dest
FUNCTIONif rguard then
temp1 ← sign_ext16to32(rsrc2<15:0>)temp2 ← sign_ext16to32(rsrc2<31:16>)if temp1 = 0xffff8000 then temp1 ← 0x7fffif temp2 = 0xffff8000 then temp2 ← 0x7fffif temp1 < 0 then temp1 ← –temp1if temp2 < 0 then temp2 ← –temp2rdest<31:16> ← temp2<15:0>rdest<15:0> ← temp1<15:0>
ATTRIBUTESFunction unit dspaluOperation code 72Number of operands 2Modifier NoModifier range —Latency 2Issue slots 1, 3
DESCRIPTIONThe h_dspidualabs operation performs two 16-bit clipped, signed absolute value computations separately on
the high and low 16-bit halfwords of rsrc2. Both absolute values are clipped into the range [0x0..0x7fff] and written intothe corresponding halfwords of rdest. All values are signed 16-bit integers. This operation requires a zero as firstargument. The programmer is advised to use the dspidualabs pseudo operation instead.
The h_dspidualabs operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controlsthe modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
TM1100 Preliminary Data Book Philips Semiconductors
A-68 PRELIMINARY INFORMATION File: ops.fm5, modified 7/23/99
Hardware absolute value
SYNTAX[ IF r guard ] h_iabs r0 rsrc2 → r dest
FUNCTIONif rguard then
if rsrc2 < 0 thenrdest ← –rsrc2
elserdest ← rsrc2
ATTRIBUTESFunction unit aluOperation code 44Number of operands 2Modifier NoModifier range —Latency 1Issue slots 1, 2, 3, 4, 5
DESCRIPTIONThe h_iabs operation computes the absolute value of rsrc2 and stores the result into rdest. The argument is a
signed integer; the result is an unsigned integer. This operation requires a zero as first argument. The programmer isadvised to use the iabs pseudo operation instead.
The h_iabs operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
Philips Semiconductors DSPCPU Operations for TM1100
File: ops.fm5, modified 7/23/99 PRELIMINARY INFORMATION A-69
Hardware 16-bit store with displacement
SYNTAX[ IF r guard ] h_st16d( d) r src1 r src2
FUNCTIONif rguard then
if PCSW.bytesex = LITTLE_ENDIAN then bs ← 1
else bs ← 0
mem[rsrc2 + d + (1 ⊕ bs)] ← rsrc1<7:0>mem[rsrc2 + d + (0 ⊕ bs)] ← rsrc1<15:8>
ATTRIBUTESFunction unit dmemOperation code 30Number of operands 2Modifier 7 bitsModifier range –128..126 by 2Latency n/aIssue slots 4, 5
DESCRIPTIONThe h_st16d operation stores the least-significant 16-bit halfword of rsrc1 into the memory locations pointed to by
the address in rsrc2 + d. The d value is an opcode modifier, must be in the range –128 and 126 inclusive, and must bea multiple of 2. This store operation is performed as little-endian or big-endian depending on the current setting of thebytesex bit in the PCSW.
If h_st16d is misaligned (the memory address computed by rsrc2 + d is not a multiple of 2), the result ofh_st16d is undefined, and the MSE (Misaligned Store Exception) bit in the PCSW register is set to 1. Additionally, ifthe TRPMSE (TRaP on Misaligned Store Exception) bit in PCSW is 1, exception processing will be requested on thenext interruptible jump.
The h_st16d operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the addressed memory locations (and the modification of cache if the locations are cacheable). If theLSB of rguard is 1, the store takes effect. If the LSB of rguard is 0, h_st16d has no side effects whatever; in particular,the LRU and other status bits in the data cache are not affected.
TM1100 Preliminary Data Book Philips Semiconductors
A-70 PRELIMINARY INFORMATION File: ops.fm5, modified 7/23/99
Hardware 32-bit store with displacement
SYNTAX[ IF r guard ] h_st32d( d) r src1 r src2
FUNCTIONif rguard then
if PCSW.bytesex = LITTLE_ENDIAN then bs ← 3
else bs ← 0
mem[rsrc2 + d + (3 ⊕ bs)] ← rsrc1<7:0>mem[rsrc2 + d + (2 ⊕ bs)] ← rsrc1<15:8>
mem[rsrc2 + d + (1 ⊕ bs)] ← rsrc1<24:16> mem[rsrc2 + d + (0 ⊕ bs)] ← rsrc1<31:24>
ATTRIBUTESFunction unit dmemOperation code 31Number of operands 2Modifier 7 bitsModifier range –256..252 by 4Latency n/aIssue slots 4, 5
DESCRIPTIONThe h_st32d operation stores all 32 bits of rsrc1 into the memory locations pointed to by the address in rsrc2 + d.
The d value is an opcode modifier, must be in the range –256 and 252 inclusive, and must be a multiple of 4. Thisstore operation is performed as little-endian or big-endian depending on the current setting of the bytesex bit in thePCSW.
If h_st32d is misaligned (the memory address computed by rsrc2 + d is not a multiple of 4), the result ofh_st32d is undefined, and the MSE (Misaligned Store Exception) bit in the PCSW register is set to 1. Additionally, ifthe TRPMSE (TRaP on Misaligned Store Exception) bit in PCSW is 1, exception processing will be requested on thenext interruptible jump.
The h_st32d operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the addressed memory locations (and the modification of cache if the locations are cacheable). If theLSB of rguard is 1, the store takes effect. If the LSB of rguard is 0, h_st32d has no side effects whatever; inparticular, the LRU and other status bits in the data cache are not affected.
Philips Semiconductors DSPCPU Operations for TM1100
File: ops.fm5, modified 7/23/99 PRELIMINARY INFORMATION A-71
Hardware 8-bit store with displacement
SYNTAX[ IF r guard ] h_st8d( d) r src1 r src2
FUNCTIONif rguard then
mem[rsrc2 + d] ← rsrc1<7:0>
ATTRIBUTESFunction unit dmemOperation code 29Number of operands 2Modifier 7 bitsModifier range –64..63Latency n/aIssue slots 4, 5
DESCRIPTIONThe h_st8d operation stores the least-significant 8-bit byte of rsrc1 into the memory location pointed to by the
address formed from the sum rsrc2 + d. The value of the opcode modifier d must be in the range -64 and 63 inclusive.This operation does not depend on the bytesex bit in the PCSW since only a single byte is stored.
The h_st8d operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the addressed memory location (and the modification of cache if the location is cacheable). If the LSBof rguard is 1, the store takes effect. If the LSB of rguard is 0, h_st8d has no side effects whatever; in particular, theLRU and other status bits in the data cache are not affected.
IF r50 h_st8d(-4) r70 r20 no change, since guard is false
r60 = 1, r30 = 0xd02,r70 = 0xaabbccdd
IF r60 h_st8d(-4) r70 r30 [0xcfe] ← 0xdd
SEE ALSOst8 st8d st16 st16d st32
st32d
h_st8d
TM1100 Preliminary Data Book Philips Semiconductors
A-72 PRELIMINARY INFORMATION File: ops.fm5, modified 7/23/99
Read clock cycle counter, most-significant word
SYNTAX[ IF r guard ] hicycles → r dest
FUNCTIONif rguard then
rdest ← CCCOUNT<63:32>
ATTRIBUTESFunction unit fcompOperation code 155Number of operands 0Modifier NoModifier range —Latency 1Issue slots 3
DESCRIPTIONRefer to Section 3.1.5, “CCCOUNT—Clock Cycle Counter” for a description of the CCCOUNT operation. The
hicycles operation copies the high 32 bits of the slave register Clock Cycle Counter (CCCOUNT) to the destinationregister, rdest. The contents of the master counter are transferred to the slave CCCOUNT register only on asuccessful interruptible jump and on processor reset. Thus, if cycles and hicycles are executed withoutintervening interruptible jumps, the operation pair is guaranteed to be a coherent sample of the master clock-cyclecounter. The master counter increments on all cycles (processor-stall and non-stall) if PCSW.CS = 1; otherwise, thecounter increments only on non-stall cycles.
The hicycles operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
Philips Semiconductors DSPCPU Operations for TM1100
File: ops.fm5, modified 7/23/99 PRELIMINARY INFORMATION A-73
Absolute valuepseudo-op for h_iabs
SYNTAX[ IF r guard ] iabs r src1 → r dest
FUNCTIONif rguard then
if rsrc1 < 0 thenrdest ← –rsrc1
elserdest ← rsrc1
ATTRIBUTESFunction unit aluOperation code 44Number of operands 1Modifier NoModifier range —Latency 1Issue slots 1, 2, 3, 4, 5
DESCRIPTIONThe iabs operation is a pseudo operation transformed by the scheduler into an h_iabs with zero as the first
argument and a second argument equal to the iabs argument. (Note: pseudo operations cannot be used inassembly source files.)
The iabs operation computes the absolute value of rsrc1 and stores the result into rdest. The argument is a signedinteger; the result is an unsigned integer.
The iabs operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 0xffffffff iabs r30 → r60 r60 ← 0x00000001
r10 = 0, r40 = 0xfffffff4 IF r10 iabs r40 → r80 no change, since guard is false
TM1100 Preliminary Data Book Philips Semiconductors
A-74 PRELIMINARY INFORMATION File: ops.fm5, modified 7/23/99
Signed add
SYNTAX[ IF r guard ] iadd r src1 r src2 → r dest
FUNCTIONif rguard then
rdest ← rsrc1 + rsrc2
ATTRIBUTESFunction unit aluOperation code 12Number of operands 2Modifier NoModifier range —Latency 1Issue slots 1, 2, 3, 4, 5
DESCRIPTIONThe iadd operation computes the sum rsrc1+rsrc2 and stores the result into rdest. The operands can be either
both signed or unsigned integers. No overflow or underflow detection is performed.The iadd operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r60 = 0x100 iadd r60 r60 → r80 r80 ← 0x200
r10 = 0, r60 = 0x100, r30 = 0xf11 IF r10 iadd r60 r30 → r50 no change, since guard is false
Philips Semiconductors DSPCPU Operations for TM1100
File: ops.fm5, modified 7/23/99 PRELIMINARY INFORMATION A-75
Add with immediate
SYNTAX[ IF r guard ] iaddi( n) r src1 → r dest
FUNCTIONif rguard then
rdest ← rsrc1 + n
ATTRIBUTESFunction unit aluOperation code 5Number of operands 1Modifier 7 bitsModifier range 0..127Latency 1Issue slots 1, 2, 3, 4, 5
DESCRIPTIONThe iaddi operation sums a single argument in rsrc1 and an immediate modifier n and stores the result in rdest.
The value of n must be between 0 and 127, inclusive. The iaddi operations optionally take a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is unchanged.
EXAMPLES
Initial Values Operation Result
r30 = 0xf11 iaddi(127) r30 → r70 r70 ← 0xf90
r10 = 0, r40 = 0xffffff9c IF r10 iaddi(1) r40 → r80 no change, since guard is false
ATTRIBUTESFunction unit dspaluOperation code 25Number of operands 2Modifier NoModifier range —Latency 2Issue slots 1, 3
DESCRIPTIONAs shown below, the iavgonep operation returns the average of the two arguments. This operation computes the
sum rsrc1+rsrc2+1, shifts the sum right by 1 bit, and stores the result into rdest. The operands are signed integers.
The iavgonep operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
Philips Semiconductors DSPCPU Operations for TM1100
File: ops.fm5, modified 7/23/99 PRELIMINARY INFORMATION A-77
Signed select byte
SYNTAX[ IF r guard ] ibytesel r src1 r src2 → r dest
FUNCTIONif rguard then
if rsrc2 = 0 then rdest ← sign_ext8to32(rsrc1<7:0>)
else if rsrc2 = 1 then rdest ← sign_ext8to32(rsrc1<15:8>)
else if rsrc2 = 2 then rdest ← sign_ext8to32(rsrc1<23:16>)
else if rsrc2 = 3 then rdest ← sign_ext8to32(rsrc1<31:24>)
ATTRIBUTESFunction unit aluOperation code 56Number of operands 2Modifier NoModifier range —Latency 1Issue slots 1, 2, 3, 4, 5
DESCRIPTIONAs shown below, the ibytesel operation selects one byte from the argument, rsrc1, sign-extends the byte to 32
bits, and stores the result in rdest. The value of rsrc2 determines which byte is selected, with rsrc2=0 selecting theLSB of rsrc1 and rsrc2=3 selecting the MSB of rsrc1. If rsrc2 is not between 0 and 3 inclusive, the result ofibytesel is undefined.
The ibytesel operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
TM1100 Preliminary Data Book Philips Semiconductors
A-78 PRELIMINARY INFORMATION File: ops.fm5, modified 7/23/99
Clip signed to signed
SYNTAX[ IF r guard ] iclipi r src1 r src2 → r dest
FUNCTIONif rguard then
rdest ← min(max(rsrc1, –rsrc2–1), rsrc2)
ATTRIBUTESFunction unit dspaluOperation code 74Number of operands 2Modifier NoModifier range —Latency 2Issue slots 1, 3
DESCRIPTIONThe iclipi operation returns the value of rsrc1 clipped into the unsigned integer range (–rsrc2–1) to rsrc2,
inclusive. The argument rsrc1 is considered a signed integer; rsrc2 is considered an unsigned integer and must havea value between 0 and 0x7fffffff inclusive.
The iclipi operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
Philips Semiconductors DSPCPU Operations for TM1100
File: ops.fm5, modified 7/23/99 PRELIMINARY INFORMATION A-79
Invalidate all instruction cache blocks
SYNTAX[ IF r guard ] iclr
FUNCTIONif rguard then
block ← 0for all blocks in instruction cache
icache_reset_valid_block(block)block ← block + 1
ATTRIBUTESFunction unit branchOperation code 184Number of operands 0Modifier NoModifier range —Latency n/aIssue slots 2, 3, 4
DESCRIPTIONThe iclr operation resets the valid bits of all blocks in the instruction cache.iclr does clear the valid bits of locked blocks. iclr does not change the replacement status of instruction-cache
blocks.iclr ensures coherency between caches and main memory by discarding all pending prefetch operations.The side effect time behavior of iclr is such that if instruction i performs an iclr, instructions i, i+1, i+2 will be
included in the discard from the instruction cache, but i+3 will be retained.The iclr operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
EXAMPLES
Initial Values Operation Result
iclrr10 = 0 IF r10 iclr no change and no stall cycles, since
guard is falser20 = 1 IF r20 iclr
SEE ALSOdcb dinvalid
iclr
TM1100 Preliminary Data Book Philips Semiconductors
A-80 PRELIMINARY INFORMATION File: ops.fm5, modified 7/23/99
Identitypseudo-op for iadd
SYNTAX[ IF r guard ] ident r src1 → r dest
FUNCTIONif rguard then
rdest ← rsrc1
ATTRIBUTESFunction unit aluOperation code 12Number of operands 1Modifier NoModifier range —Latency 1Issue slots 1, 2, 3, 4, 5
DESCRIPTIONThe ident operation is a pseudo operation transformed by the scheduler into an iadd with r0 (always contains 0)
as the first argument and rsrc1 as the second. (Note: pseudo operations cannot be used in assembly source files.)The ident operation copies the argument rsrc1 to rdest. It is used by the instruction scheduler to implement
register to register copying.The ident operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 0x100 ident r30 → r40 r40 ← 0x100
r10 = 0, r50 = 0x12345678 IF r10 ident r50 → r60 no change, since guard is false
Philips Semiconductors DSPCPU Operations for TM1100
File: ops.fm5, modified 7/23/99 PRELIMINARY INFORMATION A-81
Signed compare equal
SYNTAX[ IF r guard ] ieql r src1 r src2 → r dest
FUNCTIONif rguard then
if rsrc1 = rsrc2 thenrdest ← 1
elserdest ← 0
ATTRIBUTESFunction unit aluOperation code 37Number of operands 2Modifier NoModifier range —Latency 1Issue slots 1, 2, 3, 4, 5
DESCRIPTIONThe ieql operation sets the destination register, rdest, to 1 if the first argument, rsrc1, is equal to the second
argument, rsrc2; otherwise, rdest is set to 0. The arguments are treated as signed integers.The ieql operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 3, r40 = 4 ieql r30 r40 → r80 r80 ← 0
r10 = 0, r60 = 0x100, r30 = 3 IF r10 ieql r60 r30 → r50 no change, since guard is false
TM1100 Preliminary Data Book Philips Semiconductors
A-82 PRELIMINARY INFORMATION File: ops.fm5, modified 7/23/99
Signed compare equal with immediate
SYNTAX[ IF r guard ] ieqli( n) r src1 → r dest
FUNCTIONif rguard then
if rsrc1 = n thenrdest ← 1
elserdest ← 0
ATTRIBUTESFunction unit aluOperation code 4Number of operands 1Modifier 7 bitsModifier range –64..63Latency 1Issue slots 1, 2, 3, 4, 5
DESCRIPTIONThe ieqli operation sets the destination register, rdest, to 1 if the first argument, rsrc1, is equal to the opcode
modifier, n; otherwise, rdest is set to 0. The arguments are treated as signed integers.The ieqli operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 3 ieqli(2) r30 → r80 r80 ← 0
r30 = 3 ieqli(3) r30 → r90 r90 ← 1
r30 = 3 ieqli(4) r30 → r100 r100 ← 0
r10 = 0, r40 = 0x100 IF r10 ieqli(63) r40 → r50 no change, since guard is false
ATTRIBUTESFunction unit dspmulOperation code 93Number of operands 2Modifier NoModifier range —Latency 3Issue slots 2, 3
DESCRIPTIONAs shown below, the ifir16 operation computes two separate products of the two pairs of corresponding 16-bit
halfwords of rsrc1 and rsrc2; the two products are summed, and the result is written to rdest. All values are consideredsigned; thus, the intermediate products and the final sum of products are signed. All intermediate computations areperformed without loss of precision; the final sum of products is clipped into the range [0x80000000..0x7fffffff] beforebeing written into rdest.
The ifir16 operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
ATTRIBUTESFunction unit dspmulOperation code 92Number of operands 2Modifier NoModifier range —Latency 3Issue slots 2, 3
DESCRIPTIONAs shown below, the ifir8ii operation computes four separate products of the four pairs of corresponding 8-bit
bytes of rsrc1 and rsrc2; the four products are summed, and the result is written to rdest. All values are consideredsigned; thus, the intermediate products and the final sum of products are signed. All computations are performedwithout loss of precision.
The ifir8ii operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
ATTRIBUTESFunction unit dspmulOperation code 91Number of operands 2Modifier NoModifier range —Latency 3Issue slots 2, 3
DESCRIPTIONAs shown below, the ifir8ui operation computes four separate products of the four pairs of corresponding 8-bit
bytes of rsrc1 and rsrc2; the four products are summed, and the result is written to rdest. The bytes from rsrc1 areconsidered unsigned, but the bytes from rsrc2 are considered signed; thus, the intermediate products and the finalsum of products are signed. All computations are performed without loss of precision.
The ifir8ui operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
unsigned unsigned unsigned unsigned signed signed signed signed
signed
SEE ALSOifir8ii ufir8uu ifir16
ufir16
ifir8ui
TM1100 Preliminary Data Book Philips Semiconductors
A-86 PRELIMINARY INFORMATION File: ops.fm5, modified 7/23/99
Convert floating-point to integer using PCSWrounding mode
SYNTAX[ IF r guard ] ifixieee r src1 → r dest
FUNCTIONif rguard then
rdest ← (long) ((float)rsrc1)
ATTRIBUTESFunction unit faluOperation code 121Number of operands 1Modifier NoModifier range —Latency 3Issue slots 1, 4
DESCRIPTIONThe ifixieee operation converts the single-precision IEEE floating-point value in rsrc1 to a signed integer and
writes the result into rdest. Rounding is according to the IEEE rounding mode bits in PCSW. If rsrc1 is denormalized,zero is substituted before conversion, and the IFZ flag in the PCSW is set. If ifixieee causes an IEEE exception,such as overflow or underflow, the corresponding exception flags in the PCSW are set. The PCSW exception flags aresticky: the flags can be set as a side-effect of any floating-point operation but can only be reset by an explicitwritepcsw operation. The update of the PCSW exception flags occurs at the same time as rdest is written. If anyother floating-point compute operations update the PCSW at the same time, the net result in each exception flag is thelogical OR of all simultaneous updates ORed with the existing PCSW value for that exception flag.
The ifixieeeflags operation computes the exception flags that would result from an individual ifixieee .The ifixieee operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest and the exception flags in PCSW are written;otherwise, rdest is not changed and the operation does not affect the exception flags in PCSW.
r70 = 0xffffffff (QNaN) ifixieee r70 → r120 r120 ← 0, INV flag set
r80 = 0xffbfffff (SNaN) ifixieee r80 → r122 r122 ← 0, INV flag set
SEE ALSOufixieee ifixrz ufixrz
ifixieee
Philips Semiconductors DSPCPU Operations for TM1100
File: ops.fm5, modified 7/23/99 PRELIMINARY INFORMATION A-87
IEEE status flags from convert floating-point to integer using PCSW rounding mode
SYNTAX[ IF r guard ] ifixieeeflags r src1 → r dest
FUNCTIONif rguard then
rdest ← ieee_flags((long) ((float)rsrc1))
ATTRIBUTESFunction unit faluOperation code 122Number of operands 1Modifier NoModifier range —Latency 3Issue slots 1, 4
DESCRIPTIONThe ifixieeeflags operation computes the IEEE exceptions that would result from converting the single-
precision IEEE floating-point value in rsrc1 to a signed integer, and an integer bit vector representing the computedexception flags is written into rdest. The bit vector stored in rdest has the same format as the IEEE exception bits inthe PCSW. The exception flags in PCSW are left unchanged by this operation. Rounding is according to the IEEErounding mode bits in PCSW. If rsrc1 is denormalized, zero is substituted before computing the conversion, and theIFZ bit in the result is set.
The ifixieeeflags operation optionally takes a guard, specified in rguard. If a guard is present, its LSBcontrols the modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is notchanged.
TM1100 Preliminary Data Book Philips Semiconductors
A-88 PRELIMINARY INFORMATION File: ops.fm5, modified 7/23/99
Convert floating-point to integer with roundtoward zero
SYNTAX[ IF r guard ] ifixrz r src1 → r dest
FUNCTIONif rguard then
rdest ← (long) ((float)rsrc1)
ATTRIBUTESFunction unit faluOperation code 21Number of operands 1Modifier NoModifier range —Latency 3Issue slots 1, 4
DESCRIPTIONThe ifixrz operation converts the single-precision IEEE floating-point value in rsrc1 to a signed integer and
writes the result into rdest. Rounding toward zero is performed; the IEEE rounding mode bits in PCSW are ignored.This is the preferred rounding for ANSI C. If rsrc1 is denormalized, zero is substituted before conversion, and the IFZflag in the PCSW is set. If ifixrz causes an IEEE exception, such as overflow or underflow, the correspondingexception flags in the PCSW are set. The PCSW exception flags are sticky: the flags can be set as a side-effect of anyfloating-point operation but can only be reset by an explicit writepcsw operation. The update of the PCSWexception flags occurs at the same time as rdest is written. If any other floating-point compute operations update thePCSW at the same time, the net result in each exception flag is the logical OR of all simultaneous updates ORed withthe existing PCSW value for that exception flag.
The ifixrzflags operation computes the exception flags that would result from an individual ifixrz .The ifixrz operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest and the exception flags in PCSW are written;otherwise, rdest is not changed and the operation does not affect the exception flags in PCSW.
EXAMPLES
Initial Values Operation Result
r30 = 0x40400000 (3.0) ifixrz r30 → r100 r100 ← 3
r35 = 0x40247ae1 (2.57) ifixrz r35 → r102 r102 ← 2, INX flag set
r10 = 0,r40 = 0xff4fffff (–3.402823466e+38)
IF r10 ifixrz r40 → r105 no change, since guard is false
r20 = 1,r40 = 0xff4fffff (–3.402823466e+38)
IF r20 ifixrz r40 → r110 r110 ← 0x80000000 (-231), INV flag set
r45 = 0x7f800000 (+INF)) ifixrz r45 → r112 r112 ← 0x7fffffff (231-1), INV flag setr50 = 0xbfc147ae (-1.51) ifixrz r50 → r115 r115 ← -1, INX flag set
r70 = 0xffffffff (QNaN) ifixrz r70 → r120 r120 ← 0, INV flag set
r80 = 0xffbfffff (SNaN) ifixrz r80 → r122 r122 ← 0, INV flag set
SEE ALSOifixieee ufixieee ufixrz
ifixrz
Philips Semiconductors DSPCPU Operations for TM1100
File: ops.fm5, modified 7/23/99 PRELIMINARY INFORMATION A-89
IEEE status flags from convert floating-point to integer with round toward zero
SYNTAX[ IF r guard ] ifixrzflags r src1 → r dest
FUNCTIONif rguard then
rdest ← ieee_flags((long) ((float)rsrc1))
ATTRIBUTESFunction unit faluOperation code 129Number of operands 1Modifier NoModifier range —Latency 3Issue slots 1, 4
DESCRIPTIONThe ifixrzflags operation computes the IEEE exceptions that would result from converting the single-precision
IEEE floating-point value in rsrc1 to a signed integer, and an integer bit vector representing the computed exceptionflags is written into rdest. The bit vector stored in rdest has the same format as the IEEE exception bits in the PCSW.The exception flags in PCSW are left unchanged by this operation. Rounding toward zero is performed; the IEEErounding mode bits in PCSW are ignored. If rsrc1 is denormalized, zero is substituted before computing theconversion, and the IFZ bit in the result is set.
The ifixrzflags operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controlsthe modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
TM1100 Preliminary Data Book Philips Semiconductors
A-90 PRELIMINARY INFORMATION File: ops.fm5, modified 7/23/99
If non-zero negate
SYNTAX[ IF r guard ] iflip r src1 r src2 → r dest
FUNCTIONif rguard then
if rsrc1 = 0 thenrdest ← rsrc2
elserdest ← –rsrc2
ATTRIBUTESFunction unit dspaluOperation code 77Number of operands 2Modifier NoModifier range —Latency 2Issue slots 1, 3
DESCRIPTIONThe iflip operation copies rsrc2 to rdest if rsrc1 = 0; otherwise (if rsrc1 != 0), rdest is set to the two’s-complement
of rsrc2. All values are signed integers.The iflip operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 0, r40 = 1 iflip r30 r40 → r50 r50 ← 0x1
r10 = 0, r60 = 0xffff0000, r70 = 0xabc IF r10 iflip r60 r70 → r80 no change, since guard is false
Philips Semiconductors DSPCPU Operations for TM1100
File: ops.fm5, modified 7/23/99 PRELIMINARY INFORMATION A-91
Convert signed integer to floating-point
SYNTAX[ IF r guard ] ifloat r src1 → r dest
FUNCTIONif rguard then
rdest ← (float) ((long)rsrc1)
ATTRIBUTESFunction unit faluOperation code 20Number of operands 1Modifier NoModifier range —Latency 3Issue slots 1, 4
DESCRIPTIONThe ifloat operation converts the signed integer value in rsrc1 to single-precision IEEE floating-point format and
writes the result into rdest. Rounding is according to the IEEE rounding mode bits in PCSW. If ifloat causes anIEEE exception, such as inexact, the corresponding exception flags in the PCSW are set. The PCSW exception flagsare sticky: the flags can be set as a side-effect of any floating-point operation but can only be reset by an explicitwritepcsw operation. The update of the PCSW exception flags occurs at the same time as rdest is written. If anyother floating-point compute operations update the PCSW at the same time, the net result in each exception flag is thelogical OR of all simultaneous updates ORed with the existing PCSW value for that exception flag.
The ifloatflags operation computes the exception flags that would result from an individual ifloat .The ifloat operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest and the exception flags in PCSW are written;otherwise, rdest is not changed and the operation does not affect the exception flags in PCSW.
r80 = 0x7ffffff1 (2147483633) ifloat r80 → r122 r122 ← 0x4f000000 (2.147483648e+9), INX flag set
SEE ALSOufloat ifloatrz ufloatrz
ifixieee ifloatflags
ifloat
TM1100 Preliminary Data Book Philips Semiconductors
A-92 PRELIMINARY INFORMATION File: ops.fm5, modified 7/23/99
IEEE status flags from convert signed integer tofloating-point
SYNTAX[ IF r guard ] ifloatflags r src1 → r dest
FUNCTIONif rguard then
rdest ← ieee_flags((float) ((long)rsrc1))
ATTRIBUTESFunction unit faluOperation code 130Number of operands 1Modifier NoModifier range —Latency 3Issue slots 1, 4
DESCRIPTIONThe ifloatflags operation computes the IEEE exceptions that would result from converting the signed integer
in rsrc1 to a single-precision IEEE floating-point value, and an integer bit vector representing the computed exceptionflags is written into rdest. The bit vector stored in rdest has the same format as the IEEE exception bits in the PCSW.The exception flags in PCSW are left unchanged by this operation. Rounding is according to the IEEE rounding modebits in PCSW.
The ifloatflags operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controlsthe modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
Philips Semiconductors DSPCPU Operations for TM1100
File: ops.fm5, modified 7/23/99 PRELIMINARY INFORMATION A-93
Convert signed integer to floating-point with rounding toward zero
SYNTAX[ IF r guard ] ifloatrz r src1 → r dest
FUNCTIONif rguard then
rdest ← (float) ((long)rsrc1)
ATTRIBUTESFunction unit faluOperation code 117Number of operands 1Modifier NoModifier range —Latency 3Issue slots 1, 4
DESCRIPTIONThe ifloatrz operation converts the signed integer value in rsrc1 to single-precision IEEE floating-point format
and writes the result into rdest. Rounding is performed toward zero; the IEEE rounding mode bits in PCSW areignored. This is the preferred rounding mode for ANSI C. If ifloatrz causes an IEEE exception, such as inexact,the corresponding exception flags in the PCSW are set. The PCSW exception flags are sticky: the flags can be set asa side-effect of any floating-point operation but can only be reset by an explicit writepcsw operation. The update ofthe PCSW exception flags occurs at the same time as rdest is written. If any other floating-point compute operationsupdate the PCSW at the same time, the net result in each exception flag is the logical OR of all simultaneous updatesORed with the existing PCSW value for that exception flag.
The ifloatrzflags operation computes the exception flags that would result from an individual ifloatrz .The ifloatrz operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest and the exception flags in PCSW are written;otherwise, rdest is not changed and the operation does not affect the exception flags in PCSW.
r80 = 0x7ffffff1 (2147483633) ifloatrz r80 → r122 r122 ← 0x4effffff (2.147483520e+9), INX flag set
SEE ALSOifloat ufloatrz ifixieee
ifloatflags
ifloatrz
TM1100 Preliminary Data Book Philips Semiconductors
A-94 PRELIMINARY INFORMATION File: ops.fm5, modified 7/23/99
IEEE status flags from convert signed integer tofloating-point with rounding toward zero
SYNTAX[ IF r guard ] ifloatrzflags r src1 → r dest
FUNCTIONif rguard then
rdest ← ieee_flags((float) ((long)rsrc1))
ATTRIBUTESFunction unit faluOperation code 118Number of operands 1Modifier NoModifier range —Latency 3Issue slots 1, 4
DESCRIPTIONThe ifloatrzflags operation computes the IEEE exceptions that would result from converting the signed
integer in rsrc1 to a single-precision IEEE floating-point value, and an integer bit vector representing the computedexception flags is written into rdest. The bit vector stored in rdest has the same format as the IEEE exception bits inthe PCSW. The exception flags in PCSW are left unchanged by this operation. Rounding is performed toward zero;the IEEE rounding mode bits in PCSW are ignored.
The ifloatrzflags operation optionally takes a guard, specified in rguard. If a guard is present, its LSBcontrols the modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is notchanged.
Philips Semiconductors DSPCPU Operations for TM1100
File: ops.fm5, modified 7/23/99 PRELIMINARY INFORMATION A-95
Signed compare greater or equal
SYNTAX[ IF r guard ] igeq r src1 r src2 → r dest
FUNCTIONif rguard then
if rsrc1 >= rsrc2 thenrdest ← 1
elserdest ← 0
ATTRIBUTESFunction unit aluOperation code 14Number of operands 2Modifier NoModifier range —Latency 1Issue slots 1, 2, 3, 4, 5
DESCRIPTIONThe igeq operation sets the destination register, rdest, to 1 if the first argument, rsrc1, is greater than or equal to
the second argument, rsrc2; otherwise, rdest is set to 0. The arguments are treated as signed integers.The igeq operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 3, r40 = 4 igeq r30 r40 → r80 r80 ← 0
r10 = 0, r60 = 0x100, r30 = 3 IF r10 igeq r60 r30 → r50 no change, since guard is false
TM1100 Preliminary Data Book Philips Semiconductors
A-96 PRELIMINARY INFORMATION File: ops.fm5, modified 7/23/99
Signed compare greater or equal with immediate
SYNTAX[ IF r guard ] igeqi( n) r src1 → r dest
FUNCTIONif rguard then
if rsrc1 >= n thenrdest ← 1
elserdest ← 0
ATTRIBUTESFunction unit aluOperation code 1Number of operands 1Modifier 7 bitsModifier range –64..63Latency 1Issue slots 1, 2, 3, 4, 5
DESCRIPTIONThe igeqi operation sets the destination register, rdest, to 1 if the first argument, rsrc1, is greater than or equal to
the opcode modifier, n; otherwise, rdest is set to 0. The arguments are treated as signed integers.The igeqi operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 3 igeqi(2) r30 → r80 r80 ← 1
r30 = 3 igeqi(3) r30 → r90 r90 ← 1
r30 = 3 igeqi(4) r30 → r100 r100 ← 0
r10 = 0, r40 = 0x100 IF r10 igeqi(63) r40 → r50 no change, since guard is false
Philips Semiconductors DSPCPU Operations for TM1100
File: ops.fm5, modified 7/23/99 PRELIMINARY INFORMATION A-97
Signed compare greater
SYNTAX[ IF r guard ] igtr r src1 r src2 → r dest
FUNCTIONif rguard then
if rsrc1 > rsrc2 thenrdest ← 1
elserdest ← 0
ATTRIBUTESFunction unit aluOperation code 15Number of operands 2Modifier NoModifier range —Latency 1Issue slots 1, 2, 3, 4, 5
DESCRIPTIONThe igtr operation sets the destination register, rdest, to 1 if the first argument, rsrc1, is greater than the second
argument, rsrc2; otherwise, rdest is set to 0. The arguments are treated as signed integers.The igtr operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 3, r40 = 4 igtr r30 r40 → r80 r80 ← 0
r10 = 0, r60 = 0x100, r30 = 3 IF r10 igtr r60 r30 → r50 no change, since guard is false
TM1100 Preliminary Data Book Philips Semiconductors
A-98 PRELIMINARY INFORMATION File: ops.fm5, modified 7/23/99
Signed compare greater with immediate
SYNTAX[ IF r guard ] igtri( n) r src1 → r dest
FUNCTIONif rguard then
if rsrc1 > n thenrdest ← 1
elserdest ← 0
ATTRIBUTESFunction unit aluOperation code 0Number of operands 1Modifier 7 bitsModifier range –64..63Latency 1Issue slots 1, 2, 3, 4, 5
DESCRIPTIONThe igtri operation sets the destination register, rdest, to 1 if the first argument, rsrc1, is greater than the opcode
modifier, n; otherwise, rdest is set to 0. The arguments are treated as signed integers.The igtri operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 3 igtri(2) r30 → r80 r80 ← 1
r30 = 3 igtri(3) r30 → r90 r90 ← 0
r30 = 3 igtri(4) r30 → r100 r100 ← 0
r10 = 0, r40 = 0x100 IF r10 igtri(63) r40 → r50 no change, since guard is false
Philips Semiconductors DSPCPU Operations for TM1100
File: ops.fm5, modified 7/23/99 PRELIMINARY INFORMATION A-99
Signed immediate
SYNTAXiimm( n) → r dest
FUNCTIONrdest ← n
ATTRIBUTESFunction unit constOperation code 191Number of operands 0Modifier 32 bitsModifier range 0x80000000
..0x7fffffffLatency 1Issue slots 1, 2, 3, 4, 5
DESCRIPTIONThe iimm operation stores the signed 32-bit opcode modifier n into rdest. Note: this operation is not guarded.
EXAMPLES
Initial Values Operation Result
iimm(2) → r10 r10 ← 2
iimm(0x100) → r20 r20 ← 0x100
iimm(0xfffc0000) → r30 r30 ← 0xfffc0000
SEE ALSOuimm
iimm
TM1100 Preliminary Data Book Philips Semiconductors
A-100 PRELIMINARY INFORMATION File: ops.fm5, modified 7/23/99
Interruptible indirect jump on false
SYNTAX[ IF r guard ] ijmpf r src1 r src2
FUNCTIONif rguard then
if (rsrc1 & 1) = 0 then DPC ← rsrc2if exception is pending then
service exceptionelseif interrupt is pending then
service interruptselse
PC, SPC ← rsrc2
ATTRIBUTESFunction unit branchOperation code 181Number of operands 2Modifier noModifier range —Delay 3Issue slots 2, 3, 4
DESCRIPTIONThe ijmpf operation conditionally changes the program flow and allows pending interrupts or exceptions to be
serviced. If neither interrupts or exceptions are pending and the LSB of rsrc1 is 0, the DPC, PC, and SPC registers areset equal to rsrc2. If an interrupt or exception is pending and the LSB of rsrc1 is 0, DPC is set equal to rsrc2 and theservice routine is invoked, where exceptions have priorities over interrupts. If the LSB of rsrc1 is 1, program executioncontinues with the next sequential instruction.
The ijmpf operation optionally takes a guard, specified in rguard. If a guard is present, its LSB adds anothercondition to the jump. If the LSB of rguard is 1, the instruction executes as previously described; otherwise, the jumpwill not be taken and PC, DPC, and SPC are not modified regardless of the value of rsrc1.
EXAMPLES
Initial Values Operation Result
r50 = 0, r70 = 0x330 ijmpf r50 r70 program execution continues at 0x330 after first servicing pending interrupts
r20 = 1, r70 = 0x330 ijmpf r20 r70 since r20 is true, program execution contin-ues with next sequential instruction
r30 = 0, r50 = 0, r60 = 0x8000 IF r30 ijmpf r50 r60 since guard is false, program execution con-tinues with next sequential instruction
r40 = 1, r50 = 0, r60 = 0x8000 IF r40 ijmpf r50 r60 program execution continues at 0x8000 after first servicing pending interrupts
SEE ALSOjmpf jmpt jmpi ijmpt ijmpi
ijmpf
Philips Semiconductors DSPCPU Operations for TM1100
File: ops.fm5, modified 7/23/99 PRELIMINARY INFORMATION A-101
Interruptible jump immediate
SYNTAX[ IF r guard ] ijmpi (address )
FUNCTIONif rguard then
DPC ← addressif exception is pending then
service exceptionelse if interrupt is pending then
service interruptselse
PC, SPC ← address
ATTRIBUTESFunction unit branchOperation code 179Number of operands 0Modifier 32 bitsModifier range 0..0xffffffffDelay 3Issue slots 2, 3, 4
DESCRIPTIONThe ijmpi operation changes the program flow and allows pending interrupts or exceptions to be serviced. If no
interrupts or exceptions are pending, the DPC, PC, and SPC registers are set equal to address. If an exception orinterrupts is pending, DPC is set equal to address and a service routine is invoked, where exceptions have prioritiesover interrupts. address is an immediate opcode modifier.
The ijmpi operation optionally takes a guard, specified in rguard. If a guard is present, its LSB adds a condition tothe jump. If the LSB of rguard is 1, the instruction executes as previously described; otherwise, the jump will not betaken and PC, DPC, and SPC are not modified.
EXAMPLES
Initial Values Operation Result
ijmpi(0x330) program execution continues at 0x330
r30 = 0 IF r30 ijmpi(0x8000) since guard is false, program execution con-tinues with next sequential instruction
r40 = 1 IF r40 ijmpi(0x8000) program execution continues at 0x8000
SEE ALSOjmpf jmpt jmpi ijmpf ijmpt
ijmpi
TM1100 Preliminary Data Book Philips Semiconductors
A-102 PRELIMINARY INFORMATION File: ops.fm5, modified 7/23/99
Interruptible indirect jump on true
SYNTAX[ IF r guard ] ijmpt r src1 r src2
FUNCTIONif rguard then
if (rsrc1 & 1) = 1 then DPC ← rsrc2if exception is pending then
service exceptionelseif interrupt is pending then
service interruptselse
PC, SPC ← rsrc2
ATTRIBUTESFunction unit branchOperation code 177Number of operands 2Modifier noModifier range —Delay 3Issue slots 2, 3, 4
DESCRIPTIONThe ijmpt operation conditionally changes the program flow and allows pending interrupts or exceptions to be
serviced. If no interrupts or exceptions are pending and the LSB of rsrc1 is 1, the DPC, PC, and SPC registers are setequal to rsrc2. If an exception or interrupt is pending and the LSB of rsrc1 is 1, DPC is set equal to rsrc2 and a serviceroutine is invoked, where exceptions have priority over interrupts. If the LSB of rsrc1 is 0, program execution continueswith the next sequential instruction.
The ijmpt operation optionally takes a guard, specified in rguard. If a guard is present, its LSB adds anothercondition to the jump. If the LSB of rguard is 1, the instruction executes as previously described; otherwise, the jumpwill not be taken and PC, DPC, and SPC are not modified regardless of the value of rsrc1.
EXAMPLES
Initial Values Operation Result
r50 = 1, r70 = 0x330 ijmpt r50 r70 program execution continues at 0x330 after first servicing pending interrupts
r20 = 0, r70 = 0x330 ijmpt r20 r70 since r20 is false, program execution contin-ues with next sequential instruction
r30 = 0, r50 = 1, r60 = 0x8000 IF r30 ijmpt r50 r60 since guard is false, program execution con-tinues with next sequential instruction
r40 = 1, r50 = 1, r60 = 0x8000 IF r40 ijmpt r50 r60 program execution continues at 0x8000 after first servicing pending interrupts
SEE ALSOjmpf jmpt jmpi ijmpf ijmpi
ijmpt
Philips Semiconductors DSPCPU Operations for TM1100
File: ops.fm5, modified 7/23/99 PRELIMINARY INFORMATION A-103
ATTRIBUTESFunction unit dmemOperation code 6Number of operands 1Modifier NoModifier range —Latency 3Issue slots 4, 5
DESCRIPTIONThe ild16 operation is a pseudo operation transformed by the scheduler into an ild16d(0) with the same
argument. (Note: pseudo operations cannot be used in assembly source files.)The ild16 operation loads the 16-bit memory value from the address contained in rsrc1, sign extends it to 32 bits,
and stores the result in rdest. If the memory address contained in rsrc1 is not a multiple of 2, the result of ild16 isundefined but no exception will be raised. This load operation is performed as little-endian or big-endian depending onthe current setting of the bytesex bit in the PCSW.
The result of an access by ild16 to the MMIO address aperture is undefined; access to the MMIO aperture isdefined only for 32-bit loads and stores.
The ild16 operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register and the occurrence of side effects. If the LSB of rguard is 1, rdest is written andthe data cache status bits are updated if the addressed locations are cacheable. if the LSB of rguard is 0, rdest is notchanged and ild16 has no side effects whatever.
r50 = 0xd01 ild16 r50 → r90 r90 undefined, since 0xd01 is not a multiple of 2
SEE ALSOild16d ild16r ild16x
ild16
TM1100 Preliminary Data Book Philips Semiconductors
A-104 PRELIMINARY INFORMATION File: ops.fm5, modified 7/23/99
Signed 16-bit load with displacement
SYNTAX[ IF r guard ] ild16d( d) r src1 → r dest
FUNCTIONif rguard then
if PCSW.bytesex = LITTLE_ENDIAN then bs ← 1
else bs ← 0
temp<7:0> ← mem[(rsrc1 + d + (1 ⊕ bs)]temp<15:8> ← mem[(rsrc1 + d + (0 ⊕ bs)]rdest ← sign_ext16to32(temp<15:0>)
ATTRIBUTESFunction unit dmemOperation code 6Number of operands 1Modifier 7 bitsModifier range –128..126 by 2Latency 3Issue slots 4, 5
DESCRIPTIONThe ild16d operation loads the 16-bit memory value from the address computed by rsrc1 + d, sign extends it to 32
bits, and stores the result in rdest. The d value is an opcode modifier, must be in the range –128 to 126 inclusive, andmust be a multiple of 2. If the memory address computed by rsrc1 + d is not a multiple of 2, the result of ild16d isundefined but no exception will be raised. This load operation is performed as little-endian or big-endian depending onthe current setting of the bytesex bit in the PCSW.
The result of an access by ild16d to the MMIO address aperture is undefined; access to the MMIO aperture isdefined only for 32-bit loads and stores.
The ild16d operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register and the occurrence of side effects. If the LSB of rguard is 1, rdest is written andthe data cache status bits are updated if the addressed locations are cacheable. if the LSB of rguard is 0, rdest is notchanged and ild16d has no side effects whatever.
ATTRIBUTESFunction unit dmemOperation code 195Number of operands 2Modifier NoModifier range —Latency 3Issue slots 4, 5
DESCRIPTIONThe ild16r operation loads the 16-bit memory value from the address computed by rsrc1 + rsrc2, sign extends it
to 32 bits, and stores the result in rdest. If the memory address computed by rsrc1 + rsrc2 is not a multiple of 2, theresult of ild16r is undefined but no exception will be raised. This load operation is performed as little-endian or big-endian depending on the current setting of the bytesex bit in the PCSW.
The result of an access by ild16r to the MMIO address aperture is undefined; access to the MMIO aperture isdefined only for 32-bit loads and stores.
The ild16r operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register and the occurrence of side effects. If the LSB of rguard is 1, rdest is written andthe data cache status bits are updated if the addressed locations are cacheable. if the LSB of rguard is 0, rdest is notchanged and ild16r has no side effects whatever.
ATTRIBUTESFunction unit dmemOperation code 196Number of operands 2Modifier NoModifier range —Latency 3Issue slots 4, 5
DESCRIPTIONThe ild16x operation loads the 16-bit memory value from the address computed by rsrc1 + 2×rsrc2, sign extends
it to 32 bits, and stores the result in rdest. If the memory address computed by rsrc1 + 2×rsrc2 is not a multiple of 2,the result of ild16x is undefined but no exception will be raised. This load operation is performed as little-endian orbig-endian depending on the current setting of the bytesex bit in the PCSW.
The result of an access by ild16x to the MMIO address aperture is undefined; access to the MMIO aperture isdefined only for 32-bit loads and stores.
The ild16x operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register and the occurrence of side effects. If the LSB of rguard is 1, rdest is written andthe data cache status bits are updated if the addressed locations are cacheable. if the LSB of rguard is 0, rdest is notchanged and ild16x has no side effects whatever.
r70 = 0xd01, r30 = 1 ild16x r70 r30 → r110 r110 undefined, since 0xd01 + 2×1 is not a multiple of 2
SEE ALSOild16 uld16 ild16d uld16d
ild16r uld16r uld16x
ild16x
Philips Semiconductors DSPCPU Operations for TM1100
File: ops.fm5, modified 7/23/99 PRELIMINARY INFORMATION A-107
Signed 8-bit loadpseudo-op for ild8d(0)
SYNTAX[ IF r guard ] ild8 r src1 → r dest
FUNCTIONif rguard then
rdest ← sign_ext8to32(mem[rsrc1])
ATTRIBUTESFunction unit dmemOperation code 192Number of operands 1Modifier NoModifier range —Latency 3Issue slots 4, 5
DESCRIPTIONThe ild8 operation is a pseudo operation transformed by the scheduler into an ild8d(0) with the same
argument. (Note: pseudo operations cannot be used in assembly source files.)The ild8 operation loads the 8-bit memory value from the address contained in rsrc1, sign extends it to 32 bits,
and stores the result in rdest. This operation does not depend on the bytesex bit in the PCSW since only a single byteis loaded.
The result of an access by ild8 to the MMIO address aperture is undefined; access to the MMIO aperture isdefined only for 32-bit loads and stores.
The ild8 operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register and the occurrence of side effects. If the LSB of rguard is 1, rdest is written andthe data cache status bits are updated if the addressed location is cacheable. if the LSB of rguard is 0, rdest is notchanged and ild8 has no side effects whatever.
TM1100 Preliminary Data Book Philips Semiconductors
A-108 PRELIMINARY INFORMATION File: ops.fm5, modified 7/23/99
Signed 8-bit load with displacement
SYNTAX[ IF r guard ] ild8d( d) r src1 → r dest
FUNCTIONif rguard then
rdest ← sign_ext8to32(mem[rsrc1 + d])
ATTRIBUTESFunction unit dmemOperation code 192Number of operands 1Modifier 7 bitsModifier range –64..63Latency 3Issue slots 4, 5
DESCRIPTIONThe ild8d operation loads the 8-bit memory value from the address computed by rsrc1 + d, sign extends it to 32
bits, and stores the result in rdest. The d value is an opcode modifier in the range -64 to 63, inclusive. This operationdoes not depend on the bytesex bit in the PCSW since only a single byte is loaded.
The result of an access by ild8d to the MMIO address aperture is undefined; access to the MMIO aperture isdefined only for 32-bit loads and stores.
The ild8d operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register and the occurrence of side effects. If the LSB of rguard is 1, rdest is written andthe data cache status bits are updated if the addressed location is cacheable. if the LSB of rguard is 0, rdest is notchanged and ild8d has no side effects whatever.
Philips Semiconductors DSPCPU Operations for TM1100
File: ops.fm5, modified 7/23/99 PRELIMINARY INFORMATION A-109
Signed 8-bit load with index
SYNTAX[ IF r guard ] ild8r r src1 r src2 → r dest
FUNCTIONif rguard then
rdest ← sign_ext8to32(mem[rsrc1 + rsrc2])
ATTRIBUTESFunction unit dmemOperation code 193Number of operands 2Modifier NoModifier range —Latency 3Issue slots 4, 5
DESCRIPTIONThe ild8r operation loads the 8-bit memory value from the address computed by rsrc1 + rsrc2, sign extends it to
32 bits, and stores the result in rdest. This operation does not depend on the bytesex bit in the PCSW since only asingle byte is loaded.
The result of an access by ild8r to the MMIO address aperture is undefined; access to the MMIO aperture isdefined only for 32-bit loads and stores.
The ild8r operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register and the occurrence of side effects. If the LSB of rguard is 1, rdest is written andthe data cache status bits are updated if the addressed location is cacheable. if the LSB of rguard is 0, rdest is notchanged and ild8r has no side effects whatever.
TM1100 Preliminary Data Book Philips Semiconductors
A-110 PRELIMINARY INFORMATION File: ops.fm5, modified 7/23/99
Signed compare less or equalpseudo-op for igeq
SYNTAX[ IF r guard ] ileq r src1 r src2 → r dest
FUNCTIONif rguard then
if rsrc1 <= rsrc2 thenrdest ← 1
elserdest ← 0
ATTRIBUTESFunction unit aluOperation code 14Number of operands 2Modifier NoModifier range —Latency 1Issue slots 1, 2, 3, 4, 5
DESCRIPTIONThe ileq operation is a pseudo operation transformed by the scheduler into an igeq with the arguments
exchanged (ileq ’s rsrc1 is igeq ’s rsrc2 and vice versa). (Note: pseudo operations cannot be used in assemblysource files.)
The ileq operation sets the destination register, rdest, to 1 if the first argument, rsrc1, is less than or equal to thesecond argument, rsrc2; otherwise, rdest is set to 0. The arguments are treated as signed integers.
The ileq operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 3, r40 = 4 ileq r30 r40 → r80 r80 ← 1
r10 = 0, r60 = 0x100, r30 = 3 IF r10 ileq r60 r30 → r50 no change, since guard is false
Philips Semiconductors DSPCPU Operations for TM1100
File: ops.fm5, modified 7/23/99 PRELIMINARY INFORMATION A-111
Signed compare less or equal with immediate
SYNTAX[ IF r guard ] ileqi( n) r src1 → r dest
FUNCTIONif rguard then
if rsrc1 <= n thenrdest ← 1
elserdest ← 0
ATTRIBUTESFunction unit aluOperation code 42Number of operands 1Modifier 7 bitsModifier range –64..63Latency 1Issue slots 1, 2, 3, 4, 5
DESCRIPTIONThe ileqi operation sets the destination register, rdest, to 1 if the first argument, rsrc1, is less than or equal to the
opcode modifier, n; otherwise, rdest is set to 0. The arguments are treated as signed integers.The ileqi operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 3 ileqi(2) r30 → r80 r80 ← 0
r30 = 3 ileqi(3) r30 → r90 r90 ← 1
r30 = 3 ileqi(4) r30 → r100 r100 ← 1
r10 = 0, r40 = 0x100 IF r10 ileqi(63) r40 → r50 no change, since guard is false
TM1100 Preliminary Data Book Philips Semiconductors
A-112 PRELIMINARY INFORMATION File: ops.fm5, modified 7/23/99
Signed compare lesspseudo-op for igtr
SYNTAX[ IF r guard ] iles r src1 r src2 → r dest
FUNCTIONif rguard then
if rsrc1 < rsrc2 thenrdest ← 1
elserdest ← 0
ATTRIBUTESFunction unit aluOperation code 15Number of operands 2Modifier NoModifier range —Latency 1Issue slots 1, 2, 3, 4, 5
DESCRIPTIONThe iles operation is a pseudo operation transformed by the scheduler into an igtr with the arguments
exchanged (iles ’s rsrc1 is igtr ’s rsrc2 and vice versa). (Note: pseudo operations cannot be used in assemblysource files.)
The iles operation sets the destination register, rdest, to 1 if the first argument, rsrc1, is less than the secondargument, rsrc2; otherwise, rdest is set to 0. The arguments are treated as signed integers.
The iles operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 3, r40 = 4 iles r30 r40 → r80 r80 ← 1
r10 = 0, r60 = 0x100, r30 = 3 IF r10 iles r60 r30 → r50 no change, since guard is false
Philips Semiconductors DSPCPU Operations for TM1100
File: ops.fm5, modified 7/23/99 PRELIMINARY INFORMATION A-113
Signed compare less with immediate
SYNTAX[ IF r guard ] ilesi( n) r src1 → r dest
FUNCTIONif rguard then
if rsrc1 < n thenrdest ← 1
elserdest ← 0
ATTRIBUTESFunction unit aluOperation code 2Number of operands 1Modifier 7 bitsModifier range –64..63Latency 1Issue slots 1, 2, 3, 4, 5
DESCRIPTIONThe ilesi operation sets the destination register, rdest, to 1 if the first argument, rsrc1, is less than the opcode
modifier, n; otherwise, rdest is set to 0. The arguments are treated as signed integers.The ilesi operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 3 ilesi(2) r30 → r80 r80 ← 0
r30 = 3 ilesi(3) r30 → r90 r90 ← 0
r30 = 3 ilesi(4) r30 → r100 r100 ← 1
r10 = 0, r40 = 0x100 IF r10 ilesi(63) r40 → r50 no change, since guard is false
TM1100 Preliminary Data Book Philips Semiconductors
A-114 PRELIMINARY INFORMATION File: ops.fm5, modified 7/23/99
Signed maximum
SYNTAX[ IF r guard ] imax r src1 r src2 → r dest
FUNCTIONif rguard then
if rsrc1 > rsrc2 thenrdest ← rsrc1
elserdest ← rsrc2
ATTRIBUTESFunction unit dspaluOperation code 24Number of operands 2Modifier NoModifier range —Latency 2Issue slots 1, 3
DESCRIPTIONThe imax operation sets the destination register, rdest, to the contents of rsrc1 if rsrc1>rsrc2; otherwise, rdest is set
to the contents of rsrc2. The arguments are treated as signed integers.The imax operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 2, r20 = 1 imax r30 r20 → r80 r80 ← 2
r10 = 0, r60 = 0x100, r30 = 2 IF r10 imax r60 r30 → r50 no change, since guard is false
Philips Semiconductors DSPCPU Operations for TM1100
File: ops.fm5, modified 7/23/99 PRELIMINARY INFORMATION A-115
Signed minimum
SYNTAX[ IF r guard ] imin r src1 r src2 → r dest
FUNCTIONif rguard then
if rsrc1 > rsrc2 thenrdest ← rsrc2
elserdest ← rsrc1
ATTRIBUTESFunction unit dspaluOperation code 23Number of operands 2Modifier NoModifier range —Latency 2Issue slots 1, 3
DESCRIPTIONThe imin operation sets the destination register, rdest, to the contents of rsrc2 if rsrc1>rsrc2; otherwise, rdest is set
to the contents of rsrc1. The arguments are treated as signed integers.The imin operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 2, r20 = 1 imin r30 r20 → r80 r80 ← 1
r10 = 0, r60 = 0x100, r30 = 2 IF r10 imin r60 r30 → r50 no change, since guard is false
ATTRIBUTESFunction unit ifmulOperation code 27Number of operands 2Modifier NoModifier range —Latency 3Issue slots 2, 3
DESCRIPTIONAs shown below, the imul operation computes the product rsrc1×rsrc2 and writes the least-significant 32 bits of the
full 64-bit product into rdest. The operands are considered signed integers. No overflow or underflow detection isperformed.
The imul operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r60 = 0x100 imul r60 r60 → r80 r80 ← 0x10000
r10 = 0, r60 = 0x100, r30 = 0xf11 IF r10 imul r60 r30 → r50 no change, since guard is false
ATTRIBUTESFunction unit ifmulOperation code 139Number of operands 2Modifier NoModifier range —Latency 3Issue slots 2, 3
DESCRIPTIONAs shown below, the imulm operation computes the product rsrc1×rsrc2 and writes the most-significant 32 bits of
the full 64-bit product into rdest. The operands are considered signed integers.
The imulm operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
TM1100 Preliminary Data Book Philips Semiconductors
A-118 PRELIMINARY INFORMATION File: ops.fm5, modified 7/23/99
Signed negatepseudo-op for isub
SYNTAX[ IF r guard ] ineg r src1 → r dest
FUNCTIONif rguard then
rdest ← –rsrc1
ATTRIBUTESFunction unit aluOperation code 13Number of operands 1Modifier NoModifier range —Latency 1Issue slots 1, 2, 3, 4, 5
DESCRIPTIONThe ineg operation is a pseudo operation transformed by the scheduler into an isub with r0 (always contains 0)
as the first argument and rsrc1 as the second argument. (Note: pseudo operations cannot be used in assemblysource files.)
The ineg operation computes the negative of rsrc1 and writes the result into rdest. The argument is a signedinteger; the result is an unsigned integer. If rsrc1 = 0x80000000, then ineg returns 0x80000000 since the positivevalue is not representable.
The ineg operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 0xffffffff ineg r30 → r60 r60 ← 0x00000001
r10 = 0, r40 = 0xfffffff4 IF r10 ineg r40 → r80 no change, since guard is false
TM1100 Preliminary Data Book Philips Semiconductors
A-120 PRELIMINARY INFORMATION File: ops.fm5, modified 7/23/99
Signed compare not equal with immediate
SYNTAX[ IF r guard ] ineqi( n) r src1 → r dest
FUNCTIONif rguard then
if rsrc1 != n thenrdest ← 1
elserdest ← 0
ATTRIBUTESFunction unit aluOperation code 3Number of operands 1Modifier 7 bitsModifier range –64..63Latency 1Issue slots 1, 2, 3, 4, 5
DESCRIPTIONThe ineqi operation sets the destination register, rdest, to 1 if the first argument, rsrc1, is not equal to the opcode
modifier, n; otherwise, rdest is set to 0. The arguments are treated as signed integers.The ineqi operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 3 ineqi(2) r30 → r80 r80 ← 1
r30 = 3 ineqi(3) r30 → r90 r90 ← 0
r30 = 3 ineqi(4) r30 → r100 r100 ← 1
r10 = 0, r40 = 0x100 IF r10 ineqi(63) r40 → r50 no change, since guard is false
Philips Semiconductors DSPCPU Operations for TM1100
File: ops.fm5, modified 7/23/99 PRELIMINARY INFORMATION A-121
If nonzero select zero
SYNTAX[ IF r guard ] inonzero r src1 r src2 → r dest
FUNCTIONif rguard then
if rsrc1 != 0 thenrdest ← 0
elserdest ← rsrc2
ATTRIBUTESFunction unit aluOperation code 47Number of operands 2Modifier NoModifier range —Latency 1Issue slots 1, 2, 3, 4, 5
DESCRIPTIONThe inonzero operation writes 0 into rdest if the value of rsrc1 is not zero; otherwise, rsrc2 is copied to rdest. The
operands are considered signed integers.The inonzero operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 2, r20 = 1 inonzero r30 r20 → r80 r80 ← 0
r10 = 0, r60 = 0x100, r30 = 2 IF r10 inonzero r60 r30 → r50 no change, since guard is false
TM1100 Preliminary Data Book Philips Semiconductors
A-122 PRELIMINARY INFORMATION File: ops.fm5, modified 7/23/99
Subtract
SYNTAX[ IF r guard ] isub r src1 r src2 → r dest
FUNCTIONif rguard then
rdest ← rsrc1 – rsrc2
ATTRIBUTESFunction unit aluOperation code 13Number of operands 2Modifier NoModifier range —Latency 1Issue slots 1, 2, 3, 4, 5
DESCRIPTIONThe isub operation computes the difference rsrc1–rsrc2 and writes the result into rdest. The operands can be
either both signed or unsigned integers. No overflow or underflow detection is performed.The isub operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
Philips Semiconductors DSPCPU Operations for TM1100
File: ops.fm5, modified 7/23/99 PRELIMINARY INFORMATION A-123
Subtract with immediate
SYNTAX[ IF r guard ] isubi( n) r src1 → r dest
FUNCTIONif rguard then
rdest ← rsrc1 – n
ATTRIBUTESFunction unit aluOperation code 32Number of operands 1Modifier 7 bitsModifier range 0..127Latency 1Issue slots 1, 2, 3, 4, 5
DESCRIPTIONThe isubi operation computes the difference of a single argument in rsrc1 and an immediate modifier n and stores
the result in rdest. The value of n must be between 0 and 127, inclusive. The isubi operations optionally take a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is unchanged.
EXAMPLES
Initial Values Operation Result
r30 = 0xf11 isubi(127) r30 → r70 r70 ← 0xe92
r10 = 0, r40 = 0xffffff9c IF r10 isubi(1) r40 → r80 no change, since guard is false
Philips Semiconductors DSPCPU Operations for TM1100
File: ops.fm5, modified 7/23/99 PRELIMINARY INFORMATION A-125
Indirect jump on false
SYNTAX[ IF r guard ] jmpf r src1 r src2
FUNCTIONif rguard then
if (rsrc1 & 1) = 0 thenPC ← rsrc2
ATTRIBUTESFunction unit branchOperation code 180Number of operands 2Modifier NoModifier range —Delay 3Issue slots 2, 3, 4
DESCRIPTIONThe jmpf operation conditionally changes the program flow. If the LSB of rsrc1 is 0, the PC register is set equal to
rsrc2; otherwise, program execution continues with the next sequential instruction.The jmpf operation optionally takes a guard, specified in rguard. If a guard is present, its LSB adds another
condition to the jump. If the LSB of rguard is 1, the instruction executes as previously described; otherwise, the jumpwill not be taken regardless of the value of rsrc1.
EXAMPLES
Initial Values Operation Result
r50 = 0, r70 = 0x330 jmpf r50 r70 program execution continues at 0x330
r20 = 1, r70 = 0x330 jmpf r20 r70 since r20 is true, program execution contin-ues with next sequential instruction
r30 = 0, r50 = 0, r60 = 0x8000 IF r30 jmpf r50 r60 since guard is false, program execution con-tinues with next sequential instruction
r40 = 1, r50 = 0, r60 = 0x8000 IF r40 jmpf r50 r60 program execution continues at 0x8000
SEE ALSOjmpt jmpi ijmpf ijmpt
ijmpi
jmpf
TM1100 Preliminary Data Book Philips Semiconductors
A-126 PRELIMINARY INFORMATION File: ops.fm5, modified 7/23/99
Jump immediate
SYNTAX[ IF r guard ] jmpi (address )
FUNCTIONif rguard then
PC ← address
ATTRIBUTESFunction unit branchOperation code 178Number of operands 0Modifier 32 bitsModifier range 0..0xffffffffDelay 3Issue slots 2, 3, 4
DESCRIPTIONThe jmpi operation changes the program flow by setting the PC register equal to the immediate opcode modifier
address.The jmpi operation optionally takes a guard, specified in rguard. If a guard is present, its LSB adds a condition to
the jump. If the LSB of rguard is 1, the instruction executes as previously described; otherwise, the jump will not betaken.
EXAMPLES
Initial Values Operation Result
jmpi(0x330) program execution continues at 0x330
r30 = 0 IF r30 jmpi(0x8000) since guard is false, program execution con-tinues with next sequential instruction
r40 = 1 IF r40 jmpi(0x8000) program execution continues at 0x8000
SEE ALSOjmpf jmpt ijmpf ijmpt
ijmpi
jmpi
Philips Semiconductors DSPCPU Operations for TM1100
File: ops.fm5, modified 7/23/99 PRELIMINARY INFORMATION A-127
Indirect jump on true
SYNTAX[ IF r guard ] jmpt r src1 r src2
FUNCTIONif rguard then
if (rsrc1 & 1) = 1 thenPC ← rsrc2
ATTRIBUTESFunction unit branchOperation code 176Number of operands 2Modifier noModifier range —Delay 3Issue slots 2, 3, 4
DESCRIPTIONThe jmpt operation conditionally changes the program flow. If the LSB of rsrc1 is 1, the PC register is set equal to
rsrc2; otherwise, program execution continues with the next sequential instruction.The jmpt operation optionally takes a guard, specified in rguard. If a guard is present, its LSB adds another
condition to the jump. If the LSB of rguard is 1, the instruction executes as previously described; otherwise, the jumpwill not be taken regardless of the value of rsrc1.
EXAMPLES
Initial Values Operation Result
r50 = 1, r70 = 0x330 jmpt r50 r70 program execution continues at 0x330
r20 = 0, r70 = 0x330 jmpt r20 r70 since r20 is false, program execution contin-ues with next sequential instruction
r30 = 0, r50 = 1, r60 = 0x8000 IF r30 jmpt r50 r60 since guard is false, program execution con-tinues with next sequential instruction
r40 = 1, r50 = 1, r60 = 0x8000 IF r40 jmpt r50 r60 program execution continues at 0x8000
SEE ALSOjmpf jmpi ijmpf ijmpt
ijmpi
jmpt
TM1100 Preliminary Data Book Philips Semiconductors
A-128 PRELIMINARY INFORMATION File: ops.fm5, modified 7/23/99
ATTRIBUTESFunction unit dmemOperation code 7Number of operands 1Modifier NoModifier range —Latency 3Issue slots 4, 5
DESCRIPTIONThe ld32 operation is a pseudo operation transformed by the scheduler into an ld32d(0) with the same
argument. (Note: pseudo operations cannot be used in assembly source files.)The ld32 operation loads the 32-bit memory value from the address contained in rsrc1 and stores the result in
rdest. If the memory address contained in rsrc1 is not a multiple of 4, the result of ld32 is undefined but no exceptionwill be raised. This load operation is performed as little-endian or big-endian depending on the current setting of thebytesex bit in the PCSW.
The ld32 operation can be used to access the MMIO address aperture (the result of MMIO access by 8- or 16-bitmemory operations is undefined). The state of the BSX bit in the PCSW has no effect on MMIO access by ld32 .
The ld32 operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register and the occurrence of side effects. If the LSB of rguard is 1, rdest is written andthe data cache status bits are updated if the addressed locations are cacheable. if the LSB of rguard is 0, rdest is notchanged and ld32 has no side effects whatever.
r50 = 0xd01 ld32 r50 → r90 r90 undefined, since 0xd01 is not a multiple of 4
SEE ALSOld32d ld32r ld32x st32
st32d h_st32d
ld32
Philips Semiconductors DSPCPU Operations for TM1100
File: ops.fm5, modified 7/23/99 PRELIMINARY INFORMATION A-129
32-bit load with displacement
SYNTAX[ IF r guard ] ld32d( d) r src1 → r dest
FUNCTIONif rguard then
if PCSW.bytesex = LITTLE_ENDIAN then bs ← 3
else bs ← 0
rdest<7:0> ← mem[rsrc1 + d + (3 ⊕ bs)]rdest<15:8> ← mem[rsrc1 + d + (2 ⊕ bs)]rdest<23:16> ← mem[rsrc1 + d + (1 ⊕ bs)]rdest<31:24> ← mem[rsrc1 + d + (0 ⊕ bs)]
ATTRIBUTESFunction unit dmemOperation code 7Number of operands 1Modifier 7 bitsModifier range –256..252 by 4Latency 3Issue slots 4, 5
DESCRIPTIONThe ld32d operation loads the 32-bit memory value from the address computed by rsrc1 + d and stores the result
in rdest. The d value is an opcode modifier, must be in the range –256 to 252 inclusive, and must be a multiple of 4. Ifthe memory address computed by rsrc1 + d is not a multiple of 4, the result of ld32d is undefined but no exceptionwill be raised. This load operation is performed as little-endian or big-endian depending on the current setting of thebytesex bit in the PCSW.
The ld32d operation can be used to access the MMIO address aperture (the result of MMIO access by 8- or 16-bitmemory operations is undefined). The state of the BSX bit in the PCSW has no effect on MMIO access by ld32d .
The ld32d operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register and the occurrence of side effects. If the LSB of rguard is 1, rdest is written andthe data cache status bits are updated if the addressed locations are cacheable. if the LSB of rguard is 0, rdest is notchanged and ld32d has no side effects whatever. EXAMPLES
ATTRIBUTESFunction unit dmemOperation code 200Number of operands 2Modifier NoModifier range —Latency 3Issue slots 4, 5
DESCRIPTIONThe ld32r operation loads the 32-bit memory value from the address computed by rsrc1 + rsrc2 and stores the
result in rdest. If the memory address computed by rsrc1 + rsrc2 is not a multiple of 4, the result of ld32r isundefined but no exception will be raised. This load operation is performed as little-endian or big-endian depending onthe current setting of the bytesex bit in the PCSW.
The ld32r operation can be used to access the MMIO address aperture (the result of MMIO access by 8- or 16-bitmemory operations is undefined). The state of the BSX bit in the PCSW has no effect on MMIO access by ld32r .
The ld32r operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register and the occurrence of side effects. If the LSB of rguard is 1, rdest is written andthe data cache status bits are updated if the addressed locations are cacheable. if the LSB of rguard is 0, rdest is notchanged and ld32r has no side effects whatever.
ATTRIBUTESFunction unit dmemOperation code 201Number of operands 2Modifier NoModifier range —Latency 3Issue slots 4, 5
DESCRIPTIONThe ld32x operation loads the 32-bit memory value from the address computed by rsrc1 + 4×rsrc2 and stores the
result in rdest. If the memory address computed by rsrc1 + 4×rsrc2 is not a multiple of 4, the result of ld32x isundefined but no exception will be raised. This load operation is performed as little-endian or big-endian depending onthe current setting of the bytesex bit in the PCSW.
The ld32x operation can be used to access the MMIO address aperture (the result of MMIO access by 8- or 16-bitmemory operations is undefined). The state of the BSX bit in the PCSW has no effect on MMIO access by ld32x .
The ld32x operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register and the occurrence of side effects. If the LSB of rguard is 1, rdest is written andthe data cache status bits are updated if the addressed locations are cacheable. if the LSB of rguard is 0, rdest is notchanged and ld32x has no side effects whatever.
r70 = 0xd01, r30 = 0x1 ld32x r70 r30 → r110 r110 undefined, since 0xd01 + 4×1 is not a multiple of 4
SEE ALSOld32 ld32d ld32r st32
st32d h_st32d
ld32x
TM1100 Preliminary Data Book Philips Semiconductors
A-132 PRELIMINARY INFORMATION File: ops.fm5, modified 7/23/99
Logical shift leftpseudo-op for asl
SYNTAX[ IF r guard ] lsl r src1 r src2 → r dest
FUNCTIONif rguard then
n ← rsrc2<4:0>rdest<31:n> ← rsrc1<31–n:0>rdest<n–1:0> ← 0if rsrc2<31:5> != 0
rdest <- 0
ATTRIBUTESFunction unit shifterOperation code 19Number of operands 2Modifier NoModifier range —Latency 1Issue slots 1, 2
DESCRIPTIONThe lsl operation is a pseudo operation that is transformed by the scheduler into an asl with the same
arguments. (Note: pseudo operations cannot be used in assembly source files.)As shown below, the lsl operation takes two arguments, rsrc1 and rsrc2. Rsrc2 specify an unsigned shift amount,
and rdest is set to rsrc1 arithmetically shifted left by this amount. If the rsrc2<31:5> value is not zero, then take this asa shift by 32 or more bits. Zeros are shifted into the LSBs of rdest while the MSBs shifted out of rsrc1 are lost.
The lsl operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is unchanged.
EXAMPLES
Initial Values Operation Result
r60 = 0x20, r30 = 3 lsl r60 r30 → r90 r90 ← 0x100
r10 = 0, r60 = 0x20, r30 = 3 IF r10 lsl r60 r30 → r100 no change, since guard is false
Philips Semiconductors DSPCPU Operations for TM1100
File: ops.fm5, modified 7/23/99 PRELIMINARY INFORMATION A-133
Logical shift left immediatepseudo-op for asli
SYNTAX[ IF r guard ] lsli( n) r src1 → r dest
FUNCTIONif rguard then
rdest<31:n> ← rsrc1<31–n:0>rdest<n–1:0> ← 0
ATTRIBUTESFunction unit shifterOperation code 11Number of operands 1Modifier 7 bitsModifier range 0..31Latency 1Issue slots 1, 2
DESCRIPTIONThe lsli operation is a pseudo operation that is transformed by the scheduler into an asli with the same
argument and opcode modifier. (Note: pseudo operations cannot be used in assembly source files.)As shown below, the lsli operation takes a single argument in rsrc1 and an immediate modifier n and produces a
result in rdest equal to rsrc1 logically shifted left by n bits. The value of n must be between 0 and 31, inclusive. Zerosare shifted into the LSBs of rdest while the MSBs shifted out of rsrc1 are lost.
The lsli operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is unchanged.
EXAMPLES
Initial Values Operation Result
r60 = 0x20 lsli(3) r60 → r90 r90 ← 0x100
r10 = 0, r60 = 0x20 IF r10 lsli(3) r60 → r100 no change, since guard is false
TM1100 Preliminary Data Book Philips Semiconductors
A-134 PRELIMINARY INFORMATION File: ops.fm5, modified 7/23/99
Logical shift right
SYNTAX[ IF r guard ] lsr r src1 r src2 → r dest
FUNCTIONif rguard then
n ← rsrc2<4:0>rdest<31:32–n> ← 0rdest<31–n:0> ← rsrc1<31:n>if rsrc2<31:5> != 0
rdest <- rsrc1<31>
ATTRIBUTESFunction unit shifterOperation code 96Number of operands 2Modifier NoModifier range —Latency 1Issue slots 1, 2
DESCRIPTIONAs shown below, the lsr operation takes two arguments, rsrc1 and rsrc2. Rsrc2 specifies an unsigned shift
amount, and rsrc1 is arithmetically shifted right by this amount. If the rsrc2<31:5> value is not zero, then take this as ashift by 32 or more bits.Zeros fill vacated bits from the left.
The lsr operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is unchanged.
Philips Semiconductors DSPCPU Operations for TM1100
File: ops.fm5, modified 7/23/99 PRELIMINARY INFORMATION A-135
Logical shift right immediate
SYNTAX[ IF r guard ] lsri( n) r src1 → r dest
FUNCTIONif rguard then
rdest<31:32–n> ← 0rdest<31–n:0> ← rsrc1<31:n>
ATTRIBUTESFunction unit shifterOperation code 9Number of operands 1Modifier 7 bitsModifier range 0..31Latency 1Issue slots 1, 2
DESCRIPTIONAs shown below, the lsri operation takes a single argument in rsrc1 and an immediate modifier n and produces a
result in rdest that is equal to rsrc1 logically shifted right by n bits. The value of n must be between 0 and 31, inclusive.Zeros fill vacated bits from the left.
The lsri operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is unchanged.
ATTRIBUTESFunction unit shifterOperation code 103Number of operands 2Modifier NoModifier range -Latency 1Issue slots 1,2
DESCRIPTIONThe arguments rsrc1 and rsrc2 are vectors of two 16-bit data. The mergedual16lsb operation merges the least
significant bytes from each 16-bit data rsrc1 and rsrc2 into one 32-bit data in dest register, to convert to quad 8-bit.The mergedual16lsb operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls
the modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
ATTRIBUTESFunction unit aluOperation code 57Number of operands 2Modifier NoModifier range —Latency 1Issue slots 1, 2, 3, 4, 5
DESCRIPTIONAs shown below, the mergelsb operation interleaves the two pairs of least-significant bytes from the arguments
rsrc1 and rsrc2 into rdest. The least-significant byte from rsrc2 is packed into the least-significant byte of rdest; theleast-significant byte from rsrc1 is packed into the second-least-significant byte of rdest; the second-least-significantbyte from rsrc2 is packed into the second-most-significant byte of rdest; and the second-least-significant byte fromrsrc1 is packed into the most-significant byte of rdest.
The mergelsb operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is unchanged.
ATTRIBUTESFunction unit aluOperation code 58Number of operands 2Modifier NoModifier range —Latency 1Issue slots 1, 2, 3, 4, 5
DESCRIPTIONAs shown below, the mergemsb operation interleaves the two pairs of most-significant bytes from the arguments
rsrc1 and rsrc2 into rdest. The second-most-significant byte from rsrc2 is packed into the least-significant byte ofrdest; the second-most-significant byte from rsrc1 is packed into the second-least-significant byte of rdest; the most-significant byte from rsrc2 is packed into the second-most-significant byte of rdest; and the most-significant byte fromrsrc1 is packed into the most-significant byte of rdest.
The mergemsb operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is unchanged.
ATTRIBUTESFunction unit aluOperation code 53Number of operands 2Modifier NoModifier range —Latency 1Issue slots 1, 2, 3, 4, 5
DESCRIPTIONAs shown below, the pack16lsb operation packs the two least-significant halfwords from the arguments rsrc1 and
rsrc2 into rdest. The halfword from rsrc1 is packed into the most-significant halfword of rdest; the halfword from rsrc2is packed into the least-significant halfword of rdest.
The pack16lsb operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is unchanged.
ATTRIBUTESFunction unit aluOperation code 54Number of operands 2Modifier NoModifier range —Latency 1Issue slots 1, 2, 3, 4, 5
DESCRIPTIONAs shown below, the pack16msb operation packs the two most-significant halfwords from the arguments rsrc1 and
rsrc2 into rdest. The halfword from rsrc1 is packed into the most-significant halfword of rdest; the halfword from rsrc2is packed into the least-significant halfword of rdest.
The pack16msb operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is unchanged.
TM1100 Preliminary Data Book Philips Semiconductors
A-142 PRELIMINARY INFORMATION File: ops.fm5, modified 7/23/99
Pack least-significant byte
SYNTAX[ IF r guard ] packbytes r src1 r src2 → r dest
FUNCTIONif rguard then
rdest<7:0> ← rsrc2<7:0>rdest<15:8> ← rsrc1<7:0>
ATTRIBUTESFunction unit aluOperation code 52Number of operands 2Modifier NoModifier range —Latency 1Issue slots 1, 2, 3, 4, 5
DESCRIPTIONAs shown below, the packbytes operation packs the two least-significant bytes from the arguments rsrc1 and
rsrc2 into rdest. The byte from rsrc1 is packed into the second-least-significant byte of rdest; the byte from rsrc2 ispacked into the least-significant byte of rdest. The two most-significant bytes of rdest are filled with zeros.
The packbytes operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is unchanged.
ATTRIBUTESFunction unit dmemspecOperation code 209Number of operands 1Modifier -Modifier range -Latency -Issue slots 5
DESCRIPTIONThe pref operation is a pseudo operation transformed by the scheduler into an prefd(0) with the same arguments.
(Note: pseudo operations cannot be used in assembly files.)The pref operation loads the one full cache block size of memory value from the address computed by ((rsrc1+0) &
cache_block_mask) and stores the data into the data cache. This operation is not guaranteed to be executed. Theprefetch unit will not execute this operation when the data to be prefetched is already in the data cache. A prefoperation will not be executed when the cache is already occupied with 2 cache misses, when the operation is issued.
The pref operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the executionof the prefetch operation. If the LSB of rguard is 1, prefetch operation is executed; otherwise, it is not executed.
EXAMPLES
NOTE: This operation is supported only in TM1000 and 1100 and it is not guaranteed tobe available in future generations of Trimedia products.
Initial Values Operation Result
r10 = 0xabcd,cache_block_size = 0x40
pref r10 Loads a cache line for the address space from 0xabc0 to 0x0xabff from the main memory. If the data is already in the cache, the operation is not executed.
r10 = 0xabcd, r11 = 0,cache_block_size = 0x40
IF r11 pref r10 since guard is false, pref operation is not executed
r10 = 0xabff, r11 = 1, cache_block_size = 0x40
IF r11 pref r10 Loads a cache line for the address space from 0xabc0 to 0x0xabff from the main memory. If the data is already in the cache, the operation is not executed.
SEE ALSOpref16x pref32x prefd
prefr allocd allocr allocx
pref
TM1100 Preliminary Data Book Philips Semiconductors
A-144 PRELIMINARY INFORMATION File: ops.fm5, modified 7/23/99
ATTRIBUTESFunction unit dmemspecOperation code 211Number of operands 2Modifier NoModifier range -Latency -Issue slots 5
DESCRIPTIONThe pref16x operation loads one full cache block from the main memory at the address computed by ((rsrc1+ (2 x
rscr2)) & cache_block_mask) and stores the data into the data cache. This operation is not guaranteed to beexecuted. The prefetch unit will not execute this operation when the data to be prefetched is already in the data cache.The data cache has hardware to simultaneously sustain two cache misses or prefetches. A pref16x operation will notbe executed when the cache is already occupied with 2 cache misses, when the operation is issued.
The pref16x operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls theexecution of the prefetch operation. If the LSB of rguard is 1, prefetch operation is executed; otherwise, it is notexecuted
EXAMPLES
NOTE: This operation is supported only in TM1000 and 1100 and it is not guaranteed tobe available in future generations of Trimedia products.
Initial Values Operation Result
r10 = 0xabcd, r12 = 0xccache_block_size = 0x40
pref16x r10 r12 Loads a cache line for the address space from 0xabc0 to 0xabff from the main memory. If the data is already in the cache, the operation is not executed.
IF r11 pref16x r10 r12 Loads a cache line for the address space from 0xac00 to 0x0xac3f from the main memory. If the data is already in the cache, the operation is not exe-cuted.
SEE ALSOpref32x prefd prefr allocd
allocr allocx
Philips Semiconductors DSPCPU Operations for TM1100
File: ops.fm5, modified 7/23/99 PRELIMINARY INFORMATION A-145
ATTRIBUTESFunction unit dmemspecOperation code 212Number of operands 2Modifier NoModifier range -Latency -Issue slots 5
DESCRIPTIONThe pref32x operation loads the one full cache block size of memory value from the address computed by ((rsrc1+ (4
x rscr2)) & cache_block_mask) and stores the data into the data cache. This operation is not guaranteed to beexecuted. The prefetch unit will not execute this operation when the data to be prefetched is already in the data cache.A pref32x operation will not be executed when the cache is already occupied with 2 cache misses, when the operationis issued.
The pref32x operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls theexecution of the prefetch operation. If the LSB of rguard is 1, prefetch operation is executed; otherwise, it is notexecuted..
EXAMPLES
NOTE: This operation is supported only in TM1000 and 1100 and it is not guaranteed tobe available in future generations of this product.
Initial Values Operation Result
r10 = 0xabcd, r12 = 0xdcache_block_size = 0x40
pref32x r10 r12 Loads a cache line for the address space from 0xac00 to 0x0xac3f from the main memory. If the data is already in the cache, the operation is not exe-cuted.
IF r11 pref32x r10 r12 Loads a cache line for the address space from 0xac00 to 0x0xac3f from the main memory. If the data is already in the cache, the operation is not exe-cuted.
SEE ALSOpref16x prefd prefr allocd
allocr allocx
pref32x
TM1100 Preliminary Data Book Philips Semiconductors
A-146 PRELIMINARY INFORMATION File: ops.fm5, modified 7/23/99
ATTRIBUTESFunction unit dmemspecOperation code 209Number of operands 1Modifier 7 bitsModifier range –256..252 by 4Latency -Issue slots 5
DESCRIPTIONThe prefd operation loads the one full cache block size of memory value from the address computed by ((rsrc1+d) &
cache_block_mask) and stores the data into the data cache. This operation is not guaranteed to be executed. Theprefetch unit will not execute this operation when the data to be prefetched is already in the data cache. A prefdoperation will not be executed when the cache is already occupied with 2 cache misses, when the operation is issued.
The prefd operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the executionof the prefetch operation. If the LSB of rguard is 1, prefetch operation is executed; otherwise, it is not executed..
EXAMPLES
NOTE: This operation is supported only in TM1000 and 1100 and it is not guaranteed tobe available in future generations of this product.
Initial Values Operation Result
r10 = 0xabcd,cache_block_size = 0x40
prefd(0xd) r10 Loads a cache line for the address space from 0xabc0 to 0x0xabff from the main memory. If the data is already in the cache, the operation is not executed.
r10 = 0xabcd, r11 = 0,cache_block_size = 0x40
IF r11 prefd(0xd) r10 since guard is false, prefd operation is not executed
r10 = 0xabff, r11 = 1, cache_block_size = 0x40
IF r11 prefd(ox1) r10 Loads a cache line for the address space from 0xac00 to 0x0xac3f from the main memory. If the data is already in the cache, the operation is not exe-cuted.
SEE ALSOpref16x pref32x prefr allocd allocr allocx
Philips Semiconductors DSPCPU Operations for TM1100
File: ops.fm5, modified 7/23/99 PRELIMINARY INFORMATION A-147
ATTRIBUTESFunction unit dmemspecOperation code 210Number of operands 2Modifier NoModifier range -Latency -Issue slots 5
DESCRIPTIONThe prefr operation loads the one full cache block size of memory value from the address computed by
((rsrc1+rscr2) & cache_block_mask) and stores the data into the data cache. This operation is not guaranteed to beexecuted. The prefetch unit will not execute this operation when the data to be prefetched is already in the data cache.A prefr operation will not be executed when the cache is already occupied with 2 cache misses, when the operation isissued.
The prefr operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls theexecution of the prefetch operation. If the LSB of rguard is 1, prefetch operation is executed; otherwise, it is notexecuted..
EXAMPLES
NOTE: This operation is supported only in TM1000 and 1100 and it is not guaranteed tobe available in future generations of this product.
Initial Values Operation Result
r10 = 0xabcd, r12 = 0xdcache_block_size = 0x40
prefr r10 r12 Loads a cache line for the address space from 0xabc0 to 0x0xac3f from the main memory. If the data is already in the cache, the operation is not exe-cuted.
IF r11 prefr r10 r12 Loads a cache line for the address space from 0xac00 to 0x0xac3f from the main memory. If the data is already in the cache, the operation is not exe-cuted.
SEE ALSOpref16x pref32x prefdallocd allocr allocx
prefr
TM1100 Preliminary Data Book Philips Semiconductors
A-148 PRELIMINARY INFORMATION File: ops.fm5, modified 7/23/99
Unsigned byte-wise quad average
SYNTAX[ IF r guard ] quadavg r src1 r src2 → r dest
ATTRIBUTESFunction unit dspaluOperation code 73Number of operands 2Modifier NoModifier range —Latency 2Issue slots 1, 3
DESCRIPTIONAs shown below, the quadavg operation computes four separate averages of the four pairs of corresponding 8-bit
bytes of rsrc1 and rsrc2. All bytes are considered unsigned. The least-significant 8 bits of each average is written tothe corresponding byte in rdest. No overflow or underflow detection is performed.
The quadavg operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
Philips Semiconductors DSPCPU Operations for TM1100
File: ops.fm5, modified 7/23/99 PRELIMINARY INFORMATION A-149
Unsigned byte-wise quad maximum
SYNTAX[ IF r guard ] quadumax r src1 r src2 → r dest
FUNCTIONif rguard then
rdest<7:0> ← if rsrc1<7:0> > rsrc2<7:0> then rsrc1<7:0> else rsrc2<7:0>rdest<15:8> ← if rsrc1<15:8> > rsrc2<15:8> then rsrc1<15:8> else rsrc2<15:8>rdest<23:16> ← if rsrc1<23:16> > rsrc2<23:16> then rsrc1<23:16> else rsrc2<23:16>rdest<31:24> ← if rsrc1<31:24> > rsrc2<31:24> then rsrc1<31:24> else rsrc2<31:24>
ATTRIBUTESFunction unit dspaluOperation code 81Number of operands 2Modifier NoModifier range —Latency 2Issue slots 1,3
DESCRIPTIONThe quadumax operation computes four separate maximum values of the four pairs of corresponding 8-bit bytes of
rsrc1 and rsrc2. All bytes are considered unsigned. The quadumax operation is particularly suited to implementmedian computation on packed pixel data structures:
The quadumax operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
TM1100 Preliminary Data Book Philips Semiconductors
A-150 PRELIMINARY INFORMATION File: ops.fm5, modified 7/23/99
quadumin Unsigned bytewise quad minimum
SYNTAX[ IF r guard ] quadumin r src1 r src2 → r dest
FUNCTIONif rguard then
rdest<7:0> ← if rsrc1<7:0> < rsrc2<7:0> then rsrc1<7:0> else rsrc2<7:0>rdest<15:8> ← if rsrc1<15:8> < rsrc2<15:8> then rsrc1<15:8> else rsrc2<15:8>rdest<23:16> ← if rsrc1<23:16> < rsrc2<23:16> then rsrc1<23:16> else rsrc2<23:16>rdest<31:24> ← if rsrc1<31:24> < rsrc2<31:24> then rsrc1<31:24> else rsrc2<31:24>
ATTRIBUTESFunction unit dspaluOperation code 80Number of operands 2Modifier NoModifier range —Latency 2Issue slots 1,3
DESCRIPTIONThe quadumin operation computes four separate minimum values of the four pairs of corresponding 8-bit bytes of
rsrc1 and rsrc2. All bytes are considered unsigned. The quadumin operation is particularly suited to implementmedian computation on packed pixel data structures:
The quadumin operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
ATTRIBUTESFunction unit dspmulOperation code 89Number of operands 2Modifier NoModifier range —Latency 3Issue slots 2, 3
DESCRIPTIONAs shown below, the quadumulmsb operation computes four separate products of the four pairs of corresponding
8-bit bytes of rsrc1 and rsrc2. All bytes are considered unsigned. The most-significant 8 bits of each 16-bit product iswritten to the corresponding byte in rdest.
The quadumulmsb operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controlsthe modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
ATTRIBUTESFunction unit dmemspecOperation code 203Number of operands 1Modifier 7 bitsModifier range –256..252 by 4Latency 3Issue slots 5
DESCRIPTIONThe rdstatus operation reads the LRU and dirty bits associated with a set in the data cache and writes these bits
into the destination register rdest. The target set in the data cache is determined by bits 10..6 of the result of rsrc1 + d.The d value is an opcode modifier, must be in the range –256 to 252 inclusive, and must be a multiple of 4.
The result of rdstatus contains LRU information in bits 9..0 and dirty-bit information in bits 17..10. All other bits ofrdest are set to zero.
rdstatus requires two stall cycles to complete.The dual-ported data cache uses two separate copies of tag and status information. A rdstatus operation
returns the LRU and dirty information stored in the cache port that corresponds to the operation slot in which therdstatus operation is issued.
The rdstatus operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
EXAMPLES
Initial Values Operation Result
rdstatus(0) r30 → r60r10 = 0 IF r10 rdstatus(4) r40 → r70 no change, since guard is false
r20 = 1 IF r20 rdstatus(8) r50 → r80
SEE ALSOrdtag
rdstatus
Philips Semiconductors DSPCPU Operations for TM1100
File: ops.fm5, modified 7/23/99 PRELIMINARY INFORMATION A-153
Read data cache address tag
SYNTAX[ IF r guard ] rdtag( d) r src1 → r dest
FUNCTIONif rguard then
block_addr ← rsrc1 + d
/* block_addr<13:11> selects element, block_addr<10:6> selects set */
ATTRIBUTESFunction unit dmemspecOperation code 202Number of operands 1Modifier 7 bitsModifier range –256..252 by 4Latency 3Issue slots 5
DESCRIPTIONThe rdtag operation reads the address tag associated with a block in the data cache and writes these bits into the
destination register rdest. The target block in the data cache is determined by bits 13..6 of the result of rsrc1 + d. Bits10..6 of rsrc1 + d select the cache set and 13..11 of rsrc1 + d select the element within that set. The d value is anopcode modifier, must be in the range –256 to 252 inclusive, and must be a multiple of 4.
rdtag writes the address tag for the selected block in bits 20..0 of rdest. All other bits of rdest are set to zero.rdtag requires no stall cycles to complete.The dual-ported data cache uses two separate copies of tag and status information. A rdtag operation returns the
address tag information stored in the cache port that corresponds to the operation slot in which the rdtag operationis issued.
The rdtag operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
EXAMPLES
Initial Values Operation Result
rdtag(0) r30 → r60r10 = 0 IF r10 rdtag(4) r40 → r70 no change, since guard is false
r20 = 1 IF r20 rdtag(8) r50 → r80
SEE ALSOrdstatus
rdtag
TM1100 Preliminary Data Book Philips Semiconductors
A-154 PRELIMINARY INFORMATION File: ops.fm5, modified 7/23/99
Read destination program counter
SYNTAX[ IF r guard ] readdpc → r dest
FUNCTIONif rguard then
rdest ← DPC
ATTRIBUTESFunction unit fcompOperation code 156Number of operands 0Modifier NoModifier range —Latency 1Issue slots 3
DESCRIPTIONThe readdpc writes the current value of the DPC (Destination Program Counter) processor register to rdest.Interruptible jumps write their target address to the DPC. If an interrupt or exception is taken at an interruptible jump,
execution of the interrupted program can be resumed by jumping to the value contained in DPC. This operation can beused to save state before idling a task in a multi-tasking environment.
The readdpc operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is unchanged.
EXAMPLES
Initial Values Operation Result
DPC = 0xbeebee readdpc → r100 r100 ← 0xbeebee
r20 = 0, DPC = 0xabba IF r20 readdpc → r101 no change, since guard is false
Philips Semiconductors DSPCPU Operations for TM1100
File: ops.fm5, modified 7/23/99 PRELIMINARY INFORMATION A-155
Read program control and status word
SYNTAX[ IF r guard ] readpcsw → r dest
FUNCTIONif rguard then
rdest ← PCSW
ATTRIBUTESFunction unit fcompOperation code 158Number of operands 0Modifier NoModifier range —Latency 1Issue slots 3
DESCRIPTIONThe readpcsw writes the current value of the PCSW (Program Control and Status Word) processor register to
rdest. The layout of PCSW is shown below.Fields in the PCSW have two chief purposes: to control aspects of processor operation and to record events that
occur during program execution. Thus, readpcsw can be used to determine current processor operating modes andwhat events have occurred; this operation can also be used to save state before idling a task in a multi-taskingenvironment.
The readpcsw operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is unchanged.
EXAMPLES
Initial Values Operation Result
PCSW = 0x80110642 readpcsw → r100 r100 ← 0x80110642 (trap on MSE, INV and DBZ enabled, IEN=1 - interrupts enabled, BSX=1 - little endian mode of operation, OFZ=1 - a denormalized result was produced somewhere, INX=1 - an inexact result was produced somewhere)
r20 = 0, PCSW = 0x80000000 IF r20 readpcsw → r101 no change, since guard is false
r21 = 1, PCSW = 0x80000000 IF r21 readpcsw → r102 r102 ← 0x80000000 (trap on MSE enabled)
IEEE rounding mode0 ⇒ to nearest, 1 ⇒ to zero, 2 ⇒ to positive, 3 ⇒ to negative
Interrupt enable (1 ⇒ allow interrupts)
Byte sex (1 ⇒ little endian)
PCSW<31:16>
PCSW<15:0> UNDEF
Misaligned storeexception trap enable Trap on first exit
FP exceptions
TRPMSE TFE TRP
OFZTRPIFZ
TRPINV
TRPOVF
TRPUNF
TRPINX
TRPDBZ
1617181920212223252627283031
UNDEF U N D E F I N E D
13
WBE RSE
Write back errorReserved exception
TRPWBE
TRPRSE
Write back error trap enableReserved exceptiontrap enable
29
SEE ALSOwritepcsw
readpcsw
TM1100 Preliminary Data Book Philips Semiconductors
A-156 PRELIMINARY INFORMATION File: ops.fm5, modified 7/23/99
Read source program counter
SYNTAX[ IF r guard ] readspc → r dest
FUNCTIONif rguard then
rdest ← SPC
ATTRIBUTESFunction unit fcompOperation code 157Number of operands 0Modifier NoModifier range —Latency 1Issue slots 3
DESCRIPTIONThe readspc writes the current value of the SPC (Source Program Counter) processor register to rdest.An interruptible jump that is not interrupted (no NMI, INT, or EXC event was pending when the jump was executed)
writes its target address to SPC. The value of SPC allows an exception-handling routine to determine the startaddress of the block of scheduled code (called a decision tree) that was executing before the exception wastaken.This operation can be used to save state before idling a task in a multi-tasking environment.
The readspc operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is unchanged.
EXAMPLES
Initial Values Operation Result
SPC = 0xbeebee readspc → r100 r100 ← 0xbeebee
r20 = 0, SPC = 0xabba IF r20 readspc → r101 no change, since guard is false
Philips Semiconductors DSPCPU Operations for TM1100
File: ops.fm5, modified 7/23/99 PRELIMINARY INFORMATION A-157
Rotate left
SYNTAX[ IF r guard ] rol r src1 r src2 → r dest
FUNCTIONif rguard then
n ← rsrc2<4:0>rdest<31:n> ← rsrc1<31–n:0>rdest<n–1:0> ← rsrc1<31:32–n>
ATTRIBUTESFunction unit shifterOperation code 97Number of operands 2Modifier NoModifier range —Latency 1Issue slots 1, 2
DESCRIPTIONAs shown below, the rol operation takes two arguments, rsrc1 and rsrc2. The least-significant five bits of rsrc2
specify an unsigned rotate amount, and rdest is set to rsrc1 rotated left by this amount. The most-significant n bits ofrsrc1, where n is the rotate amount, appear as the least-significant n bits in rdest.
The rol operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is unchanged.
EXAMPLES
Initial Values Operation Result
r60 = 0x20, r30 = 3 rol r60 r30 → r90 r90 ← 0x100
r10 = 0, r60 = 0x20, r30 = 3 IF r10 rol r60 r30 → r100 no change, since guard is false
r20 = 1, r60 = 0x20, r30 = 3 IF r20 rol r60 r30 → r110 r110 ← 0x100
ATTRIBUTESFunction unit shifterOperation code 98Number of operands 1Modifier 7 bitsModifier range 0..31Latency 1Issue slots 1, 2
DESCRIPTIONAs shown below, the roli operation takes a single argument in rsrc1 and an immediate modifier n and produces a
result in rdest equal to rsrc1 rotated left by n bits. The value of n must be between 0 and 31, inclusive. The most-significant n bits of rsrc1 appear as the least-significant n bits in rdest.
The roli operations optionally take a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is unchanged.
EXAMPLES
Initial Values Operation Result
r60 = 0x20 roli(3) r60 → r90 r90 ← 0x100
r10 = 0, r60 = 0x20 IF r10 roli(3) r60 → r100 no change, since guard is false
Philips Semiconductors DSPCPU Operations for TM1100
File: ops.fm5, modified 7/23/99 PRELIMINARY INFORMATION A-159
Sign extend 16 bits
SYNTAX[ IF r guard ] sex16 r src1 → r dest
FUNCTIONif rguard then
rdest ← sign_ext16to32(rsrc1<15:0>)
ATTRIBUTESFunction unit aluOperation code 51Number of operands 1Modifier NoModifier range —Latency 1Issue slots 1, 2, 3, 4, 5
DESCRIPTIONAs shown below, the sex16 operation sign extends the least-significant 16bit halfword of the argument, rsrc1, to 32
bits and stores the result in rdest.
The sex16 operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register. If the LSB of the guard is 1, rdest is written; otherwise, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 0xffff0040 sex16 r30 → r60 r60 ← 0x00000040
r10 = 0, r40 = 0xff0fff91 IF r10 sex16 r40 → r70 no change, since guard is false
TM1100 Preliminary Data Book Philips Semiconductors
A-160 PRELIMINARY INFORMATION File: ops.fm5, modified 7/23/99
Sign extend 8 bitspseudo-op for ibytesel
SYNTAX[ IF r guard ] sex8 r src1 → r dest
FUNCTIONif rguard then
rdest ← sign_ext8to32(rsrc1<7:0>)
ATTRIBUTESFunction unit aluOperation code 56Number of operands 1Modifier NoModifier range —Latency 1Issue slots 1, 2, 3, 4, 5
DESCRIPTIONThe sex8 operation is a pseudo operation transformed by the scheduler into a ibytesel with rsrc1 as the first
argument and r0 (always contains 0) as the second. (Note: pseudo operations cannot be used in assembly sourcefiles.)
As shown below, the sex8 operation sign extends the least-significant halfword of the argument, rsrc1, to 32 bitsand writes the result in rdest.
The sex8 operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 0xffff0040 sex8 r30 → r60 r60 ← 0x00000040
r10 = 0, r40 = 0xff0fff91 IF r10 sex8 r40 → r70 no change, since guard is false
ATTRIBUTESFunction unit dmemOperation code 30Number of operands 2Modifier NoModifier range —Latency n/aIssue slots 4, 5
DESCRIPTIONThe st16 operation is a pseudo operation transformed by the scheduler into an h_st16d(0) with the same
arguments. (Note: pseudo operations cannot be used in assembly files.)The st16 operation stores the least-significant 16-bit halfword of rsrc2 into the memory locations pointed to by the
address in rsrc1. This store operation is performed as little-endian or big-endian depending on the current setting ofthe bytesex bit in the PCSW.
If st16 is misaligned (the memory address in rsrc1 is not a multiple of 2), the result of st16 is undefined, and theMSE (Misaligned Store Exception) bit in the PCSW register is set to 1. Additionally, if the TRPMSE (TRaP onMisaligned Store Exception) bit in PCSW is 1, exception processing will be requested on the next interruptible jump.
The result of an access by st16 to the MMIO address aperture is undefined; access to the MMIO aperture isdefined only for 32-bit loads and stores.
The st16 operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the addressed memory locations (and the modification of cache if the locations are cacheable). If theLSB of rguard is 1, the store takes effect. If the LSB of rguard is 0, st16 has no side effects whatever; in particular, theLRU and other status bits in the data cache are not affected.
TM1100 Preliminary Data Book Philips Semiconductors
A-162 PRELIMINARY INFORMATION File: ops.fm5, modified 7/23/99
16-bit store with displacementpseudo-op for h_st16d
SYNTAX[ IF r guard ] st16d( d) r src1 r src2
FUNCTIONif rguard then
if PCSW.bytesex = LITTLE_ENDIAN then bs ← 1
else bs ← 0
mem[rsrc1 + d + (1 ⊕ bs)] ← rsrc2<7:0>mem[rsrc1 + d + (0 ⊕ bs)] ← rsrc2<15:8>
ATTRIBUTESFunction unit dmemOperation code 30Number of operands 2Modifier 7 bitsModifier range –128..126 by 2Latency n/aIssue slots 4, 5
DESCRIPTIONThe st16d operation is a pseudo operation transformed by the scheduler into an h_st16d with the same
arguments. (Note: pseudo operations cannot be used in assembly files.)The st16d operation stores the least-significant 16-bit halfword of rsrc2 into the memory locations pointed to by the
address in rsrc1 + d. The d value is an opcode modifier, must be in the range –128 and 126 inclusive, and must be amultiple of 2. This store operation is performed as little-endian or big-endian depending on the current setting of thebytesex bit in the PCSW.
If st16d is misaligned (the memory address computed by rsrc1 + d is not a multiple of 2), the result of st16d isundefined, and the MSE (Misaligned Store Exception) bit in the PCSW register is set to 1. Additionally, if the TRPMSE(TRaP on Misaligned Store Exception) bit in PCSW is 1, exception processing will be requested on the nextinterruptible jump.
The result of an access by st16d to the MMIO address aperture is undefined; access to the MMIO aperture isdefined only for 32-bit loads and stores.
The st16d operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the addressed memory locations (and the modification of cache if the locations are cacheable). If theLSB of rguard is 1, the store takes effect. If the LSB of rguard is 0, st16d has no side effects whatever; in particular, theLRU and other status bits in the data cache are not affected.
ATTRIBUTESFunction unit dmemOperation code 31Number of operands 2Modifier NoModifier range —Latency n/aIssue slots 4, 5
DESCRIPTIONThe st32 operation is a pseudo operation transformed by the scheduler into an h_st32d(0) with the same
arguments. (Note: pseudo operations cannot be used in assembly files.)The st32 operation stores all 32 bits of rsrc2 into the memory locations pointed to by the address in rsrc1. The d
value is an opcode modifier and must be a multiple of 4. This store operation is performed as little-endian or big-endian depending on the current setting of the bytesex bit in the PCSW.
If st32 is misaligned (the memory address in rsrc1 is not a multiple of 4), the result of st32 is undefined, and theMSE (Misaligned Store Exception) bit in the PCSW register is set to 1. Additionally, if the TRPMSE (TRaP onMisaligned Store Exception) bit in PCSW is 1, exception processing will be requested on the next interruptible jump.
The st32 operation can be used to access the MMIO address aperture (the result of MMIO access by 8- or 16-bitmemory operations is undefined). The state of the BSX bit in the PCSW has no effect on MMIO access by st32 .
The st32 operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the addressed memory locations (and the modification of cache if the locations are cacheable). If theLSB of rguard is 1, the store takes effect. If the LSB of rguard is 0, st32 has no side effects whatever; in particular, theLRU and other status bits in the data cache are not affected.
TM1100 Preliminary Data Book Philips Semiconductors
A-164 PRELIMINARY INFORMATION File: ops.fm5, modified 7/23/99
32-bit store with displacementpseudo-op for h_st32d
SYNTAX[ IF r guard ] st32d( d) r src1 r src2
FUNCTIONif rguard then
if PCSW.bytesex = LITTLE_ENDIAN then bs ← 3
else bs ← 0
mem[rsrc1 + d + (3 ⊕ bs)] ← rsrc2<7:0>mem[rsrc1 + d + (2 ⊕ bs)] ← rsrc2<15:8>mem[rsrc1 + d + (1 ⊕ bs)] ← rsrc2<23:16>mem[rsrc1 + d + (0 ⊕ bs)] ← rsrc2<31:24>
ATTRIBUTESFunction unit dmemOperation code 31Number of operands 2Modifier 7 bitsModifier range –256..252 by 4Latency n/aIssue slots 4, 5
DESCRIPTIONThe st32d operation is a pseudo operation transformed by the scheduler into an h_st32d with the same
arguments. (Note: pseudo operations cannot be used in assembly files.)The st32d operation stores all 32 bits of rsrc2 into the memory locations pointed to by the address in rsrc1 + d.
The d value is an opcode modifier, must be in the range –256 and 252 inclusive, and must be a multiple of 4. Thisstore operation is performed as little-endian or big-endian depending on the current setting of the bytesex bit in thePCSW.
If st32d is misaligned (the memory address computed by rsrc1 + d is not a multiple of 4), the result of st32d isundefined, and the MSE (Misaligned Store Exception) bit in the PCSW register is set to 1. Additionally, if the TRPMSE(TRaP on Misaligned Store Exception) bit in PCSW is 1, exception processing will be requested on the nextinterruptible jump.
The st32d operation can be used to access the MMIO address aperture (the result of MMIO access by 8- or 16-bitmemory operations is undefined). The state of the BSX bit in the PCSW has no effect on MMIO access by st32d .
The st32d operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the addressed memory locations (and the modification of cache if the locations are cacheable). If theLSB of rguard is 1, the store takes effect. If the LSB of rguard is 0, st32d has no side effects whatever; in particular, theLRU and other status bits in the data cache are not affected.
Philips Semiconductors DSPCPU Operations for TM1100
File: ops.fm5, modified 7/23/99 PRELIMINARY INFORMATION A-165
8-bit storepseudo-op for h_st8d(0)
SYNTAX[ IF r guard ] st8 r src1 r src2
FUNCTIONif rguard then
mem[rsrc1] ← rsrc2<7:0>
ATTRIBUTESFunction unit dmemOperation code 29Number of operands 2Modifier NoModifier range —Latency n/aIssue slots 4, 5
DESCRIPTIONThe st8 operation is a pseudo operation transformed by the scheduler into an h_st8d(0) with the same
arguments. (Note: pseudo operations cannot be used in assembly files.)The st8 operation stores the least-significant 8-bit byte of rsrc2 into the memory location pointed to by the address
in rsrc1. This operation does not depend on the bytesex bit in the PCSW since only a single byte is stored.The result of an access by st8 to the MMIO address aperture is undefined; access to the MMIO aperture is defined
only for 32-bit loads and stores. The st8 operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the addressed memory location (and the modification of cache if the location is cacheable). If the LSBof rguard is 1, the store takes effect. If the LSB of rguard is 0, st8 has no side effects whatever; in particular, the LRUand other status bits in the data cache are not affected.
IF r50 st8 r20 r70 no change, since guard is false
r60 = 1, r30 = 0xd02,r70 = 0xaabbccdd
IF r60 st8 r30 r70 [0xd02] ← 0xdd
SEE ALSOh_st8d st8d st16 st16d
st32 st32d
st8
TM1100 Preliminary Data Book Philips Semiconductors
A-166 PRELIMINARY INFORMATION File: ops.fm5, modified 7/23/99
8-bit store with displacementpseudo-op for h_st8d
SYNTAX[ IF r guard ] st8d( d) r src1 r src2
FUNCTIONif rguard then
mem[rsrc1 + d] ← rsrc2<7:0>
ATTRIBUTESFunction unit dmemOperation code 29Number of operands 2Modifier 7 bitsModifier range –64..63Latency n/aIssue slots 4, 5
DESCRIPTIONThe st8d operation is a pseudo operation transformed by the scheduler into an h_st8d with the same
arguments. (Note: pseudo operations cannot be used in assembly files.)The st8d operation stores the least-significant 8-bit byte of rsrc2 into the memory location pointed to by the
address formed from the sum rsrc1 + d. The value of the opcode modifier d must be in the range -64 and 63 inclusive.This operation does not depend on the bytesex bit in the PCSW since only a single byte is stored.
The result of an access by st8d to the MMIO address aperture is undefined; access to the MMIO aperture isdefined only for 32-bit loads and stores.
The st8d operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the addressed memory location (and the modification of cache if the location is cacheable). If the LSBof rguard is 1, the store takes effect. If the LSB of rguard is 0, st8d has no side effects whatever; in particular, the LRUand other status bits in the data cache are not affected.
IF r50 st8d(-4) r20 r70 no change, since guard is false
r60 = 1, r30 = 0xd02,r70 = 0xaabbccdd
IF r60 st8d(-4) r30 r70 [0xcfe] ← 0xdd
SEE ALSOh_st8d st8 st16 st16d st32
st32d
st8d
Philips Semiconductors DSPCPU Operations for TM1100
File: ops.fm5, modified 7/23/99 PRELIMINARY INFORMATION A-167
Select unsigned byte
SYNTAX[ IF r guard ] ubytesel r src1 r src2 → r dest
FUNCTIONif rguard then
if rsrc2 = 0 then rdest ← zero_ext8to32(rsrc1<7:0>)
else if rsrc2 = 1 then rdest ← zero_ext8to32(rsrc1<15:8>)
else if rsrc2 = 2 then rdest ← zero_ext8to32(rsrc1<23:15>)
else if rsrc2 = 3 then rdest ← zero_ext8to32(rsrc1<31:24>)
ATTRIBUTESFunction unit aluOperation code 55Number of operands 2Modifier NoModifier range —Latency 1Issue slots 1, 2, 3, 4, 5
DESCRIPTIONAs shown below, the ubytesel operation selects one byte from the argument, rsrc1, zero-extends the byte to 32
bits, and stores the result in rdest. The value of rsrc2 determines which byte is selected, with rsrc2=0 selecting theLSB of rsrc1 and rsrc2=3 selecting the MSB of rsrc1. If rsrc2 is not between 0 and 3 inclusive, the result ofubytesel is undefined.
The ubytesel operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
TM1100 Preliminary Data Book Philips Semiconductors
A-168 PRELIMINARY INFORMATION File: ops.fm5, modified 7/23/99
Clip signed to unsigned
SYNTAX[ IF r guard ] uclipi r src1 r src2 → r dest
FUNCTIONif rguard then
rdest ← min(max(rsrc1, 0), rsrc2)
ATTRIBUTESFunction unit dspaluOperation code 75Number of operands 2Modifier NoModifier range —Latency 2Issue slots 1, 3
DESCRIPTIONThe uclipi operation returns the value of rsrc1 clipped into the unsigned integer range 0 to rsrc2, inclusive. The
argument rsrc1 is considered a signed integer; rsrc2 is considered an unsigned integer.The uclipi operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
Philips Semiconductors DSPCPU Operations for TM1100
File: ops.fm5, modified 7/23/99 PRELIMINARY INFORMATION A-169
Clip unsigned to unsigned
SYNTAX[ IF r guard ] uclipu r src1 r src2 → r dest
FUNCTIONif rguard then
if rsrc1 > rsrc2 thenrdest ← rsrc2
elserdest ← rsrc1
ATTRIBUTESFunction unit dspaluOperation code 76Number of operands 2Modifier NoModifier range —Latency 2Issue slots 1, 3
DESCRIPTIONThe uclipu operation returns the value of rsrc1 clipped into the unsigned integer range 0 to rsrc2, inclusive. The
arguments rsrc1 and rsrc2 are considered unsigned integers.The uclipu operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
TM1100 Preliminary Data Book Philips Semiconductors
A-170 PRELIMINARY INFORMATION File: ops.fm5, modified 7/23/99
Unsigned compare equalpseudo-op for ieql
SYNTAX[ IF r guard ] ueql r src1 r src2 → r dest
FUNCTIONif rguard then
if rsrc1 = rsrc2 thenrdest ← 1
elserdest ← 0
ATTRIBUTESFunction unit aluOperation code 37Number of operands 2Modifier NoModifier range —Latency 1Issue slots 1, 2, 3, 4, 5
DESCRIPTIONThe ueql operation is a pseudo operation transformed by the scheduler into an ieql with the same arguments.
(Note: pseudo operations cannot be used in assembly files.)The ueql operation sets the destination register, rdest, to 1 if the first argument, rsrc1, is equal to the second
argument, rsrc2; otherwise, rdest is set to 0. The arguments are treated as unsigned integers.The ueql operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 3, r40 = 4 ueql r30 r40 → r80 r80 ← 0
r10 = 0, r60 = 0x100, r30 = 3 IF r10 ueql r60 r30 → r50 no change, since guard is false
Philips Semiconductors DSPCPU Operations for TM1100
File: ops.fm5, modified 7/23/99 PRELIMINARY INFORMATION A-171
Unsigned compare equal with immediate
SYNTAX[ IF r guard ] ueqli( n) r src1 → r dest
FUNCTIONif rguard then
if rsrc1 = n thenrdest ← 1
elserdest ← 0
ATTRIBUTESFunction unit aluOperation code 38Number of operands 1Modifier 7 bitsModifier range 0..127Latency 1Issue slots 1, 2, 3, 4, 5
DESCRIPTIONThe ueqli operation sets the destination register, rdest, to 1 if the first argument, rsrc1, is equal to the opcode
modifier, n; otherwise, rdest is set to 0. The arguments are treated as unsigned integers.The ueqli operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 3 ueqli(2) r30 → r80 r80 ← 0
r30 = 3 ueqli(3) r30 → r90 r90 ← 1
r30 = 3 ueqli(4) r30 → r100 r100 ← 0
r10 = 0, r40 = 0x100 IF r10 ueqli(63) r40 → r50 no change, since guard is false
ATTRIBUTESFunction unit dspmulOperation code 94Number of operands 2Modifier NoModifier range —Latency 3Issue slots 2, 3
DESCRIPTIONAs shown below, the ufir16 operation computes two separate products of the two pairs of corresponding 16-bit
halfwords of rsrc1 and rsrc2; the two products are summed, and the result is written to rdest. All halfwords areconsidered unsigned; thus, the intermediate products and the final sum of products are unsigned. All intermediatecomputations are performed without loss of precision; the final sum of products is clipped into the range [0xffffffff..0]before being written into rdest.
The ufir16 operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
ATTRIBUTESFunction unit dspmulOperation code 90Number of operands 2Modifier NoModifier range —Latency 3Issue slots 2, 3
DESCRIPTIONAs shown below, the ufir8uu operation computes four separate products of the four pairs of corresponding 8-bit
bytes of rsrc1 and rsrc2; the four products are summed, and the result is written to rdest. All values are consideredunsigned. All computations are performed without loss of precision.
The ufir8uu operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
TM1100 Preliminary Data Book Philips Semiconductors
A-174 PRELIMINARY INFORMATION File: ops.fm5, modified 7/23/99
Convert floating-point to unsigned integer usingPCSW rounding mode
SYNTAX[ IF r guard ] ufixieee r src1 → r dest
FUNCTIONif rguard then
rdest ← (unsigned long) ((float)rsrc1)
ATTRIBUTESFunction unit faluOperation code 123Number of operands 1Modifier NoModifier range —Latency 3Issue slots 1, 4
DESCRIPTIONThe ufixieee operation converts the single-precision IEEE floating-point value in rsrc1 to an unsigned integer
and writes the result into rdest. Rounding is according to the IEEE rounding mode bits in PCSW. If rsrc1 isdenormalized, zero is substituted before conversion, and the IFZ flag in the PCSW is set. If ufixieee causes anIEEE exception, such as overflow or underflow, the corresponding exception flags in the PCSW are set. The PCSWexception flags are sticky: the flags can be set as a side-effect of any floating-point operation but can only be reset byan explicit writepcsw operation. The update of the PCSW exception flags occurs at the same time as rdest iswritten. If any other floating-point compute operations update the PCSW at the same time, the net result in eachexception flag is the logical OR of all simultaneous updates ORed with the existing PCSW value for that exceptionflag.
The ufixieeeflags operation computes the exception flags that would result from an individual ufixieee .The ufixieee operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest and the exception flags in PCSW are written;otherwise, rdest is not changed and the operation does not affect the exception flags in PCSW.
ATTRIBUTESFunction unit faluOperation code 124Number of operands 1Modifier NoModifier range —Latency 3Issue slots 1, 4
DESCRIPTIONThe ufixieeeflags operation computes the IEEE exceptions that would result from converting the single-
precision IEEE floating-point value in rsrc1 to an unsigned integer, and an integer bit vector representing thecomputed exception flags is written into rdest. The bit vector stored in rdest has the same format as the IEEEexception bits in the PCSW. The exception flags in PCSW are left unchanged by this operation. Rounding is accordingto the IEEE rounding mode bits in PCSW. If an argument is denormalized, zero is substituted before computing theconversion, and the IFZ bit in the result is set.
The ufixieeeflags operation optionally takes a guard, specified in rguard. If a guard is present, its LSBcontrols the modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is notchanged.
TM1100 Preliminary Data Book Philips Semiconductors
A-176 PRELIMINARY INFORMATION File: ops.fm5, modified 7/23/99
Convert floating-point to unsigned integer withround toward zero
SYNTAX[ IF r guard ] ufixrz r src1 → r dest
FUNCTIONif rguard then
rdest ← (unsigned long) ((float)rsrc1)
ATTRIBUTESFunction unit faluOperation code 125Number of operands 1Modifier NoModifier range —Latency 3Issue slots 1, 4
DESCRIPTIONThe ufixrz operation converts the single-precision IEEE floating-point value in rsrc1 to an unsigned integer and
writes the result into rdest. Rounding toward zero is performed; the IEEE rounding mode bits in PCSW are ignored.This is the preferred rounding mode for ANSI C. If rsrc1 is denormalized, zero is substituted before conversion, andthe IFZ flag in the PCSW is set. If ufixrz causes an IEEE exception, such as overflow or underflow, thecorresponding exception flags in the PCSW are set. The PCSW exception flags are sticky: the flags can be set as aside-effect of any floating-point operation but can only be reset by an explicit writepcsw operation. The update ofthe PCSW exception flags occurs at the same time as rdest is written. If any other floating-point compute operationsupdate the PCSW at the same time, the net result in each exception flag is the logical OR of all simultaneous updatesORed with the existing PCSW value for that exception flag.
The ufixrzflags operation computes the exception flags that would result from an individual ufixrz .The ufixrz operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest and the exception flags in PCSW are written;otherwise, rdest is not changed and the operation does not affect the exception flags in PCSW.
EXAMPLES
Initial Values Operation Result
r30 = 0x40400000 (3.0) ufixrz r30 → r100 r100 ← 3
r35 = 0x40247ae1 (2.57) ufixrz r35 → r102 r102 ← 2, INX flag set
r10 = 0,r40 = 0xff4fffff (–3.402823466e+38)
IF r10 ufixrz r40 → r105 no change, since guard is false
r20 = 1,r40 = 0xff4fffff (–3.402823466e+38)
IF r20 ufixrz r40 → r110 r110 ← 0x0, INV flag set
r45 = 0x7f800000 (+INF)) ufixrz r45 → r112 r112 ← 0xffffffff (232-1), INV flag setr50 = 0xbfc147ae (-1.51) ufixrz r50 → r115 r115 ← 0, INV flag set
ATTRIBUTESFunction unit faluOperation code 126Number of operands 1Modifier NoModifier range —Latency 3Issue slots 1, 4
DESCRIPTIONThe ufixrzflags operation computes the IEEE exceptions that would result from converting the single-precision
IEEE floating-point value in rsrc1 to an unsigned integer, and an integer bit vector representing the computedexception flags is written into rdest. The bit vector stored in rdest has the same format as the IEEE exception bits inthe PCSW. The exception flags in PCSW are left unchanged by this operation. Rounding toward zero is performed;the IEEE rounding mode bits in PCSW are ignored. If an argument is denormalized, zero is substituted beforecomputing the conversion, and the IFZ bit in the result is set.
The ufixrzflags operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controlsthe modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
TM1100 Preliminary Data Book Philips Semiconductors
A-178 PRELIMINARY INFORMATION File: ops.fm5, modified 7/23/99
Convert unsigned integer to floating-point
SYNTAX[ IF r guard ] ufloat r src1 → r dest
FUNCTIONif rguard then
rdest ← (float) ((unsigned long)rsrc1)
ATTRIBUTESFunction unit faluOperation code 127Number of operands 1Modifier NoModifier range —Latency 3Issue slots 1, 4
DESCRIPTIONThe ufloat operation converts the unsigned integer value in rsrc1 to single-precision IEEE floating-point format
and writes the result into rdest. Rounding is according to the IEEE rounding mode bits in PCSW. If ufloat causesan IEEE exception, such as inexact, the corresponding exception flags in the PCSW are set. The PCSW exceptionflags are sticky: the flags can be set as a side-effect of any floating-point operation but can only be reset by an explicitwritepcsw operation. The update of the PCSW exception flags occurs at the same time as rdest is written. If anyother floating-point compute operations update the PCSW at the same time, the net result in each exception flag is thelogical OR of all simultaneous updates ORed with the existing PCSW value for that exception flag.
The ufloatflags operation computes the exception flags that would result from an individual ufloat .The ufloat operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest and the exception flags in PCSW are written;otherwise, rdest is not changed and the operation does not affect the exception flags in PCSW.
EXAMPLES
Initial Values Operation Result
r30 = 3 ufloat r30 → r100 r100 ← 0x40400000 (3.0)
r40 = 0xffffffff (4294967295) ufloat r40 → r105 r105 ← 0x4f800000 (4.294967296e+9), INX flag set
r10 = 0, r50 = 0xfffffffd IF r10 ufloat r50 → r110 no change, since guard is false
r20 = 1, r50 = 0xfffffffd IF r20 ufloat r50 → r115 r115 ← 0x4f800000 (4.294967296e+9), INX flag set
r60 = 0x7fffffff (2147483647) ufloat r60 → r117 r117 ← 0x4f000000 (2.147483648e+9), INX flag set
ATTRIBUTESFunction unit faluOperation code 128Number of operands 1Modifier NoModifier range —Latency 3Issue slots 1, 4
DESCRIPTIONThe ufloatflags operation computes the IEEE exceptions that would result from converting the unsigned
integer in rsrc1 to a single-precision IEEE floating-point value, and an integer bit vector representing the computedexception flags is written into rdest. The bit vector stored in rdest has the same format as the IEEE exception bits inthe PCSW. The exception flags in PCSW are left unchanged by this operation. Rounding is according to the IEEErounding mode bits in PCSW.
The ufloatflags operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controlsthe modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
TM1100 Preliminary Data Book Philips Semiconductors
A-180 PRELIMINARY INFORMATION File: ops.fm5, modified 7/23/99
Convert unsigned integer to floating-point withrounding toward zero
SYNTAX[ IF r guard ] ufloatrz r src1 → r dest
FUNCTIONif rguard then
rdest ← (float) ((unsigned long)rsrc1)
ATTRIBUTESFunction unit faluOperation code 119Number of operands 1Modifier NoModifier range —Latency 3Issue slots 1, 4
DESCRIPTIONThe ufloatrz operation converts the unsigned integer value in rsrc1 to single-precision IEEE floating-point
format and writes the result into rdest. Rounding is performed toward zero; the IEEE rounding mode bits in PCSW areignored. This is the preferred rounding mode for ANSI C. If ufloatrz causes an IEEE exception, such as inexact,the corresponding exception flags in the PCSW are set. The PCSW exception flags are sticky: the flags can be set asa side-effect of any floating-point operation but can only be reset by an explicit writepcsw operation. The update ofthe PCSW exception flags occurs at the same time as rdest is written. If any other floating-point compute operationsupdate the PCSW at the same time, the net result in each exception flag is the logical OR of all simultaneous updatesORed with the existing PCSW value for that exception flag.
The ufloatrzflags operation computes the exception flags that would result from an individual ufloatrz .The ufloatrz operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest and the exception flags in PCSW are written;otherwise, rdest is not changed and the operation does not affect the exception flags in PCSW.
ATTRIBUTESFunction unit faluOperation code 120Number of operands 1Modifier NoModifier range —Latency 3Issue slots 1, 4
DESCRIPTIONThe ufloatrzflags operation computes the IEEE exceptions that would result from converting the unsigned
integer in rsrc1 to a single-precision IEEE floating-point value, and an integer bit vector representing the computedexception flags is written into rdest. The bit vector stored in rdest has the same format as the IEEE exception bits inthe PCSW. The exception flags in PCSW are left unchanged by this operation. Rounding is performed toward zero;the IEEE rounding mode bits in PCSW are ignored.
The ufloatrzflags operation optionally takes a guard, specified in rguard. If a guard is present, its LSBcontrols the modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is notchanged.
TM1100 Preliminary Data Book Philips Semiconductors
A-182 PRELIMINARY INFORMATION File: ops.fm5, modified 7/23/99
Unsigned compare greater or equal
SYNTAX[ IF r guard ] ugeq r src1 r src2 → r dest
FUNCTIONif rguard then
if (unsigned)rsrc1 >= (unsigned)rsrc2 thenrdest ← 1
elserdest ← 0
ATTRIBUTESFunction unit aluOperation code 35Number of operands 2Modifier NoModifier range —Latency 1Issue slots 1, 2, 3, 4, 5
DESCRIPTIONThe ugeq operation sets the destination register, rdest, to 1 if the first argument, rsrc1, is greater than or equal to
the second argument, rsrc2; otherwise, rdest is set to 0. The arguments are treated as unsigned integers.The ugeq operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 3, r40 = 4 ugeq r30 r40 → r80 r80 ← 0
r10 = 0, r60 = 0x100, r30 = 3 IF r10 ugeq r60 r30 → r50 no change, since guard is false
Philips Semiconductors DSPCPU Operations for TM1100
File: ops.fm5, modified 7/23/99 PRELIMINARY INFORMATION A-183
Unsigned compare greater or equal with immediate
SYNTAX[ IF r guard ] ugeqi( n) r src1 → r dest
FUNCTIONif rguard then
if (unsigned)rsrc1 >= (unsigned)n thenrdest ← 1
elserdest ← 0
ATTRIBUTESFunction unit aluOperation code 36Number of operands 1Modifier 7 bitsModifier range 0..127Latency 1Issue slots 1, 2, 3, 4, 5
DESCRIPTIONThe ugeqi operation sets the destination register, rdest, to 1 if the first argument, rsrc1, is greater than or equal to
the opcode modifier, n; otherwise, rdest is set to 0. The arguments are treated as unsigned integers.The ugeqi operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 3 ugeqi(2) r30 → r80 r80 ← 1
r30 = 3 ugeqi(3) r30 → r90 r90 ← 1
r30 = 3 ugeqi(4) r30 → r100 r100 ← 0
r10 = 0, r40 = 0x100 IF r10 ugeqi(63) r40 → r50 no change, since guard is false
TM1100 Preliminary Data Book Philips Semiconductors
A-184 PRELIMINARY INFORMATION File: ops.fm5, modified 7/23/99
Unsigned compare greater
SYNTAX[ IF r guard ] ugtr r src1 r src2 → r dest
FUNCTIONif rguard then
if (unsigned)rsrc1 > (unsigned)rsrc2 thenrdest ← 1
elserdest ← 0
ATTRIBUTESFunction unit aluOperation code 33Number of operands 2Modifier NoModifier range —Latency 1Issue slots 1, 2, 3, 4, 5
DESCRIPTIONThe ugtr operation sets the destination register, rdest, to 1 if the first argument, rsrc1, is greater than the second
argument, rsrc2; otherwise, rdest is set to 0. The arguments are treated as unsigned integers.The ugtr operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 3, r40 = 4 ugtr r30 r40 → r80 r80 ← 0
r10 = 0, r60 = 0x100, r30 = 3 IF r10 ugtr r60 r30 → r50 no change, since guard is false
Philips Semiconductors DSPCPU Operations for TM1100
File: ops.fm5, modified 7/23/99 PRELIMINARY INFORMATION A-185
Unsigned compare greater with immediate
SYNTAX[ IF r guard ] ugtri( n) r src1 → r dest
FUNCTIONif rguard then
if (unsigned)rsrc1 > (unsigned)n thenrdest ← 1
elserdest ← 0
ATTRIBUTESFunction unit aluOperation code 34Number of operands 1Modifier 7 bitsModifier range 0..127Latency 1Issue slots 1, 2, 3, 4, 5
DESCRIPTIONThe ugeqi operation sets the destination register, rdest, to 1 if the first argument, rsrc1, is greater than the opcode
modifier, n; otherwise, rdest is set to 0. The arguments are treated as unsigned integers.The ugeqi operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 3 ugtri(2) r30 → r80 r80 ← 1
r30 = 3 ugtri(3) r30 → r90 r90 ← 0
r30 = 3 ugtri(4) r30 → r100 r100 ← 0
r10 = 0, r40 = 0x100 IF r10 ugtri(63) r40 → r50 no change, since guard is false
ATTRIBUTESFunction unit dmemOperation code 197Number of operands 1Modifier NoModifier range —Latency 3Issue slots 4, 5
DESCRIPTIONThe uld16 operation is a pseudo operation transformed by the scheduler into an uld16d(0) with the same
argument. (Note: pseudo operations cannot be used in assembly source files.)The uld16 operation loads the 16-bit memory value from the address contained in rsrc1, zero extends it to 32 bits,
and writes the result in rdest. If the memory address contained in rsrc1 is not a multiple of 2, the result of uld16 isundefined but no exception will be raised. This load operation is performed as little-endian or big-endian depending onthe current setting of the bytesex bit in the PCSW.
The result of an access by uld16 to the MMIO address aperture is undefined; access to the MMIO aperture isdefined only for 32-bit loads and stores.
The uld16 operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register and the occurrence of side effects. If the LSB of rguard is 1, rdest is written andthe data cache status bits are updated if the addressed locations are cacheable. if the LSB of rguard is 0, rdest is notchanged and uld16 has no side effects whatever.
r50 = 0xd01 uld16 r50 → r90 r90 undefined (0xd01 is not a multiple of 2)
SEE ALSOuld16d ild16 ild16d uld16r
ild16r uld16x ild16x
uld16
TM1100 Preliminary Data Book Philips Semiconductors
A-188 PRELIMINARY INFORMATION File: ops.fm5, modified 7/23/99
Unsigned 16-bit load with displacement
SYNTAX[ IF r guard ] uld16d( d) r src1 → r dest
FUNCTIONif rguard then
if PCSW.bytesex = LITTLE_ENDIAN then bs ← 1
else bs ← 0
temp<7:0> ← mem[rsrc1 + d + (1 ⊕ bs)]temp<15:8> ← mem[rsrc1 + d + (0 ⊕ bs)]rdest ← zero_ext16to32(temp<15:0>)
ATTRIBUTESFunction unit dmemOperation code 197Number of operands 1Modifier 7 bitsModifier range –128..126 by 2Latency 3Issue slots 4, 5
DESCRIPTIONThe uld16d operation loads the 16-bit memory value from the address computed by rsrc1 + d, zero extends it to
32 bits, and writes the result in rdest. The d value is an opcode modifier, must be in the range –128 and 126 inclusive,and must be a multiple of 2. If the memory address computed by rsrc1 + d is not a multiple of 2, the result of uld16dis undefined but no exception will be raised. This load operation is performed as little-endian or big-endian dependingon the current setting of the bytesex bit in the PCSW.
The result of an access by uld16d to the MMIO address aperture is undefined; access to the MMIO aperture isdefined only for 32-bit loads and stores.
The uld16d operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register and the occurrence of side effects. If the LSB of rguard is 1, rdest is written andthe data cache status bits are updated if the addressed locations are cacheable. if the LSB of rguard is 0, rdest is notchanged and uld16d has no side effects whatever.
ATTRIBUTESFunction unit dmemOperation code 198Number of operands 2Modifier NoModifier range —Latency 3Issue slots 4, 5
DESCRIPTIONThe uld16r operation loads the 16-bit memory value from the address computed by rsrc1 + rsrc2, zero extends it
to 32 bits, and writes the result in rdest. If the memory address computed by rsrc1 + rsrc2 is not a multiple of 2, theresult of uld16r is undefined but no exception will be raised. This load operation is performed as little-endian or big-endian depending on the current setting of the bytesex bit in the PCSW.
The result of an access by uld16r to the MMIO address aperture is undefined; access to the MMIO aperture isdefined only for 32-bit loads and stores.
The uld16r operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register and the occurrence of side effects. If the LSB of rguard is 1, rdest is written andthe data cache status bits are updated if the addressed locations are cacheable. if the LSB of rguard is 0, rdest is notchanged and uld16r has no side effects whatever.
ATTRIBUTESFunction unit dmemOperation code 199Number of operands 2Modifier NoModifier range —Latency 3Issue slots 4, 5
DESCRIPTIONThe uld16x operation loads the 16-bit memory value from the address computed by rsrc1 + 2×rsrc2, zero extends
it to 32 bits, and writes the result in rdest. If the memory address computed by rsrc1 + 2×rsrc2 is not a multiple of 2,the result of uld16x is undefined but no exception will be raised. This load operation is performed as little-endian orbig-endian depending on the current setting of the bytesex bit in the PCSW.
The result of an access by uld16x to the MMIO address aperture is undefined; access to the MMIO aperture isdefined only for 32-bit loads and stores.
The uld16x operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register and the occurrence of side effects. If the LSB of rguard is 1, rdest is written andthe data cache status bits are updated if the addressed locations are cacheable. if the LSB of rguard is 0, rdest is notchanged and uld16x has no side effects whatever.
r70 = 0xd01, r30 = 1 uld16x r70 r30 → r110 r110 undefined (0xd01 + 2×1 is not a multi-ple of 2)
SEE ALSOuld16 ild16 uld16d ild16d
uld16r ild16r ild16x
uld16x
Philips Semiconductors DSPCPU Operations for TM1100
File: ops.fm5, modified 7/23/99 PRELIMINARY INFORMATION A-191
Unsigned 8-bit loadpseudo-op for uld8d(0)
SYNTAX[ IF r guard ] uld8 r src1 → r dest
FUNCTIONif rguard then
rdest ← zero_ext8to32(mem[rsrc1])
ATTRIBUTESFunction unit dmemOperation code 8Number of operands 1Modifier NoModifier range —Latency 3Issue slots 4, 5
DESCRIPTIONThe uld8 operation is a pseudo operation transformed by the scheduler into an uld8d(0) with the same
argument. (Note: pseudo operations cannot be used in assembly source files.)The uld8 operation loads the 8-bit memory value from the address contained in rsrc1, zero extends it to 32 bits,
and writes the result in rdest. This operation does not depend on the bytesex bit in the PCSW since only a single byteis loaded.
The result of an access by uld8 to the MMIO address aperture is undefined; access to the MMIO aperture isdefined only for 32-bit loads and stores.
The uld8 operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register and the occurrence of side effects. If the LSB of rguard is 1, rdest is written andthe data cache status bits are updated if the addressed location is cacheable. if the LSB of rguard is 0, rdest is notchanged and uld8 has no side effects whatever.
TM1100 Preliminary Data Book Philips Semiconductors
A-192 PRELIMINARY INFORMATION File: ops.fm5, modified 7/23/99
Unsigned 8-bit load with displacement
SYNTAX[ IF r guard ] uld8d( d) r src1 → r dest
FUNCTIONif rguard then
rdest ← zero_ext8to32(mem[rsrc1 + d])
ATTRIBUTESFunction unit dmemOperation code 8Number of operands 1Modifier 7 bitsModifier range –64..63Latency 3Issue slots 4, 5
DESCRIPTIONThe uld8d operation loads the 8-bit memory value from the address computed by rsrc1 + d, zero extends it to 32
bits, and writes the result in rdest. The d value is an opcode modifier in the range –64 to 63 inclusive. This operationdoes not depend on the bytesex bit in the PCSW since only a single byte is loaded.
The result of an access by uld8d to the MMIO address aperture is undefined; access to the MMIO aperture isdefined only for 32-bit loads and stores.
The uld8d operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register and the occurrence of side effects. If the LSB of rguard is 1, rdest is written andthe data cache status bits are updated if the addressed location is cacheable. if the LSB of rguard is 0, rdest is notchanged and uld8d has no side effects whatever.
Philips Semiconductors DSPCPU Operations for TM1100
File: ops.fm5, modified 7/23/99 PRELIMINARY INFORMATION A-193
Unsigned 8-bit load with index
SYNTAX[ IF r guard ] uld8r r src1 r src2 → r dest
FUNCTIONif rguard then
rdest ← zero_ext8to32(mem[rsrc1 + rsrc2])
ATTRIBUTESFunction unit dmemOperation code 194Number of operands 2Modifier NoModifier range —Latency 3Issue slots 4, 5
DESCRIPTIONThe uld8r operation loads the 8-bit memory value from the address computed by rsrc1 + rsrc2, zero extends it to
32 bits, and writes the result in rdest. This operation does not depend on the bytesex bit in the PCSW since only asingle byte is loaded.
The result of an access by uld8r to the MMIO address aperture is undefined; access to the MMIO aperture isdefined only for 32-bit loads and stores.
The uld8r operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register and the occurrence of side effects. If the LSB of rguard is 1, rdest is written andthe data cache status bits are updated if the addressed location is cacheable. if the LSB of rguard is 0, rdest is notchanged and uld8r has no side effects whatever.
TM1100 Preliminary Data Book Philips Semiconductors
A-194 PRELIMINARY INFORMATION File: ops.fm5, modified 7/23/99
Unsigned compare less or equalpseudo-op for ugeq
SYNTAX[ IF r guard ] uleq r src1 r src2 → r dest
FUNCTIONif rguard then
if (unsigned)rsrc1 <= (unsigned)rsrc2 thenrdest ← 1
elserdest ← 0
ATTRIBUTESFunction unit aluOperation code 35Number of operands 2Modifier NoModifier range —Latency 1Issue slots 1, 2, 3, 4, 5
DESCRIPTIONThe uleq operation is a pseudo operation transformed by the scheduler into an ugeq with the arguments
exchanged (uleq ’s rsrc1 is ugeq ’s rsrc2 and vice versa). (Note: pseudo operations cannot be used in assemblysource files.)
The uleq operation sets the destination register, rdest, to 1 if the first argument, rsrc1, is less than or equal to thesecond argument, rsrc2; otherwise, rdest is set to 0. The arguments are treated as unsigned integers.
The uleq operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 3, r40 = 4 uleq r30 r40 → r80 r80 ← 1
r10 = 0, r60 = 0x100, r30 = 3 IF r10 uleq r60 r30 → r50 no change, since guard is false
Philips Semiconductors DSPCPU Operations for TM1100
File: ops.fm5, modified 7/23/99 PRELIMINARY INFORMATION A-195
Unsigned compare less or equal with immediate
SYNTAX[ IF r guard ] uleqi( n) r src1 → r dest
FUNCTIONif rguard then
if (unsigned)rsrc1 <= (unsigned)n thenrdest ← 1
elserdest ← 0
ATTRIBUTESFunction unit aluOperation code 43Number of operands 1Modifier 7 bitsModifier range 0..127Latency 1Issue slots 1, 2, 3, 4, 5
DESCRIPTIONThe uleqi operation sets the destination register, rdest, to 1 if the first argument, rsrc1, is less than or equal to the
opcode modifier, n; otherwise, rdest is set to 0. The arguments are treated as unsigned integers.The uleqi operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 3 uleqi(2) r30 → r80 r80 ← 0
r30 = 3 uleqi(3) r30 → r90 r90 ← 1
r30 = 3 uleqi(4) r30 → r100 r100 ← 1
r10 = 0, r40 = 0x100 IF r10 uleqi(63) r40 → r50 no change, since guard is false
TM1100 Preliminary Data Book Philips Semiconductors
A-196 PRELIMINARY INFORMATION File: ops.fm5, modified 7/23/99
Unsigned compare lesspseudo-op for ugtr
SYNTAX[ IF r guard ] ules r src1 r src2 → r dest
FUNCTIONif rguard then
if (unsigned)rsrc1 < (unsigned)rsrc2 thenrdest ← 1
elserdest ← 0
ATTRIBUTESFunction unit aluOperation code 33Number of operands 2Modifier NoModifier range —Latency 1Issue slots 1, 2, 3, 4, 5
DESCRIPTIONThe ules operation is a pseudo operation transformed by the scheduler into an ugtr with the arguments
exchanged (ules ’s rsrc1 is ugtr ’s rsrc2 and vice versa). (Note: pseudo operations cannot be used in assemblysource files.)
The ules operation sets the destination register, rdest, to 1 if the first argument, rsrc1, is less than the secondargument, rsrc2; otherwise, rdest is set to 0. The arguments are treated as unsigned integers.
The ules operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 3, r40 = 4 ules r30 r40 → r80 r80 ← 1
r10 = 0, r60 = 0x100, r30 = 3 IF r10 ules r60 r30 → r50 no change, since guard is false
Philips Semiconductors DSPCPU Operations for TM1100
File: ops.fm5, modified 7/23/99 PRELIMINARY INFORMATION A-197
Unsigned compare less with immediate
SYNTAX[ IF r guard ] ulesi( n) r src1 → r dest
FUNCTIONif rguard then
if (unsigned)rsrc1 < (unsigned)n thenrdest ← 1
elserdest ← 0
ATTRIBUTESFunction unit aluOperation code 41Number of operands 1Modifier 7 bitsModifier range 0..127Latency 1Issue slots 1, 2, 3, 4, 5
DESCRIPTIONThe ulesi operation sets the destination register, rdest, to 1 if the first argument, rsrc1, is less than the opcode
modifier, n; otherwise, rdest is set to 0. The arguments are treated as unsigned integers.The ulesi operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 3 ulesi(2) r30 → r80 r80 ← 0
r30 = 3 ulesi(3) r30 → r90 r90 ← 0
r30 = 3 ulesi(4) r30 → r100 r100 ← 1
r10 = 0, r40 = 0x100 IF r10 ulesi(63) r40 → r50 no change, since guard is false
ATTRIBUTESFunction unit dspaluOperation code 64Number of operands 2Modifier NoModifier range —Latency 2Issue slots 1, 3
DESCRIPTIONAs shown below, the ume8ii operation computes four separate differences of the four pairs of corresponding
signed 8-bit bytes of rsrc1 and rsrc2; the absolute values of the four differences are summed, and the sum is written tordest. All computations are performed without loss of precision.
The ume8ii operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
ATTRIBUTESFunction unit dspaluOperation code 26Number of operands 2Modifier NoModifier range —Latency 2Issue slots 1, 3
DESCRIPTIONAs shown below, the ume8uu operation computes four separate differences of the four pairs of corresponding
unsigned 8-bit bytes of rsrc1 and rsrc2. The absolute values of the four differences are summed and the result iswritten to rdest. All computations are performed without loss of precision.
The ume8uu operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
ATTRIBUTESFunction unit ifmulOperation code 138Number of operands 2Modifier NoModifier range —Latency 3Issue slots 2, 3
DESCRIPTIONAs shown below, the umul operation computes the product rsrc1×rsrc2 and writes the least-significant 32 bits of the
full 64-bit product into rdest. The operands are considered unsigned integers. No overflow or underflow detection isperformed.
The umul operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r60 = 0x100 umul r60 r60 → r80 r80 ← 0x10000
r10 = 0, r60 = 0x100, r30 = 0xf11 IF r10 umul r60 r30 → r50 no change, since guard is false
ATTRIBUTESFunction unit ifmulOperation code 140Number of operands 2Modifier NoModifier range —Latency 3Issue slots 2, 3
DESCRIPTIONAs shown below, the umulm operation computes the product rsrc1×rsrc2 and writes the most-significant 32 bits of
the 64-bit product into rdest. The operands are considered unsigned integers.
The umulm operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
Philips Semiconductors DSPCPU Operations for TM1100
File: ops.fm5, modified 7/23/99 PRELIMINARY INFORMATION A-203
Unsigned compare not equalpseudo-op for ineq
SYNTAX[ IF r guard ] uneq r src1 r src2 → r dest
FUNCTIONif rguard then
if rsrc1 != rsrc2 thenrdest ← 1
elserdest ← 0
ATTRIBUTESFunction unit aluOperation code 39Number of operands 2Modifier NoModifier range —Latency 1Issue slots 1, 2, 3, 4, 5
DESCRIPTIONThe uneq operation is a pseudo operation transformed by the scheduler into an ineq . (Note: pseudo operations
cannot be used in assembly source files.)The uneq operation sets the destination register, rdest, to 1 if the two arguments, rsrc1 and rsrc2, are not equal;
otherwise, rdest is set to 0.The uneq operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 3, r40 = 4 uneq r30 r40 → r80 r80 ← 1
r10 = 0, r60 = 0x1000, r30 = 3 IF r10 uneq r60 r30 → r50 no change, since guard is false
TM1100 Preliminary Data Book Philips Semiconductors
A-204 PRELIMINARY INFORMATION File: ops.fm5, modified 7/23/99
Unsigned compare not equal with immediate
SYNTAX[ IF r guard ] uneqi( n) r src1 → r dest
FUNCTIONif rguard then
if (unsigned)rsrc1 != (unsigned)n thenrdest ← 1
elserdest ← 0
ATTRIBUTESFunction unit aluOperation code 40Number of operands 1Modifier 7 bitsModifier range 0..127Latency 1Issue slots 1, 2, 3, 4, 5
DESCRIPTIONThe uneqi operation sets the destination register, rdest, to 1 if the first argument, rsrc1, is not equal to the opcode
modifier, n; otherwise, rdest is set to 0. The arguments are treated as unsigned integers.The uneqi operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 3 uneqi(2) r30 → r80 r80 ← 1
r30 = 3 uneqi(3) r30 → r90 r90 ← 0
r30 = 3 uneqi(4) r30 → r100 r100 ← 1
r10 = 0, r40 = 0x100 IF r10 uneqi(63) r40 → r50 no change, since guard is false
Philips Semiconductors DSPCPU Operations for TM1100
File: ops.fm5, modified 7/23/99 PRELIMINARY INFORMATION A-205
Write destination program counter
SYNTAX[ IF r guard ] writedpc r src1
FUNCTIONif rguard then
DPC ← rsrc1
ATTRIBUTESFunction unit fcompOperation code 160Number of operands 1Modifier NoModifier range —Latency 1Issue slots 3
DESCRIPTIONThe writedpc copies the value of rsrc1 to the DPC (Destination Program Counter) processor register. Whenever
a hardware update (during an interruptible jump) and a software update (through a writedpc ) coincide, thesoftware update takes precedence.
Interruptible jumps write their target address to the DPC. The value of DPC is intended to be used by an exception-handling routine as a jump address to resume execution of the program that was running before the exception wastaken.
The writedpc operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of DPC. If the LSB of rguard is 1, DPC is written; otherwise, DPC is unchanged.
EXAMPLES
Initial Values Operation Result
r30 = 0xbeebee writedpc r30 DPC ← 0xbeebee
r20 = 0, r31 = 0xabba IF r20 writedpc r31 no change, since guard is false
TM1100 Preliminary Data Book Philips Semiconductors
A-206 PRELIMINARY INFORMATION File: ops.fm5, modified 7/23/99
Write program control and status word
SYNTAX[ IF r guard ] writepcsw r src1 r src2
FUNCTIONif rguard then
PCSW ← (PCSW & ~rsrc2) | (rsrc1 & rsrc2)
ATTRIBUTESFunction unit fcompOperation code 161Number of operands 1Modifier NoModifier range —Latency 1Issue slots 3
DESCRIPTIONThe writepcsw copies the value of rsrc1 to the PCSW (Program Control and Status Word) processor register
using rsrc2 as a mask. A bit in PCSW is affected by writepcsw only if the corresponding bit in rsrc2 is set to 1; thevalue of any bit in PCSW with a corresponding 0-bit in rsrc2 will not be changed by writepcsw . Whenever ahardware update (e.g., when a floating-point exception is raised) and a software update (through a writepcsw )coincide, the PCSW bits currently being updated by hardware will reflect the hardware-determined value while the bitsnot being affected by hardware will reflect the value in the writepcsw operand. The layout of PCSW is shownbelow. The programmer should take care not to alter UNDEF fields in the PCSW.
Fields in the PCSW have two chief purposes: to control aspects of processor operation and to record events thatoccur during program execution. Thus, writepcsw can be used to effect changes in some aspects of processoroperation and to clear fields that record events; this operation can also be used to restore state before resuming anidled task in a multi-tasking environment. Note: The latency of writepcsw is 1, i.e. the PCSW reflects the new value inthe next cycle. But it takes additional 3 cycles for updates to the exception flags and exception enable bits to takeeffect in the hardware. Therefore 3 delay slots / nops shall be inserted between writepcsw and the next interruptiblejump, if exception flags or enable bits are changed. This guarantees that the new state is recognized in the interruptlogic during execution of the ijump.
The writepcsw operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of PCSW. If the LSB of rguard is 1, PCSW is written; otherwise, PCSW is unchanged.
IEEE rounding mode0 ⇒ to nearest, 1 ⇒ to zero, 2 ⇒ to positive, 3 ⇒ to negative
Interrupt enable (1 ⇒ allow interrupts)
Byte sex (1 ⇒ little endian)
PCSW<31:16>
PCSW<15:0> UNDEF
Misaligned storeexception trap enable
Trap on first exit
FP exceptions
TRPMSE TFE TRP
OFZTRPIFZ
TRPINV
TRPOVF
TRPUNF
TRPINX
TRPDBZ
1617181920212223252627283031
UNDEF U N D E F I N E D
13
WBE RSE
Write back errorReserved exception
TRPWBE
TRPRSE
Write back error trap enable
Reserved exceptiontrap enable
29
SEE ALSOreadpcsw fadd faddflags
ijmpf cycles hicycles
writepcsw
Philips Semiconductors DSPCPU Operations for TM1100
File: ops.fm5, modified 7/23/99 PRELIMINARY INFORMATION A-207
Write source program counter
SYNTAX[ IF r guard ] writespc r src1
FUNCTIONif rguard then
SPC ← rsrc1
ATTRIBUTESFunction unit fcompOperation code 159Number of operands 1Modifier NoModifier range —Latency 1Issue slots 3
DESCRIPTIONThe writespc copies the value of rsrc1 to the SPC (Source Program Counter) processor register. Whenever a
hardware update (during an interruptible jump) and a software update (through a writespc ) coincide, the softwareupdate takes precedence.
An interruptible jump that is not interrupted (no NMI, INT, or EXC event was pending when the jump was executed)writes its target address to SPC. The value of SPC is intended to allow an exception-handling routine to determine thestart address of the block of scheduled code (called a decision tree) that was executing before the exception wastaken.
The writespc operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of SPC. If the LSB of rguard is 1, SPC is written; otherwise, SPC is unchanged.
EXAMPLES
Initial Values Operation Result
r30 = 0xbeebee writespc r30 SPC ← 0xbeebee
r20 = 0, r31 = 0xabba IF r20 writespc r31 no change, since guard is false
TM1100 Preliminary Data Book Philips Semiconductors
A-208 PRELIMINARY INFORMATION File: ops.fm5, modified 7/23/99
Zero extend 16 bitspseudo-op for pack16lsb
SYNTAX[ IF r guard ] zex16 r src1 → r dest
FUNCTIONif rguard then
rdest ← zero_ext16to32(rsrc1<15:0>)
ATTRIBUTESFunction unit aluOperation code 53Number of operands 1Modifier NoModifier range —Latency 1Issue slots 1, 2, 3, 4, 5
DESCRIPTIONThe zex16 operation is a pseudo operation transformed by the scheduler into a pack16lsb with 0 as the first
argument and rsrc1 as the second. (Note: pseudo operations cannot be used in assembly source files.)As shown below, the zex16 operation zero extends the least-significant 16-bit halfword of the argument, rsrc1, to
32 bits and writes the result in rdest.
The zex16 operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 0xffff0040 zex16 r30 → r60 r60 ← 0x00000040
r10 = 0, r40 = 0xff0fff91 IF r10 zex16 r40 → r70 no change, since guard is false
Philips Semiconductors DSPCPU Operations for TM1100
File: ops.fm5, modified 7/23/99 PRELIMINARY INFORMATION A-209
Zero extend 8 bitspseudo-op for ubytesel
SYNTAX[ IF r guard ] zex8 r src1 → r dest
FUNCTIONif rguard then
rdest ← zero_ext8to32(rsrc1<7:0>)
ATTRIBUTESFunction unit aluOperation code 55Number of operands 1Modifier NoModifier range —Latency 1Issue slots 1, 2, 3, 4, 5
DESCRIPTIONThe zex8 operation is a pseudo operation transformed by the scheduler into a ubytesel with r0 (always contains
0) as the first argument and rsrc1 as the second. (Note: pseudo operations cannot be used in assembly source files.)As shown below, the zex8 operation zero extends the least-significant byte of the argument, rsrc1, to 32 bits and
writes the result in rdest.
The zex8 operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls themodification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
EXAMPLES
Initial Values Operation Result
r30 = 0xffff0040 zex8 r30 → r60 r60 ← 0x00000040
r10 = 0, r40 = 0xff0fff91 IF r10 zex8 r40 → r70 no change, since guard is false
TM1100 Preliminary Data Book Philips Semiconductors
A-210 PRELIMINARY INFORMATION File: ops.fm5, modified 7/23/99
MMIO Register Summary Chapter B
by Gert Slavenburg, and Selliah Rathnam
B.1 MMIO REGISTERS
The following table lists all the MMIO registers implemented in TM1100. The registers are grouped according to theunit to which they belong. For compatibility with future devices, any undefined MMIO bits should be ignored when read,and written as zeroes.
MMIO Register Name Offset (in hex)
Accessibility
DescriptionDSPCPU
External PCI
Initiators
DSPCPU Registers
DRAM_BASE 10 0000 R/W R/W Start of DRAM address aperture
DRAM_LIMIT 10 0004 R/W R/W End of DRAM address aperture
IIC_AR 10 3400 R/W R/W Address, Byte count and Direction
IIC_DR 10 3404 R/W R/W Data Register
IIC_STATUS 10 3408 R/— R/— Status Register
IIC_CTL 10 340C R/W R/W Control Register
Synchronous Serial Interface
SSI_CTL 10 2C00 R/W R/W Control Register
SSI_CSR 10 2C04 R/W R/W Additional Control and Status register
SSI_TXDR 10 2C10 —/W —/W Transmit Data Register
SSI_RXDR 10 2C20 R/— R/— Receive Data Register
SSI_RXACK 10 2C24 —/W —/W Write a ‘1’ here to ACK read of Receive Data Register
SEM Device
SEM 10 0500 R/W R/W Simple muti-processor semaphore
MMIO Register Name Offset (in hex)
Accessibility
DescriptionDSPCPU
External PCI
Initiators
File: mmio.fm5, modified 7/23/99 PRELIMINARY INFORMATION B-5
TM1100 Preliminary Data Book Philips Semiconductors
B-6 PRELIMINARY INFORMATION File: mmio.fm5, modified 7/23/99
Endian-ness Appendix C
by Selliah Rathnam, Luis Lucas
C.1 PURPOSE
TM1100 has been designed in order to support both Lit-tle and Big Endian systems. The PCI system bus (con-trolled by the BIU unit) operates in Little Endian mode inboth systems. This document describes how the dual en-dian-ness feature is handled in TM1100.
C.2 LITTLE AND BIG ENDIAN ADDRESSING CONVENTIONS
In Big Endian mode, a given word address (32-bit) basecorresponds to the most significant byte (MSB) of theword. Increasing the byte address generally means de-creasing the significance of the byte being accessed. InLittle Endian mode, the same word address base refers
to the least significant byte (LSB) of that word. Increasingthe byte address generally means increasing the signifi-cance of the byte being accessed. This addressing con-vention is shown in Figure C-1.
In Figure C-1, there is a two-line ‘C’ code which definesa 32-bit constant in hex format assigned to the variable‘w’ (assumes “int” is 32-bit) and its address is copied intothe byte (character) pointer variable “cp”. The value ofaddress referenced by the “cp” has a value of “0x04” inBig Endian machine and a value of “0x07” in Little Endianmachine.
It is possible to transfer from one endian-ness to anotherjust by swapping the bytes within a word as shown in Fig-ure C-2.
int w = 0x04050607;char *cp = (char *)&w;
Figure C-1. Big and Little Endian address references
031
04 05 06 07
Big Endian Mode Little Endian Mode
cp+0
04 05 06 07
cp+3cp+1 cp+2 cp+3 cp+2 cp+1 cp+0
031
Figure C-2. Data conversion from Big Endian to Little Endian (BSW)
int w = 0x04050607;char *cp = (char *)&w;
031
07 06 05 04
Big Endian Mode
Little Endian Mode
cp+0
04 05 06 07
cp+3
cp+1 cp+2 cp+3
cp+2 cp+1 cp+0
031
File: endian.fm5, modified 7/23/99 PRELIMINARY INFORMATION C-1
TM1100 Preliminary Data Book Philips Semiconductors
C.3 TEST TO VERIFY THE CORRECT OPERATION OF TM1100 IN BIG AND LITTLE ENDIAN SYSTEMS
The following test may be used to verify the correct oper-ation of TM1100 in Little Endian and Big Endian systems.
1. Store a 32-bit constant “0x04050607” from the host CPU to the TM1100’s SDRAM through PCI interface. Load the word from the same address to one of the TM1100’s global register and check for the same val-ue.
2. Store a 32-bit constant “0x04050607” from the host CPU to the TM1100’s SDRAM through PCI interface. Load a byte from the same address to one of the TM1100’s global register. Check for the value of “0x04” in Big Endian systems, and check for the value of “0x07” in Little Endian systems.
C.4 REQUIREMENT FOR THE TM1100 TO OPERATE IN EITHER LITTLE ENDIAN OR BIG ENDIAN MODE
The endian-ness handling in each unit is described in thefollowing sections. Most of the units use Highway/PCIbus to transfer the data. The data format used in eachunit is shown when the data pass through the highway/PCI bus. The highway/PCI bus has four byte lanes. Thebit assignment of the highway/PCI bus lanes is shown inTable C-2.
The PCI and TM1100’s highway buses are address in-variant buses, i.e the data corresponds to address offset“zero” uses the byte-0 lane of the PCI/Hwy bus, the datacorresponds to address offset “one” uses the byte-1 laneof the PCI/Hwy bus etc.
C.4.1 Data Cache
TM1100’s PCSW register has a byte-sex (BSX) bit toconfigure the TM1100 in Big Endian or Little Endianmode. This bit needs to be set to ‘1’ for the Little Endianmode as defined in Chapter 3, “DSPCPU Architecture.”
This BSX bit is used by TM1100’s data cache unit for thestore/load operation from the data cache. Data Cacheperforms three categories of data transactions:
• Read/write data from/to DSPCPU registers to/fromData Cache or SDRAM memory space.
• Read/write of MMIO data from/to DSPCPU registersto/from MMIO registers. and
• Read/write data from/to DSPCPU registers to/fromPCI address space through special registers in theBIU unit.
The DSPCPU’s endian-ness of operation is determinedby the value of the BSX bit in the PCSW register. TableC-1 and Table C-3 describe the data translation formatbeing used by the data cache to transfer the data to/fromDSPCPU register to/from Data Cache or SDRAM. TableC-1 and Table C-3 are restricted to addresses that fall inthe DRAM_BASE and DRAM_LIMIT range.
There is no byte-swap required for the MMIO data trans-action from/to DSPCPU register to the MMIO registers.However, one of the special register, PCI_DATA registerdoes not follow the normal MMIO transactions. The datacache byte-swapes the data to/from the PCI_DATA reg-ister using the data translation format as defined in TableC-1 and Table C-3 for the memory cycle.
For the configuration and I/O cycle transactions fromDSPCPU, programmer byte-swaps the data in DSPCPUregister and write to the PCI_DATA register using MMIOwrite operation. There is no byte-swap from thePCI_DATA register in BIU unit to the PCI bus. Softwareuses the Table C-1 or Table C-3 data to byte-swap thedata within the CPU register before writing the data toPCI_DATA register for the configuration and I/O cycletransactions.
Table C-1. Little Endian data format in TM1100 register, Highway, SDRAM memory, PCI bus, Host memory, Host CPU register
PCSW-BSX value
Endian Mode
Data Transaction type Address
Data in DSPCPU register
msb lsb
Data in Highway/Dcache/SDRAM/
PCI-busbyte3 byte0[31:24] [7:0]
Data in Host CPU registermsb lsb
Data in Host memory
byte3 byte0 [31:24] [7:0]
1 Little Word r/w 00001000 01020304 01020304 01020304 01020304
1 Little Half-Word r/w 00001000 xxxx0304 xxxx0304 xxxx0304 xxxx0304
1 Little Half-Word r/w 00001002 xxxx0304 0304xxxx xxxx0304 0304xxxx
1 Little Byte read/write 00001000 xxxxxx04 xxxxxx04 xxxxxx04 xxxxxx04
1 Little Byte read/write 00001001 xxxxxx04 xxxx04xx xxxxxx04 xxxx04xx
1 Little Byte read/write 00001002 xxxxxx04 xx04xxxx xxxxxx04 xx04xxxx
1 Little Byte read/write 00001003 xxxxxx04 04xxxxxx xxxxxx04 04xxxxxx
Table C-2. Bit assignment of the highway/PCI bus lanes
byte 3 byte 2 byte 1 byte 0
Bits 31:24 23:16 15:8 7:0
C-2 PRELIMINARY INFORMATION File: endian.fm5, modified 7/23/99
Philips Semiconductors Endian-ness
C.4.2 Instruction Cache
It is assumed that the Instruction Cache always operatein Little Endian regardless of the host and TM1100 endi-an-ness. Instruction Cache does not use the PCSW’sbyte sex bit (BSX). The compiler supports the loading ofinstructions in memory differently for Big Endian and Lit-tle Endian modes.
C.4.3 TM1100’s PCI Interface Unit (BIU)
TM1100’s highway bus and the PCI bus are address in-variant buses, i.e. a data corresponding to address zerois always transferred through the byte-zero line regard-less of the endian-ness. This address invariant nature ofthe PCI and the highway buses allows to transfer thedata from/to PCI bus directly to/from SDRAM withoutbyte-swapping in either Big or Little Endian mode Thebyte-swapping of data for Big Endian mode is performedby the Data Cache unit. However, the MMIO data doesnot go through the byte swapper in the Data cache. Thisresults in using a byte-swapper in BIU to byte-swap theMMIO data in Big Endian mode.
TM1100’s PCI interface unit (BIU) has a separate bytesex (SE, Swap Enabled) flag defined in its control regis-ter (BIU_CTL). This byte-sex flag has to be set by thesoftware, i.e. MMIO write operation from the host CPU.This byte-sex flag is used only for MMIO data accessesand non of the MMIO data accesses is affected by thisSE flag. Table C-4 shows the byte-swap logic to handlethe MMIO accesses from DSPCPU, Host CPU and thenon MMIO data accesses from any source.
BIU has several special registers to handle memory, PCIconfiguration, I/O and DMA accesses. BIU does notbyte-swap the in/out data from the special registers.The Data Cache and software does perform the neces-sary byte-swap for this data.
When using TM1100 in Little Endian based systems, thefirst transaction to the TM1100 is to set the SE bit in BIU’sconfiguration register to avoid unnecessary softwarebyte-swapping in the host CPU for the subsequent MMIOread/write accesses. The SE bit in BIU_CTL registercontrols the byte swapping of outgoing and incomingdata from PCI bus. The default value of SE is zero, i.eBIU byte-swapes the MMIO data including the write op-eration to BIU_CTL register. Software is required to byteswap the BIU_CTL register value within the host CPUbefore storing the value in BIU_CTL register. Once, theBIU.SE bit has been set, no additional software byte-swap is required for further read/write operations to anyMMIO registers.
C.4.4 Image Co-Processor (ICP)
The source data for the image co-processor (ICP) mightcome from different places such as Video-in, DSPCPU,PCI bus, etc. through the SDRAM. The data consistencyneeds to be maintained when the TM1100 operates inLittle or Big Endian systems/mode. The ICP needs thecapability to operate on the SDRAM as source data andSDRAM or PCI as destination data in either Little or BigEndian mode. Figure C-3, Figure C-4, Figure C-5 andFigure C-6 illustrate the Big and Little Endian memoryimage format for the image input format (Figure C-3) andthe three supported image overlay formats.
ICP can output the data to either SDRAM or PCI bus.RGB 8R and RGB 8A pixel formats are byte streams andtherefore do not require any swapping in Big Endianmode or Little Endian mode. Figure C-9 pictures the dataformat. RGB-24+α, RGB-15+α, RGB-16 and YUV-4:2:2pixel formats can be used to output the pixels to PCI orSDRAM in both endian mode. Output formats are shown,respectively, in Figure C-4, Figure C-5, Figure C-8, andFigure C-7. Packed RGB-24cannot be used in Big Endi-an mode. Little Endian data format is shown in Figure C-11.
Table C-3. Big Endian data format in TM1100 register, Highway, SDRAM memory, PCI bus, Host memory, Host CPU register
PCSW-BSX value
Endian Mode
Data Transaction type Address
Data in DSPCPU register
msb lsb
Data in Highway/Dcache/SDRAM/
PCI-busbyte3 byte0[31:24] [7:0]
Data in Host CPU registermsb lsb
Data in Host memory
byte0 byte3 [31:24] [7:0]
0 Big Word r/w 00001000 01020304 04030201 01020304 01020304
0 Big Half-Word r/w 00001000 xxxx0304 xxxx0403 xxxx0304 0304xxxx
0 Big Half-Word r/w 00001002 xxxx0304 0403xxxx xxxx0304 xxxx0304
0 Big Byte read/write 00001000 xxxxxx04 xxxxxx04 xxxxxx04 04xxxxxx
0 Big Byte read/write 00001001 xxxxxx04 xxxx04xx xxxxxx04 xx04xxxx
0 Big Byte read/write 00001002 xxxxxx04 xx04xxxx xxxxxx04 xxxx04xx
0 Big Byte read/write 00001003 xxxxxx04 04xxxxxx xxxxxx04 xxxxxx04
Table C-4. BIU.SE bit usage in processing data in BIU unit
BIU.SEvalue
Endian Mode
MMIO access
from DSPCPU
MMIO access
from PCI side
Non MMIO data
0 Big Endian
No byte-swap
Byte-swap No byte-swap
1 Little Endian
No byte-swap
No byte-swap
No byte-swap
File: endian.fm5, modified 7/23/99 PRELIMINARY INFORMATION C-3
TM1100 Preliminary Data Book Philips Semiconductors
Note: A+0 corresponds to byte-zero lane of SDRAM/Hwyand A+3 corresponds to byte-three lane of SDRAM/Hwy
Figure C-3. Byte Mask, Planar YUV 4:2:0 and YUV 4:2:2 for ICP, VO or VI memory data in Little and Big En-dian modes
Y Pixel Byte Data
Y7 Y6 Y5 Y4
Y3 Y2 Y1 Y0
Big Endian Mode Little Endian Mode
in Memory
A+3
(Same for U, V, B)
Y3 Y2 Y1 Y0
Y7 Y6 Y5 Y4
A+3A+2 A+1 A+0 A+2 A+1 A+0
31 31 00
Figure C-4. RBG-24+ α data format for ICP in Little and Big Endian modes
α0R0G0B0Pixel Word Data
α1 R1 G1 B1α1R1G1B1
α0 R0 G0 B0
Big Endian Mode Little Endian Mode
in Memory or PCI
Note: A+0 corresponds to byte-zero lane of SDRAM/Hwy/PCIand A+3 corresponds to byte-three lane of SDRAM/Hwy/PCI
A+3 A+3A+2 A+1 A+0 A+2 A+1 A+0
31 31 00
Figure C-5. RBG-15+ α data format for ICP in Little and Big Endian modes
Pixel Half-Word Data in Memory or PCI
A+3 A+3A+2 A+1 A+0 A+2 A+1 A+0
αR0G’0G0B0αR1G’1G1B1
αR2G’2G2B2αR3G’3G3B3
αR0G’0 G0B0αR1G’1 G1B1
αR2G’2 G2B2αR3G’3 G3B3
Big Endian Mode Little Endian Mode
Pn+1 Pn+1PnPn
31 31 00
Note: A+0 corresponds to byte-zero lane of SDRAM/Hwy/PCIand A+3 corresponds to byte-three lane of SDRAM/Hwy/PCI
C-4 PRELIMINARY INFORMATION File: endian.fm5, modified 7/23/99
Philips Semiconductors Endian-ness
Figure C-6. Packed YUV 4:2:2+ α data format for ICP or VO in Little and Big Endian modes
Pixel Half-Word Data
Big Endian Mode Little Endian Mode
in Memory or PCI
A+3 A+3A+2 A+1 A+0 A+2 A+1 A+0
Pn+1 Pn+1PnPn
U0α0 Y0V0α1 Y1
U1α2 Y2V1α3 Y3
U0α0Y0V0α1Y1
U1α2Y2V1α3Y3
31 31 00
Note: A+0 corresponds to byte-zero lane of SDRAM/Hwy/PCIand A+3 corresponds to byte-three lane of SDRAM/Hwy/PCI
Figure C-7. Packed YUV 4:2:2 data format for ICP in Little and Big Endian modes
Pixel Half-Word Data
Big Endian Mode Little Endian Mode
in Memory or PCI
A+3 A+3A+2 A+1 A+0 A+2 A+1 A+0
Pn+1 Pn+1PnPn
U0 Y0V0 Y1
U1 Y2V1 Y3
U0Y0V0Y1
U1Y2V1Y3
31 31 00
Note: A+0 corresponds to byte-zero lane of SDRAM/Hwy/PCIand A+3 corresponds to byte-three lane of SDRAM/Hwy/PCI
Figure C-8. RBG-16 data format for ICP in Little and Big Endian modes
Pixel Half-Word Data in Memory or PCI
A+3 A+3A+2 A+1 A+0 A+2 A+1 A+0
R0G’0G0B0R1G’1G1B1
R2G’2G2B2R3G’3G3B3
R0G’0 G0B0R1G’1 G1B1
R2G’2 G2B2R3G’3 G3B3
Big Endian Mode Little Endian Mode
Pn+1 Pn+1PnPn
31 31 00
Note: A+0 corresponds to byte-zero lane of SDRAM/Hwy/PCIand A+3 corresponds to byte-three lane of SDRAM/Hwy/PCI
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TM1100 Preliminary Data Book Philips Semiconductors
Figure C-9. RGB8A and RGB8R data format for ICP in Little and Big Endian modes
RGB 8A or 8R
P7 P6 P5 P4
P3 P2 P1 P0
Big Endian Mode Little Endian Mode
in Memory or PCI
A+3
(Same for U, V, B)
P3 P2 P1 P0
P7 P6 P5 P4
A+3A+2 A+1 A+0 A+2 A+1 A+0
31 31 00
Note: A+0 corresponds to byte-zero lane of SDRAM/Hwy/PCIand A+3 corresponds to byte-three lane of SDRAM/Hwy/PCI
Figure C-10. Half-word Swap Within a Half-word (BSH)
031
05 04 07 06
Before swap
After Swap
04 05 06 07
031
Figure C-11. Packed RBG-24 data format for ICP in Little Endian mode only
Pixel Word Data
B1 R0 G0 B0
Big Endian Mode Little Endian Mode
in Memory or PCI
Note: A+0 corresponds to byte-zero lane of SDRAM/Hwy/PCIand A+3 corresponds to byte-three lane of SDRAM/Hwy/PCI
A+3 A+2 A+1 A+0
31 0
R2
G2 B2NOT SUPPORTED
G1R1
R3 G3 B3
C-6 PRELIMINARY INFORMATION File: endian.fm5, modified 7/23/99
Philips Semiconductors Endian-ness
The Table C-5 shows the byte-swap implementation ofvarious pixel formats used in the ICP unit. Refer to FigureC-2 and Figure C-10 for the byte-swap code used in Ta-ble C-4 and Table C-5. Byte-swapping is performed onlyin Big Endian mode. No swapping is done in the Little En-dian mode.
Image Co-Processor has a byte sex bit (L) defined in itsMMIO based configuration register. The setting of thisbyte-sex bit and the BSX bit in the PCSW register should
be equal. This byte-sex bit (L) has to be set by the soft-ware.
C.4.5 Video-In (VI) and Video-Out (VO)
The VI unit stores the YUV pixels in planar 4:2:2 or 4:2:0image format as shown in Figure C-3 and stores the raw8 and 10 bit data as shown in Figure C-12.
The VO unit uses YUV-4:2:2 planar, YUV-4:2:0 planar,and YUV-4:2:2+α packed as input pixel formats. The pla-nar memory image format of the YUV-4:2:2 and YUV-4:2:0 are shown in Figure C-3. The YUV-4:2:2+α memo-ry image format for overlay is pictured in Figure C-6.
The VI and VO units have a byte-sex bit (Little endianand LTL_END) defined in control MMIO registers,VI_CONTROL and VO_CONTROL. The definition ofthese byte-sex bits and the BSX bit in the PCSW registershould be treated as same. Little Endian and LTL_ENDbits have to be set by the software.
C.4.6 Audio-In (AI) and Audio-Out (AO)
The AI and AO units use 8-bit Mono, 8-bit stereo, 16-bitmono and 16-bit stereo data and the memory image for-mat of these data is presented in Figure C-13.
The swapping takes place at byte level and the bits with-in a byte never get disturbed. The AI and AO units havea byte sex bit (LITTLE_ENDIAN) defined in its MMIObased configuration register. The definition of the thesebits and the BSX bit in the PCSW register should betreated as same. This byte sex bit has to be set by thesoftware.
C.4.7 Variable Length Encoder (VLD)
The VLD takes the input from SDRAM in the form of bitstream, with byte aligned starting address and outputs aheader stream and a “run-level” data stream.
The VLD unit has a byte sex bit (LITTLE_ENDIAN) de-fined in its MMIO based configuration register. The defi-
Table C-5. ICP Byte Swapping Type for Input Data
Endian-ness L bit Pixel TypeSwap Type
(see Figure C-2 & Figure C-10 )
Big Endian 0 Y,U,V Planar No Swap
Big Endian 0 RGB 24+α BSW
Big Endian 0 YUV-4:2:2+α BSH
Big Endian 0 RGB 15+α BSH
Table C-6. ICP Byte Swapping Type for Output Data
Endian-ness L bit Pixel TypeSwap Type
(see Figure C-2 & Figure C-10 )
Big Endian 0 RGB 8A: 233
No Swap
Big Endian 0 RGB 8R: 332
No Swap
Big Endian 0 RGB 15+α BSH
Big Endian 0 RGB 16 BSH
Big Endian 0 RGB 24+α BSW
Big Endian 0 RGB24 packed
No support for Big Endian
Big Endian 0 YUV- 4:2:2packed
BSH
Figure C-12. Memory image format for raw 8-bit and 10-bit data
Dn+3 Dn+2 Dn+1 Dn
Big Endian Mode Little Endian Mode
A+3 A+3A+2 A+1 A+0 A+2 A+1 A+0
raw 8-bit datain Memory
Dn+3 Dn+2 Dn+1 Dn
A+3 A+3A+2 A+1 A+0 A+2 A+1 A+0
raw 10-bit datain Memory
Dn+1 Dnlsb msbmsblsb Dn+1 Dn lsbmsbmsb lsb
Note: A+0 corresponds to byte-zero lane of SDRAM/Hwyand A+3 corresponds to byte-three lane of SDRAM/Hwy
lsb is the Least Significant Bytemsb is the Most Significant Byte
File: endian.fm5, modified 7/23/99 PRELIMINARY INFORMATION C-7
TM1100 Preliminary Data Book Philips Semiconductors
nition of the this bit and the BSX bit in the PCSW registershould be treated as same. This byte sex bit has to be setby the software.
Figure C-14 describes the VLD input and output data for-mat as seen in the SDRAM and Highway bus. The input
data is byte oriented and no swapping at VLD is required.However, the output data is read by CPU in terms ofword unit. VLD needs to swap the output bytes within aword as shown in Figure C-14 to compensate for theCPU swap.
Figure C-13. Memory image format for audio data
Ln+3 Ln+2 Ln+1 Ln
Big Endian Mode Little Endian Mode
A+3 A+3A+2 A+1 A+0 A+2 A+1 A+0
8-bit data (Mono)in Memory
Ln+3 Ln+2 Ln+1 Ln
A+3 A+3A+2 A+1 A+0 A+2 A+1 A+0
16-bit data (Mono)in Memory
Ln+1 Lnlsb msbmsblsb Ln+1 Ln lsbmsbmsb lsb
Note: A+0 corresponds to byte-zero lane of SDRAM/Hwyand A+3 corresponds to byte-three lane of SDRAM/Hwy
lsb is the Least Significant Bytemsb is the Most Significant Byte
Rn+1 Ln+1 Rn Ln
A+3 A+3A+2 A+1 A+0 A+2 A+1 A+0
8-bit data (Stereo)in Memory
Rn+1 Ln+1 Rn Ln
A+3 A+3A+2 A+1 A+0 A+2 A+1 A+0
16-bit data (Stereo)in Memory
Rn Lnlsb msbmsblsb Rn Ln lsbmsbmsb lsb
Figure C-14. VLD input and output data format
Byten+3 Byten+2 Byten+1 Byten
Big Endian Mode Little Endian Mode
A+3 A+3A+2 A+1 A+0 A+2 A+1 A+0
Input data Byten+3 Byten+2 Byten+1 Byten
12 34 56 78
A+3 A+3A+2 A+1 A+0 A+2 A+1 A+0
Header OutputHeader = 0x12345678
Note: A+0 corresponds to byte-zero lane of SDRAM/Hwyand A+3 corresponds to byte-three lane of SDRAM/Hwy
12345678
12 34 56 78
A+3 A+3A+2 A+1 A+0 A+2 A+1 A+0
Run Level OutputRun value = 0x1234Level value = 0x5678
12345678
At word Address A
C-8 PRELIMINARY INFORMATION File: endian.fm5, modified 7/23/99
Philips Semiconductors Endian-ness
C.4.8 Synchronous Serial Interface
The synchronous serial interface (SSI) unit has I/O con-nections through the external serial pins and also to theinternal 32-bit data highway via MMIO transactions. Theminimum quantity of data to be analyzed by CPU is 16-bits (i.e. one half word). The SSI uses a 16-bit or 1-bit en-dian-ness and it is detailed in Section 16.8 on page 16-7. The 32-bit quantity contained in the CPU register iswritten or read as is into/from SSI MMIO register. EMSbit in SSI_CTL allows to determine which half-word (16-bit) is sent first as pictured in Figure C-15.
C.4.9 Compiler
The compiler supports the loading of instruction in mem-ory differently for Big Endian and Little Endian modes.
C.5 SUMMARY
TM1100 is required to operate in the same endian-nessas the host CPU. TM1100 operates by default in Big En-dian mode and no special steps are required to set theEndian bits in the TM1100. When using the TM1100 inLittle Endian systems, the first transaction to the TM1100is to set the SE bit in the TM1100’s BIU_CTL register asdescribed in the second paragraph of Section 10.7.5 onpage 10-11.
Index-2 PRELIMINARY INFORMATION File: bookix.fm, modified 7/25/99
A B C HED F G I J K L M N O P Q R S T U V W X Y Z
memory hole 5-5miss processing order 5-4, 5-8miss transfer order 5-3MMIO registers summary 5-13noncachable region 5-3non-cacheable region 5-5number of sets 5-3operation ordering 5-7overview 5-1overview,memory system 5-1parameters 5-3partial word transfers 5-4partial words 5-3performance evaluation support 5-13performance events
table 5-13ports 5-3rdstatus result format 5-6rdtag result format 5-6replacement policies 5-3, 5-4replacement policy 5-9scheduling constraint 5-4set 5-3size 5-3special data cache operations 5-5special opcodes 5-4special operation ordering 5-7status operations 5-6, 5-7summary of characteristics 5-2tag field of address 5-3tag operations 5-6, 5-7valid bits 5-3word in set 5-3write misses 5-4
cache line sizePCI interface register 10-7
carry A-17CCCOUNT
definition 3-3CCIR 656
line timingdescription 7-5
pixel timingdescription 7-4
video connector on video out unit,picture 7-2CCIR 656 frame timing
description 7-5description table 7-5
CCIR 656 line timingpicture 7-5
CCIR 656 pixel timingpicture 7-4
CCIR656 serial D1 7-2
chromakeying 13-1
chroma keying 13-1, 13-9circuit board design
guidelines 11-7class code
PCI interface register 10-6codec 8-1coherency 5-4coherency,instruction cache 5-9command ID
Index-12 PRELIMINARY INFORMATION File: bookix.fm, modified 7/25/99
A B C HED F G I J K L M N O P Q R S T U V W X Y Z
cache line size 10-7class code 10-6command
fields 10-5command ID 10-3device ID 10-3DRAM_BASE 10-7expansion ROM base address 10-9header type 10-7interrupt line 10-9interrupt pin 10-9latency timer 10-7max_lat 10-9min_gnt 10-9MMIO_BASE 10-7revision ID 10-6status 10-5
fields 10-6vendor ID 10-3
single word load/store 10-2target of operations 10-3
V.34 interfaceblock diagram 16-2, 16-3, 16-4external pins,table 16-1programming model 16-8setup of SSI_CTL register 16-5test modes 16-8transmitter logic model 16-5used as general purpose I/O
File: bookix.fm, modified 7/25/99 PRELIMINARY INFORMATION Index-15
A B C HED F G I J K L M N O P Q R S T U V W X Y Z
16-1, 16-2, 16-3V.34 modem 16-1vectored interrupts 3-9vendor ID
connection to video encoder,picture 7-2connection to video in unit,picture 7-2connection,CCIR656,picture 7-2data streaming 7-18data transfer timing 7-7dds 7-19DDS and PLL setting,examples 7-20error conditions 7-18field definition
