Track F- Designing the kiler soc - sonics

© Sonics, Inc., All rights reserved, May 2011

Designing the Killer SoC: Keeping Pace with InnovationJack Browne, Senior VP, Sales & Marketing

4 May 2011 – ChipEx

2May 2011 © Sonics, Inc., All rights reserved, May 2011

Apple’s success impacts the market leaders

The battle of devices has now become a war of ecosystems . . .Stephen Elop, Nokia CEO, Feb 2011


Market Driver: Internet of Things

100,000

10,000

1,000

100

10

1

M unitsLog scale

1960 1970 1980 1990 2000 2010 2020

Mainframe

1M+ units

Minicomputer

10M+ units

PC

100M+ units

Desktop Internet

1B+ units

Mobile Internet

10B+ units

1,000,000

SmartphoneE readerTabletMP3Cell PhonePDAAutomotive- Telematics- GPS, ABS, AVHome CEWireless Home Appliances

M2M

Source: Morgan Stanley, 2010, Sonics


SoC Design Costs GrowingSoC Design Costs Growing

HW

SW HW-independent SW

HW-dependent SW

HW IP Design

VerificationImplementation

Team Size

ArchitectureIntegration

$15 $20 $25 $30 $35

$26M (90nm)

$42.4M (65nm)

$68.6M (40nm)

$85.6M (28nm)*

-

5

10

15

20

25

30

35

40

45

SoC

M U

nit

Vol

um

es

Expected SoC ASP

NR

E D

esig

n C

osts

So

C V

olu

me

(M#)

10

20

30

40

$26M $26M 90nm 90nm

$42M 65nm

$69M 40nm

$86M 28nm

NR

E D

esig

n C

osts

Expected SoC ASP

SoC Unit Volumes Needed to Reach Breakeven Point

Source: Semico Research, October 2010


Challenge: SoC Architecture TrendsDistributed Heterogeneous Architectures

System On Chip

■ Massive feature integration• Driven by Moore’s Law (supply)

and convergence (demand)

■ Distributed architectures• Higher scalability (and independence)• Sharing memory

■ Multiple processors• (Multicore) CPU• DSP• Special purpose (MPEG, GFX, …)

■ Distributed DMA• Removes centralized DMA bottleneck• Simplifies driver software integration

■ Increasing software complexity• Re-use with multiple platform SoCs• Broader end use market coverage per SoC

with software programmability

CAGR = 18.7%


Concurrency in Consumer SoCs

iScan

iQuant

iScan

iQuant iTransiTrans Recon-

struction

Recon-

structionLoop

Filter

Loop

Filter

Intra

Prediction

Intra

Prediction

MC

Prediction

MC

Prediction

Entropy

Decoding

Entropy

Decoding

Bitstream Decoded

FramesiScan

iQuant

iScan


struction

Recon-

structionLoop

Filter

Loop

Filter

Intra

Prediction

Intra

Prediction

MC

Prediction

MC

Prediction

Entropy

Decoding

Entropy

Decoding

Bitstream Decoded

Frames

H.264 Decode

Audio Decode

Video Out

Transport demux

Consumer SoCs process data in parallel, but communicate…


Concurrency in Consumer SoCs

iScan

iQuant

iScan


struction

Recon-

structionLoop

Filter

Loop

Filter

Intra

Prediction

Intra

Prediction

MC

Prediction

MC

Prediction

Entropy

Decoding

Entropy

Decoding

Bitstream Decoded

FramesiScan

iQuant

iScan


struction

Recon-

structionLoop

Filter

Loop

Filter

Intra

Prediction

Intra

Prediction

MC

Prediction

MC

Prediction

Entropy

Decoding

Entropy

Decoding

Bitstream Decoded

Frames

H.264 Decode

Audio Decode

Video Out

Transport demux

DRAM alternatives: eDRAM, DDRx, LPDDRx, TSV/Wide I/O


■ Applications require massive feature sets

■ Cost, power and performance dictate many IP cores

■ Driving up integration complexity

■ SoC communications:Complexity ~ (# IP Cores)2

Complex SoC Circa 2006: Ad Hoc & Fragile – Marority of designs with in-house solutions

Failure to Abstract Communications Causes High SoC Costs


Complex SoC Circa 2010: 4X More Complex – HELP!!

SoC Design and Verification Carry a High Price Tag


Semico’s View: Subsystems IP market

Computing Subsystem CPU’s (multicore, coherent clusters), Memory resources, etc.,

Multi Media Subsystem Graphics & computing, multi-screen, 3D, etc

Memory Subsystem Memory blocks, Memory i/f (xDDRy, TSV, Wide I/O), Memory Schedulers, Multi-channel, QoS, ECC, etc

Video Subsystem Audio and video codecs

Communications Subsystem

Ethernet, WiFi, 3G, 4G, USB, SerDes, etc.

Security Subsystem: Encryption / Decryption engine, Content Protection, Network Security, SoC Firewalls, Error handling

System Resource Management Subsystem

Virtualized system functionality (Apps and/or OS)e.g. Power management functions, security functions, fine-tuning of memory operations to reduce latency, management of software iterations

Source: Semico: IP Subsystems: The Next IP Market Paradigm, SC106-10 October 2010

IP Subsystem Market Estimated to Grow from $95.8M in 2010 to $880.6M by 2015 with a 55.8% CAGR


Complexity Drives Repartitioning

Applications

Operating System

Device Drivers

HostCPU

IP Core Firmware

IP Cores

Applications

Operating System

HostCPU

IP Core Firmware

IP Cores

Device Drivers

IP Core Delivery Subsystem Delivery

IP Providers To Deliver Complete Subsystems, ReducingSoC Architecture, Verification and Software Costs

IP Providers Need to Deliver Subsystems

© Sonics, Inc., All rights reserved, May 2011

SNAPSonics Network for AMBA Protocol


The problems…

DSP core

L1 cache & SRAM

Bus MatrixL2

SRAM

DSPDMA

SYSTEM RAM (L3)ar

bit

erar

bit

er

arb

iter

arb

iter

Bus Matrix

Data cache

Instr cache

CPU

EBC

SOC

FOC External Memeory

FLASH NAND NOR

SDRAM …

Boot ROM

PPI EBU32

SYSDMA

APPDMA

B SPORT

Viterbi CypherCypher

DSP IRQ FIFO TEP

GSP GSP RTCUSB OTG

SD/ MMC

weel buzz keybBack light

SIM WDT

TimerMCU IRQ

MCU Cipher

A PORT C PORT

GPIO

MCUPBUS

MCUSBUS MC

UR

BU

S

MC

UE

BU

S

RB

US

DS

PB

US

DA

BU

S

DPBUS

SYSL2

APBUS

APB

DD

BU

S

DMABUS

ADABUS

Need to combine buses and bus matrix with different protocols (AXI, AHB,

APB). Components comes from various suppliers: difficult to design, validate

Arbiters need to deal with uniform data width; need to insert data width

converters when required

Need to deal with multiple interfaces types: AHB, AXI, OCP, proprietary…

(ARM, MIPS, Tensilica, ARC, etc.)

Tired of the AHB low performances? (only 1 outstanding transaction)


SNAP is replacing…

Blackfin® DSP core

L1 cache & SRAM

Bus interface unitL2

SRAM

DSPDMA

SYSTEM RAM (L3)ar

bit

erar

bit

er

arb

iter

arb

iter

Bus interface unit

Data cache

Instr cache

ARM926EJS

EBC

SOC

FOC External Memeory

FLASH NAND NOR

SDRAM …

Boot ROM

PPI EBU32

SYSDMA

APPDMA

B SPORT

Viterbi CypherCypher

DSP IRQ FIFO TEP

GSP GSP RTCUSB OTG

SD/ MMC

weel buzz keybBack light

SIM WDT

TimerMCU IRQ

MCU Cipher

A PORT C PORT

GPIO

MCUPBUS

MCUSBUS MC

UR

BU

S

MC

UE

BU

S

RB

US

DS

PB

US

DA

BU

S

DPBUS

SYSL2

APBUS

PBUS

DD

BU

S

DMABUS

ADABUS

•Bus Matrixes

•Protocol translation bridges

•Clock division bridges

•AHB buses

•APB buses


SNAP Architecture overview

■ High performance Interconnect Matrix backbone

• Improved Arbitration• QoS support

■ Master layers to connect up to 8 cores to a Matrix port

■ Slave branches to connect up to 16 slaves to a Matrix port

■ Interconnect Matrix can be split in 2 clusters

• Easier timing closure

• No change in connectivity

■ Optional pipeline registers in agents to support high frequency

• Up to 266MHz in 90nm

• > 300 MHz in 65nm

DSP core

L1 cache & SRAMDSPDMA

CP

U L

ayer

EBU32 DDRC

GS

PG

SP

RT

CU

SB

O

TG

SD

/ M

MC

weel

bu

zzkeyb

Back

ligh

tS

IMW

DT

MC

U

IRQ

MC

U

Cip

her

A P

OR

TC

PO

RT G

PIO

CP

U P

ER

IPH

ER

AL

bran

ch

SY

SD

MA

AP

PD

MA

D c

ach

eI

cach

e

CP

U

SY

SD

MA

Lay

er

XB2XB1

Viterb

i

Cyp

herC

yph

er

DS

P

IRQ

FIF

O

TE

PB

S

PO

RT

DS

P P

ER

IPH

ER

AL

bran

chSYSTEM RAM (L3)

L2 SRAMBoot ROMPPI


SNAP Development Environment

SNAPCapture

SN

AP

Clien

t

SN

AP

Server

Design.xls

RTL Files+ Scripts

PerformanceTestbench

Files

ValidationTestbench

Files

RTL Files+ Scripts

PerformanceTestbench

Files

ValidationTestbench

FilesSNAP Test

SNAP Test

RTL gen

translatorDesign.dsnDesign.dsn

Design_rtl.conf

Cli

ent

Do

wn

load

RT

L G

ener

atio

nP

erfo

rmT

est

ben

chV

alid

atio

n


SNAP advantages

■ Interconnect design involve solving many tradeoffs:• Speed = short wires => pipeline stages

• Pipeline stages = gates = higher power

■ SNAP easy to use tool enable exploration of the interconnect design space:• Give control to the user to select the best choice for its application

• Allow to specify independently connectivity and topology o Find the best topology amongst multiple options

• Capability to insert pipeline registers on critical points of the communication path to ease timing closure


Performance exploration flows

■ Interconnect topology and features (pipelines registers, etc.) impact system performances

• In combination with DRAM subsystem in most SoC

■ SNAP enable easy early performance explorations!

• Masters and slaves replaced by high level models

• Inject a simplified traffic representative of the application

• Test bench automatically generated, can be customized

• Instrumented with monitors• Tools to analyze performances out of

monitors traces

BFM-M1BFM-M1

BFM-M2BFM-M2 SN

AP

SN

AP

BFM-M3BFM-M3

Model-M4Model-M4

BFM-S0BFM-S0

BFM-S1BFM-S1

BFM-S2BFM-S2

Model-SWMModel-SWM

WMphy

Performance scenario

Performance monitors


SNAP Validation approach

■ Each generated SNAP instance is unique

• Validation need generator support!

■ Validation need to ensure:• IP interface protocols are fully

respected (generator)• Internal interconnect

components works as expected (generator)

• Whole interconnect works as expected

■ SNAP deliver a complete validation testbench

• Run on your machine• As simple as typing “make”

■ Extremely robust approach• 150+ design wins for our

technology, not a single production bug

BFM-M1BFM-M1

BFM-M2BFM-M2

Inte

rco

nn

ec

tIn

terc

on

ne

ctBFM-M3BFM-M3

BFM-M4BFM-M4

BFM-S1BFM-S1

BFM-S2BFM-S2

BFM-S3BFM-S3

BFM-S4BFM-S4

Protocols monitors / checkers

Random constraint scenario

Internal checkers


User Input – simple GUI

SNAP GUI demo X_

File Options

Structure Connects Properties Sockets Clocks

_

_

_

_

To add a master to a layer, right click on the layer. A popup menu will appear. Select from the options displayed.

To add components to SNAP rightclick over a hub. A popup menu will appear. Select from the displayedoptions.

__

_

_

layer concurrencyfifo

depth

layer0

optimize

layer1

2

1

1 performance

1 area

Check

TitleMenu Bar

Tool Bar Diagram

Tabbed Notebook Help

Quick Help


You can try it by yourself!

http://www.sonicsinc.com/snap.htm


Summary - Benefits

■ Seamless upgrade path from a multilayer AHB architecture■ Superior Performance, Power, and Area than Competitive Solutions

Using AXI matrix + AHB buses■ Ultra-Low Power

• Automatic clock gating

■ High Performance • Cross-bar structure, separate request / response network, out of order

response completion• AHB multi-ports agents: up to 8x the bandwidth of an AHB bus

■ Supports all popular interfaces• Does all the protocol, data width and clock conversions• No need for bridges• No validation required

■ Lowest Risk• Fully verified IP, guaranteed good-by-design by Sonics

■ Easy Delivery Process and Attractive business model


Industry Leader in System-Level IP

■ Answering the Challenge• Help designers integrate entire

systems onto one piece of silicon and connect any IP on-chip

■ Proven Technology for 15 years• >1 Billion units shipped• >150 designs taped out

■ Key Designs with Semi Leaders• 7 of top 10 SoC semi companies• 4 of top 10 systems companies

■ Pioneering Technology Leader• Pioneer and World’s #1 supplier of

on-chip networks for advanced SoCs• Highest efficiency memory

subsystems

■ Market Leader• Leading supplier of on-chip networks

in digital entertainment, wireless segments

25May 2011 © Sonics, Inc., All rights reserved, May 2011Sonics Confidential

Thank you

Jack [email protected]

Date post:	15-Jan-2015
Category:	Education
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Track F- Designing the kiler soc - sonics

Education