Traffic Route Finder

7/28/2019 Traffic Route Finder

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GPS BASED TRAFFIC ROUTE FINDER

Traffic route finder project based micro controller and IR sensor. Here

we are connecting three sensors in three different locations. The ir

receiver section is connect to the micro controller. If traffic at any

place the vehicle could not move for few seconds or few minutes and

the vehicle is waiting one by one until to traffic clear. If continuously

the vehicle could not move or slowly move the sensor signal will

continually interrupt to the micro controller. The micro controller will

check the interrupt signal and it could not receive any interrupt signal

from the sensor immediately micro controller will display the message

CLEAR .if the sensor receives one interrupt signal the message

will display as NORMAL in the LCD display section. If it receives

two interrupt it display BUSY message and finally it revues three

interrupt signal HEAVY message will display.


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BLOCK DIAGRAM

The first section of the block diagram is an IR transmitter and a

receiver which is used to sense the traffic.

CIRCUIT OPERATION.

The total system can be divided into three groups.

1. Transmitter section

2. Receiver section

3. Controller section

4 Display section.

TRANSMITTER

This system can be implemented at anywhere at places where it is

necessary. The system contains three sensors which are placed in

one route. The system is completely based on infra-red rays. Infra-

red rays are invisible rays. Infrared rays are passed in between the

transmitter and the receiver.The transmitting section is simply driven

by a resistor i.e., a IR transmitting LED is directely connected to the

+Vcc of the system It starts to glow or produce infra red rays from the

IR led transmitting section. The rays produced from the IR led are


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produced as a square wave. These rays are transmitted towards the

receiver section. The LED connected in the transmitting end starts to

glow the infrared rays

RECEIVER:

The receiver section of the When any object passes in between the

sensors the rays gets cut in between the sensors. This ray cut is

sensed by the system and gives signal for the first sense.The signal

received from the from the receiver LED of infrared rays and it will

connect to the micro controller section.


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Sensor:

A sensor is a type of transducer, or mechanism, that responds to a

type of energy by producing another type of energy signal, usually

electrical. They are either direct indicating (an electrical meter) or are

paired with an indicator (perhaps indirectly through an analog to

digital converter, a computer and a display) so that the value sensed

is translated for human understanding. Types of sensors include

electromagnetic, chemical, biological and acoustic. Aside from other

applications, sensors are heavily used in medicine, industry and

robotics.

In order to act as an effectual sensor, the following guidelines must

be met:

the sensor should be sensitive to the measured property the sensor

should be insensitive to any other property the sensor should not

influence the measured property In theory, when the sensor is

working perfectly, the output signal of a sensor is exactly proportional

to the value of the property it is meant to measure. The gain is then

defined as the ratio between output signal and measured property.


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For example, if a sensor measures temperature and has an actual

voltage output, the gain is a constant with the unit.

When the sensor is not perfect, various deviations can occur,

including gain error, long term drift, and noise. These and other

deviations can be classified as systematic, or random, errors.

Systematic deviations may be compensated for by means of some

kind of calibration strategy. Noise is an example of a random error

that can be reduced by signal processing, such as filtering, usually at

the expense of the dynamic behavior of the sensor.

I


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INFRA RED LED

Infra red (IR) LEDs are often used in remote control systems. Here

the IR LED is used to transmit a coded invisible light signal, which is

detected by a matching infrared diode (and subsequently decoded) in

a receiver system some distance away.

To give an adequate remote control range (up to 10m) the IR LED

must pass ON currents of several hundred milliamps, but for practical

reasons the complete transmitter must be small enough to fit into the

hand, must be self powered via an inexpensive battery, and must be

capable of giving many hours of continuous control operation before

needing battery replacement. These conflicting requirements can be

met by using the basic circuit of fig1. Which is driven via the

waveforms shown in fig2.

The coded IR transmitter signal comprises 1ms bursts of 20khz

pulses, repeated at 51ms time base intervals, i.e., at a 1:50M/S-ratio.

The transmitter generates peak IR LED currents of about 600ma,

giving a mean current of 300ma during the mark part of each


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transmitting cycle, but a mean of only 6ma when averaged over the

complete 51ms time base period.

In the actual transmitter, the coded waveform is fed to the base of q2

via r3. when the waveform is high, q2 is driven to saturation, driving

on q1 and LED1 and feeding roughly 600ma into the IR LED via

r1;when the waveform is low, zero current feeds into the IR LED.

Note the capacitor c1 acts as a low impedance energy storage unit

and provided the required high driver currents to their LED; these

currents could not be provided by battery B1 alone.

A simple invisible Light beam intrusion detector or alarm system can

be made by connecting an infra red (IR) light transmitter and receiver

as shown in fig 3. here the transmitter feeds a coded signal (often a

simple square wave) into an IR LED which has its output focused into

a fairly narrow beam (via a moulded-in lens in the LED casing) that is

aimed at a matching IR photo detector (phototransistor or

photodiode) in the remotely placed receiver. The system action is

such that the receiver output is OFF when the light beam reaches the

receiver, but turns on and activates an external alarm, counter or


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relay if the beam is interrupted by a person, animal or object. This

basic type of system can be designed to give an effective detection

range of up to 30m.

System waveforms

Infrared beam systems are usually used in conditions in which high

levels of ambient or background IR radiation (usually generate by

heat sources such as radiators, tungsten lamps and human bodies

etc.,) already exists. To enable the systems to differentiate against

this background radiation and give good effective detection ranges,

the transmitter beams are invariably frequency modulated, and the

receivers are fitted with matching frequency detectors. In practice, the

transmitted beam invariably used either continuous tone or tone burst

frequency modulation, as shown in fig 4.

Infrared LEDs and photo detectors are very fast acting devices, and

the effective range of an IR beam system is thus determined by the

peak current fed into the transmitting LED, rather than by its mean


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LED current. Thus if the waveforms of fig 4 are used in transmitters

giving peak LED currents of 100ma, both systems will give the same

effective operating range, but the fig 4.a, continuous tone transmitter

will consume a mean LED current of 50ma, while the tone burst

system of fig 4.b, will consume a mean current of only 1ma (but will

require more complex circuit design).

The operation parameters of the tone burst waveform system require

some consideration, since the system actually works on the sampling

principle. For example it is a fact that at normal walking speed a

human takes about 200ms to pass any given point, so a practical IR

light beam burglar alarm system does not need to be turned on

continuously, but only needs to be turned on for brief sample periods

at repetition period at repetition periods far less than 200ms. (At say

50 ms) the sample period should be short relative to repetition time,

but long relative to the period of the tone frequency. Thus a good

compromise is to use a 20khz tone with a burst or sample period of

1ms and a repetition time of 50 ms as shown in fig 4.b.


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Transmitter circuit

Fig5. Shows the practical circuit of a simple continuous tone dual light

beam IR transmitter. Here a standard 555 timer IC is wired as an

astable multivibrator that generates a non symmetrical 20khz square

wave output that drives the two IR LEDs at peak output current of

about 400ma via r4 and q1 and the low source impedance of storage

capacitor C1. The timing action of this circuit is such that the ON

period of the LEDs is controlled by C2 and R2, and the OFF period by

C2 and (r1+r2), i.e., so that the LEDs are ON for only about one eight

of each cycle; the circuit thus consumes a mean current of about

50ma.

The above circuit can use either TIL38 or LD271 (or similar) high

power IR LEDs. These devices can handle mean currents up to only

150ma, but can handle brief repetitive peak currents several times

greater than this value. Fig 6 shows the outline and connections of

these devices, which have a moulded-in lens that focuses the output

into a radiating beam of about 60* width; at the edge of this beam the

IR signal strength is half of that at the center of the beam.


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Minor weaknesses of the IR output stage (q1 and r3-r4) of the fig 5.

Circuits are that it has a very low input impedance (about 300R), that

it gives an inverting action (the LEDs are ON when the input is low)

and that the Led output current varies with the circuit supply voltage.

Receiving circuit

All silicon junctions are photosensitive and a photodiode can be

regarded as a conventional diode housed in case that lets external

light reach its photosensitive semiconductor junction. Fig7 shows the

standard photodiode symbol. In use, the photodiode is reverse biased

and the output voltage is taken from across a series connected load

resistor. This resistor may be connected between the diode and

ground, as in fig 8 or between the diode and the positive supply line

as in fig 9.


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The human eye is sensitive to a range of light radiation, as shown in

fig 10. It has a peak spectral response to the color green, which has a

wavelength of about 550nm, but has a relatively low sensitivity to the

color violet (400nm) at one end of the spectrum and to dark red

(700nm) at the other. Photodiodes also have spectral response

characteristics, and these are determined by the chemistry used in

the semiconductor junction material. Fig 10 shows typical response

curves of a general-purpose photodiode, and a infrared (IR)

photodiode.

Photodiodes have a far lower light sensitivity than cadmium sulphide

LDRs, but give a far quicker response to changes in light level.

Generally, LDRs are ideal for use in slow acting direct coupled light

level sensing applications, while photodiodes are ideal for use in fast

acting AC coupled signaling applications. Typical photodiode

applications include IR remote control circuits, IR beam switches and

alarm circuits and photographic flash slave circuits etc.

The signal reaching the photo sensor may at some times be very

weak, and at other times very strong. Also the sensor may be


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subjected to a great deal of noise in the form of unwanted light

(visible or invisible) signals etc. To help minimize these problems the

link is usually operated in the infrared range, and the optosensor

output is passed to processing circuitry via a low noise pre amplifier

with a wide dynamic operating range.

20KHZ selective preamplifier circuit for use in an IR light beam alarm

application, in which the alarm sounds when the beam is broken.

Here the IR photodiode is placed, so that beam signal is lost only

when the diode signals are cut off, and share the load resistor. This

resistor is shunted by C1 to reject unwanted high frequency signals

and the r1 output signal are fed to the *100 op-amp inverting amplifier

via C2, which rejects unwanted low frequency signals. And it follows

a amplification stage and monostable multivibrator section which

gives the output signal in the form

POWER SUPPLY


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The power supply section is an important one. It should delivery

constant output regulated supply for sucessuful working of the

project. A 12V-0-12V / 1 Amp transformer is used for our purpose, the

primary of this transformer is connected to the mains supply through

a ON/OFF switch and a fuse holder for protecting from overload and

short circuit protection. The secondary side is connected to diodes to

convert from 12V ac to 12V dc voltage. Here the diodes are formed

as two full-wave rectifier, one is for delivering +12V to +15V for the

operation of the relay & a Capacitor of 2200mfd/25V is used for

filtering purpose and another side +12V to +15V is fed to the input of

the 7805 regulator IC for getting constant output voltages for the

operation of Digital ICs, & a Capacitor of 1000mfd/25V is used for

filtering purpose to get pure dc voltage.

Low power IC regulators of the 78 series offer the advantages

ofgood regulation, current limiting and short circuit protection at 100

mA and thermal shutdown in the event of excessive power

dissipation. In fact virtually the only way in which these regulators can

be damaged is by


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incorrect polarity or by an excessive input voltage. Regulators

in the 78 series up to the 8v type will withstand input voltages up to

about 35V. Normally, of course, the regulators would not be operated

with such a large input-output differential as this would lead to

excessive power dissipation. A choice of 5V output voltages is offered

inthe 78 series of regulators, as shown below.

Uin Uout Type Imax C1

35V 5 V 7805 100 mA 1000 mfd/25V

All the regulators in the 78 series will deliver a maximum

current of 100 mA provided the input-output voltage differential does

not exceed 7V, otherwise excessive power dissipation will result and

the thermal shutdown will operate. This occurs at a dissipation of

about 700 mW.

A regulator circuit using the 78 is shown in fig. together with

the layout of a suitable printed circuit board. To obtain the rated

output voltages at a current up to 100 mA are given in table 1,


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together with suitable values for the reservoir capacitor, C1. The

capacitance/voltage product of

these capacitors is choosen so that any one of them will fit the

printed circuit board without difficulty.

The microcomputer is making great impact on every activity of

the mankind and is playing and expected to play very important role

in the daily functioning of the developed and developing societies. In

the early years of powerful computers. Larger computers were

designed to solve complex scientific and industrial problems and

handle records of large corporations and Govt. organisations. Only

big industies and institutions were able to purchase large computers.

A trend started in the middle of 60s to design smaller computers for

smaller organisations and institutions. This situation gave the birth

minicomputer in the late 60s which pave the way for smaller

institutions, organisations, offices etc to use computers.

The microcomputer outcome of the trend towards smaller

computers which started in the middle of 60s. With the rapid

advancement in the semiconductor technology it became possible to


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fabricate the whole CPU of a digital computer on a single chip using

LSI and VLSI technology. The LSI technology refers to packing as

many as 1,000 to 10,000

transistors on a single chip. A CPU built into a single LSI or

VLSI chip is called a microprocessor. A digital computer having

microprocessor as the CPU along with memory and I/O devices is

called microcomputer. The prefix micro refers to its physical size, but

not its computing powers. As far as its computing power is

concerned, the latest 32-bit microcomputers are as powerful as a

traditional mainframe computer. Presently it is possible to construct a

microcomputer having most of the features of 3rd generation

mainframe computers using just handful of ICs.

The number of bits that a digital computer can process in

parallel at a time is called its word length. It is a measure of the

computing power of a computer. The microcomputers have word

lengths of a 4-32 bits whereas large computers have 32-64 bits. 4-bit

microprocessors are used for applications in domestic appliances


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control, calculators, video games, toys etc. A calculator is not a

computer as because it is not a programmable device. The user

does not prepare any program for his calculations. He performs

calculations using step by step method. As far as calculators

internal systems is concerned, it is a single chip microcomputer which

contains 4-bit microprocessor as its CPU, semiconductor memory

and I/O devices. The manufacturers have stored permanent

program in on-chip semiconductor memory for making calculations.

The data entered by the user are stored in the memory and utilised

by the processor while making calculations. The manufacturers have

not made any provision for users to enter programs.

A single chip microcomputer is also called a microcontroller.

A single chip microcomputer contains all essential elements of a

microcomputer on a single chip. It contains the CPU, ROM/EPROM,

RAM, I/O ports, timer, counters, decoder, interrupts, ADC etc.

Previously microcomputers were designed using number of chips,

each one meant for different functions. A microcontroller is designed


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for a dedicated application and hence it is called dedicated

microcontroller.

Intel introduced 8048 series of single chip microcomputers in

1976. It is popularly known as MCS-48. It contains a 8-bit CPU,

1/2/4K ROM/EMPROM, 64/128/256 byte RAM, timer/counter, parallel

I/O ports and 8-bit ADC.

In the year 1980, Intel introduced a more powerful

microcontroller series 8051 in the form of a single chip

microcomputer. It has 8-bit CPU, 4/8K ROM/EPROM, 128/256 byte

RAM, timer/counter, parallel I/O ports, serial I/o ports etc. It has

provisions to increase its memory size using external EPROMs and

RAMs.

In 1983, Intel introduced a 16-bit single chip microcomputer

series as MCS-96. It contains 16-bit CPU, 8K ROM, 232 byte RAM,

timer/counter, parallel I/O ports, serial I/O ports, serial I/O ports, 10-


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bit ADC, high speed I/O, pulse width modulated output, watch dog

timer etc. It is used in sophisticated missile guidance control to

complex instrumentation system.

All the standard features of a microcomputer embeded on a

single chip with its performance equal to that of a multiple chip

devices. The integration of all the basic blocks of a microcomputer

system into one circuit brings about some architectural advantages.

When the device is used as a standard one controller, it need

interface only with its I/O peripherals. This means that the execution

speed of the processing is limited only by the speed of the chip,

because there is no slowdown form transfering data between memory

and CPU as in multi chip design. The inclusion of data and program

memories simplifies the users hardware interface problem and

system implementation.


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Examples of single chip microcomputers are Intel 8048,8051

and 8096 series. Motorolas M6801 series, Texas instrument

TMS1000, Atmel 89C51,89C52 and Zilog Z-80. The 16-bit

microcontroller family is 8094/8095/8096/8097 and

8394/8395/8396/8397.

The AT89C51 is a low power, high performance CMOS 8-bit

microcomputer with 4K bytes of flash programmable and erasable

read only memory(PEROM). The device is manufactured using

Atmels high-density nonvolatile memory technology and is

compatible with the industry-standard MCS-51 instruction set and

pinout. The on-chip flash allows the program memory to be

reprogrammed in-system or by a conventional nonvolatile memory

programmer. By combining a versatile 8-bit CPU with flash on a

monolithic chip, the AtmelAT89C51 is a powerful microcomputer

which provides a highly-flexible and cost-effective solution to many

embedded control applications.


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The AT89C51 provides the following standard features: 4K

bytes of flash, 128 bytes of RAM, 32 I/O lines, two 16bit

timer/couters, a five vector two-level interrupt architecture, a full

duplexserial port, on-chip oscillator and clock circuitry. In addition, the

AT89C51 is designed with static logic for operation down to zero

frequency and supports two software selectable power saving modes.

The Idle mode stops the CPU while allowing the RAM,

timer/counters,serial port and interrupt system to continue functioning

. The Power down mode saves the RAM contents but freezes the

oscillator disabling all other chip functions until the next hardware

reset.

PROGRAMMING THE FLASH

The AT89C51 is normally shipped with the on-chip flash

memory array in the erased state (that is, contents=FFH) and ready

to be programmed. The programming interface accepts either a high-

voltage (12volt) or a low voltage(Vcc) program enable signal. The low

voltage programming mode provides a convenient way to program

the AT89C51 inside the users system, while the high-voltage


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programming mode is compatible with conventional third- party flash

or EPROM programmers.

The AT89C51 is shipped with either the high-voltage or low-

voltage programming mode is enabled. The respective top-side

marking and device signature codes are listed below.

Vpp = 12V Vpp = 5V

Top-side mark AT89C51 AT89C51

xxxx xxxx-5

yyww yyww

Signature (030H)= 1EH (030H)=1EH

(031H)= 51H (031H)=51H

(032H)= FFH (032H)=05H

The AT89C51 code memory array is programmed byte-by-byte

in either programming mode. To program any nonblank byte in the

onchip flash memory, the entire memory must be erased using the

Chip erase mode.

Programming Algorithm:


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Before programming the AT89C51, the address, data and

control signals should be set up according to the Flash programming

mode table . To program the AT89C51, take the following steps.

1. Input the desired memory location on the address lines.

2. Input the appropriate data byte on the data lines.

3. Activate the correct combination of control signals.

4. Raise EA/Vpp to 12V for the high-voltage programming

mode.

5. Pulse ALE/PROG once to program a byte in the Flash array

or the lock bits. The byte-write cycle is self-timed and typically takes

no more than 1.5ms. Repeat steps 1 through 5, changing the address

and data for the entire array or until the end of the object file is

reached.

Data polling:

The AT89C51 features Data polling to indicate the end of a

write cycle. During a write cycle, an attempted read ofthe last byte

written will result inthe complement of the written datum on P0.7 .

Once the write cycle has been completed, true data are valid on all


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outputs, and the nextcycle may begin. Data polliing may begin any

time after a write cycle has been initiated.

Ready/Busy:

The progress of byte programming can also be monitored by

the RDY/BSY output signal. P3.4 is pulled low after ALE goes high

during programming to indicate busy. P.3.4 is pulled high again when

programming is done to indicate READY.

Program Verify: If lock bits LB1 and LB2 have not been

programmed, the programmed data codes can be read back via the

addresss and data lines for verification. The lock bits cannot be

verified directly. Verification of the lock bits is achieved by observing

that their features are enabled.

Chip Erase:

The entire flash array is erased electrically by using the proper

combination of control signals and by holding ALE/PROG low for

10ms. The code array is written with all1"s. The chip erase operation

must be executed before the code memory can be re-programmed.


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Reading the Signature Bytes:

The signature bytes are read by the same procedure as a

normal verification of locations 030H, 031H, and 032H, exept that

P3.6 and P3.7 must be pulled to a logic low. The values returned are

as follows.

(030H) = 1EH indicates manufactured by Atmel

(031H) = 51H indicates 89C51

(032H) = FFH indicates 12V programming

(032H) = 05H indicates 5V programming.

Programming Interface

Every code byte in the Flash array can be written and the entire

array can be erased by using the appropriate combination of control

signals. The write operation cycle is selftimed and once initiated, will

automatically time itself to completion.

All major programming vendors offer worldwide support for the

Atmel microcontroller series.

Vss > Circuit ground potential


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Vcc > Supply voltage during programming, verification and

normal operation.

I/O port pins and their functions

> Port-0 is an 8-bit port .It can be used for input or output. To

use the pins of port 0 as both input or output ports, each pin must be

connected to externally to 10K ohm pull-up resistor. This is due to the

fact that P0 is an open drain, unlike P1,P2 and P3. Open drain is a

term used for MOS chips in the same way the open collector is used

forTTL chips. In IN 89C51 we connect port 0 to pullup resistors.With

external pull up resistor upon reset, port 0 is configureds as an output

port . For example the following codes will continuosly send out port 0

the alternating values 55H and AAH.

MOV A, #55H

BACK: MOV P0,A

ACALL DELAY

CPL A

SJMP BACK

Port 0 as input:

With resistors connected to port 0, in order to make it an input,

the port must be programmed by writing 1 to all the bits. In the


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following code, port 0 is configured as an input port by writing 1s to it,

and then data is received from that port and send to p1.

MOV A, #0FFH

MOV P0, A

BACK: MOV A, P0

MOV P1,A

SJMP BACK

Dual role of port 0

Port 0 is also designated as AD0 - AD7, allowing it to be used

for both address and data. When connecting 8951 to external

memory , port0 provides both address and data. The 8951

multiplexes address and data through port 0 to save pins .ALE

indicates if P0 has address or data . When ALE=0, it provides data

D0- D7 , but when ALE =1 it has address A0- A7. Therefore ALE is

used to demultiplexing address and data with

the help of a 74LS373 latch.

Port1:

Port1 occupies a total of 8 pins. It can be used as input or

output. In contrast to port0, this does not need any pull up resistor


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since it is already has pull-up resistors internally. Upon reset, port1

configured as output port.

For example, the following codes will continuosly send out to

port 1 the alternating values 55H and AAh.

MOV A, #55HBACK: MOV P1,A ACALL DELAY CPL

A SJMP BACK

Port1 as input

To make port 1 as an input port, it must be programmed as

such by writing 1 to all its bits. In the following code port 1 is

configured first as input port by writing 1s to it, then data is received

from the port and saved in R7,R6 and R5.

MOV A,#0FFH MOV P1,A MOV A,P1

MOV R7,A

ACALL DELAY MOV A,P1

MOV R6,A

ACALL DELAY


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MOV A,P1 MOV R5,A

Port 2:

Port 2 occupies a totalof 8 pins. It can be used as input or

output. Just like P1, port2 does not need pull-up resistors since it has

pullup resistors internally. Upon reset,port 2 configured as an output

port . For example the following code will send out continuosly to port

2 the alternating values 55H and AAH. That is ,all the bits of P2

toggle continuosly.

MOV A, #55H

BACK: MOV P2,A

ACALL DELAY

CPL A

SJMP BACK

Port 2 as input

To make port 2 an input , it must be programmed as such by

writing 1 to all its bits. In the following code, port2 is configured as an

input port by writing 1s to it .Then data is received from that port and

is send P1 continuosly.

MOV A,#0FFH

MOV P2,A


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BACK: MOV A,P2

MOV P1,A

SJMP BACK

Dual role of port 2

In systems based on the 8751, 89C51, P2 is used as simple

I/O. However, in 8031 based systems port2 must be used along with

P0 to provide 16bit address for the external memory. Port 2 is also

designated as A8- A15, indicating its dual function.Since an 8031 is

capable of accessing 64K bytes for external memory, it needs a path

for the 16 bit address . While the P0 provides 8 bit via A0-A7 it is the

job of P2 to provide bits A8-A15 of the address.

Port 3:

Port 3 occupies a total of 8 pins ,pins 10 through 17. It can be

used as input or output.P3 does not need any pull up resistors, the

same as P1 and P2 did not. Although port 3 is configured as an

output port upon reset, this is not the way it is most commonly used.


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Port 3 has the additional function of providing some extremely

important signals such as interrupts.

P3.0 and P3.1 is used for the RxD and TxD serial

communication signals.P3.2 and P3.3 is used to provide external

interrupts.Bits P3.4 and P3.5 for timers and finally P3.6 and p3.7 are

used for WR and RD signals.

Port-3 can sink/source four LS TTL inputs.

RST > While the oscillator is running a high on this pin for

two machine cycles resets the device. A small external pulldown

resistor (8.2k) from RST to Vss permits power ON reset when a

capacitor (10F) is also connected from this pin to Vcc.

____

ALE/PROG > Address Latch Enable output for latching the

low byte of the address during access to external memory. ALE is

activated at a constant rate of 1/6 the oscillator frequency except

during an external data memory access at which time one ALE pulse

is skipped. ALE can sink/source 8LS

____TTL inputs. This pin is also the program pulse input (PROG)

____


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during EPROM programming. PSEN > Program Store Enable

Output is the read strobe to external program memory. PSEN is

activated twice each machine cycle during fetches from external

program memory. (However, when executing out of external program

Memory two activations of PSEN are skipped

____during each access to external data memory) PSEN is not

____activated during fetches from internal program memory. PSEN

can sink/source 8-LS TTL inputs.

EA/Vpp> When External Access Enable (EA) is held high,the

8751H execute out of internal program memory (unless the program

counter exceeds OFF(H) when EA is held low,the 875(H) executes

only out of external program memory. This pin also receives the 21V

programming supply voltage (Vpp) during EPROM progrmming This

pin should not be floated during normal operation.

XTAL1 ->Inputs to the inverting amplifier that forms the

oscillator XTAL should be grounded when an external oscillator is

used.


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XTAL2-> ouptput of the inverting amplifier that forms the

oscillator,and input to the internal clock generator,receives the

external osciillator signal when an external oscillator is used.

OBSOLUTE MAXIMUM RATINGS:

Ambient temperature Emiter Bias 0. C to 70.C

Storage Temperature -65.C to +150.C

Voltage on any Pin to Vss(Except Vpp) 0.5V to + 7V

Voltage from Vpp to Vss 21.5V

Power Dissipation 2W

Note:

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress rating

only and functional operation of the device at these or any other

conditions above those indicated in the operational sections of this


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specification is not implied. Exposure to absolute maximum rating

conditions for extended

periods may affect device reliability.

8951H Architecture: .cw12

Architecture of 8951H can be given in brief as follows.

Accumalator:

ACC is the Accumalator register. The mnemonics for

accumulator-specific instructions,however,refer to the accumulator

simply as A.

B-Register:

The B-register is used during multiply and divide operations.

For other instructions it can be treated as another scratch pad

register.

Program Status Word:


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The PSW register containts program status information. The

Program STatus Word(PSW) Contains several status bits that reflect

the current state of the CPU. The PSW, shown in fig. resides up

SFR space. It contains the Carry bit,the Auxilary Carry (for BCD

operations), the two register bank select bits,the Overflow flag,a

Parity bit and two user definable status flags.

C>Carry Flag receives carry out from bit-1 of ALU

operation.

AC>Auxilary Carry Flag receives carry out from bit-1

of Addition operands. F0> General purpose status flag RS1>

Register bank select bit-1

RS0>Register bank select bit-0

OV>Overflow flag set by arthmetic operation

>User definable flag

P>Parity of accumulator by hardware to 1 if it contains an

odd number of 1s,otherwise set to 0.


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The Carry bit other than seving the funcitons of a carry bit in

arithmetic operations, also seves as the Accumulator for a number

of Boolean operations. The bits RS0 and RS1 are

used to select one of the four register bans shown in fig. A

number of instructions refer to these RAM Locations as R-0 througth

R-7 The selection of which of the four bank is being referred to is

made on the basis of the bits RS0 and RS1 at execution time.

The lower 32B are grouped into 4-banks of 8-registers.

Program instruction call out these reisters as R0 throuhg R7 2-bits ub

tge PSW select which register bank is in use.

The Parity bit reflects the number of 1s in the

Accumumulator:P=1 if the Accumulator contains an odd numbner of

1s in the Accumulator plus P is always even.

TWo bits in the PSW are uncommitted and may be used as

general purpose status flags.


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Stack Pointer:

The stack pointer register is 8-bits wide. It is incremented

before data stored during pPUSH and CALL execution while the

stack may reside anywhere in on-chip RAM. The stack pointer is

intialized to 07(H) after a reset. This causes the stack to bigin at

location 08(H).

Data Pointer:

The data pointer (DPTR) consists of a high byte (DPH and a

low byte (DPL). Its intended function is to hold a 16-bit address. It

may be manipulated as a 15-bit register or as two independent 8-bit

registers.

Ports-0 to 3->P0,P1,P2,and P3 are the SFR latches of Ports-

0,1,2 and 3 respectively.

Serial Data Buffer:

The Serial Data Buffer is actually two separate registers:a

transmit buffer and a receive buffer register. When data is moved to


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SBUF,it goes to the transmit buffer where it is held for serial transmit

buffer where it is held for serial transmission/ (Moving a byte tp

SBUF is what initiates the transmission). When datas is moved from

SBUF,it comes from the receive buffer.

Timer Registers:

Register pairs (THO,TLO),(TH1,TL1),AND (TH2,TL2) are the

16-bit counting registers for Timer/Counters0,1 and 2 respectively.

Capture Registers:

The register pair (RCAP2H,RCAP2L) are the Capture registers

for the Timer2 capture mode. In this mode,in response to a

transition at the 8051s T2EX pin,TH2 and TL2 are copied into

RCAP2H and RCAP2L. Timer-s also has a 16-bit auto-reload mode,

and RCAP2H and RCAP2L hold the reload value for this mode.

Control Registers:

Special Function Register IP,IE,TMOD,T2CON,SCON,and

PCON contains control and status bits for the interrupt system,the

timer counters,and the serial port.

(1)ACALL - Absolute CAll


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Description: This instruction unconditionally calls a subroutine

located at the indicated address. The instruction increments the PC

twice to obtain the address of the following instruction,then pushes

16-bit result into the stack(low-order byte first ) and increments the

SP twice. The destination address is obtained by successively

concatenating the five high-order bits of the incremented PC, opcode

bits 7-5, and the second byte of the program memory as the frist byte

of the insruction following ACALL. No flags are affected.

(2)ADD A,:Add(ACC),(Source-byte)

Description: This is a simple Add instruction which adds the

byte variable indicated to the Accumulator,leaving the result in the

Accumulator. The Carry and auxiliary-carry flags are set,respectively,

if there is a carry-out from bit-7 or bit-3,and cleared otherwise. When

adding unsigned integers,the carry flag indicates that overflow

occurred.


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0V is set if there is a carry-out of bit-6 but not out of bit-7,or a

carry-out of bit-7 but not bit-6;otherwise 0V is cleared.

When adding signed integers,0V indicates a negative number

produced as the sum of two positive operands,or a positive sum from

two negative operands.

Four source operand addressing modes are allowed:

register,

direct,

rgister-indirect,or

immediate.

(3)ADDC A,:Add with Carry

Description: This instruction adds simultaneously the byte

variable indicated, the carry flag and the Accumulator

contents,leaving the result in the Accumulator. The carry and

auxilary-carry flags are set respectively,if there is a carry-out from bit-

7 or bit-3 and cleard otherwise. When adding unsigned integers, the


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carry flag indicates an overflow occurred 0V is set if there is a carry-

out of bit-6 but not of bit-7,or a carry-out ofbit-7 but not out of bit-

6,otherwise oV is cleared. When adding signed integers,0V indicates

a negative number produced as the sum of two positive operands or

a positive sum from two negative operands.

Four source operand addressing modes are allowed:

register

direct,

register-indirect or

immediate.

(4)AJMP addr: Absolute Jump:

Description: This instruction transfers program execution to the

indicated address, which is formed at run-time by concatenating the

high -order five bits of the PC (after incrementing PC twice),opcode

bits7-5, and the second byte of the instruction. The destination must


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therefore be within the same 2K block of program memory as the first

byte of the instruction following AJMP.

(5)ANL,:Logical AND for byte variables

Describtion: This instruction performs the bitwise logical-AND

operation between the variables indicated and stores the results in

the destination variable. No flags are affected.

The two operands allow six addressing mode combinations.

when the destination is the Accumulator,the source can use

register,dirct,register direct address,the source an be the

Accumulator or immediate data.

NOTE:When this instructionb is used to modify an output

port,the value used as the original port data will be read from the

output data latch,not the input pins.

(6)ANL C,:Logical AND for bit variables

Description: If the Boolean value of the source bit is a logical-0

then clear the carry flag;otherwise leave the carry flag in its current


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state. A slash(/) preceding the operand in the assembly language

indicates that the logical complement of the addressed bit is used as

the source value,but the source bit itself is not affected. No other

flags are affected. Only direct addresing is allowed for the source

operand.

(7)CJNE,,rel:Compare and Jump if Not

Equal.

Description: CJNE compares the magnitudes of the first two

operands. and branches if their values are not equal. The branch

destination is computed by adding the signed relative-displacement in

the last instruction byte to the PC, after incrementing the PC to the

start of the next instruction. The carry flag is set if the unsigned

integer value of is less than the unsigned integer value of

;otherwise the carry is cleared. Neither operand is

affected.

The first two operands allow four addressing mode

combinations:the Accumulator may be compared with any directly


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addressed byte or immediate data,and any indirect RAM location or

workng register can be compared with an immediate constant.

(8) CLR A - Clear Accumulator:

Description :The accumulator is cleared (all bits set on zero).

No flags are affected. (A)


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(C)


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If the carry flag is now set, or if the four high-order bits now

exceed incremented by six,producing the proper BCD digit in the

high-order nibble. Again, this would set the carry flag if there was a

carry-out of the high-order bits,but wouldnt clear the carry. The carry

flag thus indicates if the sum of the original two BCD variables is

greater than 100, allowing multiple precision decimal addition. 0V is

not affected.

All of this occurs during the one instruction cycle.Essentially,this

instruction performs the decimal conversion by adding

00(H),06(H),60(H),or66(H) to the Accumuator and PSW conditions.

NOTE:DAA cannot simply convert a hexadecimal number in the

Accumulator to BCD notation, nor does DAA apply to decimal

subtraction.

(12)DEC byte :Decrement

Description;The variable indicated is decremented by 1.An

original value of 00(H) will underflow to OFF(H). No flags are

affected. Four operand addressing modes are allowed:

accumulater, register,

direct, or register-indirect.


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(13)DIV AB :Divide Description: DIV AB divides the unsigned

eight-bit integer in the Accumulator by the unsigned eight-bit integer

in register B. The Accumulater recieves the

register the integer part of the quotient,register recieves the

integer remainder. The carry and OV flags will be cleared.

(14) DJNZ,:Decrement and jump if Not Zero

Description: This instruction decrements the location indicated by 1,

and branches to the address indicated by the second operand if the

resulting value is not zero. An original value of 00(H)will underflow to

OFF(H).No flags are affected. The branch destination would be

computed by adding the signed relative-displacement value in the last

instruction byte to the PC, after incrementing the PC to the first byte

of the following instruction. The location decremented may be a

register or directly addressed byte.


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(15) INC : Increment Description: INC increments the

indicated variable by 1. An original value of OFF(H)will overflow to

00(H). No flags are affected. Three addressing modes are

allowed:register,direct, or register-indirect.

NOTE: When ths instruction is used to modify an output port

data latch,not the input pins.

(16)INC DPTR:Increment Data Pointer by 1.A 16-bit increment

(modula 216) is performed; an overflow of the low-order byte of the

data pointer (DPL) from 0FF(H) to 00(H) will increament the high-

order byte (DPH). NO flags are affected.

(17) JB bit,rel : Jump if Bit set

Description: If the indicated bit is a one, jump to the address

indicated otherwise proceed with the next instruction. The branch


the third instruction byte to the PC, after incrementing the PC to the

first byte of the next instruction. The bit tested is not modified. No

flags are affected.


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(18) JBC bit,rel : Jump if Bit is set and Clear bit

Description : If the indicated bit is one, branch to the address

indicated, otherwise proceed with the next instruction. The bit will not

be cleared if it already a zero. The branch destination is computed by

adding the signed relative-displacement in the third instruction byte to

the PC, after incrementing the PC to the first byte of the next

instruction. No flags are affected.

(19) JC rel : Jump if Carry is set

Description : If the carry flag is set, branch to the address

indicated, otherwise proceed with the next instruction. The branch


the second instruction byte to the PC, after incrementing the PC

twice. No flags are affected.

(20) JMP @A + DPTR : Jump Indirect

Description : Add the eight-bit unsigned contents of the

Accumulator with the sixteen-bit data pointer, and load the resulting

sum to the program counter. This will be the address for subsequent

instruction fetches. 16-bit addition


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is performed (modulo 216): a carry-out from the low-order 8-bits

propagates through the higher-order bits. Neither the Accumulator

nor the Data Pointer is altered. No flags are affected.

(21) JNB bit,rel : Jump if Bit Not set

Description : If the indicated bit is a zero, branch to the

indicated address; otherwise proceed with the next instruction. The

branch destination is completed by adding the signed relative

displacement in the third instruction byte to the PC, after incrementing

the PC to the first byte of the next instruction. The bit tested is not

modified. No flags are affected.

(22) JNC rel-Jump if Carry not set

Description : If the carry flag is zero, branch to the address

indicated; otherwise proceed with the next instruction. The branch

destination is computed by adding

the signed relative-displacement in the second instruction byte

to the PC, after incrementing the PC twice to point to the next

instruction. The carry flag is not modified.


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(23) JNZ rel: Jump if Accumulator Not Zero

Description : If any bit of the Accumulator is a one, branch to

the indicated address; otherwise proceed with the next instruction.

The branch destination is computed by adding the signed relative-

displacement in the second instruction byte to the PC, after

incrementing the PC twice. The Accumulator is not modified. No

flags are affected. (24) JZ rel : Jump if Accumulator Zero

Description : If all bits of the Accumulator are zero, branch to

the address indicated; otherwise proceed with the next instruction.

The branch destination is computed by adding signed relative-

displacement in the second instruction byte to the PC, after

incrementing the PC twice. The Accumulator is not modified. No

flags are affected.

(25) LCALL addr16 : Long call

Description : LCALL calls a subroutine located at the indicated

addres. The instruction adds three to the program counter to

generate the address of the next instruction and then pushes the 16-

bit result onto the stack (low byte

first), incrementing the Stack Pointer by two. The high-


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order and low-order bytes of the PC are then loaded,

respectively, with the second and third bytes of the LCALL instruction.

Program execution continues with the instruction at this address. The

subroutine may therefore begin anywhere in the full 64K byte

program memory address space. No flags are affected.

(26) LJMP addr16 : Long Jump

Description : LJMP causes an unconditional branch to the

indicated address, by loading the high-order and low-order bytes of

the PC (respectively) with the second and third instruction bytes. The

destination may therefore by anywhere in the full 64K program

memory address space. No flags are affected.

(27) MOV , : Move byte variable

Description : The byte variable indicated by the second operand

is copied into the location specified by the first operand. The source

byte is not affected. No other register or flag is affected. This is by

far the most flexible operation. Fifteen combinations of source and

destination addressing modes are allowed.


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(28) MOV , : Move bit data

Description : The Boolean variable indicated by the second

operand is copied into the location specified by the first operand.

One of the operands must be the carry flag, the other may be any

directly addressable bit. No other register or flag is affected.

(29) MOV DPTR,#data 16: Load DPTR with a 16-bit constant

Description : The Data pointer is loaded with the 16-bit constant

indicated. The 16-bit constant is loaded into the second and third

bytes of the instruction. The second byte (DPH) is the high-order

byte, while the third byte (DPL) holds the low-order byte. No flags are

affected. This is the only instruction which moves 16-bits of data at

once.

(30) MOVC A,@A + : Move Code byte

Description : The MOVC instruction loads the Accumulator with

a code byte, or constant from program memory. The address of the

byte fetched is the sum of the original unsigned eight-bit Accumulator

contents and the contents of a sixteen-bit


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base register, which may be either the Data Pointer or the PC.

In the later case, the PC is incremented to the address of the

following instruction before being added with the Accumulator,

otherwise the base register is not altered. Sixteen-bit addition is

performed so a carry-out from the low-order eight bits may propagate

through higher-order bits. No flags are affected.

(31) MOVX , : Move External

Description : The MOVX instructions transfer data between the

Accumulator and a byte of external data memory, hence the X

appended to MOV. There are two types of instructions, differing in

whether they provide an eight-bit or sixteen-bit indirect address to the

external data RAM. In the first type, the contents of R0 or R1 in

the current register bank provide an eight-bit address multiplexed with

data on P0. Eight bits are sufficient for external I/O expansion

decoding or for a relatively small RAM array. For somewhat larger

arrays, any output port pins can be used to output higher-order

address bits. These pins would be controlled by an output instruction

preceding the MOVX.


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In the second type of MOVX instruction, the Data Pointer

generates a sixteen-bit address. P2 outputs the high-order 8-address

bits(the contents of DPH) while P0 multiplexes the low-order 8

bits(DPL) with data. The P2 special Function Register retains its

previous contents while the P2 output buffers are emitting the

contents of DPH . This form is faster and more effecient when

accessing very large data arrays (up to 64K bytes),since no additional

instructions are needed to set up the output ports. It is possible in

some situations to mix the two MOVX types. A large RAM array with

its high-order address lines driven by P2 can be addressed via the

DPTR or with code to output high-order address bits to P2 formed by

a MOVX instruction using R0 or R1.

(32)MULAB:Multiply

Description: MUL AB multiplies the unsigned 8-bit integers in

the Accumulator and registerB. The low-order byte of the sixteen-bit

product is left in the Accumulator,and the high-order byte in B. If the

product is greater than 255 {OFF(H)} the overflow flag is

set,otherwise it is cleared. The carry flag is always cleared


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(A)7-0


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complement of the addressed bit is used as the source value,but the

source bit itself is not affected. No flags are affected.

(a) ORL C,bit

(C)


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(38)RET: Return from subroutine

Descrition: RET pops the high and low-order bytes of the PC

successively from the stack,decrementing the SP by two. Program

execution continues at the resulting address, generally the instruction

imediately following an ACALL or LCALL. No flags are affected.

(PC15-8)


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is generally the instruction immediately after the point at which the

interrupt request was detected. If a lower-or

same-level interrupt had been pending when the RET1

instruction is executed, that one instruction will be executed before

the pending interrupt is processed.

(PC 15-8)


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Description:: The eight bits in the Accumulator and the carry

flag are together rotated one bit to the left. Bit-7 moves into the carry

flag; the original state of the carry flag moves into the bit-0 position.

No other flags are affected.

(An+1)


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(An)


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multiple indicates that a borrow was needed for the previous

step in a multiple indicates that a borrow was needed for the previous

step in a multiple precision subtraction, so the carry is substracted

from the Accumulator along with the source operand). AC is set if a

borrow is needed for bit-3 and cleard otherwise. 0V is set if a borrow

is needed into bit-6,but not into bit-7,or into bit-7,but not bit-6.

When subtracting signed integers 0V indicates a negative

number produced when a negative value is subtracted from a positive

value, or a positive result when a positive number is subtracted from

a negative number,. The source operand allows four addressing

modes:register, direct,register-indirect,or immediate.

(47)SWAP A: Swap nibbles within the Accumulator

Description: SWAP A interchanges the low-and high-order

bibbles ($-bit fields) of the Accumulator (bits3-0 and bits7-

4). The operation can also be thought of as a four-bit rotate

insturction. No flags are affected.

(48)XCH A,:Exchange Accumulator with byte variable


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Description XCH loads the Accumulator with the contents of the

indicated variable, at the same time writing the original Accumulator

contents to the indicated variable. The source\destination operand

can be use register,direct,or register-indirect addressing.

(49)XCHD A,@ R: Exchange Digit Description: XCHD

exchanges the low-order nibble of the Accumulator (bits3-0),generally

representing a hexadecimal or BCD digit, with that of the internal

RAM location indirectly addressed by the specified register. The

high-order nibbles (bits7-4) of each register are not affected. No flags

are affected.

(A3-0)


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operation between the indicate variables, storing the results in

the destination. No flags are affected. The two operands allow six

addressing mode combinations.

When the destination is the Accumulator, the source can use

register, direct, register-indirect, or immediate addressing; when the

destination is a direct address, the source can be the Accumulator or

immediate data.

BIBLIOGRAPHY.

1. Introduction to microprocessor for Engineers and Scientists.

- P.K.GHOSH & P.K.SRIDHAR.

2. Microprocessor & Programmed logic.

- KENNETH L.SHORT.


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3. Fundamentals of Microprocessors & microcomputer.

- B.RAM

4. Microprocessor & Microcomputer based System Design.

- MOHAMMED RAFIQUZZAMAN.

5. Microcontroller Applications.

- B.P.Singh.

6. Microcontroller Architecture, programming & application.

- A. Kenneth Ayala

7. Electronics for You- Volume 9.

Date post:	03-Apr-2018
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