Triana Single Design Review TRIANA COMPUTATION HUB Quang Nguyen/Code 561 NASA/Goddard Space Flight...

Triana Single Design Review

TRIANA COMPUTATION HUB

Quang Nguyen/Code 561

NASA/Goddard Space Flight Center

Triana SDRJune 7 - 9, 1999

Computation Hub


Computation Hub - 2

Computation Hub Changes from SMEX-LITE design

Make design modification on the CIS to meet Triana requirements:

Add variable Transponder Mod Index selections based on previous SMEX design

Change downlink data rates from four rates (4, 2, .5 and .25 Mbps) to the wide range of programmable rates (from 4 Mbps to 300 bps)

Add the Reed-Solomon (RS-16) encoder used on many NASA missions (XTE, TRMM, MAPS, and FUSE)

Replace the Pegasus serial interface with the PLASMAG serial interface

Modify RAD6000 processor to accommodate 7 Mbytes SRAM:

C&DH / EPIC flight software requires additional processor memory for new tasks

Make a minor design modification and new layout on the BMS to accommodate new DRAM modules

Replace the obsolete Irvine Sensor DRAM modules used on previous SMEX missions with the tested Dense Pack DRAM modules being developed for NRL-NEMO program


Computation Hub - 3

Computation Hub Changes from SMEX-LITE Design (Cont.)

Replace the +5VActel FPGA PCI target with the new +3.3V ASIC PCI target : The RAD6000 PCI ASIC initiator (LIO) requires the 3.3V power to improve the

reliability The +3.3V ASIC PCI target being developed is functionally compatible with the existing

SMEX ACTEL PCI target and is electrically compatible with LIO ASIC PCI initiator

Redesign the backplane to support +3.3V PCI interfaceUse the tested SMEX-lite/Solstice LVPC design to provide additional 3.3V power

buses on the backplane


Computation Hub - 4

Computation Hub ImplementationMake necessary changes to existing SMEX-LITE Computation Hub design for Triana

requirementsUse EEE parts from SMEX-LITE inventoryProvide technical support to Triana instrument design teams GFE flight boards and subsystems to Triana instrument teams:

LM - EPIC Computer Hub Flight RAD 6000 Flight Memory and 1553 Summit card Flight EPIC Camera Interface card Flight LVPC Flight backplane Flight enclosure PCI ASIC target and user interface design Computation Hub documentation Spacecraft simulator for software/hardware development

Ball - NISTAR Flight RAD 6000 Flight Memory and 1553 Summit card Computation Hub documentation Spacecraft simulator for software/hardware development


Computation Hub - 5

Computation Hub Functional Capabilities

LMF RAD 6000 32-bit Processor Card Uses SMEX-Lite/VCL RAD 6000 version with 7 Mbytes RAD Hard SRAM Hosts flight software (C&DH, ACS, spacecraft safehold, and Power Control) Provides PCI bus master data transferring between cards through PCI backplane Provides direct Instrument data transfer through high speed serial interfaces

Communication Interface Card Supports CCSDS Command and Telemetry standards Hardware generated fill-frame construction minimizes the processor burden Supports selectable downlink encoding options including Reed-Solomon Generates MET, watchdogs, PLASMAG serial interface and 3 UARTS

Memory & 1553 Summit Card 320 Mbytes DRAM baseline implementation with onboard EDAC capability 1 Mbytes EEPROM for normal mode use 1553 B interface with use of UTMC 1553 Summit chip

PCI backplane Allows DMA and other transfers between cards

Four cards plus backplane


Computation Hub - 6

TRIANA COMPUTATION HUB TOP LEVEL BLOCK

SUROM

OSC

Main Memory

RAD6000

Local I/O Interfaces RS232

Hardware Test IF

Timer/Time-Out

Intr/Discretes

PCI Local Bus

HighSpeed

Serial IF

JTAG

320 MbytesDRAM

1 MbytesEEPROM

1553B

+5V & 3.3V ONLY

EEPROM

TRIANAPROCESSOR

Downlink I/F

Uplink I/F

HW CMD

To Mag_Plasma

UARTS1

1553 B1553 A 1553b BUS

Communication I/F card Memory & 1553 Sum card

UplinkDownlink

METUARTS

LVPC

UART

Lockheed Martin Design ( one card) SMEX Designs ( three cards)

EPIC computer


Computation Hub - 7

TRIANA COMPUTATION HUB FUNCTIONAL REQUIREMENTS (1)

Transponder interface for telemetry and command links

CCSDS COP-1 uplink command decoding 2 Kbps

CCSDS downlink telemetry encoding

Hardware generation of CCSDS telemetry fill frames

Spacecraft clock, time distribution, and synchronization

EPIC Science data collection over high speed serial interface

5 Mbps (max.) data rate

RS-422 electrical interface

Bulk telemetry data storage with EDAC 256 Mbytes science data + 64 Mbytes EDAC = 320 Mbytes total


Computation Hub - 8

TRIANA COMPUTATION HUB FUNCTIONAL REQUIREMENTS (2)

PLASMAG UART serial interface Receive telemetry data from Triana PLASMAG Instrument Send command data to Triana PLASMAG Instrument RS-422 electrical interface

1553 Bus Controller interface Command distribution Housekeeping data collection

Processor & UART interfacesWatchdog & Power strobe interfaces:

PCI reset (triggered by hardware watchdog, Barker watchdog) Power strobing (triggered by ground hardware command )

Host Flight Software C&DH, ACS, Power Control & Safehold

PCI bus Interface


Computation Hub - 9


SUROM

OSC

Main Memory

RAD6000


Hardware Test IF

Timer/Time-Out

Intr/Discretes

PCI Local Bus

HighSpeed

Serial IF

JTAG

320 MbytesDRAM

1 MbytesEEPROM

1553B

+5V & 3.3V ONLY

EEPROM

TRIANAPROCESSOR

Downlink I/F

Uplink I/F

HW CMD

PLASMAG TLM/CMD

UART

1553 B1553 A 1553b BUS

EPIC computer


UplinkDownlink

METUARTS

LVPC

Lockheed Martin Design ( one card) SMEX Designs ( three cards)


Computation Hub - 10

FLIGHT PROCESSOR CARD

Side A: Side B:

S/N 001


Computation Hub - 11PCI Local Bus

TRIANA FLIGHT PROCESSOR TOP LEVEL BLOCK

Computation Hub Backplane

SUROM64Kbytes

20 MhzOSC

LIO

UART-RS422

H/W Test IF

Timer/Time-Out

Intr/Discretes

HighSpeed Serial

IF(QHSS)

JTAG+5V DC

+3.3 V DC

Interrupts/Discretes Function

Local Memory Address& Control Function

UART Interface Function

Clocks & Timers Function

Reset Control

PCI Master/Central Arbiter

Main Memory7 Mbytes RHSRAM

RAD6000

Floating Point Unit

Cache Unit (8K)

Fixed Point Unit

Memory InterfaceUnit w/ EDAC

Pipeline Control Unit

I/O Sequencer Unit

Address Translation Unit

Fetch/Instruction Buff Unit

PCI Bridge Function

Interrupt Collection &Reporting Function

SUROM Control Function

JTAG Master Function

Proc Avail Seq Function

Chip Test/Diags Functions

EEPROM1 Mbytes

RS-422



Flight Processor Card (1)

PCI Industry Standard Interface Any qualified PCI component will

interface to TRIANA Comp-Hub Future upgrade path to any PCI Master

processor w/out ripple through system interfaces

Delivers RAD-hard performance needed to accommodate additional software requirements Boot mode safehold, power control

Processor hardware debug environment available off-the-shelf RISCwatch, JTAG, VMETRO PCI Bus

Analyzers

Real Time Multi-tasking Kernel support VxWorks Operating System



Flight Processor Card (2)Memory Interface Unit

handles accesses to/from local memory and provides RAM data to the Cache Unit

Cache Unit coordinates accesses to the Cache

Instruction Buffer Unit pulls instructions from the cache and

dispatches instructions to the fixed point, floating point, and in-page fetcher (branch instructions)

Fixed Point Unit provide pipelined execution for fixed

point instructions

I/O Sequencer Interfaces to RSC I/O bus and provides

for initialization of the processor at startup

Pipeline Control Unit Controls sequencing and interlocking

operation of other functional units

COP (Chip On Processor) Unit Interfaces with external test equipment

and assists in the resetting and initialization of the processor registers and arrays



Flight Processor Card (3)RAD6000 32-bit RISC Super Scalar

Single Chip22 MIPS @ 20 MHz7 Mbytes RHSRAM1 Mbytes EEPROM64 Kbytes SUROMProgrammable Processor/PCI clocks:

20, 10, 5 or 2.5 MHZ10 External Programmable Interrupts

via LIO8 RAD6000 level interrupts

Peripheral Component Interconnect(PCI) Bus Full Mastership Local to PCI I/O Space DMA capable 16 Mbytes/sec Bus Transfers

Four High Speed Serial Interfaces 5 Mbps per each Full Duplex (RS-422 electrically) DMA capable

UART Interface (RS-422)Power @ 20 MHz < 7 W

+5.0 VDC, +3.3 VDC



Flight Processor Card (4)Board Radiation Characteristics

Total Dose :

50K rads(Si) (Hitachi 128Kx8 EEPROM in Austin Semi. package)

Latch-up Immune Upset rate:

GCR: .374125 per 5-year

mission

Solar Flares: 1.0 per 5 year mission (5 flares in a day)

SEU (LET): >80 Mev/mg/cm**2

Physical 7.07 in. X 7.3 in. 1.989 pounds or .904 kgs

11 SMEX-Lite RAD6000 processor boards built and delivered: 3 for Triana 4 for EOS-Solstice 2 for VCL 2 for SMEX-Lite

VxWorks Operating SystemHost Flight Software




6/6/96

SUROM

OSC

Main Memory

RAD6000

Local I/O Interfaces UART-RS422

Hardware Test IF

Timer/Time-Out

Intr/Discretes

PCI Local Bus

HighSpeed

Serial IF

JTAG

UplinkDownlink

METUARTS

320 MbytesDRAM

1 MbytesEEPROM

1553B

+5V & 3.3V ONLY

SMEX Designs ( three cards)Lockheed Martin Design ( one card)

EEPROM

TRIANAPROCESSOR

Downlink I/F

Uplink I/F

HW CMD

To PLASMAG

UART

1553 B1553 A 1553b BUS

Memory & 1553 Sum cardCommunication I/F card LVPC

EPIC computer

UART



PCI Target Interface ImplementationPCI target core purchased PCI Bus interface implemented and tested with +5V FPGA in the SMEX_lite Comp-

HubModified user interface to support specific peripheral component interfacesPCI target core implemented in LMFS RAD HARD ASICCore Simulated per PCI Specification Rev 2.0

Single Configuration Reads/Writes Single and Burst Memory Reads/Writes



COMMUNICATION INTERFACE CARD IMPLEMENTATION

Uplink 2 Kbps uplink interface, H/W command decoder

Downlink Programmable downlink rate range: 4 M bps-300 bps Programmable 32 modulation index levels Hardware fill frame generator Coding options (Reed Solomon, Convolutional, PN and/or Bi-phase L encoding)

Timers Hardware watchdog, Mission Elapsed Time

PLASMAG UART Serial Interface External Interfaces

1 UART (RS-422 electrically)

PCI Slave interface



COMMUNICATION INTERFACE CARD

Side A Side B



COMMUNICATION INTERFACE TOP-LEVEL BLOCK DIAGRAM

PC

I_TA

RG

ET

LOC_ADDRESS

LO

C_D

ATA

MET_UARTSCONTROLLER

HW WATCHDOG PULSE

1 HZ

8PM_DAT_IN

UDATA

8

PLASMAG_SERIAL

SER_CHANNEL

UART

UART_SEL, CNTRL

TO

BA

CK

PLA

NE

MET8 MHZ

UART IF

PM_UART

DOWNCONTROLLER

16 MHZ

CMD IF

8X4KX9

DN_FIFO

32

UP_FIFO8

UP_WR

DN_WR

DN_DAT

UP_DAT

TELEMETRY OUT

8 MHZ

16 MHZ HW CMD DECODER

3 FPGAs

ASIC

FPGA

UPCONTROLLER

To Transponder

Hardline to GSERS422

PM_FIFO4 k x9

FPGA

RS

8

RD,WR,FLAG_STAT



6/6/96


SUROM

OSC

Main Memory

RAD6000


Hardware Test IF

Timer/Time-Out

Intr/Discretes

PCI Local Bus

HighSpeed

Serial IF

JTAG

320 MbytesDRAM

1 MbytesEEPROM

1553B+5V & 3.3V ONLY


EEPROM

TRIANAPROCESSOR

Downlink I/F

Uplink I/F

HW CMD

To PLASMAG

UART

1553 B1553 A 1553b BUS


UplinkDownlink

METUARTS

LVPC

UART



MEMORY & 1553 SUMMIT CARD

DRAM Bulk Memory 320 Mbytes of data storage using 10 32Mx8 bit DRAM modules (Dense-pac

DPD32MX8RG5-06C): Organized into 2 160-Mbyte banks DRAM module consists of 4 64M bit Samsung DRAM (KM48C8000AS-6, 5.0V, REV A)

chips stacked in a module by Dense-Pac

EDAC with single & multi bit error interrupts DRAM Refresh Controller

EEPROM Memory 1Mbytes of normal mode code storage Use 8 128Kx8 Hitachi CMOS EEPROM dies packaged by Austin Semiconductor On-orbit programmable

1553 Bus Controller InterfacePCI Slave Interface



MEMORY & 1553 SUMMIT CARD

Side A Side B



MEMORY&1553 SUMMIT TOP-LEVEL BLOCK DIAGRAM

PC

I_TA

RG

ET

1553SUMMIT

1553SUMMIT

CHANNEL A

CHANNEL B

SHARED RAM64K x 16

LOC_ADDRESS

LO

C_D

ATA

ADDR

DAT

TO

BA

CK

PLA

NE

EEPROM5

EEPROM5

EEPROM 1

EEPROM 4

EEPROM 8

1 M BYTES EEPROM

32

EEPROM_SUMCONTROLLER

DRCKBITS

DRAM/EDACCONTROLLER

DRDATA

DRADDR 12

32

24 MHZ

DRAM MODULES

(10 X 32M X 8 BITS)8

FPGA

FPGA

ASIC

48 MHZ




6/6/96

SUROM

OSC

Main Memory

RAD6000


Hardware Test IF

Timer/Time-Out

Intr/Discretes

PCI Local Bus

HighSpeed

Serial IF

JTAG

320 MbytesDRAM

1 MbytesEEPROM

1553B

+5V & 3.3V ONLY


EEPROM

TRIANAPROCESSOR

Downlink I/F

Uplink I/F

HW CMD

UART

1553 B1553 A 1553b BUS


UplinkDownlink

METUARTS

LVPC

To PLASMAGUART



Low Voltage Power Converter

LVPC: Uses SMEX-Lite/Solstice LVPC version

Uses the COTS Interpoint EMI filter and DC-to-DC converters

Complies 461 EMI specification

Converts +28V input to +5V and +3.3V outputs

Provides +5V to Communication I/F, Memory & 1553 Summit, Processor, & Backplane terminations

Provides +3.3V to Flight Processor and PCI target ASICs

Generates PCI Reset (POR 0) signal



Low Voltage Power Converter



LVPC FUNCTIONAL BLOCK DIAGRAM

OPTO-ISOLATEDRESET I/F

DC-TO-DC +3.3 V

DC-TO-DC+5.0 V

CONTROLLOGIC

INHIBIT ON

+3.3V LINE

+5.0V LINE

+28 V

+28 V RTN

SW_RST

RST#

PC

I_ B

AC

KPLA

NE I/F

SW_RST

TLM_3.3V

RESET_A

RESET_B

EMI FILTER

+28 V_C

+28 V RTN_C

TLM_IF

THERM_IF

TLM_5V

THERM_3.3V

THERM_5V

PO

WER

CO

NN

EC

TO

RS

IGN

AL

CO

NN

EC

TO

R



Computation Hub BackplaneSupport PCI Interface

Signals (48) Pull-up resistors

Support discrete signals Interrupts(4) Reset

Distribute Power +5.0V DC at 8 Amp. (max.)

DRAM/1553B/EEPROM Communications Interface Flight Processor

+3.3V DC at 3 Amp. (max.) Flight Processor ASICs 2 PCI target ASICs

Com

munication

Interface card

RA

D6000

Processor

DR

AM

/1553/EE

PR

OM

card

Low

Voltage

Pow

er Converter

CompHub Backplane

PCI Bus Signal Interface+5.0 V & +3.3 V Power

Interrupts(4) & HW Reset



Computation Hub Enclosure Implementation

SMEX.Lite Computation Hub:

Houses all Comp Hub cardsCard size (inches):

7.0 x 7.3

Box dimension (inches): 5 W x 7.5 H x 8.2 D

Total weight: 12.25 lbs measured/estimated

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Triana Single Design Review TRIANA COMPUTATION HUB Quang Nguyen/Code 561 NASA/Goddard Space Flight...

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