Date post: | 06-May-2015 |
Category: |
Technology |
Upload: | ashim-saha |
View: | 1,013 times |
Download: | 2 times |
1
Computer organization
2
I / O
3
interrupts
Interrupt is a signal ; on receiving this signal, the processor suspends the execution of the program that it currently executing and transfers control to an interrupt handling program
At least one of the bus control lines called the interrupt request line should be dedicated for carrying the signal
The routine executed in response to an interrupt is called interrupt service routine
4
interrupts
On handling the request , the processor must inform the device that made the request.
This is done by sending a interrupt acknowledge signal
The time delay between the interrupt request and execution of interrupt service routine is called interrupt latency
5
interrupts
Basic execution of an interrupt The device raises an interrupt
The processor interrupts the program it currently being executed
Interrupts are disabled by changing the control bits in the processor status register
The action requested by the interrupt is performed by the ISRInterrupts are enabled and execution of interrupted program is resumed
6
interrupts
Types of interrupts External interrupts
Internal interrupts
Software interrupts
7
interrupts
External interrupts come from I/O devices, from timing device, from circuit monitoring the power supply etc.
Internal interrupts arise from illegal use of an instruction or data.
Internal interrupts are also called as traps.
The service program that processes the internal interrupt determines the corrective measure to be taken
8
interrupts
The internal interrupt is initiated by some exceptional condition caused by the program itself rather than by an external event.
Internal interrupts are synchronous with the program, while external interrupts are asynchronous. ie if the program is rerun, the internal interrupts will occur in the same place each time. External interrupts depend on external conditions that are independent of the program.
9
interrupts
External and internal interrupts are initiated from signals that occur in the hardware
Software interrupt is initiated by executing an instruction.
This instruction can be used by the programmer to initiate and interrupt procedure at any desired point in the program
The most common s/w interrupt used is an supervisor call , which is used for switching from a user mode to supervisor mode
10
Modes of data transfer
Information received from an external device is stored in the memory later for later processing
Information is transferred to and from the memory involves can happen in different modes
In certain transfers , the CPU acts as an intermediate path ,and in other ones the transfer take place between the memory and external devices directly
The different modes are Programmed I/O
Interrupt initiated I/O
Direct Memory access
11
Modes of data transfer
programmed I/O
The i/o devices have no direct access to memory
CPU registers act as an intermediate storage
The operations are the result of i/o instruction written in the computer program
Once a data transfer is required , the CPU is required to monitor the interface to see when a transfer can again be made
The programmed instructions has to take care of everything that is taking place in the interface unit and the I/O device
12
IO mapped i/o
Data validAddress bus
i/o bus
CPU
Status Fregister
IO device
interface
Data register
Data
accepted
Data bus
I/o read
I/o write
13
Modes of data transfer
programmed I/O
The device transfers data one at a time
When data is available the device places it in i/o bus and enable data valid line
Interface accepts the byte into data register and enables data accepted line
Interface sets the flag and disable data valid line
CPU checks stats flag and if it is sets, CPU reads data and flag is cleared either by CPU or interface
Data accepted line is set invalid
14
Modes of data transfer
I/O addressing
In systems using programmed i/o the CPU ,M and IO devices usually communicate through system bus
The address lines of the system bus that are used to select memory locations can be used to select I/O devices.
An i/o device is connected to the bus through an i/o port, which from the CPU’s perspective , is an addressable data register like a memory location
15
Modes of data transfer
If a part of the main memory address space is assigned to IO ports, then the technique is called memory-mapped IO
An instruction that causes data to be fetched from or stored at address X becomes an IO instruction if X is made the address of an I/O port
16
Modes of data transfer
If the memory and IO address spaces are separate , then the arrangement is called IO-mapped IO
A memory referencing instruction activates the read or write M control line which does not affect the I/O devices
The CPU must execute separate instructions for Read or write IO
When the processor repeatedly checks the status of the I/O in operation for to achieve required synchronization between the processor and i/o device, we say the processor polls the device
17
Memory mapped i/o
data
Address
readwrite
Main memory
CPU IO port 1 IO port 2 IO port 3
IO device A
IO device B
18
IO mapped i/o
data
AddressRead M
write
Main memory
CPU IO port 1 IO port 2 IO port 3
IO device A
IO device B
Write M
Read IO
Write IO
19
Modes of data transfer
Interrupt driven I/O
In programmed IO method , the CPU stays in a program loop until the IO indicates that it is ready for data transfer
This is a time consuming process
it can be avoided by using an interrupt facility and special command to inform the interface to issue an interrupt request signal when the data is available from the device
20
Modes of data transfer
In the meantime, processor can proceed to execute another program
The interface will keep monitoring the device and generate the signal when the device is ready
The CPU will suspend the current task and process the IO transfer
21
Modes of data transfer
When the flag is set, the CPU is interrupted and is ready to handle I/O
After transfer is completed CPU will return to the previous process
The CPU responds to the interrupt signal by storing the return address to a memory stack and control branches to a service routine that process the I/O transfer
22
Modes of data transfer
There are two methods called vectored and non vectored interrupts for collecting the branch address
In non vectored interrupt , the branch address is assigned to a fixed location in the memory
In vectored interrupt, the source that interrupt supplies the branch address
This information is called interrupt vector
23
Modes of data transfer
Handling multiple I/O request
Priority interrupt system – this system checks which request should be served first if two or more request comes at the same time
Higher priority levels are assigned to requests which if delayed or interrupted could have serious consequences
24
Modes of data transfer
Handling multiple I/O request
The polling procedure can be used to identify the highest-priority
In Polling the status registers , the priority is determined by the way in which the devices are polled
The highest priority source is tested first , if interrupt signal is on ,control branches to its ISR.
When vectored interrupts are used, we must ensure that only one device is selected to send its interrupt vector code
25
Modes of data transfer
DMA
In Direct Memory Address (DMA) , the interface transfers data into and out of the memory unit through the memory bus without continuous intervention by processor
This is done to transfer large block of data at high speed
DMA transfers are performed by a control circuit that is a part of I/O interface, called as DMA controller
For each word transferred ,it provides memory address and signals that control data transfer
26
Modes of data transfer
The operation of DMA controller is under the supervision of a program executed by the processor
To initiate a transfer , processor sends the starting address and number of blocks and direction of transfer
When the entire block is transferred, the controller informs the processor by raising an interrupt
Two registers are used for storing the starting address and word count. Third register contains the control flags
27
Modes of data transfer -DMA
ProcessorMain
memory
Disk/DMAcontroller
DMA controller Printer Keyboard
Network interface
disk disk
System bus
28
Modes of data transfer
To start DMA , the program writes the address and word count into registers and also provides information to identify data for future retrieval
Controller performs required operation and on completion, it set the bits of status line
The status register can keep information about errors etc.
Request by DMA devices are given priority than processor requests for using the bus
29
Modes of data transfer
The processor generates memory access cycles, and DMA controller can be said to steal memory cycles from the processor. This process is called cycle stealing
DMA controller is given exclusive access to the main memory to transfer a block of data without interruption. This is known as block or burst mode
30
Modes of data transfer
If two DMA controllers try to access bus at same time, an arbitration procedure is necessary and is called as bus arbitration
The device that is allowed to initiate data transfers on the bus at any given time is known as bus master
When current master relinquishes control, another device can become bus master
Bus arbitration is the process by which the next device to become bus master is selected and control is transferred to it.