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IEEE 1801

UPF Solutions Guide

July 200

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IEEE 1801-2009™ is an IEEE Standard for Design and Verification of

Low Power Circuits

The power supplied to elements in an electronic design affects the way circuits

operate. Although this is obvious when stated, today’s set of high-level design

languages have not had a consistent way to concisely represent the regions

of a design with different power provisions, nor the states of those regions or

domains. This standard provides an HDL-independent way of annotating a

design with power intent. In addition, the level-shifting and isolation between

power domains may be described for a specific implementation, from high-

level constraints to particular configurations. When the logic in a power domain

receives different power supply levels, the logic state of portions of the design

may be preserved with various state- retention strategies. This standard pro-

vides mechanisms for the refined and specific description of intent, effect, and

implementation of various retention strategies. Incorporating components into

designs is greatly assisted by the encapsulation and specification of the char-

acteristics of the power environment of the design and the power requirementsand capabilities of the components; this information encapsulation mechanism

is also described in this standard. The analysis of the various power modes of a

design is enabled with a combination of the description of the power modes and

the collection, generation, and propagation of switching information.

Order On-Line at: http://standards.ieee.org/prod-serv/index.html

Part Number: STD95919 Format: PDF ISBN: 978-0-7381-5929-4

UPF is a Copyright of Accellera.  All other trademarks and copyrights belong

to their respective owners. There is no intent to violate anyone’s rights.

Latest UPF Solutions Guide can be downloaded from:

http://www.accellera.org/upf/SolutionsGuide.pdf

 All the information contained in this solution guide about products and contacts

is provided by respective vendors. The user of this solution guide is requested

to check the latest product information by contacting the respective vendor.

This solution guide should not be used as the sole source of information for

making decisions regarding suitability of UPF or any UPF related products for

any purpose.

Original Version: July 2007

4th Edition: July 2009

For corrections and additions, please contact Yatin Trivedi, trivedi@synopsys.com

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 6 July 2009

mailto:gray@spiritconsortium.org

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 8 July 2009

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July 2009 9

Low Power Design & Verification Flow

UPF

HDL(RTL)

UPF

Verilog(Netlist)

UPF

Verilog(Netlist)

Synthesis

P&R

 S i  m ul   a t  i   on ,L  o gi   c al  E  q ui  v a

l   en c e C h  e ck i  n g ,… 

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 10 July 2009

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14 July 2009

 

 

 

mailto:upf@atrenta.comhttp://www.atrenta.com/

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July 2009 15

MPSimSimulation 

Testbench

RT 

DesignerDebug

ProtometerCoverage

UPF Specification   Simulate power off corruption  Simulate retention and

save/restore of states

  Simulate isolation and clamping

  Trace complete power networkand switches

  Visualize power switch states  Visualize the states of powered

off blocks throughout simulation

  Annotate powered off signals

  Automate power verificationcombinations

  Verify all possible powercombinations

  Power verification closure

MPSim

Designer

ProtoMeter

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16 July 2009

 

 

 

 

mailto:upf@axiom-da.comhttp://www.axiom-da.com/

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http://www.azuro.com/rubix/http://www.azuro.com/powercentric/

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18 July 2009

PowerCentric™ Clock TreeSynthesis

Rubix™ Clock ConcurrentOptimization 

RTL

Synthesis

Initial Place

Routing

GDSII

CTS

Phys. Opt.

Post-CTS Opt.

Verilog

netlist

Placed

DEF

SDC

PowerCentric

PRO

Verilog

netlist

Placed

DEF

RTL

Synthesis

Initial Place

Routing

GDSII

CTS

Phys. Opt.

Post-CTS Opt.

Verilog

netlist

Placed

DEF

SDC

R ubix

PRO

Verilog

netlist

Placed

DEF

http://www.azuro.com/mailto:upf@azuro.comhttp://www.azuro.com/mailto:upf@azuro.commailto:upf@azuro.comhttp://www.azuro.com/

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20 July 2009

mailto:upf@chipvision.comhttp://www.chipvision.com/

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22 July 2009

mailto:upf@commonplatform.comhttp://www.commonplatform.com/

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➔Architecture exploration, use case profiling

➔Early Power and Temperature estimation

➔Automatic generation of UPF format

➔Package and cooling technique selection

IPPower Model Database

ACEplorer 

Fast Electro-thermal Simulator 

Platform model Use Case model

Electronic SystemSpecification

High Level Model Builder 

Platform : Board, SoC, SiP, IP : Pow er intents, power related parameters,

architecture structu re, thermal behavior 

Use cases 

 Activi ty 

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24 July 2009

UPF

ACEplorer 

Low power architecture capture :Power domains, voltage/clock network, power

reduction techniques modelling

System Structure Power Characterization

High Level Power Model

XML based

Standard RTL to GDSII flow

mailto:upf@doceapower.commailto:upf@doceapower.comhttp://www.doceapower.com/

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July 2009 25

Specialty Blocks

SERDES and PLL

Memory CompilersHi-Performance and Low PowerFull Redundancy (Single & DualPort SRAM, 1, 2 & 4-Port RegFile

Custom Memory and

High Speed/High DensityStandard Cells >1GHZ Designs

Ultra High Density and Low Power

I/O Blocks

Standard Cells

Memories

Specialty High Speed I/O’s andStandard I/O cells

mailto:upf@dolphin-ic.comhttp://www.dolphin-ic.com/

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26 July 2009

mailto:upf@elastix-corp.comhttp://www.elastix-corp.com/

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July 2009 27

http://www.ieee.org/web/standards/home/find.htmlhttp://standards.ieee.org/http://standards.ieee.org/corpforum/index.html

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28 July 2009

http://www.interrasystems.com/

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mailto:upf@interrasystems.comhttp://www.interrasystems.com/

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mailto:upf@libtech.comhttp://www.libtech.com/http://www.libtech.com/http://www.libtech.com/http://www.libtech.com/http://www.libtech.com/http://www.libtech.com/http://www.libtech.com/

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32 July 2009

T

 

mailto:upf@magma-da.comhttp://www.magma-da.com/

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mailto:upf@magma-da.comhttp://www.magma-da.com/

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34 July 2009

Vista Architect

Power-Aware TLM 

Vista ArchitectVista Architect

Power Power -- Aware TLM  Aware TLM 

Catapult HLS Architectural 

Trade-Off Analysis

Catapult HLSCatapult HLS Architectural  Architectural 

TradeTrade--Off AnalysisOff Analysis

RTL SynthesisRTL SynthesisRTL Synthesis

Olympus SoCMulti-Corner Multi-Mode

Place & Route

OlympusOlympus SoCSoCMulti Multi --Corner Multi Corner Multi --ModeMode

Place & RoutePlace & Route

     Q    u    e    s     t    a

     Q    u    e    s     t    a

     F    o    r    m

    a     l     P    r    o

     F     F    o    r    m

    a     l     P    r    o

    o    r    m

    a     l     P    r    o

TestKompressTestKompressTestKompress

0-In ® CDC00--InIn ® CDCCDC

Calibre PERC CalibreCalibre PERC PERC 

   I   E   E   E    1

   8   0   1

   (   U   P   F   )

   I   E   E

   E    1

   8   0   1

   (   U   P   F   )

   I   E   E

   E    1

   8   0   1

   (   U   P   F   )

Vista Architect

Power-Aware TLM 

Vista ArchitectVista Architect

Power Power -- Aware TLM  Aware TLM 

Catapult HLS Architectural 

Trade-Off Analysis

Catapult HLSCatapult HLS Architectural  Architectural 

TradeTrade--Off AnalysisOff Analysis

RTL SynthesisRTL SynthesisRTL Synthesis

Olympus SoCMulti-Corner Multi-Mode

Place & Route

OlympusOlympus SoCSoCMulti Multi --Corner Multi Corner Multi --ModeMode

Place & RoutePlace & Route

     Q    u    e    s     t    a

     Q    u    e    s     t    a

     F    o    r    m

    a     l     P    r    o

     F     F    o    r    m

    a     l     P    r    o

    o    r    m

    a     l     P    r    o

TestKompressTestKompressTestKompress

0-In ® CDC00--InIn ® CDCCDC

Calibre PERC CalibreCalibre PERC PERC 

   I   E   E   E    1

   8   0   1

   (   U   P   F   )

   I   E   E

   E    1

   8   0   1

   (   U   P   F   )

   I   E   E

   E    1

   8   0   1

   (   U   P   F   )

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July 2009 35

Synthesis

UPFUPF

HDL(RTL)

HDL(RTL)

UPFUPF

Verilog(Netlist)

Verilog(Netlist)

UPFUPF

Verilog(Netlist)

Verilog(Netlist)

P&R

     Q    u    e    s     t    a

     Q    u    e    s     t    a

     F    o    r    m    a     l     P    r    o

     F     F    o    r    m    a     l     P    r    o

    o    r    m    a     l     P    r    o

Synthesis

UPFUPF

HDL(RTL)

HDL(RTL)

UPFUPF

HDL(RTL)

HDL(RTL)

UPFUPF

Verilog(Netlist)

Verilog(Netlist)

UPFUPF

Verilog(Netlist)

Verilog(Netlist)

UPFUPF

Verilog(Netlist)

Verilog(Netlist)

UPFUPF

Verilog(Netlist)

Verilog(Netlist)

P&R

     Q    u    e    s     t    a

     Q    u    e    s     t    a

     F    o    r    m    a     l     P    r    o

     F     F    o    r    m    a     l     P    r    o

    o    r    m    a     l     P    r    o

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http://www.mentor.com/products/ic_nanometer_design/cl_floorplan/olympus/index.cfmhttp://www.mentor.com/products/fvmailto:upf@mentor.comhttp://www.mentor.com/

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38 July 2009

mimasic Low Power SoC Design and Verification Services

 

 

 

 

 

 

 

 

 

mailto:upf@mimasic.comhttp://www.mimasic.com/

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40 July 2009

mailto:upf@sequencedesign.comhttp://www.sequencedesign.com/

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mailto:us_support@springsoft.comhttp://www.springsoft.com/

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42 July 2009

Predictable Success

mailto:upf@synopsys.comhttp://www.magma-da.com/http://www.synopsys.com/eclypse

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44 July 2009

http://www.tsmc.com/

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46 July 2009

RTLcode

Floor Planning

IC Compiler 

Netlist

Logic Synthesis & STA

PrimeTimeDesign Compiler 

RTL Simulation

MVSIM

Floor plan

Place & RouteIC Compiler 

Multi-Voltage Rule Checker 

Power Analysis (PrimeRail)

Formal Checking (Formality)

Chip Finishing

RC Extraction (Star-RCXT)

DRC/LVS (Hercules)

UMC UPF Solu tions 

• Standard Cell Libr aries • UPF tags/header embedd ed 

• Timing & Power Models 

• Techn ology Files 

• Based on UMC ’ s premium

device models 

• DRC / LVS / LPE inclu ded 

• Reference Design Flow (*) 

• EDA script examples 

• Applicat ion notes 

• Sil icon experimental docum ents 

(*) Slated for availability in Q3 2008 

http://www.umc.com/

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48 July 2009

mailto:upf@viragelogic.comhttp://www.viragelogic.com/

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July 2009 49

ISBN: 978-0-387-71818-7

mailto:Alex.Greene@springer.comhttp://www.lpmm-book.org/http://www.springer.com/

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50 July 2009

http://www.vmmcentral.org/cgi-bin/contactus.cgihttp://www.vmmcentral.org/vmmlp

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What is UPF?

Unified Power Format (UPF), a format to describe low power intent fordesign implementation, analysis and verification, is the standard developed by

 Accellera as UPF 1.0 in February 2007 and ratified by IEEE as IEEE 1801™ 

Standard for Design and Verification of Low Power Circuits in March 2009.

It enables open, multi-vendor tool flows and solutions for low-power ASIC

and SoC design. The true value of a single, widely adopted standard is dem-

onstrated by interoperability of products from a range of EDA suppliers who

support the UPF standard. Designers of modern, low-power ICs are the ultimate

beneficiaries of UPF.

UPF 1.0 standard from Accellera is accessible to everyone. The latest version of

this document can be downloaded from Accellera’s website at:

http://www.accellera.org.

IEEE 1801 standard can be purchased from IEEE Standards website:http://standards.ieee.org/prod-serv/index.html 

For more details on the IEEE 1801 Working Group activity, you can sign up for

1801 email group by sending an email to owner-p1801@eda.org.

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UPF Solutions Providers

Dolphin Technology