VALLIAMMAI ENGINEERING COLLEGE

SRM Nagar, Kattankulathur – 603 203

DEPARTMENT OF INFORMATION TECHNOLOGY

QUESTION BANK

III SEMESTER

CS6303-Computer Architecture

Regulation – 2013

Academic Year 2017-2018 (Odd Semester)

Prepared by

Ms.S.Jeyalakshmi, Assistant Professor (Sel.G)/IT

Mr.E.Prabhakarraj, Assistant Professor (O.G)/IT

UNIT I OVERVIEW & INSTRUCTIONS

Eight ideas – Components of a computer system – Technology – Performance – Power wall-Uniprocessors

to multiprocessors; Instructions – operations and operands – representing instructions – Logical operations –

control operations – Addressing and addressing modes.

PART-A

Q.No. Question Level Competence

1. Define Amdhal’s Law BTL 1 Remembering

2. State the need for indirect addressing mode.Give an example. BTL 1 Remembering

3. List the major components of a computer system. BTL 1 Remembering

4. Distinguish Pipelining from Parallelism BTL 2 Understanding

5. What is an Instruction register? BTL 1 Remembering

6. How CPU execution time for a program is calculated? BTL 1 Remembering

7. How to represent Instruction in a Computer System? BTL 1 Understanding

8. Distinguish between auto increment and auto decrement

addressing mode BTL 2 Understanding

9. Discuss briefly about VLSI BTL 2 Understanding

10. Differentiate Throughput and Response Time BTL 2 Understanding

11. Select and Apply the formula for the calculation of CPU clock

cycles required for a program. BTL 3 Applying

12. Illustrate – Stored Program Concepts BTL 3 Applying

13. How will you measure the dynamic power dissipation? How it

differs from static power dissipation.

BTL 3 Applying

14. Explain operations to perform sum of four variables b,c,d,e and

store the result in a. BTL 4 Analyzing

15. Analyze the fields in an MIPS instruction? BTL 4 Analyzing

16. Analyze shortly about the functions of data path and control

path BTL 4 Analyzing

17. Explain application binary interface BTL 5 Evaluating

18. Compare DRAM from SRAM BTL 5 Evaluating

19. List the advantages of multiprocessor over uniprocessor BTL 6 Creating

20.

Formulate If computer A runs a program in 10 seconds, and

computer B runs the same program in 15 seconds, how much

faster is A over B.

BTL 6 Creating

PART-B

Q.No. Question Level Competence

1

Examine the following

i) Assume a two address format specified as source, destination.

Examine the following sequence of instructions and explain the

addressing modes used and the operation done in every

instruction. (8)

(1) Move (R5)+,R0

(2) Add (R5)+,R0

(3) Move R0, (R5)

(4) Move 16(R5), R3

(5) Add #40,R5

ii) Consider the computer with three instruction classes and

CPI measurements as given below and instruction counts for

each instruction class for the same program from two different

compilers are given. Assume that the computer’s clock rate is

4GHz. Which code will execute faster according execution

time? (5)

Code from CPI for this Instruction Class

A B C

CPI 1 2 3

Code from Instruction count for each class

A B C

BTL 3

Remembering

Compiler 1 2 1 2

Compiler 2 4 1 1

2

i) Examine the various components of computer System with

neat diagram (7)

ii) State and show the CPU performance equation and discuss

the factors that affect performance. (6)

BTL 4

Remembering

3 Describe about the various techniques to represent instructions

in a computer system (13) BTL 4 Understanding

4 What is the need for addressing in a computer system? Explain

the different addressing modes with suitable examples (13) BTL 4 Remembering

5

i)Explain in detail about Eight great ideas of computer

Architecture.(7)

ii) Explain in detail about Technologies for Building Processors

and Memory (6)

BTL 5

Analyzing

6 Explain operations and operands of computer Hardware in

detail (13) BTL 5 Analyzing

7

i)Discuss the Logical operations and control operations of

computer (9)

ii)Discuss shortly about Power wall(4)

BTL 6

Understanding

8

Analyze the following

Consider three different processors P1, P2, and P3 executing

the same instruction set. P1 has a 3 GHz clock rate and a CPI of

1.5. P2 has a 2.5 GHz clock rate and a CPI of 1.0. P3 has a 4.0

GHz clock rate and has a CPI of 2.2.

a. Which processor has the highest performance expressed in

instructions per second?(7)

b.If the processors each execute a program in 10 seconds, find

the number of cycles and the number of instructions.

c.We are trying to reduce the execution time by 30% but this

leads to an increase of 20% in the CPI. What clock rate should

we have to get this time reduction?(6)

BTL 6

Analyzing

9

Measure the Following

Assume a program requires the execution of 50 × 106 FP

instructions,110 × 106 INT instructions, 80 × 106 L/S

instructions, and 16 × 106 branch instructions. The CPI for each

type of instruction is 1, 1, 4 and 2 respectively. Assume that the

processor has a 2 GHz clock rate.

a. By how much must we improve the CPI of FP instructions if

we want the program to run two times faster?(5)

b. By how much must we improve the CPI of L/S instructions if

we want the program to run two times faster?(4)

c. By how much is the execution time of the program improved

if the CPI of INT and FP instructions is reduced by 40% and

the CPI of L/S and Branch is reduced by 30%?(4)

BTL 5

Evaluating

10 Summarize Branching operations with example.(13) BTL 6 Creating

11 Examine the CPU performance equation and discuss the factors

that affect performance.(13) BTL 3 Applying

12

Illustrate the following addressing modes in detail with diagram

i)Immediate addressing

ii)Register addressing

iii)Base or displacement addressing,

iv)PC-relative addressing

v)Pseudo direct addressing (13)

BTL 3 Applying

12 Explain the important measures of the performance of a

computer and derive the basic performance equation. (13) BTL 1 Remembering

14 Summarize the Technologies for Building Processors

And Memory and The chip manufacturing process.(13) BTL 2 Understanding

PART – C

Q.No. Question Level Competence

1 A pipelined processor uses delayed branch technique.

Recommend any one of the following possibility for the design

of the processor. In the first possibility, the processor has a 4-

stage pipeline and one delay slot. In the second possibility, it

has a 6-stage pipeline and two delay slots. Compare the

performance of these two alternatives, taking only the branch

penalty into account. Assume that 20% of the instructions are

branch instructions and that an optimizing compiler has an 80%

success rate in filling in the single day slot. For the second

alternative, the compiler is able to fill the second slot 25% of

the time.(15)

BTL 5

Evaluating

2 Integrate the eight ideas from computer architecture to the

following ideas from other fields:

a. Assembly lines in automobile manufacturing. (5)

b. Express elevators in buildings. (5)

c. Aircraft and marine navigation systems that incorporate

wind information.(5)

BTL 6 Creating

3 Explain the steps that transform a program written in a high

level language such as C into a representation that is directly

executed by a computer processor. (15)

BTL 4 Analysing

4 Explain the basic functional units with an example.(15) BTL 4 Analysing

UNIT II ARITHMETIC OPERATIONS

ALU - Addition and subtraction – Multiplication – Division – Floating Point operations – Subword

parallelism.

PART-A

Q.No. Question Level Competence

1. Define Little Endian arrangement BTL 1 Remembering

2. What is DMA? BTL 1 Remembering

3. What is arithmetic overflow? BTL 1 Remembering

4. Summarize the representation of double precision floating

point number BTL 2 Understanding

5. Write the rules to perform addition on floating point numbers. BTL 1 Remembering

6. What do you mean by sub word parallelism? BTL 1 Remembering

7. What is a guard bit and what are the ways to truncate the guard

bits? BTL 1 Remembering

8. Give the Multiplication hardware diagram BTL 2 Understanding

9. Describe fast multiplication? BTL 2 Understanding

10. Differentiate the scientific notation and normalization? Give

an example. BTL 2 Understanding

11. Illustrate the overflow and under flow with examples BTL 3 Applying

12. Examine – Guard and Round BTL 3 Applying

13. Apply the MIPS assembly code for the following C

expression?

f = g + (h − 5)

BTL 3 Applying

14.

Analyze and connect the corresponding C statements for the

following MIPS assembly instructions

add f, g, h

add f, i, f

BTL 4 Analyzing

15. Point out the representation of single precision floating point

number BTL 4 Analyzing

16. Analyze and subtract(11010)2-(10000)

2 using 1’s complement

and 2’s complement method BTL 4 Analyzing

17. Integrate the steps of floating point multiplication BTL 5 Evaluating

18. Explain the floating point instructions in MIPS? BTL 5 Evaluating

19. Substitute and Multiply 100010 * 100110. BTL 6 Creating

20. Substitute and Add 610 to 710 in binary and Subtract 610 from

710 in binary BTL 6 Creating

PART-B

Q.No. Question Level Competence

1.

Examine the following

i) Multiply the following pair of signed nos.

using Booth’s bit-pair recording of the

multiplier. A=+13 (Multiplicand) and B=-6

(Multiplier). (8)

ii) Briefly explain Carry look ahead adder. (5)

BTL 1 Remembering

2.

Analyze the following

Divide (12)10 by (3)10using the Restoring and

Non restoring division algorithm with step by

step intermediate results and explain.(13)

BTL 4 Analyzing

3. Explain the sequential version of multiplication

algorithm and its hardware (13) BTL 1 Remembering

4.

Discuss how floating point addition is carried

out in a computer system. Give an example for a

binary floating point addition.(13)

BTL 3 Applying

5.

Explain in detail about the (Booth)

multiplication algorithm with suitable example

and diagram (13)

BTL 2 Understanding

6. Discuss in detail about division algorithm in

detail with diagram and examples(13) BTL 3 Applying

7. Explain briefly about floating point addition and

subtraction algorithms. (13) BTL 1 Remembering

8. Give the algorithm for multiplication of signed 2’s

complement numbers and illustrate with an

example (13) BTL 4 Analyzing

9.

Substitute and Add the numbers 0.510 and -

0.437510using binary Floating point Addition

algorithm (13)

BTL 5 Evaluating

10.

a.Design an arithmetic element to perform the

basic floating point operations.(7)

b.What is meant by subword parallelism?.

Formulate an example(6)

BTL 6

Creating

11.

Describe steps and Calculate the division of A

and B

A : 3.264 X 103 B: 6.52 X 10

2 . (13)

BTL 2 Understanding

12.

Summarize the IEEE 754 binary representation

of the number -0.75 10in single and double

precision. (13)

BTL 2 Understanding

13. Write in detail about sub word parallelism. (13) BTL 1 Remembering

14.

a.Demonstrate and Explain multiplication of two

binary numbers with an example. Design an

arithmetic element to perform this

multiplication.(7)

b.Explain non restoring division with an

example.(6)

BTL 4 Analyzing

PART – C

Q.No. Question Level Competence

1 Evaluate 4 bit version of the algorithm to

save pages, for dividing 000001112 by 00102

with hardware design.(15)

BTL 5

Evaluating

2 Develop the binary representation of the

decimal number 63.25 assuming IEEE

754

A.single precision format. (8)

B.Double precision format. (7)

BTL 6 Creating

3 What is the disadvantage of Riple carry

addition and how it is overcome in carry

look ahead adder and Design the logic

circuit CLA.(15)

BTL 6 Creating

4 Design a binary multiplier using sequential

adder. Explain its operation. (15) BTL 6 Creating

UNIT III PROCESSOR AND CONTROL UNIT

Basic MIPS implementation – Building datapath – Control Implementation scheme – Pipelining –

Pipelined datapath and control – Handling Data hazards & Control hazards – Exceptions.

PART-A

Q.No. Question Level Competence

1. Describe the need for speculation? BTL 2 Understanding

2. Discuss about Exception? BTL 2 Understanding

3. Summarize R-Type instructions? BTL 2 Understanding

4. Demonstrate branch prediction buffer? BTL 3 Applying

5. Describe hazard? Summarize its types? BTL 2 Understanding

6. What is a Data path? BTL 1 Remembering

7. Show the advantages of pipelining? BTL 3 Applying

8. Name the control signals required to perform

arithmetic operations. BTL 1 Remembering

9. Explain the use of PC register? BTL 4 Analyzing

10. Define hazard. Give an example for data hazard. BTL 1 Remembering

11. What is meant by delayed branch? BTL 1 Remembering

12. What is meant by forwarding? BTL 1 Remembering

13. Illustrate pipeline bubble? BTL 3 Applying

14. Rewrite the 5 pipeline stages? BTL 6 Creating

15. Explain with example exceptions and interrupts? BTL 5 Evaluating

16. Define – Vectored Interrupts BTL 1 Remembering

17. Analyze the five steps in MIPS instruction

execution? BTL 4 Analyzing

18. Measure the three instruction classes and their

instruction formats? BTL 5 Evaluating

19. Compose the formula for calculating time between

instructions in a pipelined processor. BTL 6 Creating

20. Differentiate branch taken from branch not taken. BTL 4 Analyzing

PART-B

Q.No. Question Level Competence

1. What is Hazard? Explain its types with suitable

example.(13) BTL 1 Remembering

2.

a.Explain the hazards caused by unconditional branching

branching statements.(7)

b.Describe and Explain operand forwarding in a pipeline

processor with a diagram.(6)

BTL 4 Analyzing

3. Discuss the different types of pipeline hazards with

suitable examples.(13) BTL 2 Understanding

4. Explain in detail how exceptions are handled in MIPS

architectures (13) BTL 1 Remembering

5. Why is branch prediction algorithms needed?

Differentiate between static and dynamic techniques.(13) BTL 2 Understanding

6.

Illustrate with an example How the instruction pipeline

works? What are the various situations where an

instruction pipeline can stall? (13)

BTL 3 Applying

7. What is pipelining? Discuss about pipelined data path and

control. (13) BTL 1 Remembering

8.

Summarize the following in detail

a. Building a datapath.(7)

b. Control implementation scheme.(6)

BTL 5 Evaluating

9. Discuss the modified data path to accommodate pipelined

executions with a diagram.(13) BTL 2 Understanding

10. What is data hazard? How do you overcome it? What are

its side effects? (13) BTL 1 Remembering

11. Classify the control hazards? Explain the methods for

dealing with the control hazards. (13) BTL 4 Analyzing

12. Illustrate the basic MIPS implementation of instruction set

(13) BTL 3 Applying

13. Explain the Multiple-clock-cycle pipeline diagram of five

instructions. (13) BTL 4 Analyzing

14. Prepare the scenario in which forwarding or stalling is

preferable. (13) BTL 6 Creating

PART – C

Q.No. Question Level Competence

1 Assume the following sequence of instructions are

executed on a 5 stage pipelined datapath:

add r5,r2,r1

lw r3,4(r5)

lw r2,0(r2)

or r3,r5,r3

sw r3,0(r5).Analyse and answer the following questions.

a.if there is no forwarding or hazard detection, insert

NOPS to ensure correct execution.If the processor has

forwarding, but we forgot to implement the hazard

detection unit, what if happens when this code executes?

(5)

b.If there is forwarding, for the first five cycles, compose

which Signals are asserted in each cycle.(5)

c.If there is no forwarding, what if new inputs and output

signals do we need for the hazard detection unit.(5)

BTL 4

Analysing

2 Plan the pipelining in MIPS architecture and generate the

exceptions handled in MIPS.(15) BTL 6 Creating

3 Draw and explain the modified three bus structure of the

processor suitable for four –stage pipelined execution.

How this structure is suitable to provide four stage

pipelined execution?(15)

BTL 5 Evaluating

4 Explain the function of a six segment pipelines and draw a

space diagram for a six segment pipeline showing the time

it takes to process eight tasks. (15)

BTL 5 Evaluating

UNIT IV PARALLELISM

Instruction-level-parallelism – Parallel processing challenges – Flynn's classification – Hardware

multithreading – Multicore processors

PART-A

Q.No. Question Level Competence

1. What is Flynn’s Classification? BTL 1 Remembering

2. Explain about multithreading BTL 4 Analyzing

3. Compare Strong scaling and Weak Scaling BTL 5 Evaluating

4. Differentiate UMA and NUMA multiprocessors BTL 4 Analyzing

5. What is instruction level parallelism? BTL 1 Remembering

6. Define a super scalar processor BTL 1 Remembering

7. Classify the need for Instruction Level parallelism BTL 3 Applying

8. Rewrite about fine grained Multithreading BTL 6 Creating

9. Demonstrate multiple issues? Write any two approaches. BTL 3 Applying

10. What is meant by speculation BTL 1 Remembering

11. Classify – Issue Slots and Issue Packet BTL 3 Applying

12. Describe shortly about– VLIW BTL 2 Understanding

13. Distinguish implicit multithreading and explicit

multithreading. BTL 2 Understanding

14. Discuss about anti-dependence? How is it removed? BTL 2 Understanding

15. Differentiate in-order execution from out-of-order

execution. BTL 4 Analyzing

16. Prepare the two main approaches to hardware

multithreading? BTL 6 Creating

17. What is SMT? BTL 1 Remembering

18. Compare SMT from hardware multithreading.

BTL 5 Evaluating

19. Define a cluster BTL 1 Remembering

20. Discuss shortly about – SMP BTL 2 Understanding

PART-B

Q.No. Question Level Competence

1. Explain Instruction level parallelism. State the challenges

of parallel processing. (13) BTL 4 Analyzing

2.

Combine and write notes about single core and multicore

processors in terms of their physical limits, complexity,

speed with an example.(13)

BTL 5 Evaluating

3. Discuss shared memory multiprocessor with a neat

diagram.(13) BTL 2 Understanding

4.

What is hardware multithreading? Compare and contrast

Fine grained Multi-Threading and Coarse grained Multi-

Threading. (13)

BTL 1 Remembering

5.

a.Discuss the challenges in parallel processing with

necessary examples.(7)

b.Describe Flynn’s classification of parallel processing

with necessary diagrams.(6)

BTL 2 Understanding

6. Describe in detail about hardware Multithreading.(13) BTL 1 Remembering

7. Explain cluster and other Message passing Multiprocessor

(13) BTL 4 Analyzing

8. What is a Multicore processor, Explain how it is

implemented? (13) BTL 1 Remembering

9. Explain the four principal approaches to multithreading

with necessary diagrams.(13) BTL 4 Analyzing

10. Write a short on different types of multithreading (13) BTL 1 Remembering

11.

Solve the following To achieve the speed-up of 20.5 on

the previous larger problem with 40 processors, we

assumed the load was perfectly balanced. That is, each of

the 40 processors had 2.5% of the work to do. Instead,

show the impact on speed-up if one processor’s load is

higher than all the rest. Calculate at twice the load (5%)

and five times the load (12.5%) for that hardest working

processor. How well Utilized are the rest of the

processors?(13)

BTL 3 Applying

12. Write a differentiation notes on Thread-level parallelism,

Instruction-level parallelism, Data-level parallelism BTL 2 Understanding

13.

Design: Suppose you want to perform two sums: one is a

sum of 10 scalar variables, and one is a matrix sum of a

pair of two-dimensional arrays, with dimensions 10 by 10.

For now let’s assume only the matrix sum is

parallelizable. What speed-up do you get with 10 versus

40 processors? Next, calculate the speed-ups assuming the

matrices grow to 20 by 20.(13)

BTL 6 Creating

14.

Illustrate the following

Suppose you want to achieve a speed-up of 90 times faster

with 100 processors. What percentage of the original

computation can be sequential?(13)

BTL 3 Applying

PART – C

Q.No. Question level Competence

1 Explain how would this loop be scheduled on a static two issue pipeline for MIPS? Loop: lw $t0,0($s1) #$t0=array element Addu $t0,$t0,$s2 #add scalar in $s2 Sw $t0, 0($s1) # store result Addi; %s1,$s1, -4#decrement pointer Bne $s1,$zero,loop # branch $s1!=0

Decide and reorder the instruction to avoid as

many pipeline stalls as possible. Assume

branches are predicted, so that control hazards

are handled by the hardware.(15)

BTL 5 Evaluating

2 Explain the principle of hardware

multithreading and elaborate its types in a

detailed way.(15)

BTL 5 Evaluating

3 Explain SISD,MISD,MIMD and SIMD with

an example.(15)

BTL 4 Analysing

4 Explain in detail how branch penalties are

reduced with dynamic hardware

prediction.(15)

BTL 4 Analysing

UNIT V MEMORY AND I/O SYSTEMS

Memory hierarchy - Memory technologies – Cache basics – Measuring and improving cache performance -

Virtual memory, TLBs - Input/output system, programmed I/O, DMA and interrupts, I/O processors.

PART-A

Q.No. Question Level Competence

1. Differentiate Programmed I/O and Interrupt

I/O BTL 4 Analyzing

2. Describe the purpose of Dirty/Modified bit in

Cache memory? BTL 2 Understanding

3. Define memory interleaving. BTL 1 Remembering

4. Prepare and Point out how DMA can improve

I/O speed BTL 5 Evaluating

5. Explain the various memory technologies? BTL 4 Analyzing

6. Define Hit ratio BTL 1 Remembering

7. Discuss about Memory hierarchy? BTL 2 Understanding

8. Discuss the advantages of virtual memory? BTL 2 Understanding

9. What is cache memory? BTL 1 Remembering

10. Differentiate SRAM from DRAM. BTL 2 Understanding

11. Define − Rotational Latency BTL 1 Remembering

12. Solve-Consider a cache with 64 blocks and a

block size of 16 bytes. To what block number

does byte address 1200 map?

BTL 3 Applying

13. Solve -How many total bits are required for a

direct-mapped cache with 16 KB of data and

4-word blocks, assuming a 32-bit address?

BTL 3 Applying

14. Explain the writing strategies in cache

memory? BTL 4 Analyzing

15. Examine the steps to be taken in an

instruction cache miss? BTL 3 Applying

16. Define – AMAT BTL 1 Remembering

17. Formulate the three ways to improve MTTF? BTL 6 Creating

18. Compare physical address from logical

address. BTL 6 Creating

19. Evaluate and summarize the sequence of

events involved in handling an interrupt

request from a single device.

BTL 5 Evaluating

20. What is meant by address mapping? BTL 1 Remembering

PART-B

Q.No. Question Level Competence

1.

i) Explain mapping functions in cache

memory to determine how memory blocks are

placed in Cache. (7)

ii) Explain in detail about the Bus Arbitration

techniques in DMA. (6)

BTL 3 Applying

2.

Illustrate the following

i) Draw different memory address layouts and

brief about the technique used to increase the

average rate of fetching words from the main

memory. (7)

ii) Explain in detail about any two Standard

Input and Output Interfaces required to

connect the I/O device to the bus.(6)

BTL 3 Applying

3. Summarize the various memory technologies

and its relevance (13) BTL 2 Understanding

4.

What is virtual memory? Explain the steps

involved in virtual memory address

translation. (13)

BTL 1 Remembering

5.

Describe and Draw the typical block diagram

of a DMA controller and explain how it is

used for direct data transfer between memory

and peripherals.(13)

BTL 2 Understanding

6. Explain in detail about I/O processor. (13) BTL 6 Creating

7. Describe in detail about programmed

Input/output with neat diagram.(13) BTL 1 Remembering

8. Explain in detail about interrupts with

diagram.(13) BTL 4 Analyzing

9. Discuss DMA controller with a block

diagram. (13) BTL 2 Understanding

10. Explain in detail about memory Hierarchy

with neat diagram. (13) BTL 4 Analyzing

11. Explain in detail

i). various mapping schemes used in cache

design (8) BTL 4 Analyzing

ii). A byte addressable computer has a small

data cache capable of holding eight 32-bit

words. Each

Cache block contains 132-bit word. When a

given program is executed, the processor reads

data

from the following sequence of hex addresses –

200, 204, 208, 20C, 2F4, 2F0, 200, 204,218,

21C, 24C, 2F4. The pattern is repeated four

times. Assuming that the cache is initially

empty,

show the contents of the cache at the end of

each pass, and compute the hit rate for a direct

Mapped cache. (5)

12. Formulate the Procedure to handle TLB

Misses and Page Faults.(13) BTL 5 Evaluating

13.

Describe in detail about Memory mapped and

Interrupted Input /output with neat

diagram.(13)

BTL 1 Remembering

14.

Examine the procedure in which a page table

is indexed with the virtual page number and

obtain the physical address.(13)

BTL 1 Remembering

PART – C

Q.No. Question Level Competence

1 i.Explain mapping functions in cache memory

to determine how memory blocks are placed in

cache.(8)

ii.Explain in detail about the Bus Arbitration

techniques in DMA.(7)

BTL 5 Evaluating

2 Design and explain a parallel priority

interrupt hardware for a system with eight

interrupt sources.(15) BTL 6 Creating

3 For a direct mapped cache design with a 32 bit

address, the following bits of the address are

used to access the cache.Analyse and answer

the following questions.

Tag : 31-10 Index: 9-5 Offset: 4-0

a.Judge what is the cache block size? (5)

BTL 4 Analyzing

b.Decide how many entries does the cache

have? (5)

c.Assess what is the ratio between total bits

required for such a cache implementation

over the data storage bits?(5)

4 Compare and summarize how the TLB works

on the intrinsity fast math processor.(15) BTL 5 Evaluating