Abstract: We present a compact 50 µm x 100 µm cell for single-photon detection, based on a new circuitry monolithically integrated together with a 20 µm-diameter CMOS Single-Photon Avalanche Diode (SPAD). The detector quenching relies on a novel mechanism based on starving the avalanche current till quenching through a variable-load (VLQC, Variable-Load Quenching Circuit). Fabricated in a standard 0.35 µm CMOS technology, the topology allows a SPAD bias voltage higher than the chip supply voltage to be used. Moreover it preserves the advantages of active quenching circuits, in terms of hold-off capability (from 40 ns to 2 µs) and fast reset (≤2 ns), while maintaining the low avalanche charge (≤1.6 pC/avalanche) and extremely small dimensions of passive quenching circuits. The cell enables the development of large-dimension dense arrays of SPADs, for two-dimensional imaging at the photon counting level with photon-timing jitter better than 40 ps.
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and based on an Event-Driven Readout for TCSPC Experiments,” Proc. SPIE 6372, 63720S (2006). 8. H. Finkelstein, M.J. Hsu, S. Zlatanovic, S.C. Esener, “Performance trade-offs in single-photon avalanche
diode miniaturization,” Review of Scientific Instruments 78, 103103 (2007). 9. D. Mosconi, D. Stoppa, L. Pancheri, L. Gonzo, A. Simoni, “CMOS Single-Photon Avalanche Diode Array
for Time-Resolved Fluorescence Detection,” in Proceedings of 32nd European Solid-State Circuit Conference - ESSCIRC '06 (Institute of Electrical and Electronics Engineers, New York, 2006), pp.564-567.
10. F. Zappa, A. Lotito, A. C. Giudice, S. Cova, and M. Ghioni, “Monolithic active-quenching and active-reset circuit for single-photon avalanche detectors,” IEEE J. Solid-State Circuits 38, 1298-1301 (2003).
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14. A.C. Giudice, M. Ghioni, S. Cova, F. Zappa, “A process and deep level evaluation tool: afterpulsing in avalanche junctions,” in Proceedings of 33rd European Solid-State Device Research - ESSDERC '03 (Institute of Electrical and Electronics Engineers, New York, 2003), pp. 347-350.
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16. A Gulinatti, P. Maccagnani, I. Rech, M. Ghioni, S. Cova, “35 ps time resolution at room temperature with large area single photon avalanche diodes,” IEEE Electron. Lett. 41, 272-274 (2005).
1. Single-photon counting
High-sensitivity two-dimensional (2D) arrays of photodetectors are required in many fields, the most demanding of them requiring single-photon sensitivity in the visible and near-infrared (400 nm – 850 nm) wavelength range, like Fluorescence Lifetime Imaging (FLIM) [1], micro-array-based biological analysis [2], adaptive optics [3] and confocal microscopy [4], just to name a few.
In many cases such arrays may have a limited amount of pixels (e.g. 8x8), but single-photon sensitivity, low pixel noise and high fill-factor (possibly no blind regions) are still mandatory characteristics. Moreover, advanced applications require also very fast frame rates, up to 100 kframe/s, hardly attained with conventional CCD sensors, in order to enable precise time-tagging of incoming photons for movie-like 2D acquisition of fast optical transients [5].
The most suitable solid-state detector with single-photon sensitivity is the Single-Photon Avalanche Diode (SPAD) [6] that, when biased above its breakdown voltage VB, can be triggered by a photon that ignites a self-sustaining avalanche multiplication process. The SPAD is a “trigger” (Geiger-mode) detector, hence it differs from an Avalanche Photodiode (APD), which is operated below breakdown in the analog multiplication regime. As a matter of fact, SPAD relies on a positive feedback loop of impact ionizations, ignited by a first single carrier and sustained by the ionization-induced electron-hole pairs generation. Ignitions not due to photons, but caused by thermal generation or tunneling effect within the semiconductor, are called dark-counts, and represent the SPAD intrinsic noise. Moreover, ignitions due to carriers released by trapping centers are called afterpulses and impair detection linearity and detector noise in general [6].
The final avalanche current (tens or hundreds of milliamps) is limited only by the overall series resistance and depends on the excess voltage above breakdown at which the SPAD is biased. After the SPAD gets triggered, a suitable quenching/reset electronics must quench the avalanche current, by lowering the bias voltage down to VB, and then must restore the operating voltage [6].
State-of-the-art SPADs are fabricated in custom technologies, have spectral efficiency tailored to the wavelength range of interest, and provide the best performances in terms of dark-counts and afterpulsing. However, in recent years, different researchers reported on SPADs fabricated in standard high-voltage [7,9] or even low-voltage [8] CMOS processes with sufficiently high degree of purity. Such CMOS-compatibility opened the way to the development of arrays of SPADs and to the monolithic integration of SPADs with quenching/reset circuits [10] and with additional electronics [11].
The main challenge of SPAD arrays is the need to have many quenching/reset circuits, one for each pixel, that could act in parallel with no cross-talk, small power consumption, and limited area overhead. We present a very compact fully-standard CMOS cell, comprising a SPAD and a novel quenching/reset electronics that provides a building block for the fabrication of high-density photon counting and photon timing arrays.
2. Traditional quenching circuits and drawbacks
The simpler way to employ a SPAD is through a passive-quenching circuit (PQC), i.e. a simple resistance put in series with the detector. However PQC sets severe limitations on the maximum admissible photon counting rate and on the detector performance in general [6]. Moreover it does not allow holding off the detector for a user-adjustable time after each avalanche ignition, in order to reduce afterpulsing [6].
Better approaches were pioneered and developed by Cova [6], in order to fully exploit the best performance of SPADs through Active-Quenching Circuits (AQC). The basic idea is to sense the rise of the avalanche pulse and react back on the detector, through swift quenching and reset transitions, by means of a controlled voltage driver. The advantages are manifold. (i)
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The duration of the avalanche current pulse is constant and depends on the time taken by the signal to travel from the SPAD to the AQC, forth and back, and on the speed of the quenching action. By reducing this loop time and speeding up quenching action, power dissipation is minimized. (ii) Also the number of filled trapping centers (proportional to the number of flowing charges) is reduced, thus minimizing afterpulsing. (iii) The hold-off time is easily adjustable by means of a monostable. (iv) Reset action is fast (few nanoseconds), thus minimizing the probability of an avalanche being anomalously triggered during it.
A mixed passive-active quenching [10] approach is very useful for minimizing avalanche charge, particularly for SPADs having intrinsically small stray capacitance and series resistance, which could be impaired by electronics parasitism. As shown in Fig. 1, a high-value passive load RL provides a prompt passive quasi-quenching of the avalanche current. Then a comparator senses the signal across a sensing resistance RS and starts an active action that completes the quenching, by forcing the SPAD voltage definitely below breakdown through the quench switch. After an adjustable hold-off time, the control logic applies a fast reset transition to the SPAD through the reset switch.
In recent years, several other quenching circuits were proposed in literature. Since they are all based on traditional passive, active or mixed ones (see for instance the passive quenching – active reset scheme reported in Ref. [8]), the previous discussion is still applicable.
In general, in order to reduce afterpulsing and power dissipation, it is necessary to limit the avalanche charge, i.e. to reduce both the capacitance connected to the detector and the duration of the avalanche process. Concerning the capacitance, there is both the intrinsic SPAD capacitance and parasitic loading (due to interconnections and electronics). The former depends on detector size, layout design, fabrication technology, and depends on whether sensing is done at the anode or at the cathode. The latter depends mostly on the circuitry and can not be neglected, in particular when small area SPADs are employed. It is important to note that the integration of the quenching circuit on the same chip as the SPAD strongly reduces the parasitic capacitances due to interconnections. Concerning the avalanche process duration, the circuit must sense the ignition and act as soon as possible.
It is worth noting that the aforementioned requirements are well managed by the PQC, though with the discussed drawbacks. Conversely, AQCs tend to increase parasitic loading (due to the sensing components) and pulse duration (due to the need to reveal the avalanche before quenching the SPAD). Eventually, mixed passive-active quenching (and its derivatives) add the advantages of PQC and AQC approaches, while solving their drawbacks: passive quenching promptly begins as soon as the avalanche is ignited; active action introduces a reliable and adjustable hold-off time before reset. The last problem to solve is the reduction of the capacitance associated with the sensing input.
Fig. 1. Simplified schematic of a mixed passive-active quenching circuit. RL is the quenching resistor, while RS is a low value sensing resistor.
3. Variable-load quenching circuit
We devised a new circuit approach with the intent of reducing transistor count and sizes, in order to minimize loading without losing performance. Our goal was to develop a cell,
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consisting of a SPAD and the required quenching/reset electronics, to provide a building block for fabricating CMOS SPAD arrays.
Fig. 2 shows the cross-section of the CMOS SPAD detector, fabricated in AustriaMicroSystems 0.35 µm high-voltage technology, based on a 0.8 µm structure we previously reported in Ref. [11]. The active p+n junction is formed between an n-well (e.g. a standard high-voltage PMOS well), and a shallow p+ implantation (e.g. a PMOS source/drain region). A deeper diffused guard-ring (e.g. a high-voltage NMOS well) raises the breakdown voltage at the edge of the junction far above that of the active area (VB): in this technology the former is 60 V while the latter is 24 V. We chose a SPAD diameter of 20 µm, which provides a good trade-off between low dark-counts (that increase with the depleted volume) and large active area. The p-substrate is shared with the electronics, hence it must be kept to ground, in order to avoid direct biasing of the p-substrate/n-well junction. As can be seen from Fig. 2, due to the wider space charge region between the cathode n-well and the p-substrate, compared to that between the p+ anode and the substrate, the detector intrinsic capacitance to ground is higher at the cathode than at the anode. For this reason we decided to sense and quench the SPAD through the anode.
Concerning the electronics, we opted for a novel quenching/reset via a resistive path, whose value is adjusted while time elapses, in order to ensure the best value in each phase of SPAD operation. Indeed, after ignition, an increasing resistance is desirable for augmenting passive quenching hence starving the current until the avalanche process stops; during hold-off an open circuit prevents further ignitions; eventually during reset a very low resistance is advisable to quickly restore quiescent condition and promptly enable the detection of a new photon.
A voltage-controlled MOS transistor can be a solution. The basic idea is shown in Fig. 3, left. In quiescence, the SPAD cathode is reverse biased above breakdown (VREV > VB) with the desired excess voltage (VEX = VREV - VB), while the anode is kept to ground through transistor MS, whose gate is at the positive supply. As soon as an avalanche is ignited, the comparator senses the voltage rise across the transistor and the control logic reacts by lowering the voltage applied to its gate, thus increasing the transistor resistance until it switches completely off. Eventually the gate voltage is raised again, thus grounding the anode and resetting the SPAD.
Note that transistor MS is not a simple on/off reset switch, as employed in other circuits reported in literature. It plays more advanced roles in sensing, quenching, and reset phases. At first sight, it could seem that its low-impedance path after the reset phase (i.e. during the avalanche sensing) is a drawback. In effect, if MS would remain in the triode region with a low-value RON resistance, the avalanche current would reach too high a level before triggering the comparator (see Fig. 3). Instead transistor MS acts as an active variable-impedance, even with no intervention of the control logic (i.e. even if its gate voltage is kept constant), since it moves from triode to saturated (current-limited) region, during the avalanche build-up, thus current-starving the SPAD and efficiently providing its partial quenching. Moreover, with the intervention of the control logic, an active quenching action further speeds up and completes the suppression of the avalanche process.
Fig. 2. Cross-section of the CMOS SPAD integrated into the cell.
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Fig. 3. Principle of the proposed quenching/reset intervention by means of a variable-resistance MOS transistor (left) and current-voltage characteristics of a SPAD (right). Light lines connecting on and off branches represent ignitions that can occur when SPAD is biased above breakdown. VEX is the excess voltage, equal to the difference between the applied reverse bias VREV and the breakdown voltage VB.
Fig. 4. (Top) The non-linear characteristic of the transistor is able to limit avalanche current even with no intervention of the control logic, moving from few hundreds Ohm toward some hundreds kΩ. (Center) The active action of the control logic switches off the transistor and speeds up the quenching. (Bottom) Eventually the transistor actively resets the SPAD. Note VT is the threshold voltage of transistor MS while VTH is the threshold of the following sensing stage.
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Fig. 4 illustrates how the cell carries out the different tasks. In order to locate the time-varying operating point, the simplified trans-characteristics of transistor MS is intersected with the SPAD characteristics. The latter (Fig. 3, right) shows two branches, depending if SPAD is still in quiescence (off-branch) or avalanche has been triggered (on-branch). Fig. 4 comprises all parasitism hanging to the sensing node, in particular the SPAD anode-to-ground capacitance Canode and the SPAD anode-to-cathode intrinsic capacitance CSPAD. The spurious loading of transistor MS and the comparator can be included into Canode. Since during the avalanche process some charge is spent to modify the space-charge region (i.e. the reverse voltage across the SPAD), the avalanche current through the junction splits into three paths, a current flow through CSPAD (effectively “within” the detector), one through Canode, and another through transistor MS (namely Isense).
During quiescence, the SPAD is off (i.e., off-branch of its characteristic), while transistor MS is on, hence Isense = 0 A and Vsense = 0 V. When a photon is absorbed and the avalanche is ignited, the SPAD turns to its on-branch. A high current, limited by the series resistance of the SPAD, starts flowing in Canode and CSPAD, thus the operating point of the circuit moves along the curve shown in Fig. 4, top. As the voltage Vsense increases, the current through Canode and CSPAD decreases, since an increasing part of the SPAD current is sunk by MS. As can be seen, notwithstanding the RON resistance of MS is initially low (about 800 Ω in our design), it promptly moves to much a higher value (hundreds of kΩ) as soon as the transistor enters into current-saturation, at a voltage of about VGS-VT, thus effectively limiting the current into the SPAD. In our design, the gate-source voltage of transistor MS is VGS = 3.3 V, while its threshold is VT = 0.7 V, hence it would enter into saturation at about 2.6 V. However, as soon as Vsense reaches the threshold voltage of the comparator (VTH = 0.7 V in our case, since it is equal to the threshold of the following MOS), the control logic enforces the active quenching.
During active intervention (Fig. 4, center), the control logic switches transistor MS completely off. Initially, the SPAD is still on, and its current flowing into Canode and CSPAD raises Vsense up to VEX. At this point, since the impedance of MS is very high (ideally infinite), the current in the SPAD is no more able to sustain the avalanche process, hence the SPAD turns to its off-branch and stays quenched for the hold-off time imposed by the control logic, until the reset transition is begun.
During reset (Fig. 4, bottom), transistor MS is switched on; though the SPAD is still off, since Vsense is at VEX, transistor MS is forced to enter first in the current-saturated regime and then, progressively, into the linear region, thus discharging the Sense node down to ground. Eventually the SPAD is restored to quiescence and is ready to detect another photon.
4. Cell structure
Figure 5 shows the cell schematics of the Variable-Load Quenching Circuit (VLQC). For reducing area, all passive components are made with MOS transistors. In order to reduce the loading at the anode, we simplified the comparator stage by employing a pass-transistor MP and a single-transistor amplifier MH. In this way, the pass-transistor decouples the sensing node from the loading of the gate-source and, especially, gate-drain capacitances of transistor MH.
In quiescence, the SPAD is waiting for a photon and acts as an open circuit, so the sensing node A is at ground. Since transistor MP is on, node B is grounded too, thus keeping transistor MH switched off. Nodes C and D are at the power supply VDD = 3.3 V, thus keeping transistor MS on.
When a photon (or a thermal generation or an afterpulse) triggers the SPAD, the avalanche current begins to flow and raises the voltage at nodes A and B, until transistor MH turns on and swiftly pulls down node C. Eventually transistor MS turns off, thus actively quenching the SPAD. While MS is off, node E lowers to ground, thus switching off pass-transistor MP and disconnecting the SPAD from transistor MH. The latter goes off, thanks to the high-value resistor Rpulldown, thus node C rises back to VDD, with time constant Rhold-off ⋅Chold-off. The time elapsed from MP switching off to MS switching on represents the circuit hold-off time.
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Fig. 5. VLQC cell schematics. Pass-transistor MP efficiently de-couples the sensing node from the capacitive loading of MH. (CA is the parallel of CSPAD and Canode of Fig. 3).
Fig. 6. Typical waveforms (solid lines) of the VLQC cell shown in Fig. 5 and effect (dashed lines) of an insufficient delay introduced by inverters I3 and I4 on the falling edge of node D.
Signal timings deserve some further comments. Though inverters I3 and I4 seem
unnecessary, on the contrary they play a fundamental role in differently delaying the rising and falling transitions of node D. Both delays must be precisely calibrated to allow reliable operations. Fig. 6 summarizes the typical waveforms. Dashed lines schematically show what happens in case of an insufficient delay of the falling edge of node D. As long as transistor MP is on, node B follows node A (except for the limitation due to the threshold voltage VT of transistor MP). During this phase it is important that MP remains on long enough to let signal
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B turn MH completely on and pull node C down to ground. Otherwise the discharge of capacitor Chold-off would start too soon, thus altering the effective hold-off time. Therefore inverters I3 and I4 must be properly sized, depending on the characteristics of the SPAD attainable in the technology in use (e.g. depending on its internal resistance, anode capacitance, etc.).
Conversely, Fig. 7 shows the importance of the delay introduced in respect to the rising edge at node D. When node D returns high, the reset phase begins, while the low level still present at node E keeps MH disconnected from the SPAD. Transistor MP should not be enabled too soon, otherwise when node D goes high and the SPAD starts being reset, MH could sense again the SPAD anode (not yet at ground) thus causing a spurious triggering and a false detection.
After reset, when the circuit is again ready to sense the SPAD (i.e. when MP turns on), two scenarios are possible depending if nothing happened or a photon hit the SPAD during the reset phase. In the former case, the circuit stays quiescent waiting for a photon. Instead, in the latter case (see Fig. 7), even if the exact waveforms at node A and B depends on the time instant the second avalanche was ignited during reset, node E will go high after the delay introduced by the inverters I3 and I4, thus starting a new quenching cycle. Since current keeps flowing through the SPAD until node E is low, care must be taken to trim this delay to be barely enough to avoid spurious ignition. This behavior was designed on purpose, in order to guarantee that the VLQC would never miss triggering occurring during the reset phase, thus showing high detection linearity. Indeed at increasing photon rates, the number of output pulses increases linearly and eventually saturates to roughly the inverse of the hold-off time (i.e. the maximum achievable counting rate). Instead, standard PQC approaches show a non monotonic trend at increasing photon fluxes: the number of output pulses initially increases, but then starts to decrease due to the increasing probability to have uncounted ignitions during reset. With those PQCs, with very high illumination levels, no output pulses are even produced, since the complete reset is always inhibited by the continuous current flow.
Fig. 7. When a photon hits the detector during the reset phase, the correct behavior of the cell must be guaranteed by a proper delay introduced by inverters I3 and I4 on the rising edge of node D.
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As concern the slew-rate of the reset transition, it is well known that it should be as fast as possible, in order to reduce dead-time and the probability of triggering occurring during reset. However, in every active reset circuit there is a clear trade-off between MOS driving capability as opposed to area occupation, capacitive load and peak current of avalanches triggered during reset. In addition, in our approach the transistor on-resistance should be not too low, otherwise the avalanche sensing would be too slow, and the initial passive quenching ineffective. For this reason, we performed parametric simulations in order to minimize the charge flowing during standard avalanches, while keeping at a reasonable level the charge flowing during avalanche triggered in the reset phase.
5. Cell fabrication
For designing and sizing the components of the VLQC cell, we employed the CAD environment by Cadence. In order to properly simulate the SPAD, we implemented the model reported in Ref. [12], with the resistance and capacitances values extracted from a SPAD fabricated in a test chip. Fig. 8 shows a microphotograph of the cell with the 20 µm-diameter SPAD. A thick polyamide passivation, visible on the left side of the Fig. as an opaque brown layer, covers all the chip, except for the bonding pads and the SPAD active area. The magnified picture on the right was instead taken after mechanical removal of the polyamide. The overall dimension is about 300 µm x 300 µm, including bonding pads and output buffer, though they are not necessary when the cell is used as one of many smart pixels to be put side by side to form an array. The dimensions of a single VLQC cell (SPAD included, but no output buffer) are only 50 μm x 100 μm, yielding a bare fill-factor of 6 %, that can be noticeably increased using micro lenses.
The SPAD breakdown voltage is VB = 24 V. The VLQC cell is biased at VDD = 3.3 V and the SPAD at a voltage supply Vrev, whose value is equal to VB augmented by the desired excess-bias VEX (see Fig. 5). It is very important to note that the maximum applicable excess bias is not limited to VDD like in all other AQCs so far reported in literature. In fact, though the SPAD cathode is biased to a high voltage (e.g. Vrev = 29V), the sensing node will swing from ground (as forced by transistor MS during reset) to a positive value imposed by the SPAD when it switches off (after an avalanche ignition), i.e. when the current through MS goes off and the voltage across the SPAD reduces to VB. Therefore the maximum positive value reached by the sensing node is equal the operating excess bias. This value can exceed the cell power supply VDD, but should not exceed the maximum absolute voltage rating of the technology, limited for instance by the maximum drain-gate voltage sustainable by transistors MS and MP of Fig. 5. For this reason we used transistors with thick oxide. In the 0.35 µm CMOS technology we employed, at VDD = 3.3 V the maximum sustainable voltage at the sensing node is 5 V. Therefore the maximum excess voltage is 5 V, hence Vrev must be limited to VB + VEX = 29V.
Fig. 8. Microphotograph of the VLQC cell. Note that a major part of the silicon estate is occupied by bonding pads and the output buffer, that are not necessary when the cell is merged into an array.
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At room temperature, at a counting rate of 20 Mcps (counts per second) and with 5 V-excess bias, the cell draws only 17 µA from the VDD supply of 3.3 V (350 µA including also the output buffer) and 30 µA from the Vrev supply.
In order to easily vary the hold-off time of the VLQC cell, we implemented the resistor Rhold-off of Fig. 5 with a p-channel MOS transistor. By varying its gate voltage from 0 V to 3.3 V, the hold-off time ranges from 40 ns to 2 µs. This feature is extremely useful for reducing the afterpulsing of the SPAD, as discussed in the following section.
6. Experimental results
We performed a full electrical and optical characterization of the VLQC cell. A summary of the key performance metrics at different excess bias with a 600 ns hold-off time is reported in Table 1. As can be seen, the dark-counting rate is well below 5 kcps (counts per second), while the photon detection efficiency reaches 42% at 430 nm-wavelength with negligible afterpulsing (less than 1%).
Table 1. Performances of 20 µm-SPAD cell, with 600 ns hold-off time.
Since it is well known [8, 13] that afterpulsing is the major problem of SPADs fabricated
in CMOS technologies, we accurately measured the dependence of the dark-counting rate on the hold-off time imposed after each avalanche ignition. In case of simple thermal generation, the intrinsic noise of the SPAD should be independent of hold-off duration. Instead, the increase of the dark-counting rate at short hold-off durations shown in Fig. 9 is a clear sign of afterpulsing. The longer the hold-off, the higher the probability that charges trapped during the previous avalanche current flow were released while the SPAD was off, hence the closer the dark-counting to the intrinsic thermal generation level. The latter is estimated at sufficiently long hold-off times, when all trapped charges are released and no longer contribute to SPAD ignitions.
Fig. 9. Dark-counting rate vs. hold-off time of the VLQC cell with the 20 µm-SPAD.
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Fig. 10. Total afterpulsing probability at different excess bias and hold-off times, for the 20 µm SPAD operated by the VLQC electronics.
We quantitatively measured the afterpulsing probability, by employing the Time-
Correlated Carrier Counting setup described in Ref. [14]. Results are presented in Fig. 10. Though afterpulsing is very high at short hold-off times, it drops to few percent at 300 ns, and it gets almost negligible (below 1%) beyond 600 ns. These values are comparable to those reported in literature for CMOS SPADs built in a similar technology but with only a 10 µm-diameter [7], and considerably lower if the same diameter is considered [9]. We compared this VLQC performance with those obtained by a stand-alone CMOS 20 µm SPAD from the same run, but with an off-chip AQC described in Ref. [15]. We measured an afterpulsing probability higher than 7% even with a 20 µs hold-off time. This proves the effectiveness of the VLQC cell in drastically reducing the total charge flowing through the detector, as well as allowing a fast release of trapped carriers.
Moreover, we noticed that afterpulsing probability of the VLQC cell is almost independent of excess bias, for a given hold-off duration. Since the peak avalanche current through the SPAD is proportional to the excess bias [6], one would expect a much higher increase in the afterpulsing probability with the excess bias. This low dependence is indeed an evidence that standard avalanche pulses give only a small contribution to afterpulsing. We ascertained instead that the main cause of afterpulsing are extended current pulses, as that shown in Fig. 11. These extended pulses are due to triggerings occurring during the reset phase, and they are present in all circuits employing an active reset, albeit often ignored in literature. In fact, if the SPAD is ignited when the reset switch is on, a large current (usually limited by the MOS itself) will keep flowing until the reset switch is reopened (or, in our case, the sensing loop is restored). Since the current is limited to the transistor saturation value, it does not depend on the applied excess bias and it shows an almost rectangular shape, as in Fig. 11. These ignitions could be due to afterpulsing, but also to real photon hitting the SPAD. In any case, this large amount of charge is likely to cause an important increase in afterpulsing. In addition, an improper handling of these events could even results in spurious or missed triggering, as well as circuit hang-up.
In our circuit, those pulses sustain a current of longer duration if compared with standard ones, and with an intensity equal to the saturated current of MS (see Fig. 4, top, when Vsense > VGS – VT) hence not related to excess bias. Such value is 900µA, depending on transistor sizing. For this reason, we are confident that we can further reduce afterpulsing by means of a more aggressive tailoring of the delay introduced by inverters I3 and I4 (as described in Sect. 4), that can shorten secondary pulses.
#89033 - $15.00 USD Received 25 Oct 2007; revised 7 Dec 2007; accepted 8 Dec 2007; published 1 Feb 2008
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Fig. 11. Measured VLQC output and SPAD current when a second triggering happens during the reset phase of first ignition. The hold-off (Thold-off) was set to about 40 ns. Note the extremely short duration of the first standard current pulse and the extended pulse of the second one.
Figure 12 shows the measured photon detection efficiency of the VLQC cell. The peak
reaches 42% at 5 V-excess bias in the blue-region of the visible wavelength range, due to the very shallow p-diffusion (see Fig. 2). The ringing in the detection spectrum is caused by the thick (few micrometers) intermetal oxide layers and passivation layer that cover the SPAD active area and act as optical interference coating.
Finally, we measured the time-jitter performance of the VLQC cell, of major importance in photon timing applications. The overall instrumental response to a 820 nm-laser with a pulse width shorter than 10 ps is reported in Fig. 13. The Full Width at Half Maximum at 5 V-excess bias is 39 ps, the Full Width at 1/100th of the Maximum is about 620 ps. The slow exponential tail has a time constant of 230 ps and is due to photons absorbed in the neutral region under the active junction, within the n-well diffusion (see Fig. 2). These values are better than those reported in literature for CMOS SPAD built in a similar technology [7,9] and favorably compare also to those obtained with SPADs fabricated in custom processes and operated by specifically designed current pick-up circuits [16]. All comparisons prove the effectiveness of the present VLQC cell in exploiting the high intrinsic time resolution of the SPAD.
Fig. 12. Detection efficiency at different excess bias for the VLQC cell. In order to avoid any artificial increase in the measured efficiency due to afterpulsing, the hold-off time was set to 600 ns.
#89033 - $15.00 USD Received 25 Oct 2007; revised 7 Dec 2007; accepted 8 Dec 2007; published 1 Feb 2008
(C) 2008 OSA 4 February 2008 / Vol. 16, No. 3 / OPTICS EXPRESS 2243
Fig. 13. Overall time resolution Full Width at Half Maximum and Full-Width at 1/100th of Maximum for the VLQC cell at 820 nm wavelength and at a 5 V-excess bias.
7. Conclusions
We have discussed in depth the design of an innovative quenching/reset circuit for operating single-photon avalanche diodes in the above-breakdown regime. The monolithic 50 µm x 100 µm cell is a complete single-photon detection pixel, with an on-chip 20 µm-diameter SPAD and active quenching and active reset electronics. The latter relies on a novel mechanism based on starving the avalanche current till quenching through a variable-load. The Variable-Load Quenching Circuit (VLQC) is fabricated in a standard 0.35 µm CMOS technology and allows the SPAD to be operated at an excess bias above the chip power supply voltage.
The cell enables the development of large-dimension dense arrays of SPADs, for two-dimensional imaging at the photon counting level. We are designing arrays of 8 x 8 and 10 x 10 such pixels with fully-parallel read-out for photon counting at high frame rates (faster than tens of kframes/s), time tagging of single photons (with resolution of few microseconds), and image acquisition with photon timing resolution of 40 ps.
#89033 - $15.00 USD Received 25 Oct 2007; revised 7 Dec 2007; accepted 8 Dec 2007; published 1 Feb 2008
(C) 2008 OSA 4 February 2008 / Vol. 16, No. 3 / OPTICS EXPRESS 2244
