Vhdl Design and Synthesis

7/30/2019 Vhdl Design and Synthesis

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VHDL DESIGN AND SYNTHESIS


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1. INTRODUCTION

DESIGN METHODOLOGY

Digital system design starts from the user specifications.Design of large systems is done at several levels. Translfrom natural language specification to silicon is a giant stIt has to be broken down in several stages.


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The hardware can be described in two ways:

STRUCTURALLYAs an interconnection of known components.

BEHAVIORALLYAs a functional description of signals.

There are three approaches of system design:

TOP DOWNFirst design the top-level behavior and then partition it intsmaller subsystem, then further smaller subsystem till you reachsimplecomponent level. Behavioral description is suitable for this approach. Thapproach is suitable for many FPGA based designs.

BOTTOM UPThis approach is used when a library of known low-levelstandard components are available. First build medium subsystem fromavailable components and then finally design the overall system.This issuitable for design of smaller system.

MIXEDThis approach starts from top-level but doesnt go right up to thcomponent level. It can be stopped when suitable medium level entities

realizing the design are found. This approach is suitable for ASIC desigvendor supplied cell libraries.

INTRODUCTION


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DIGITAL DESIGN FLOW FOR AUTOMATION

G S G O O O O


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DIGITAL DESIGN FLOW FOR AUTOMATION


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DESIGN METHODOLOGY

VHDL ( VHSIC Hardware Description Language ) is a language for

describing hardware. It is the result of workshop sponsored by US D1981. Due to restrictions, it was not made public till 1985. In 1985, thspecs were handed over to the release of IEEE 1076/A standard in

IMPORTANT ISSUES HANDLED BY VHDL:

1.CONCURRENCYIn an electronic circuit, all components are actithe time and therefore, unlike procedural languages, the order of

execution of statements in VHDL program is not sequential. Thestatements are executed whenever a variable in RHS changes.

For e.g. A


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2.SEQUENTIAL BLOCKSIt is not possible to describe complicated

operations with concurrent statements. To take care of such cases,process, procedure and function blocks are used. The statements inthese blocks execute in a sequential manner like normal proceduralprogramming language.

3.DELAYSVHDL provides delay statements to realize real circuits

The delay can be of two types, Inertial or Transport.

Inertial : RC low pass circuits typically causes inertial delay. If a pulswhose width is less than the delay time appears at the input, then it not be passed to the output.

For e.g. B


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4. DELTA TIMETo maintain the cause and effect relationship betwe

inputs and outputs, the concept of delta time is introduced. If a delaynot mentioned in a statement, then a delta time is assigned to it. Thesimulation process goes in two phases, namely evaluate and propag

5.BACK ANNOTATIONOnly the analysis tool uses the timing paramused in VHDL code, the synthesis tool ignores them. After realizing tcircuit and routing, the synthesis tool calculates the delays and paste

them back to the higher level for more realistic simulation, this is calback annotation. IEEE has evolved a standard called VITAL for thispurpose.

6. FREEMIXVHDL allows structural and behavioral styles to be fremixed.

7.HIERARCHICAL STRUCTUREVHDL allows a hierarchical desig

making use of libraries and packages.

DESIGN METHODOLOGY


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The first character must be an alphabet, last character can not be an underscore. Eg. my_iedn is valid, 6_bit_cnt_ is invalid

Digits can be inserted in an identifier. Eg. my_6_bit_cnt, cnt6are valid

Lower or Upper case character can be used. Eg MY_ADD and my_addare same

Special characters can be used between two backslashes. Eg \$_#_*_132\

BASE SPECIFIERS -

Integer and floating point literals can also be written in a base other than decimal. The base can be any value from 2 to 16. S

Form 1 :< BASE> # < BASED_VALUE> #

2 # 101_101_000 # 8 # 550 # 10 # 360 #

Form 2 :< BASE> # < BASED_VALUE> #

16 # F # E1 15 * 161

2 # 101 # E31*25+ 0 * 24+ 1* 23

BASE SPECIFIERS FOR BIT_VECTORSThe syntax is

Base specifier BIT_VECTOR ; where Base specifier is B|O|X or b|o|x

B1010_110 , O126, X56 are same.

The default specifier is binary.

IDENTIFIERS IN VHDL


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VHDL is a strongly typed language. Every object can only have valu

its defined type. New types can be introduced in VHDL model by usitype declarations.

Syntax is

TYPE_DECLARATION type_identifier IS type definition; e.g. TYPE apples IS RANGE 0 TO 100 ;

TYPE orange IS RANGE 0 TO 100 ;

SIGNAL a : apples ;

SIGNAL b : orange ;

We cannot assign a value of type apples to a SIGNAL of type orang

e.g. TYPE op_type IS ( add, sub, mul, div ) ; --ALU instructions

SIGNAL op_code : OP_TYPE ;

TYPE two_level_logic IS ( 1, 0) ; --1< 0is TRUE SIGN: two_level_logic ;

TYPE DECLARATION


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TYPE DECLARATION

SUBTYPES

A subtype is a type with constraint. An object can be declared to belong to either a type or a subty

The set of Operations belonging to a subtype is the same as tassociated with its base type.

Eg.

TYPE apples IS RANGE 0 TO 100 ;

SIGNAL a : apples ;

SUBTYPE my_integer IS apples 48 TO 56 ;

SIGNAL c : my_integer ;


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DATA TYPES IN VHDL

VHDL provides unlimited number of data types for characterizthe values held by the signal, variable and constant. Data type

arecategorized into 4 major categories. 1.Scalar types 2.Composite types 3.Access types 4.File types 1.5.1 SCALER TYPES are further divided into 4 types EnumerationInteger Floating PointPhysical The values belonging to these types have ordered relationship

relational operations can be used on these values. For e.g. BI

scalar type and the expression 0< 1is valid and has the valuTRUE


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ENUMERATION

User can define new data type, which describes its internstructure using Type Declaration.

It is a powerful tool for abstract modeling. Designer can use an enumerated type to represent exac

the values required for specific operation. These values can be identifiers or single character literal

An identifier is like a name e.g idle, new etc.

Character literals are single character enclosed in singlequotes such as X, Iand0

Eg. TYPE my_state IS ( reset, got1, got10, got101 ) ;

SIGNAL state, next_state : my_state


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INTEGER TYPE

The type integer includes at least numbers (-231to +231).

We can define a new integer type using a range constraint.

Eg TYPE new_integer IS RANGE 0 TO 1000;

TYPE my_integer IS RANGE 2000 DOWNTO 0;

SIGNAL a : new_integer ;

SIGNAL b : my_integer ;

SIGNAL c : integer ; --Default range

TIME TYPE This is predefined data type in VHDL having default time asfs(femtosecond ). The user can enumer

data type for certain rangeof time values.

TYPE MY_TIME is

ns ;

us = 1000 ns ;

ms = 1000 us ;

s = 1000 ms ;

END MY_TIME ;

SIGNAL CLK : MY_TIME ;


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REAL TYPES (FLOATING POINT TYPES )

There is predefined floating point type called real, which

includes at least the range1.0 E +38 to +1.0 E +38, witleast 6 decimal digits of precision.

New floating point type can be defined using rangeconstraint.

Eg. TYPE new_real IS RANGE 0.0 TO 10.9 ;TYPE my_real IS RANGE 20.00 DOWNTO 3.7 ;

SIGNAL a : new_real ;

SIGNAL b : my_real ;

SIGNAL c : real ; --Default range


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PHYSICAL TYPES

The physical data type is used to define a quantity having somunit. The definitions of a physical type includes the primary un

measure and may also include some secondary units, which aintegral multiples of the primary unit.Eg: TYPE resistance IS RANGE 0 to 1E9

unitsohm ;

Kohm = 1000 ohm ;Mohm = 1000 Kohm ;end units ;

SUBTYPE my_resis IS resistance RANGE 1 Kohm to 100 Mohm It need not be power of 10. Literal value of this type are written

a numeric literal followed by the unit name. For e.g 5 ohm, 47Kohm. We must include space before the unit name.


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COMPOSITE TYPES

Data objects of Composite types on the other hand can hmultiple values at a time. Composite types consists of ar

types and record types. Arrays are homogeneous compodata type and Records are hetrogeneous composite datatype.

Array types -An object of an array type consists of multip

elements of the same type.Eg of one dimensional array

TYPE my_array IS ARRAY ( 0 TO 4 ) OF REAL ;

TYPE byte is ARRAY ( 7 DOWNTO 0 ) OF BIT ;

SIGNAL my_sig_array : my_array ;CONSTANT byte1, byte2 : byte ;


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Eg of two dimensional array

TYPE column IS RANGE 1 TO 20 ; TYPE row IS RANTO 10 ;

TYPE table IS ARRAY ( row, column )OF BOOLEAN ;

SIGNAL alu_cc_table : table ;

OR

SIGNAL alu_cc_table IS ARRAY ( 1 TO 10, 1 TO 20 )OF BOOLEAN ;

Eg. of two dimensional array representing memory

TYPE data_wd IS ARRAY ( 0 TO 125 ) OF BIT_VECTOR ( 7DOWNTO 0);

SIGNAL my_mem : data_wd ;

COMPOSITE TYPES


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UNCONSTRAINEDARRAY

An unconstrained array type is a type whose range is notcompletely specified when it is declared.

This allows multiple subtypes to share a common base type.Eg.

TYPE bit_vector IS ARRAY( NATURAL RANGE ) OF BIT;

Eg.

TYPE std_logic_vector IS ARRAY( NATURAL RANGE ) OFSTD_LOGIC; RANGE specifies that the type being defined has an unconstrain

range.

The word NATURAL specifies that the type is bounded only by theraof natural.

Type natural is defined in the standard package to have a rangefromlargest integer value i.e. 231.


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RECORD

Records are heterogeneous composite types i.e. the elements of a reco

can be of different types.Eg.

TYPE register_bank IS RECORD

F0 : REAL ;

F1 : REAL ;

R0 : INTEGER ;

R1 : INTEGER ;

A0 : address ;

I : instruction ;

END RECORD;

SIGNAL bank : register_bank ;

Members of a record can be addressed by means of the dot operator.Eg. bank.F0


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2. OPERATORS IN VHDL

Adding Operators : +, -, & ( concatenation of strings )

Eg. VARIABLE sum1, sum2, a, b : INTEGER ;SIGNAL s3 : STRING ;

CONSTANT s1 : STRING := abc;

CONSTANT s2 : STRING := def;

sum1 := a + b ;

sum2 := a -b ;

s3


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Multiplying operators :*, /, MOD (modulus), REM (remainder)

MOD and REM operators operate on operands of integer type

and the result is also of the same type.a REM b = a(a / b ) * b , the result of rem operator has a sigthe first operand.

Eg: ( -7 ) REM 4 has value -3

a MOD b = ab * N, where N is some integer value, the resultmod operator has a sign of the second operand.

Eg. 7 MOD ( -4 ) has value1

Relational operators: =, /=, =

Eg: BIT_VECTOR (0, 1, 1) < BIT_VECTOR (1, 0, 1)

result is TRUE since the first element of array 1 is less than thits counter part in array 2.


2 OPERATORS IN VHDL


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Miscellaneous operators :ABS ( absolute ), ** (exponentiation )

Absolute is defined for any numeric type. Exponentiationoperator is defined for the left operand to be integer orfloating-point type and the exponent to be of integer typeonly.

Eg. A ** 2 equal to A*A

B ** 3 equal to B*B*B

Eg. ABS 11ABS(-1)1


2 OPERATORS IN VHDL


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Shift operators -SLL, SLR, SLA, SRA , ROL, RORA logical shift rightshift left SLL) operation shifts an array operand to the right ( left ) ele

and fills the left ( right) side of the array with a fill value. The fill valuethe left most enumeration element of the array. For an array of bit, thvalue is 0.An arithmetic shift right ( left ) operations shifts its array

operand to the right ( left ) and uses the left most ( right most ) elemethe left ( right ) fill.


3 DATA OBJECTS


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3. DATA OBJECTS

Data objects hold values of specified types. They belongone of three objects : constants, signals, variables and m

bedeclared before they are used. CONSTANTS

A constant holds a value that cannot be changed within the dedescription.

This value is usually assigned upon declaration. Constant can be declared in package, entity, architecture or

process declarative regions.

Eg. CONSTANT width : INTEGER := 8 ;

:=Symbol indicates initialization of constant, they

cannot be assigned values elsewhere.

VARIABLES


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VARIABLES

Variables are used only in process or subprogrammes.

They must be declared in the declarative region of a process

orsubprogram. The assignment of variable can be represented as

Variable_object := expression ;

The expression is evaluated when the statement is executed a

the computed value is assigned to the variable objectinstantaneously i.e. at the current simulation time.

Eg:

VARIABLE a : BIT_VECTOR ( 3 DOWNTO 0 ) ;

VARIABLE b : STD_LOGIC := Z;

a := 1100;

SIGNALS


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SIGNALS

Signals can represent wires and can therefore interconnectcomponents.

Ports are Signals. Signals can be inputs or outputs of logic gates. Signals can also represent the state of memory elements. Signal keeps track of the value and corresponding time Signals declared as ports have modes, while signals declared

locally are both readable and writable.Eg.

SIGNAL count :BIT_VECTOR ( 3 DOWNTO 0 ) ; SIGN: BIT := 0;

count


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SIGNAL DRIVER Whenever signal is declared, VHDL compiler creates a driver for every s

The job of storing information on signals i.e. its value w.r.t. time is perforby the driver.

No matter how many values are assigned inside a process, there is onlydriver per signal per process.

All operations are performed on the driver which is copied to the signal owhen the process suspends.

If there are more than one assignment to a signal, only the last one will teffect.

EVENTS & TRANSACTIONS The process of adding a state change to the signal driver is called a

Transaction.

If the transaction causes change in signal value, then it is called an Eve

Every transaction need not necessarily cause an event.

SIGNALS

DELTA DELAY


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DELTA DELAY

Signal value does not change in a process as soon as thsignal assignment is executed. The process does not seeeffect of the assignment until the next time it resumes, evthis is at the same simulation time. If delay is not explicitlmentioned in a signal assignment then delta delay is thedefault delay.

It does not correspond to any real delay and actualsimulation time does not advance. This delay modelshardware a minimum amount of time is required for chanto occur.

TRANSPORT AND INERTIAL DELAY


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TRANSPORTAND INERTIAL DELAY

Transport delays model an ideal device with infinitefrequency response in which any input pulse, no matter hshort appears at the output without change in itscharacteristics. An example of such a device is an idealtransmission line, which transports all input changes delaby some amount.

Eg. trans_line: PROCESS

BEGIN

line_out


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E.g. asym_delay : PROCESS ( a )

BEGIN

CONSTANT Tpd01 : TIME := 700 ps ;

CONSTANT Tpd10 : TIME := 500 ps ;

BEGIN

IF a = 1THEN

Z < = TRANSPORT aAFTER Tpd -01;

ELSEZ < = TRANSPORT aAFTER Tpd -10;

ENDIF ;

END PROCESS asym_delay ;

RULES FOR ADDING A TRANSACTION TO A TRANSPORT DEL


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RULESFORADDINGATRANSACTIONTOATRANSPORTDEL

If the delay time of new transaction already present on thdriver is later than the current time, then the new transacwill be added at the end of the driver.

If the delay time of the new transaction is earlier than orequal to one or more transactions on the driver, then pretransactions are deleted from the driver and the newtransaction is added at the end of the driver.

EFFECT OF TRANSPORT DELAY ON SIGNAL DRIVER


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EFFECTOFTRANSPORTDELAYONSIGNALDRIVER

E.g. Process

beginRX_DATA


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EFFECTOFTRANSPORTDELAYONSIGNALDRIVER

E.g. Inertial delay

inv : PROCESS ( a )BEGIN

y < = INERTIAL NOT a AFTER 3 ns ;

END PROCESS inv ;

RULES FOR ADDING A TRANSACTION TO A INERTIAL DELAY


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RULESFORADDINGATRANSACTIONTOAINERTIALDELAY

All transaction on a driver that are scheduled to occur at or aftthe delay of the new transaction are deleted.

If the value of the new transaction is the same as the value of transaction on the driver, the new transaction is added to thedriver.

If the value of the new transaction is different from the values one or more transactions on the driver, these transactions aredeleted from the driver and the new transaction is added.

For a single signal assignment statement, if the first waveformelement is added to the driver, all subsequent waveform elemof that signal assignment are also added to the driver.

EFFECT OF INERTIAL DELAY ON SIGNAL DRIVER


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EFFECTOFINERTIALDELAYONSIGNALDRIVER

process

begin

TX_DATA


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STD_LOGIC

This data type has been defined in IEEE standard library. It defines foll9 states for logic variable. It defines the logic state as well as the drivstrength so that the simulator can properly predict the state of multi d

signals.0--forcing 0 or strong 0

1--forcing 1 or strong 1

L--weak 0 or low

H--weak 1 or high

Z--strong tristate or high impedanceW--weak tristate

U--uninitialised storage mode ( treated as Xby simulator )

X--forcing unknown

---dont care for synthesis

STD_LOGIC_VECTOR is the vector of STD_LOGIC.To use STD_LOGis required to include IEEE library.

ATTRIBUTES OF OBJECTS


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ATTRIBUTES OF OBJECTS

The VHDL objects have various properties apart from their value.These properticalled attributes. There are several predefined attributes in the language. The at

is written as< object name > < attribute name >

ATTRIBUTES TO ARRAY : The index number should be given in bracket after thattribute name for multidimensional arrays.

If declaration is

TYPE nibble IS ARRAY ( 3 DOWNTO 0 ) OF BIT ;

TYPE nib_vect IS ARRAY ( 3 DOWNTO 0, 0 TO 7 ) OF BIT ;SIGNAL qvect : nib_vect ;

SIGNAL q : nibble ;

then qvectleft (1) = 3 qvectright (1) = 0

qvecthigh (2) = 7 qvectlow (2) = 0

qvectrange (1) = 3 downto 0 qvectrange (2) = 0 to 7

qvectlength = 4 qvectlength (1) = 4

qrange = 3 downto 0 qrevese_range = 0 to 3

ATTRIBUTES TO DATA TYPES


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ATTRIBUTES TO DATA TYPES

If declaration is TYPE bit_position IS RANGE 15 DOWNTO 0 ;

TYPE fraction IS RANGE0.999 TO 0.999

thenbit_positionLOW = 0 bit_positionHIGH = 15

bit_positionLEFT = 15 bit_positionRIGHT = 0

fractionRIGHT = 0.999 fractionLEFT = -0.999

ATTRIBUTES TO SIGNALS :

Consider the statement SIGNAL a : BIT ;

aEVENT = TRUE if A has changed state at current simulation cycle.

aSTABLE = TRUE if A has not changed state at current simulation cycle.

aSTABLE ( 5 ns ) = TRUE if A has not changed within last 5 ns.

aLAST_EVENT = time elapsed since last event on A ( 0 ifAevent is TRUE ).

aLAST_VALUE = value of A before the most recent event.

aDELAYED ( 10 ns ) = another copy of A delayed by 10 ns.

ENTITY DECLARATION


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ENTITY DECLARATION

An entity declaration describes the inputs and outputs of design entry. It can also define parameterized values usi

generic statement . The entity declaration is analogous toschematic symbol which describes a components conneto the rest of the design. A schematic symbol for a 4 bitadder(add4) is shown below.

Fig:-Symbol equivalent of 4-bit adder

SYNTAX FOR ENTITY DECLARATION


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SYNTAXFORENTITYDECLARATION

ENTITY entity_name IS

PORT ( signal_name : MODE DATA_TYPE, more signal

END entity_name ;

E.g.

ENTITY add4 IS PORT (

a, b : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;

ci : IN STD_LOGIC ;

sum : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ;

co: OUT STD_LOGIC ) ;

END add 4 ;

PORTS


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Each I/O signals in an entity declaration is referred to as port, which is analogous to a pin in a schematic symbol.

The set of ports defined for an entity is referred to as a pdeclaration.

Each port declared must have a name, a direction (modeand a data type.

The mode describes the direction in which data is transfethroa port.

The mode can be one of 4 values in, out, inout or buffer.


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IN :-Data flows into the entity. The driver for a port in is externthe entity. Mode in is used primarily for clock inputs, control in

OUT :-Data flows only from its source to the O/P of the entity. driver for a port mode out is inside the entity. Mode out does nallow for feedback because such a port is not considered readwithin the entity.

BUFFER :-For internal feedback a port that is declared as mo

buffer is similar to a one declared as mode out , except that it allow for internal feedback .

INOUT :-For bidirectional signals, you must declare a port as inout. In addition to specifying identifiers and modes for ports must also declare the data types for ports.

ARCHITECTURE DECLARATION


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Every architecture bodies is associated with an entity declaration.

It describes an entitys function. If the entity declaration is viewed as the enginee

black box, then the architecture body is the internal view of the black box. VHDL allows to write the designs using various styles of architecture and to mix

match these styles as desired.

The styles are behavioural, data flow and structural.

Syntax for architecture declaration

ARCHITECTURE arch_name OF entity_name IS

< signal, procedure, function and component declaration >

BEGIN

< concurrent statements >< processes >< component instantiation >

END arch_name ;


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ARCHITECTURE dataflow OF add4 IS

BEGIN

sum


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It specifies how data will be transferred from signal to signal a

input to output without the use of sequential statements.

The statements written in dataflow style of modeling must lie oside the process, procedure or functions.

One is likely to use dataflow descriptions in cases where it is m

succinct to write simple equation, conditional signal assignmeWHEN-ELSE ) statements or selected signal assignment ( WISELECT-WHEN ) statements rather than a complete algorithm

Data flow architectures use concurrent signal assignmentstatements


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There are 3types of concurrent statements used in data flowdescription.

Concurrent signal assignment statements with Boolean equat

e.g x


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The WITH-SELECT-WHEN statement provides a selective signalassignment, which means that a signal is assigned a value based on th

value of a selection signal.

WITH selection_signal SELECT

SIGNAL_NAME


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E.g. 2:4 DECODER

ENTITY decoder IS

Port ( adr : in std_logic_vector ( 1 DOWNTO 0 ) ;

Y :out std_logic_vector ( 3DOWNTO 0 ) ) ;

END decoder ;

ARCHITECTURE df OF decoder IS

BEGIN

WITH adr SELECTY


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The WHEN-ELSEstatements are used for conditional assignment

which means that a signal is assigned a value based on a condition.

SIGNAL_NAME


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Eg. OCTAL BI-DIRECTIONAL TRISTATE BUFFER (74LS245)

LIBRARY IEEE ;

USE IEEE.STD_LOGIC_1164.ALL ;ENTITY bidibuf8 IS

PORT ( A : INOUT STD_LOGIC_VECTOR ( 7 DOWNTO 0 ) ;

B : INOUT STD_LOGIC_VECTOR ( 7 DOWNTO 0 ) ;

dir, en : IN STD_LOGIC) ;

END bidibuf8 ;ARCHITECTURE dataflow OF bidibuf8 IS

BEGIN

A


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They are sometimes referred as high level descriptionsbecause of their resemblance to high level programming

languages. Ratherthan specifying the structure or netlist circuit you specify a set of statement that when executedsequence model the functionalityof the entity (or part of tentity ).

Process statement is one of VHDLs design constructs foembodying algorithms.

An architecture body can contain more than one processeach process is concurrent with the others.


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[PROCESS_ LABEL:] PROCESS( Sensitivity _ list)

Declaration

| variable declaration| alias_ declaration}

begin| wait_statement| Signal_assignment.statement

| variable_assignment.statement| if statement| case statement| loop statement

END PROCESS [PROCESS-LABEL] ;

VARIABLE ASSIGNMENT STATEMENT


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Variables are created at the time of elaboration and retaivalues throughout the entire simulation run. A process is

enteredat the start of the simulation at which time it isexecuted until it suspends because of a wait statement osensitivity list.

Eg. PROCESS ( A )

VARIABLE events_on_A : integer := -1 ;BEGIN

events_on_A := A + 1 ;

END PROCESS ;

IF STATEMENT


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An if statement selects a sequence of statements for execution basethe value of a condition.The condition can be any expression thatevaluates to a Boolean value.

Simple IF statement :IF (condition) THEN IF sum


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IF-ELSIF statement : The IF-THEN-ELSE can be expanded further to include an ELSIF to allow for furtheconditions to be specified and prioritized .

IF (condition1) THEN

Do something ;

ELSIF (condition2) THEN

Do something different ;

ELSE

Do something completely different;

ENDIF;

Eg:

IF nickel_in THEN

deposited


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In the case construct,a set of statements is executed based on the valuthe selection signal.

CASE selection_signal ISWHEN value_1_of_selection_signal => ( do something ) --st

WHEN value_2_of_selection_signal => (do something )st2

------

------

WHEN last_value_of_selection_signal => (do something) ;Eg: 1

CASE count IS

WHEN 00=> A A A


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FORM 3 : LOOP and EXIT The third form of the iteration scheme is one where no

iterationscheme is specified. The loop continues to beexecuteduntillsome other action causes the loop to exit.

Eg.sum := 1;j := 0 ;

L2 : LOOPj := j + 2 ;sum := sum * 10 ;EXIT WHEN sum > 100 ;END LOOP L2 ;

EXIT STATEMENT


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The EXIT Statement is a sequential statement that can be useonly inside a LOOP. It causes execution to jump out of the inn

mostLOOP or the LOOP whose label is specified. IF no loop-lis specified, the inner most loop is exited.

Syntax :

EXIT [ loop-label ] [ WHEN condition ] ;

Eg:LOOP

WAIT on A, B ;

EXIT WHEN A = B ; --since no label, inner most loop is exited

END LOOP;


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--FSM TO DETECT 1011 SEQUENCE USING DATAFLOW STYLE

entity FSM1011 is

port (RST,X,CLK : in BIT ; Z : out BIT );


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p ( , , ; );

end FSM1011 ;

architecture DF of FSM1011 is

type STATE_TABLE is(RESET,GOT1,GOT10,GOT101) ;

signal STATE,NEXT_STATE : STATE_TABLE ;

beginprocess(CLK,RST,X)

begin

if ( RST = '1' ) then STATE


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STRUCTURAL STYLE OF MODELING


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An entity is modeled as a set of components connected bsignals, that is, as a netlist. The component instantiation

statement is the primary mechanism used for describing a model of an entity. An entity is modeled as a set ofcomponents connected by signals, that is, as a netlist. Thcomponent instantiation statement is the primary mechan

use for describing such a model of an entity.

ENTITY gating IS

PORT ( A, CK, MR, Din : IN BIT ;

RD CTRL 4 OUT BIT )


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RDyCTRL 4 : OUT BIT );

END gating;

ARCHITECTURE structural_view OF gating IS

COMPONENT and2

PORT( x,y : IN BIT; z : OUT BIT) ;

END COMPONENT;

COMPONENTdffIS

PORT(d,clock : IN BIT; q,q_bar : OUT BIT) ;

END COMPONENT;

COMPONENT nor2

PORT(da,db:IN bit;dz:out bit);

END COMPONENT;

SIGNAL s1,s2,s3:bit;

BEGIN

D1 : dff1 PORT MAP ( a,ck,s1,s2 ) ;

A1 : and2 PORT MAP ( s2,din,ctrla) ;

N1 : nor2 PORT MAP ( s1,mr,rdy) ;

END structural_view;


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Three components are instantiated in the architecture bousing three component instantiation statements and the

instantiated components are connected to each other viasignals s1 and s2.The component statements are concurstatements and their order of appearance in the architectbody is thus not important.

7.1 COMPONENT DECLARATION

A t i t ti t d i t t l d i ti t fi t


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A component instantiated in a structural description must first declared using a component declaration. A component declaradeclares the name and the interface of a component. The intespecifies the mode and the type of ports.

The syntaxis

COMPONENT Component_name

[ PORT ( list of interface-ports ) ]

END COMPONENT [component_name] ; The list of interface ports specifies the name, mode, and type

each port of the component in a manner similar to that specifiean entity declaration. Component declaration appear in thedeclarations part of an architecture body. Alternatively, they ca

appear in a package declaration.

7.2 COMPONENT INSTANTIATION

A t i t ti ti t t t d fi b t f th


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A component instantiation statement defines a sub component of theentity in which it appears. It associates the signals in the entity with tports of that sub components. A format of component instantiation

statement is: Component_label : component_name

[ port map ( association list ) ] ;

The component label can be any legal identifier and can be considethe name of the instance. The component name must be the name o

component declared earlier using a component declaration. Theassociation list associates signals in the entity called actuals with theports of a component called formals. An actual may be a keyword opindicate a port that is not connected. There are two ways to perform association of formals with actuals.

Positional association

Named association

In positional association an association list is of the form


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In positional association an association list is of the formactual1, actual2, actual3..actualn. Each actual in thecomponent association is mapped by position with each

in the component declaration. i.e the first port in thecomponent declaration corresponds to the first actual in tcomponent instantiation ,the second with the second andon.

PORT MAP ( actual1, actual 2,actualn) ;

In named association an association list is of the form

PORT MAP ( formal1=>actual1, formal2=>actual 2,form=>actualn) ;

Here in either ways the data types of the formal and actu

being associated must be the same.

CONFIGURATIONSTATEMENT

Sometimes multiple architectures for the same entity are available a


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Sometimes multiple architectures for the same entity are available ahave to choose one particular architecture for our design. Insuch casneed to use a configuration statement in the declaration zone, i.e. af

component declaration and before begin. Following examples illustrathe various forms of configuration. If the names of the port signalsantheir order are different, they can be matched properly by using a naassociation in the configuration statement.

Syntax:

For < Component ID > : USE

()[ port map ( formal_signal_Name => actual_signal_Name .] ;

In the place of we may give actual component ID othe keywords othersandall. The port map clause should be includthe names of the order of the port signals in the library differ from thothe component declaration.


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GENERATE STATEMENT

The generate statement is useful for defining iterative network


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The generate statement is useful for defining iterative networki.e. identical copies of same component wired in a systematic

generate_label : FOR generate_identifier IN discrete-rangeGENERATE

[block_declarations BEGIN]

concurrent statements

END GENERATE [generatelabe]; For realizing BA, we will need 8 copies of FA from FA0 to FA7

instances FA0 and FA7 have to be handled separately. The mones can be defined with a port map as follows.

Fam: FA PORTMAP ( a(i), b(i), c(i-1), s(i), c(i) ) ;

Eg. BYTE ADDER using GENERATE statement

libraryieee;

useieee.std_logic-1164.all;


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_ g

ENTITY BA IS

PORT(a, b : IN STD_LOGIC_VECTOR ( 7 DOWNTO 0 ) ;

cin: IN _LOGIC ;

s : OUT STD_LOGIC_VECTOR ( 7 DOWNTO 0 ) ;cout: OUT STD_LOGIC ) ;

END BA ;

ARCHITECTURE structural OF BA IS

COMPONENT FA

PORT ( x, y, ci : in std_logic; sum, co : out std_logic ) ;

END COMPONENT;

SIGNAL c : STD_LOGIC_VECTOR ( 6 DOWNTO 0 ) ;

BEGIN

FA0 : FA PORTMAP ( a(0), b(0),cin, s(0), c(0) ) ;

Famid: FOR i IN 1 TO 6 GENERATE

Fam: FA PORTMAP ( a(i), b(i), c(i-1), s(i), c(i) ) ;

END GENERATEFamid;

FA7 : FA PORTMAP ( a(7), b(7), c(6), s(7),cout) ;

end structural ;

GENERIC STATEMENT

It is often useful to pass certain types of information into a design description fro


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p yp g penvironment. Examples of such information rise and fall delays and size of interfports etc. This is accomplished by using generic statement. Generics of an entitdeclared along with its ports in the entity declaration. A generic declares a const

object of mode in i.e. the value can only be read and can be used in the entitydeclaration and its corresponding architecture besides the value of this constantbe specifiedas a globally static expression in one of the following.

1. Entity declaration:

e. g ENTITYnand_gate IS

GENERIC ( M : integer := 2 ) ;

PORT( A : IN BIT_VECTOR ( M DOWNTO 1 )) ;

ENDnand_gate ;

2. Component declaration

3. Component instantiation

4. Configuration specification

5. Configuration declaration

The value of a generic must beexplictlyspecified at least once using

of the declarations mentioned.


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Eg. Use of generic specifications in a component declaration and in component instantiation.

ENTITY another_gen_ex ISEND another_gen_ex ;

ARCHITECTUREgen_in_comp OF another_gen_ex IS

COMPONENTnand_gate

GENERIC ( M : INTEGER ) ;

PORT ( A:IN BIT_VECTOR ( M DOWNTO 1 ) ; Z:OUT BIT ) ;

END COMPONENT

COMPONENT and_gate

GENERIC ( N : NATURAL := 5 ) ;

PORT ( A : IN BIT_VECTOR ( 1 to N ) ; Z : OUT BIT ) ;

END COMPONENT

SIGNAL s1, s2,s3, s4 : BIT ;

SIGNALsa: BIT_VECTOR ( 1 to 5 ) ;

SIGNALsb: BIT_VECTOR ( 2 downto 1 ) ;

SIGNAL sc : BIT VECTOR ( 1 to 10 ) ;


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SIGNAL sc : BIT_VECTOR ( 1 to 10 ) ;

SIGNALsd: BIT_VECTOR ( 5 downto 0 ) ;

BEGIN

N1 :nand_gate GENERIC MAP ( 6 ) PORT MAP (sd, s1 );A1 : and_gate GENERIC MAP ( N=>10) PORT MAP ( sc, S3);

A2 : and_gate PORT MAP (sa, s4);

--N2:nand_gate PORT MAP (sb, s2 );

ENDgen_in_comp ;

In N1 instance the value M will be 6.

In A1 instance the value N => 10 will override value of N = 5 defined in component declara

In A2 instance the value N = 5 i.e. default value.

In N2 instance the value of M is not initialized in generic statement, therefore it may give er

If generic map is not mentioned the default value in the entity declaration or comp declaratbe considered ( if it is not mentioned in comp declaration then entity value of generic is con)

8.1 PACKAGE

A package is a design unit that can be used to make its type,


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p g g yp ,component function and other declarations visible to design uother than itself. This is in contrast to architecture declarative

region for which its type, component, function and otherdeclaration cannot be made visible to other design units.A package consists of a package declaration and optionally, a

package body. A package declaration is used to declare itemsas types, components, functions and procedures. A package bis where the functions and procedures in a package declaratio

are defined. A package body that does not declare any functioprocedures does not need an associated package body. If youwish all items in the package to be visible, you can use thekeyword all.

The package std_logic_1164 declares several types and definseveral functions.

Eg. Package declaration


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PACKAGE my_Pack is

TYPE color IS ( red, green, blue ) ;

TYPE logic4 IS ( X, Z, 0, 1) ;

CONSTANT rise_time : TIME := 7 ns ;

CONSTANT fall_time : TIME := 3 ns ;

END my_Pack ; The above package declaration contains only data type

declarations and constant definitions and therefore it is scontained. It does not need a package body.

Eg. Package body and declaration

PACKAGE my_pack IS

FUNCTION parity ( A : BIT VECTOR ) RETURN BIT ;


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p y ( _ ) ;

CONSTANT delay : TIME ;

END my_pack ;

PACKAGE BODY my_pack ISCONSTANT delay : TIME := 2 ns ;

FUNCTION parity( A: BIT_VECTOR ) RETURN BIT IS

VARIABLE X : BIT := 0;

BEGIN

FOR I in ARANGE LOOP

IF A(I) = 1THEN

X := NOT X ;

END IF ;

END LOOP ;

WAIT FOR delay ;

RETURN X ;

END parity ;

END my_pack ;

SUBPROGRAMS

In many programming languages subprograms are used


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In many programming languages, subprograms are usedsimplify coding, modularity and readability of descriptions

VHDL uses subprograms for these applications as well athose that are more specific to hardware descriptions. VHallows two forms of subprograms i.e. FUNCTIONS andPROCEDURES. Functions and procedures are used tocompute values or define processes for type conversionsoperator overloading or as an alternative to componentinstantiation.

The typical syntax of a function declaration is

FUNCTION identifier [( parameter interface list ) ]

9.1 FUNCTIONS


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RETURN type_mark IS

{subprogram_declarative_item)}

BEGIN{sequential_statement}

END identifier ;

e.g. Functions as shorthand for simple components

FUNCTION inc_by ( a : BIT_VECTOR ) RETURN bit_vector IS

VARIABLE s : BIT_VECTOR (aRANGE) ;

VARIABLE carry : BIT ;

BEGIN

carry: =1;

FOR I INaLOWTOaHIGHLOOP

S(i) : = a(i) XOR carry;

Carry : = a(i) AND carry;

END LOOP;

RETURN (s);

END inc_by;

Eg. Function showing type conversion frombooleanto bit


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FUNCTION bl2bit ( a : BOOLEAN ) RETURN BIT IS

BEGINIF a THEN

RETURN 1;

ELSE

RETURN 0;END IF;

END bl2bit;

9.2CALLING FUNCTIONS

A FUNCTION may be defined in the declaration region o


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A FUNCTION may be defined in the declaration region oarchitecture in which case the function definition also ser

as the function declaration. Alternatively a package may used to declare a function with the definition of the functiappearing in the package body. The above function can bcalled as

SIGNAL a : BOOLEAN ;

SIGNAL b : BIT ;

b


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p g gcompute values or define processes that you can use forconversions or operator overloading or as an alternative component instantiation.

Procedures differ from functions in a few ways .A procedcan have a wait statement, whereas a function cannot. Awith functions, all statements within procedure must be a

sequential statements, and procedures cannot declaresignals. But variables can be declared in a declarative reof a procedure.

Procedures are defined in the same way as a function i.ethe architectures declarative region or in a package with

associated definition in the package body.

Eg. Procedure to convert a bit_vector to integer

PROCEDURE byte_to_int( byte : IN BIT_VECTOR ;eq_int: OUT INTEGIS VARIABLE sum : INT := 0 ;


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S su 0 ;

BEGIN

FOR I INbyteRANGELOOP

IF byte (i) = 1THEN

sum:= sum+2**I;

END IF;

END LOOP:

eq_int b, byte => a ) ; --Named association

OPERATOR OVERLOADING

One of the most useful applications of overloading is the


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pp goverloading of operators. The need for overloading opera

arises because the operators supplied in VHDL work onlywith specific types. For instance, the +operator works onwith integer, real and physical types. If a designer wants use a particular operator on a user defined type or other predefined type , then the operator must be overloaded t

handle the user type.

Type LOGIC4 is ( 0, 1, Z, X) ;

Type L4_TWO_DIM_ARR is array ( LOGIC4, LOGIC4 ) of LOGIC4 ;

Type L4_ONE_DIM_ARR is array ( LOGIC4 ) of LOGIC4 ;


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y y ( )

function and ( a, b : LOGIC4 ) is

Constant and_table : L4_TWO_DIM_ARR :=

( (0, 0, 0, 0), (0, 1, 1, X), (0, 1, 1, X), (0, X, X, X) ) ; begin

return and_table ( a, b ) ;

end and;

function not ( a : LOGIC4 ) is

constant not_table : L4_ONE_DIM_ARR := (1, 0, 0, X) ;

begin

return not_table ( a ) ;

end not ;

Result

and ( Z, X ) Xand ( 1, Z ) 1

not ( Z ) 0not ( X ) X

RESOLVING SIGNAL CONFLICTS Each concurrent signal assignment creates a driver for the signal being

assigned In this case a signal has more than one driver If thesignal is o


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assigned. In this case a signal has more than one driver. If thesignal is otype std_logic_vector or std_logic, there is a readymade packageinsidestd_logic_1164 to resolve the conflicts. If the signal is of different data ty

then RESOLUTION FUNCTION has to be written. Eg. In the following case :

ENTITY two_dr_ex IS

PORT( a, b, c : IN BIT ; z : OUT BIT ) ;

END two_dr_ex ;

ARCHITECTURE not_legal OF two_dr_ex ISBEGIN

z


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FILE I/O OPERATIONS File I/O can be performed through the FILE object. First, a data type

associated with an identifier that is defined as a FILE type Then a F


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associated with an identifier that is defined as a FILE type. Then a Fobject is declared to specify the name of the object, data type, modeor out ) and the file name in the host environment. For file operationsnecessary to include the statement use std.textio.all ; .

Syntax :

TYPE IS FILE OF ;

FILE : IS ;

Reading and writing is performed through read and write commands

Syntax:write ( file object name, variable name ) ;

read ( file object name, variable name ) ;

The function ENDFILE ( File object name )returns a boolean value Tif the end of the file has been reached, else it returns FALSE.

It is more convenient to perform formatted ASCII I/O using predefinedata type text. It uses a data type line, which is predefined as accesto a string. For writing into the file, we have to first use read and writ

FORMATTED ASCII I/O


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to a string. For writing into the file, we have to first use read and writfunctions on the buffer, i.e. line. Then we use write line function to traline to the file. Similarly for reading from a file, we first read the file in

line buffer and then use the read function to extract the data item intvariable.

Syntax of write:

write ( line variable name, variable name,

[ alignment ( default LEFT ) ], [width ( default 0 ) ] ) ;

Alignment can be LEFT or RIGHT. If the specified width is less than required width, then it is automatically expanded to fit. If thewidth is then the output is padded with blanks.

Syntax of read:

read ( line variable name, variable name ) ;

The FILE I/O example illustrates the use of assert and file I/O operat

Eg. FILE and console I/O example

library IEEE ;

use IEEE.std_logic_1164.all ;

use std.textio.all ;


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;

entity FTEST is end FTEST;

architecture TB of FTEST is

signal a, b : bit_vector ( 7 downto 0 ) := "00001111" ;signal c : integer := 100 ;

file TEST: text is out fileio.txt " ;

Begin

c


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to define a block of statements, which is sensitive to a given lisignals. The assignment statements within the block can

automatically make use of the block sensitivity list by means oguarded keyword. If the guard condition is an edge expressionthen it represents an edge triggered storage device.

BLOCK statement is used only in non synthesisable program test benches.

syntax :

< label > : block [ , guard expression > ] [ < local signal declar> ]begin< concurrent statement >end block [ label ] ;

Eg. positive edge triggered D type flip-flops.

entity DFF is

port ( D1 D2 clk: in BIT ; Q1 Q2 : out BIT ) ;


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port ( D1,D2,clk: in BIT ; Q1,Q2 : out BIT ) ;

end DFF ;

architecture DF of DFF isbegin

MyBlock: block (clkeventandclk= 1)

begin

Q1


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test. Its a means of verifying the DUT. All constructs of V

can be used in test-bench. It is not required to synthesizetest-bench. The data generated through test-bench shoucover all possible values at the input of the DUT.

In VHDL, test bench is the top level module in the hierarcin which the DUT is instantiated. The following exampleshows the DUT & its test bench.

Eg. SRAM module

libraryieee;

useieee.std_logic_1164.all;

useieee std logic unsigned all;


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useieee.std_logic_unsigned.all;

entitys_ram is

port(data:inout std_logic_vector (7 downto0);wr_bar,rd_bar,cs:in std_logic;

address:in std_logic_vector (7 downto0));

ends_ram;

architecturebehofs_ram is

typemem1 isarray(0 to255) ofstd_logic_vector(7 downto0);

signalmem:mem1;

begin

mem(conv_integer(address))


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entitytb_sram_new is

endtb_sram_new;

architecturetest oftb_sram_new is

componentram1k

port ( adr : in std_logic_vector ( 7 downto0 ) ;

cs_bar,oe_bar,wr_bar : in std_logic ;

d : inout std_logic_vector ( 7 downto0 ) ) ;

endcomponent;

signalsadr,sd: std_logic_vector ( 7 downto0 ) ;

signalscs_bar,soe_bar,swr_bar : std_logic ;

begin

u1 : ram1k port map ( adr =>sadr,cs_bar =>scs_bar,oe_bar

=>soe_bar,wr_bar =>swr_bar, d=>sd) ;

processbeginscs bar


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scs_bar 0 ;swr_bar


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signals is supposed to be ON at any given time. Also design a test bfor it.

Start by defining the entity and architecture of the encoder. Then defpackage to declare general utilities and use it in the entity TB(TestBench). The APPLY_VECTOR process which generates the stimuluthe TWO_CHANNEL_RECORDER process captures all changes in output variables OUT1 and OUT2. Two files are made. One file is wrin ASCII for manual checking and the other is written in binary for dis

in waves or for comparison.

use std.textio.all;

entity ENCODER is

generic ( DELAY : time := 5 ns ) ;

port ( I1, I2, I3, I4 : in BIT ; MSB, LSB : out BIT ) ;

end ENCODER ;


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architecture BEHAV of ENCODER is

begin

process ( I1, I2, I3, I4 )variable BIT1, BIT0 : BIT ;

begin

if ( ( I1 or I2 or I3 or I4 ) = '0' ) then assert false report "ALL LOW" ;

else

if I4 = '1' then BIT1 := '1' ; BIT0 := '1' ;

elsifI3 = '1' then BIT1 := '1' ; BIT0 := '0' ;

elsifI2 = '1' then BIT1 := '0' ; BIT0 := '1' ;

else BIT1 := '0' ; BIT0 := '0' ;

end if ;

MSB


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;CH0 : BIT ;

AT : time ;end record ;type TWO_CHANNEL_TRACE_FILE is file ofTWO_CHANNEL_TRACE_ELEMENT;component ENCODER port ( I1, I2, I3, I4 : in BIT ; MSB, LSB

BIT ) ;end component ;constant BITS_IN_VECTOR : integer := 4 ;subtype TEST_VECTOR is BIT_VECTOR ( BITS_IN_VECTOdownto 0 ) ;

end TB ;

use std.textio.all ;

use work.tb.all ;

entity TBENCH is

end TBENCH ;

architecture TB1 of TBENCH is

constant NO_OF_VECTORS : integer := 5 ;

t VECTOR MEMORY i ( 1 t NO OF VECTORS ) f TEST VECTOR


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type VECTOR_MEMORY is array ( 1 to NO_OF_VECTORS ) of TEST_VECTOR ;

constant INPUT_VECTORS : VECTOR_MEMORY :=

( "1010", "0010", "1100", "0110", "1111" ) ;constant VECTOR_PERIOD : time := 100 ns ;

signal IN1, IN2, IN3, IN4 : BIT ;

signal OUT1, OUT2 : BIT ;

begin

ENCODER1 : ENCODER port map ( IN1, IN2, IN3, IN4, OUT2, OUT1 ) ;

APPLY_VECTORS : process

begin

for J in 1 to NO_OF_VECTORS loopIN1


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file TRACE_OF_OUT12 :TWO_CHANNEL_TRACE_FILE is out "NEW_TRACE.DAT";

file ASCII_OF_OUT12 : TEXT is out " NEW_TRACE.TXT " ;

variable SAMPLE : TWO_CHANNEL_TRACE_ELEMENT ;

variable ASCII_LINE : LINE ;

begin

SAMPLE.CH1 := OUT2 ;

SAMPLE.CH0 := OUT1 ;

SAMPLE.AT := NOW ;

write ( TRACE_OF_OUT12, SAMPLE ) ;write ( ASCII_LINE, OUT2, LEFT, 10 ) ;

write ( ASCII_LINE, OUT1, LEFT, 10 ) ;

write ( ASCII_LINE, NOW, LEFT, 10 ) ;

writeline( ASCII_OF_OUT12, ASCII_LINE ) ;

end process TWO_CHANNEL_RECORDER ;

end TB1;

DATA FILE NEW TRACE TXT


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DATA FILE NEW_TRACE.TXT

0 0 0 NS1 1 5 NS

0 1 105 NS

1 1 205 NS

1 0 305 NS

1 1 405 NS

CODINGSTYLESANDDESIGNINGFORSYNTHESIZABILITY a. Avoid initialization: A statement like signal A : BIT := 0; has no

hardware counterpart and hence should be avoided. Instead ofinitialization the memory elements should be initialized with


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initialization, the memory elements should be initialized withasynchronous reset or preset signals.

b. Completely specify all possibilities: In conditional assignments if apossibilities are not specified, it means that the old value should becarried forward. E.g. X


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Clkeventandclk= 1

Clkeventandclk= 0

not clkstable and Clk=1

Following statement is likely to give trouble.

If (clkeventandclk= 1and Y = 0) then Q


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( )

then Q


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