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, VHDL
,
VHDL.
, .
VHDL
: . VHDL
[1, 3, 8, 9]. Entity() Package (). Architecture
() Package Body (/ ),
.
, . . 1
VHDL .
. 1 VHDL
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1.1 VHDL
VHDL (, , , .),
VHDL .
CYPRESS, VHDL , .
.
,
. ,
. , [6]. library,
. :
LIBRARY ;
:
LIBRARY gates, my_lib;
gates my_lib VHDL , .
VHDL , work. Work ,
. VHDL work,
. work,
.
library [7], use:
library logical-name-identifier { ,logical-name-identifier } ;
use selected-name { , selected-name } ;
selected-name prefix . suffix
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LIBRARY IEEE, HARDI;USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL, HARDI.Devices.ALL;
LIBRARY PACK;
USE WORK.OnePackage.MyType;
PACK.AnotherPackage.ALL;
-- :LIBRARY WORK, STD; USE STD.STANDARD.ALL;
all . library
, , use . WORK, STD,
STD.STANDARD .
. 2 VHDL, .
. 2 , .
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1.2 - ENTITY
Entity
VHDL . VHDL Entity,
entity . Entity () (
). ,
entity , , , . 3.
. 3: VHDL Entity
ENTITY
Entity
. - :
entity identifieris[ formal-generic-clause ][ formal-port-clause ]
{ subprogram-decl. | subprogram-body | type-decl. | subtype-decl. | constant-decl. | signal-decl. | shared-variable-decl. | f ile-decl. | alias-decl. | attribute-decl. | attribute-spec. | disconnect-spec. | use-clause | group-template-decl. |group-decl. }
end [ entity ] [ entity-name-identifier ] ;
entity, is,
end,
()
(),
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entity. . 4
VHDL - .
. 4 Entity
Entity
VHDL , , Entity.
LIBRARY IEEE, TYPES, HARDI;USE IEEE.STD_LOGIC_1164.ALL;USE TYPES.TypePackage.ALL;USE HARDI.Timing.ALL;ENTITY Design IS
GENERIC (n : NATURAL);PORT (data : IN STD_LOGIC_VECTOR(n DOWNTO 0);
clk : IN STD_LOGIC;
outData : OUT OutDataType);END ENTITY Design;
entity
. , entity, .
Entity . 5.
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. 5 Entity
1.3 (Architecture)
entity
, , .
entity ,
.
. . 6
.
. 6
, . 7:
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. 7
- .
- , , . . Dataflow,
.
entity . begin,
, end, .
Architecture identifierofentity-name is{ subprogram-declaration | subprogram-body | type-declaration |subtype-declaration | constant-declaration | signal-declaration |shared-variable-declaration | file-declaration | alias-declaration |component-declaration | attribute-declaration | attribute-specification |configuration-specification | disconnect-specification | use-clause |group-template-declaration | group-declaration }
begin{ concurrent-statement }
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end [ architecture ] [ architecture-name-identifier ] ; VHDL
ARCHITECTURE Behave OF Design IS
FUNCTION InternalCalc(v : STD_LOGIC_VECTOR(7 DOWNTO 0))RETURN BIT_VECTOR(1 TO 4) ISBEGIN
END FUNCTION InternalCalc;SUBTYPE MyArray IS BIT_VECTOR(3 DOWNTO 0);SIGNAL internal : MyArray;SHARED VARIABLE data : STD_LOGIC_VECTOR(1 TO 8);
BEGINPROCESS(clk)BEGIN
END PROCESS;internal
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1.4 VHDL
, - VHDL , , ,
, , ,
[13]. .
:
- , .
- ( .) .
VHDL
package identifieris
{ subprogram-declaration | type-declaration | subtype-declaration | constant-declaration
| signal-declaration | shared-variable-declaration | file-declaration | alias-declaration |
component-declaration |
attribute-declaration | attribute-specification | disconnect-specification | use-clause |
group-template-declaration | group-declaration }
end [ package ] [package-name-identifier ] ;
.
, .9
. 9 PROJECT_PACK, .
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, .
, .
VHDL
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
PACKAGE Various IS
CONSTANT hold : TIME;
PROCEDURE Push(SIGNAL button : INOUT STD_LOGIC; hold : TIME);
TYPE Display IS RECORD
...
END RECORD ; COMPONENT ClockIS
PORT(mode, set, reset, clk : IN STD_LOGIC;LCD : OUT Display;
backPlane, alarmSignal : OUT STD_LOGIC);
END COMPONENT Clock; END PACKAGE Various
. 10.
. 10
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, , .
package bodypackage-name-identifieris
{ subprogram-declaration | subprogram-body | type-declaration | subtype-declaration |
constant-declaration | shared-variable-declaration | f ile-declaration | alias-declaration | use-
clause | group-template-declaration |
group-declaration }end [ package body ] [package-name-identifier ] ;
.
VHDL
LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;
PACKAGE BODY Various IS
CONSTANT hold : TIME := 100 ns;PROCEDURE Push(SIGNAL button : INOUT STD_LOGIC; hold : TIME) IS
BEGINbutton
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. 11
. 11
1.5 VHDL
VHDL entity
.
, , .
. , entity
.
- , begin.
.
- , , .
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( ).
componentcomponent_name [i s][port (port_signal_names: modetype;
port_signal_names: mode type;:
port_signal_names: mode type);]end component [component_name];
entity
, , ,
VHDL . , .
VHDL
COMPONENT LargeFlipFlop ISGENERIC(n : NATURAL;
t : TIME);PORT(d : IN BIT_VECTOR(n DOWNTO 0);
clk : IN BIT;q : OUT BIT_VECTOR(n DOWNTO 0));
END COMPONENT LargeFlipFlop;
. , , .
. 12.
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. 12
()
, [4]. ,
. 13:
- ;
- ;
- .
. 13 VHDL
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, :
instantiation-label : instantiated-unit[ generic-map ]
[ port-map ] ;[ component ] component-name |entity entity-name [ (architecture-identifier ) ] |configurationconfiguration-name
ENTITY LargeFlipFlop ISGENERIC(n : NATURAL; t : TIME);PORT(d : IN BIT_VECTOR(n DOWNTO 0);
clk : IN BIT;q : OUT BIT_VECTOR(n DOWNTO 0));
END ENTITY LargeFlipFlop;ARCHITECTURE Behave OF LargeFlipFlop IS...ENTITY Design IS ...ARCHITECTURE Behave OF Design IS
COMPONENT LargeFlipFlop ISGENERIC(n : NATURAL; t : TIME);PORT(d : IN BIT_VECTOR(n DOWNTO 0);
clk : IN BIT;q : OUT BIT_VECTOR(n DOWNTO 0));
END COMPONENT LargeFlipFlop;BEGIN
C1 : LargeFlipFlop GENERIC MAP(t => 12 ns, n => 5)PORT MAP(clk => clk, q => q1, d => d1);
C2 : ENTITY WORK.LargeFlipFlop(Behave) GENERIC MAP(7, 15 ns)PORT MAP(d2, clk, q2);
END ARCHITECTURE Behave;
. 14
XOR_4. [17]
. 15.
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. 14: XOR_4
architecture STRUCTURE_2 ofEXAMPLE iscomponent XOR_4 is
port(A,B: in BIT_VECTOR(0 to 3);C: out BIT_VECTOR(0 to 3));
endcomponent XOR_4;
signal S1,S2 : BIT_VECTOR(0 to 3);signal S3 : BIT_VECTOR(0 to 3);
beginX1 : XOR_4 portmap(S1,S2,S3);
endarchitecture STRUCTURE_2;
XOR_4 4
( )
( ).
STRUCTURE_2, 1
- S1,
S2 S3.
. 15
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entity
, .
.
:-
entity,
.
- entity
. .
forinstance_label:component_nameuse entity library_name.entity_name(arch_name);
forinstance_label:component_nameuse configuration library_name.config_name;
ENTITY LargeFlipFlop ISGENERIC(n : NATURAL; t : TIME);PORT(d : IN BIT_VECTOR(n DOWNTO 0);
clk : IN BIT;q : OUT BIT_VECTOR(n DOWNTO 0));
END ENTITY LargeFlipFlop;ARCHITECTURE Behave OF LargeFlipFlop IS ...
ENTITY Design IS ...ARCHITECTURE Behave OF Design ISCOMPONENT LargeFlipFlop IS
GENERIC(n : NATURAL; t : TIME);PORT(d : IN BIT_VECTOR(n DOWNTO 0);
clk : IN BIT;q : OUT BIT_VECTOR(n DOWNTO 0));
END COMPONENT LargeFlipFlop;
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BEGINC1 : LargeFlipFlop GENERIC MAP(n => 5, t => 12 ns)PORT MAP(d1, clk, q1);
END ARCHITECTURE Behave;
. 16.
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