VHDL micros a - Worcester Polytechnic Instituteusers.wpi.edu/~rjduck/VHDL micros.pdf · – Use...

Jim Duckworth, WPI Embedded Microprocessors1

Embedded Microprocessors

Module 12


Topics

• Microcontrollers versus FPGAS

– What is the best for your application?

• Debugging embedded designs

– Chipscope Pro and Agilent FPGA Dynamic Probe

– Use VHDL models of system components (e.g. SDRAM)

• Xilinx Virtex-4, Virtex-5

– DSPslices, Ethernet MAC, integrated processors

• Adding Microcontrollers to FPGAs

– Picoblaze, Microblaze, Power PC

• Adding DSP functions to FPGAs

– Xilinx System Generator for Simulink

• Lessons learned and pitfalls to be avoided


Microcontrollers versus FPGAs

• Microcontrollers

– Execute compiled programs written in ‘C’ or Assembler

• Program may be on the micro or in external flash memory

• Micro fetches instructions, decodes, manipulates data or I/O

– Sequential execution

• Requires multiple clock cycles for most operations

– Can be easily optimized for battery powered operations

• Only wake up in response to external interrupts

– Limited I/O of standard logic

• FPGAs

– ‘Sea of gates’ can be configured for any required logic

– Very good for high-speed parallel data processing (e.g. networks)

– Lots of I/O – versatile logic interface (LVDS etc)

– Can be easily partitioned into different functional blocks

– Not appropriate for simple control applications (not vending machine!)


Digital Controller Board – Virtex II FPGA

SDRAM

Config

PROMLVDS

Interface

FPGA

Ethernet Transceiver


FPGA Functional Blocks


DDR SDRAM Controller – 128 byte writes


Start of Write Cycle


Start of ROW read cycle (2048 bytes)


Part of SDRAM Initialization Sequence


Virtex 4

$1,000

(25 off)

9604,320K98,304

96 DSP

slices

12,2885MXC4VLX100

29,504

9,312

1,920

CLB

flip-flops

<$9376648K3,6881.6MXC3S1600E

$30 1-

off

232360K1,164500KXC3S500E

<$210872K240100KXC3S100E

Price

(250K)

User

IO

Block

Ram (bits)

CLBs

(4 slices)

Syste

m

Gates

Device


PPL Transceiver – Based on Virtex 4


Transceiver Box




Debugging Embedded Designs

• VHDL models of standard devices

– Micron models of all SDRAM devices – simulates behavior

• Xilinx ChipScope Pro

– Poor man’s logic analyzer!

– Connected and analyzed through JTAG port

– See on-line introduction (with CoreGen)

• Agilent FPGA Dynamic Probe

– Interfaces through special core inside FPGA


Embedded Software Tools

CPU

Logic Design Tools

I/O

FPGA

Memory

Logic Design Tools

FPGA +

Memory + IP +

High Speed IO

(4K & Virtex)


CPU

Inte

gra

tio

n o

f F

un

ctio

ns

Inte

gra

tio

n o

f F

un

ctio

ns

TimeTime

Logic Design Tools


Logic + Memory

+ IP +

Processors +

RocketIO

(Virtex-II Pro)

Programmable Systems

usher in a new era of system

design integration

possibilities

Programmable Systems

usher in a new era of system

design integration

possibilities

Integration in System Design


Embedded Processors

• Soft core processors – use on any FPGA

– Picoblaze 8-bit microcontroller

• Programmed in assembler

• Very useful for replacing complex state machines

– Microblaze 32-bit microcontroller

• Use Xilinx EDK – base system builder

• Program in ‘C’

• Hard Processor cores

– IBM Power PC 405 32/64-bit Processor

• 16 KB data cache and 16 KB instruction cache

• On Virtex II Pro and Virtex-4 devices

• Can add and mix multiple processors!

– Need to be familiar with micros (as well as logic design)


Xilinx - Embedded Processing


Picoblaze 8-bit microcontroller


Picoblaze 8-bit microcontroller


Picoblaze overview


Picoblaze User Guide


Picoblaze Block diagram


Micro versus Logic


Picoblaze connected to ROM


Processor and ROM


Adding Inputs (UART example)


UART Transmit (assembler example)


Simple Picoblaze Project


Picoblaze resources – very low!


KCPSM3 with ROM and UARTS


Creating the ROM – using pBLAZE IDE


Simulating the picoblaze code


VHDL template to create ROM

-- Ken Chapman (Xilinx Ltd) October 2002

-- This is the VHDL template file for the KCPSM assembler.

-- Adapted for pBlazIDE by Henk van Kampen, www.mediatronix.com, March 2003

-- It is used to configure a Virtex(E, II) and Spartan-II(E, 3) block RAM to act as

-- a single port program ROM.

-- This VHDL file is not valid as input directly into a synthesis or simulation tool.

-- The assembler will read this template and insert the data required to complete the

-- definition of program ROM and write it out to a new '.vhd' file as specified by the

-- '.psm' file being assembled.

-- The assembler identifies all text enclosed by {} characters, and replaces these

-- character strings. All templates should include these {} character strings for

-- the assembler to work correctly.

-- The next line is used to determine where the template actually starts and must exist.

{begin template}

library IEEE ;

use IEEE.STD_LOGIC_1164.all ;

use IEEE.STD_LOGIC_ARITH.all ;

use IEEE.STD_LOGIC_UNSIGNED.all ;

library unisim ;

use unisim.vcomponents.all ;

entity {name} is

port (

clk : in std_logic ;

address : in std_logic_vector( 9 downto 0 ) ;

instruction : out std_logic_vector( 17 downto 0 )

) ;


Simulating the whole design


Microblaze 32-bit Soft Processor


Microblaze Overview


MicroBlaze-based Embedded Design

Flexible Soft IPMicroBlaze32-Bit RISC Core

UART10/100

E-Net

On-Chip

Peripheral

Off-ChipMemory

FLASH/SRAM

LocalLink™

FIFO Channels

0,1…….32

Custom

FunctionsCustom

Functions

BRAMLocal Memory

BusD-Cache

BRAM

I-Cache

BRAM

ConfigurableSizes

Arb

ite

r

Processor Local Bus

Instruction Data

PLBBus

Bridge

PowerPC

405 Core

Dedicated Hard IP

Arb

ite

r

Processor Local Bus

Instruction Data

PLBBus

Bridge

Bus

Bridge

PowerPC

405 Core

Dedicated Hard IP

PowerPC

405 Core

Dedicated Hard IP

PowerPC

405 Core

Dedicated Hard IPPossible in

Virtex-II Pro

Hi-SpeedPeripheral

GB E-Net

e.g.Memory

Controller

Hi-SpeedPeripheralHi-Speed

PeripheralGB

E-NetGB

E-Net

e.g.Memory

Controller

e.g.Memory

Controller

Arb

iter OPB

On-Chip Peripheral Bus


Embedded DevelopmentTool Flow Overview

Data2MEM

Bitstream

Compiler/Linker

(Simulator)

C Code

Debugger

Standard Embedded SWDevelopment Flow

CPU code in on-chip memory

?

CPU code in off-chip memory

Download to Board & FPGA

Object Code

Standard FPGA HWDevelopment Flow

Synthesizer

Place & Route

Simulator

VHDL/Verilog

?

Download to FPGA


EDK (Xilinx Platform Studio)


Base System Builder


Configuring Processor and I/O


Microblaze Hardware Block Diagram


Microblaze Software – C Program


PowerPC405 Core

Dedicated Hard IP

Flexible Soft IP

RocketIO

PowerPC-based Embedded Design

Full system customization to meet performance, functionality, and cost goals

DCR Bus

UART GPIOOn-Chip

PeripheralHi-SpeedPeripheral

GB E-Net

e.g.Memory

Controller

Arb

iter

On-Chip Peripheral Bus

OPB

Arb

iter

Processor Local Bus

Instruction Data

PLB

DSOCM

BRAM

ISOCM

BRAM

Off-ChipMemory

ZBT SSRAMDDR SDRAM

SDRAM

Bus

Bridge

IBM CoreConnect™

on-chip bus standard

PLB, OPB, and DCR


Lessons Learned and Pitfalls to be Avoided

• Do we start with VHDL for synthesis or modeling?

• How do we understand timing behavior?

• VHDL is not a programming language

• Where have my signals or ports gone?

• How do I debug my design?

• Use std_logic types for all ports

• Make a test bench as soon as possible

• How do I debug my embedded microprocessor?

• How do I keep track of all the acronyms?

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