Video and DDR3 Nios II DisplayPort Design Example (RX and TX) · DisplayPort Design Example (RX and...

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© 2013 Altera Corporation—Confidential

DisplayPort Design Example (RX and TX)

This design example demonstrates the use of the Altera DisplayPort MegaCore Function in a receive and

transmit mode application. The design example is implemented using Altera’s Qsys tool and standalone

HDL modules. The design example demonstrates the following:

Altera’s DisplayPort (DP) sink and source in real application

A video loop-through system based on DP sink and source function

Quick starting point for building a video system

Figure 1 is the system diagram of the design example.

Figure 1.Design Example System

DisplayPort CapableMonitor

DisplayPortGPU

DisplayPortMegaCore Function (Source)

DisplayPortMegaCore Function

(Sink)

Video and Image

Processing (VIP)

IP Cores

MainLink

MainLink

AUX

HPD

AUX

HPD

Nios II Procesor

DDR3

FPGA

This document has the following sections:

Functional Description

Software Description

Using the Design Example

Viewing the Results

Document Revision History

http://www/literature/ug/ug_displayport.pdf

July 2013 Confidential Altera Corporation

Functional Description This design example receives video data over the DP sink RX link. The received video is converted to

Avalon-ST image stream and stored into external memory. The buffered image is then mixed with a

1920x1200 background color bar and is sent to the DP source. The combined image is transmitted to a

DP capable monitor over DP source TX link.

Figure 2 shows a block level diagram of the design example.

The design example has the following four major functional components.

System Reset

Clocking

Link Initialization

o Transceiver Reconfiguration

o DP TX link

o DP RX link

o Link Bandwidth

o DP Configuration Data Fields

Qsys System - Video Receive and Transmit Paths

o DP sink

o DP source

o VIP Suite IP Cores

o Nios II Processor

The following sections describe these major functional components.


Figure 2.Design Example Block Diagram

DP TX

XCVR PHY

DisplayPortMonitor

Lane 0

Lane 1

Lane 2

Lane 3

DisplayPort Source

AUX Channel

HPD

Tx AUX Debug FIFO

Transceiver Reconfiguration

Controller

reconfig_ mgmt_hw_ctrl

Nios II Processor

Tx AUX Transaction Monitoring

TX Management

Tx AUXDebug Stream

System Reset

Video PLL

Transceiver PLL

154MHz

16MHz

162MHz

270MHz

xcvr_pll_lock

video_pll_lock

Clocked Video

Output

Test Pattern

Generator

xcvr_pll_refclk clk resetn

I2C Master

SCL

SDA

UserLEDs

User Push Buttons

1920x1200 BackgroundColor Bars

timer

sysid

Qsys System

(sv_dp_control.v)

Video withSync Signals

IP components generated with MegaWizard Plug-In Manager

IP components generated with Qsys

JTAG UART

Top Module

(sv_dp_demo.v)

Custom logic/component

onchip_mem

PIO

DP RX

XCVR PHY

DisplayPort Sink

Mixer

Triple Frame Buffer

Clocked Video Input

Rx AUX Debug FIFO

Video withSync Signals

Avalon-ST Video

DDR Memory

ControllerDDR3 Memory

Rx AUXDebug Stream

Rx AUX Transaction Monitoring

RX Management

AUX Buffer

AUX Buffer

HPD

Lane 0

Lane 1

Lane 2

Lane 3

AUX Channel

DisplayPort Graphics Card

clk

clk

system_resetn

system_resetn

ddr_clk

EDID memory

Avalon-ST Video

Avalon-MM Interface


System Reset The system reset in the design example is triggered by an external hard reset (e.g. push-button), the

PLLs not achieving lock, or the PLLs losing lock. The system reset signal is kept asserted for 32K clock

cycles, after the PLLs have locked to their reference clock. This ensures the system stays in the reset

state until the PLL output clocks reach a stable state.

Clocks The design example instantiates two PLLs in the top level module: Transceiver PLL and Video PLL. These

PLLs generate internal clocks required by the design. Table 1 lists the clocks used in the design, their

frequencies, and the main blocks driven by the clock signals.

Table 1.Clock Signals

Clock Signal Description Loads

clk 100 MHz external clock source DisplayPort IP core Avalon-MM

interface

Nios II processor and peripherals

DisplayPort IP core transceiver

reconfiguration and mgmt logic

Video PLL input clock

162 MHz Transceiver PLL outclk0. Used as the

transceiver reference clock for 1.62 Gbps

rate

DisplayPort transceiver PHY reference

Clock

270 MHz Transceiver PLL outclk1. Used as the

transceiver reference clock for 2.7, and 5.4

Gbps rates

DisplayPort transceiver PHY reference

Clock

154 MHz Video PLL outclk0. Video clock for Avalon

Streaming (Avalon-ST) video data path for

1920x1200 @ 60 Hz

Clock for DisplayPort IP core video

input and output, and VIP suite IP

cores

16 MHz Video PLL outclk1. Clock for 1 Mbps AUX

channel interface

DisplayPort IP core TX and RX AUX

channel controller

TX and RX AUX channel debug FIFOs

ddr_clk 100 MHz external clock source for memory

controller

DDR3 SDRAM controller IP core for

Frame Buffer


Link Initialization


During link training, the following transceiver features are reconfigured through the transceiver

reconfiguration controller IP core and a finite state machine (FSM) to obtain a functional link.

Data rate

Output voltage swing (VOD)

Pre-emphasis

Figure 3 below shows the diagram of the reconfiguration control block, DP source and sink, and the Nios

II processor in the design example.

Figure 3.Transceiver Reconfiguration Control

reconfig_ mgmt_ hw_ctrl

FSM

TX data rate reconfiguration request


Controller IP core

DisplayPortSource

tx_mgmt

Nios II Processor

IRQAvalon-MMInterface

dptx_hpd_isr(..);link_training(..);

Main Link

xcvr

DisplayPort Sink

rx_mgmt

Main Link

xcvr

HPD

AUXChannel

IRQ*Avalon-MMInterface *

RX data rate reconfiguration request

* The Nios II processor control for DisplayPort Sink is optional. By default, internal AUX FSM is used.

HPD

AUXChannel

TX VOD, Pre-emphasis reconfiguration request

Reconfiguration Control


Table below lists the custom RTL modules responsible for the transceiver data rate and analog

reconfiguration during link training. The RTL modules are available in clear text Verilog in the design

example.

Table 2.Clear-text Verilog Modules for Transceiver Reconfiguration

Module Name Description

reconfig_mgmt_hw_ctrl.v This module is a high level FSM responsible for generating the

control signals to reconfigure the VOD, pre-emphasis and selects

PLL reference clock, and reconfigures clock divider setting. It loops

through all the channels and transceiver settings.

reconfig_mgmt_write.v This module is instantiated in the ‘reconfig_mgmt_hw_ctrl.v’. It

generates a reconfiguration write cycle on the Avalon-MM

interface to the transceiver reconfiguration controller IP core. This

is done with a simple state machine which steps through the low

level commands to write to the transceiver reconfiguration

controller IP core.

dp_mif_mappings.v This module is instantiated in ‘reconfig_mgmt_hw_ctrl.v’. It maps

the 2-bit requested data rates to the Memory Initialization File

(MIF) settings that need to be written during a direct

reconfiguration mode of the transceiver reconfiguration controller

IP core.

dp_analog_mappings.v This module is instantiated in ‘reconfig_mgmt_hw_ctrl.v’. It maps

per-channel 2-bit VOD and 2-bit pre-emphasis settings from the DP

source to the transceiver analog settings.

Note: To enable analog reconfiguration, turn on ‘Support analog

reconfiguration’ parameter in the DP source parameter editor. By

default, the DP source analog reconfiguration is disabled. If you are

not using an external re-driver solution, this parameter should be

turned on.

The DP main link in the design example uses external re-driver devices on the Bitec HSMC daughter

board. Therefore, the DP source ‘Support analog reconfiguration’ parameter is not turned on. The re-

driver’s output is automatically adjusted based on link training result. The input equalization (EQ)

settings are programmable through the I2C interface. The ‘main.c’ in the design example software

includes the code that allows you to configure the re-driver EQ settings. Depending on the channel

conditions such as the cable quality and length, you may need to adjust these settings.

http://www.bitec-dsp.com/hsmc_dp.htmlhttp://www.bitec-dsp.com/hsmc_dp.html


DP TX Link

The DP link must be initialized through link training before transporting a main video stream. The

training sequence is initiated by the link policy maker running on the Nios II processor after detecting a

Hot Plug Detect (HPD) event asserted by a sink device.

Figure below shows the typical flow of the DP source link management software running on the Nios II

processor in this design example. Refer to the C source code ‘software/dp_demo_src/tx_utils.c’.


Figure 4.Typical Flow of the DP Source Link Management

HPD Detected

Read HPD event type in DPTX_TX_STATUS register:

IORD(..);

Read the sink EDID: btc_dptx_edid_read(..);

Perform link training:btc_dptx_link_training(..);

Check automated test request: Read sink DPCD

DEVICE_SERVICE_IRQ_VECTOR

AUTOMATED_TEST_REQUEST ?

Perform automated test:btc_dptx_test_autom(..);

Read sink and link status DPCD 200h~205h:

btc_dptx_aux_read(..);

Set DisplayPort IP TX color space:

btc_dptx_set_color_space(..);

Long HPD &&HPD Level == 1

Short HPD(HPD IRQ)

Yes

No

Check link status bits: CR_DONE, EQ_DONE,

SYMBOL_LOCKED, ALIGN_DONE

DOWNSTREAM_PORT_STATUS_CHANGED ?

Read the sink EDID:btc_dptx_edid_read(..);

Disable DisplayPort source Interrupts:

BTC_DPTX_DISABLE_IRQ();

Enable DisplayPort IP TX Interrupts:

BTC_DPTX_ENABLE_IRQ()

Yes

No

Link status bits deasserted on enabled

lanes ?

Yes

No

Read DisplayPort source configuration from the dashboard:

Maximum link rate & lane count


Table below describes the DP source API functions and macros shown in the Figure 4. For details about

the DP API functions, refer to the DisplayPort API Reference chapter of the DisplayPort MegaCore

Function User Guide.

Table 3.DP Source API Functions and Macros

DP Source API and Macros Description Path in design example software

BTC_DPTX_DISABLE_IRQ(), BTC_DPTX_ENABLE_IRQ()

DisplayPort library macro to disable or enable DisplayPort source interrupt

btc_dptx_syslib/btc_dptx_syslib.h

IORD(…), IOWR(…)

Nios II HAL macro that provides a read or write access to a component register

dp_demo_bsp/HAL/inc/io.h

btc_dptx_edid_read(…) This function reads the complete EDID of the connected DisplayPort sink

btc_dptx_syslib/btc_dptx_syslib.h

btc_dptx_set_color_space(…) This function sets the color space for DP source transmitted video

btc_dptx_test_autom(…) This function handles test automation requests from the connected DisplayPort sink

btc_dptx_aux_read(…) This function reads 1 to 16 data bytes from the connected DisplayPort sink’s DPCD via AUX channel

btc_dptx_link_training(…) This function performs link training with the connected DisplayPort sink

DP RX Link

The DP sink implements a finite state machine (FSM) that decodes the incoming AUX channel

transaction requests. All lane training and EDID link layer services are performed by the AUX channel

FSM in non-GPU mode, enabling DP sink to run autonomously without a controller. DP sink

instantiations greatly benefit from and may optionally use an embedded controller (Nios II processor or

another controller). If your design needs a controller to control DP sink instances, turn on ‘Enable GPU

control’ parameter in the DP sink parameter editor.

Link Bandwidth

Altera’s DP sink and source supports scalable main link with 1, 2, or 4 lanes. The initialized link

bandwidth after link training must be greater than the required video data bandwidth.

The design example receives and transmits the video frames in the following format.

Resolution – 1920 x 1200 @ 60 Hz

Color depth – 24 bits-per-pixel

Horizontal blanking – 160 pixels

Vertical blanking – 35 lines

The pixel clock frequency and required raw bandwidth are:


Pixel Clock Frequency – (1920+160) pixels * (1200+35) lines * 59.95 Hz = 154.0 MHz

Required Raw Bandwidth (BW) – 24 bits-per-pixel * 154.0 MHz * 1.25 (8b/10b) = 4.62 Gbps

The number of lanes required at RBR, HBR, and HBR2 rates to support the bandwidth are highlighted in

the table below.

Table 4. Link Rate and Lane Count

RBR rate (Gbps) 1.62

Lane count 1 2 4

Total raw BW (Gbps) 1.62 3.24 6.48

HBR rate (Gbps) 2.7

Lane count 1 2 4


HBR2 rate (Gbps) 5.4

Lane count 1 2 4


DisplayPort Configuration Data Fields

The DisplayPort Configuration Data (DPCD) fields of DP sink address space are accessed by a upstream

DP source device to discover the DP sink capability, initialize the link, and check the link/sink status via

the AUX channel.

The following section describes the DPCD fields for link initialization:

Receiver Capability Field

Link Configuration Field

Link/Sink Status Field

Receiver Capability Field

Table below lists example locations of the receiver capability field that DP source reads to determine the

DP sink capability. For the complete list of the receiver capability locations, refer to the DP 1.2a

specification.

Table 5. Receiver Capability DPCD Locations

DisplayPort Address

Description Read/Write over AUX CH

00000h

DPCD_REV : DPCD revision number Bits 3:0 = Minor revision number Bits 7:4 = Major revision number 10h for DPCD Rev.1.0 11h for DPCD Rev.1.1 12h for DPCD Rev 1.2

Read Only


00001h

MAX_LINK_RATE : Maximum link rate of Main Link lanes = Value x 0.27Gbps per lane Bits 7:0 = MAX_LINK_RATE 06h = 1.62Gbps per lane 0Ah = 2.7Gbps per lane 14h = 5.4Gbps per lane

Read Only

00002h

MAX_LANE_COUNT : Maximum number of lanes = Value Bits 4:0 = MAX_LANE_COUNT 1h = 1-lane 2h = 2-lanes 4h = 4-lanes For 1-lane configuration, Lane 0 is used. For 2-lane configuration, Lane 0 and Lane 1 are used. Bits 6:5 = RESERVED. Read all 0s. Bit 7 = ENHANCED_FRAME_CAP (in Single Stream Format) 0 = Enhanced Framing symbol sequence for BS, SR, CPBS, and CPSR is not supported. 1 = Enhanced Framing symbol sequence for BS, SR, CPBS, and CPSR is supported

Read Only

00003h

MAX_DOWNSPREAD Bit 0 = MAX_DOWNSPREAD 0 = No down spread 1 = Up to 0.5% down-spread Bit 5:1 = RESERVED. Read all 0s. Bit 6 = NO_AUX_HANDSHAKE_LINK_TRAINING 0 = Requires AUX CH handshake to synchronize to DisplayPort transmitter 1 = Does not require AUX CH handshake when the link configuration is already known. Bit 7 = RESERVED. Read all 0s.

Read Only

Link Configuration Field

DP source writes to the link configuration field of the DPCD to configure and initialize the link.

Table below lists DPCD link configuration locations. For the complete list of the link configuration

locations, refer to the DP 1.2a specification.

Table 6. Link Configuration DPCD Locations

DisplayPort Address


00100h

LINK_BW_SET Main Link Bandwidth Setting=Bits[7:0] x 0.27Gbps per lane 06h = 1.62Gbps per lane 0Ah = 2.7Gbps per lane 14h = 5.4Gbps per lane

Write/Read


00101h

LANE_COUNT_SET Main Link Lane Count = Bits[4:0] 1h = 1-lane 2h = 2-lanes 4h = 4-lanes

Write/Read

00102h

TRAINING_PATTERN_SET Bits 1:0 = TRAINING_PATTERN_SELECT : Link Training Pattern Selection 00 – Training not in progress (or disabled) 01 – Training Pattern 1 10 – Training Pattern 2 11 – Training Pattern 3 For DPCD Version 1.2 Bits 3:2 are RESERVED (always 00), replaced with per-lane control in LINK_QUAL_LANEn_SET (DPCD 0010Bh-0010Eh) Bit 4 = RECOVERED_CLOCK_OUT_EN Bit 5 = SCRAMBLING_DISABLE 0 – DP transmitter scrambles data symbols before transmission 1 – DP transmitter disables scrambler and transmits all symbols without scrambling Bits 7:6 = SYMBOL ERROR COUNT SEL 00: Disparity error and Illegal Symbol error 01: Disparity error 10: Illegal symbol error 11: RESERVED SYMBOL_ERROR_COUNT_SEL applies to the main lanes

Write/Read

00103h

TRAINING_LANE0_SET: Link Training Control_Lane 0 Bits 1:0 = VOLTAGE SWING SET 00 –Voltage swing level 0 01 –Voltage swing level 1 10 –Voltage swing level 2 11 –Voltage swing level 3 Bit 2 = MAX_SWING_REACHED Bit 4:3 = PRE-EMPHASIS_SET 00 = Pre-emphasis level 0 01 = Pre-emphasis level 1 10 = Pre-emphasis level 2 11 = Pre-emphasis level 3 Bit 5 = MAX_PRE-EMPHASIS_REACHED Bits 7:6 = RESERVED. Read all 0s.

Write/Read

00104h TRAINING_LANE1_SET (Bit definition identical to that of TRAINING_LANE0_SET.)

Write/Read


Write/Read


Write/Read

00107h DOWNSPREAD_CTRL: Down-spreading Control Write/Read


Bit 3:0 = RESERVED. Read all 0s Bits 4 = SPREAD_AMP (Spreading amplitude) 0 = Main link signal is not downspread 1 = Main link signal is downspread by equal to or less than 0.5% with a modulation frequency in the range of 30kHz ~ 33kHz Bit 6:5 = RESERVED. Read all 0s. Bit 7 = MSA_TIMING_PAR_IGNORE_EN

Link/Sink Status Field

Table below lists link/sink status field of the DPCD. For the complete list of the link/sink status locations,

refer to the DP 1.2a specification.

Table 7. Link/Sink Status DPCD Locations

DisplayPort Address


00202h

LANE0_1_STATUS Bit 0 = LANE0_CR_DONE Bit 1 = LANE0_CHANNEL_EQ_DONE Bit 2 = LANE0_SYMBOL_LOCKED Bit 3 = Reserved. Read 0. Bit 4 = LANE1_CR_DONE Bit 5 = LANE1_CHANNEL_EQ_DONE Bit 6 = LANE1_SYMBOL_LOCKED Bit 7 = RESERVED. Read 0.

Read Only

00203h LANE2_3_STATUS Bit definition identical to that of LANE0_1_STATUS

Read Only

00204h

LANE_ALIGN_STATUS_UPDATED Bit 0 = INTERLANE_ALIGN_DONE Bit 5-1 = Reserved. Read all 0s Bit 6 = DOWNSTREAM_PORT_STATUS_CHANGED Bit 6 is set in a branch device when it detects a change in the connection status of any of its Downstream ports Bit 7 = LINK_STATUS_UPDATED Link Status and Adjust Request updated since the last read. Bit 7 is set when updated and cleared after read.

Read Only

00205h

SINK_STATUS Bit 0 = RECEIVE_PORT_0_STATUS 0 = SINK out of synchronization 1 = SINK in synchronization Bit 1 = RECEIVE_PORT_1_STATUS 0 = SINK out of synchronization 1 = SINK in synchronization The Sink device must set each of these bits as soon as it determines that the corresponding received stream is properly re-generated and within the supported stream format range, and clear each of these bits as soon as it determines that the corresponding received stream

Read Only


is no longer being properly regenerated or within the supported stream format range Bits 7:2 = RESERVED. Read all 0s

When a DP link with four lanes is successfully trained and ready for normal operation, the link status will

be as follows.

LANE0_1_STATUS (00202h) – 77h

LANE2_3_STATUS (00203h) – 77h

LANE_ALIGN_STATUS_UPDATED (00204h) – 01h (or 81h, if the status has been updated since the

last read)

Qsys System - Video Paths The video receive and transmit function is implemented using Altera’s Qsys tool. Figure 5 below is the

block diagram of the Qsys system showing the video receive and transmit paths that include the DP

source, DP sink, the VIP Suite IP cores, and the SDRAM Controller IP core.

Figure 5. Qsys Video Paths

ClockedVideo

OutputMixer

DisplayPort IP Core

TX

tx_vid_v_synctx_vid_h_sync

tx_vid_data[3v-1:0]*tx_vid_datavalid

video_clk

Qsys System

tx_serial_data[3:0](Main Link)

ClockedVideoInput

FrameBuffer

DisplayPort Sink(RX)

rx_serial_data[3:0](Main Link)

rx_vid_v_syncrx_vid_h_sync

rx_vid_data[3v-1:0]*rx_vid_locked

rx_vid_de * v = bits-per-color

Test PatternGenerator

DDR3 SDRAMController IP

1920x1200Color Bar

Video and Image Processing (VIP) Suite IP Cores

DisplayPort Source

(TX)

Video data paths

Figure below is the Qsys system contents integrated in the Qsys tool.


Figure 6. Qsys System Contents Tab


DP Sink

The DP sink has the following features:

1, 2, or 4 lane operation

1.62, 2.7, and 5.4 Gbps per lane

16, 18, 20, 24, 30, 32, 36, or 48 bits per pixel color depths

RGB and YCrCb color modes

Finite state machine (FSM) and embedded controller AUX channel operation

Produces a proprietary video output

Support for OpenCore Plus evaluation

o Allows you to evaluate the IP core before you purchase a license

DP Sink Parameters

The following figure is the screenshot of the DP sink parameter editor.

Figure 7. DP Sink Parameter Editor

Table below describes the DP sink parameters.

Table 8.DP Sink Parameters

Parameter Description


Device family Targeted device family (Arria V, Arria V GZ, or Stratix V); matches the project device family.

Support DisplayPort sink Enable DisplayPort sink.

IEEE OUI Specify an IEEE organizationally unique identifier (OUI) as part of the DPCD registers.

Maximum video output color depth Video output interface port bits per color (bpc). Determines top-level video outport width. 6,8,10,12, or 16 bpc.

RX maximum link rate Maximum link rate. 20 = 5.4 Gbps, 10 = 2.7 Gbps, 6 = 1.62 Gbps.

Maximum lane count Maximum lanes used (1, 2, or 4).

Invert transceiver polarity Invert transceiver polarity.

Sink scrambler seed value Initial seed for scrambler block. Use 16’hFFFF for normal DP and 16’hFFFE for eDP.

Enable AUX debug stream Send source AUX traffic output to an Avalon-ST port.

Enable GPU control Use an embedded controller to control the sink.

Export MSA Outputs MSA on top level port interface.

Support secondary data channel Enables secondary data.

Support audio data channel Enables audio packet decoding.

Number of audio data channels Number of audio channels supported.

Support CTS test automation Support CTS test automation.

6-bpc RGB or YCbCr 4:4:4 (18 bpp) Support 18 bpp decoding.





8-bpc YCbCr 4:2:2 (16 bpp) Support 16 bpp decoding.




The “Maximum video output color depth” parameter defines the maximum color depth supported and

determines the top level video output port width while the “RGB” or “YCbCr” (e.g. “6-bpc RGB or YCbCr

4:4:4 (18bpp)”) parameters allow the color depth decoding to be enabled one by one.

For example, DP sink could be set up to support the maximum 10-bpc video output color depth, but

enable only 8-bpc and 10-bpc color depth decoding. This will remove the 6-bpc decoding logic and save

resource.

The “Enable AUX debug stream” parameter enables the IP core to output an AUX traffic debugging

stream so that you can inspect the activity on the AUX channel in real time. The AUX debug stream is

enabled in the design example. The AUX debug output port is directly connected with the downstream

Avalon-ST FIFO to enable monitoring of the AUX transactions on the Nios II terminal during link training.


The “Enable GPU control” parameter allows you to control the DP sink from the controller (e.g. Nios II

processor) and gives access to the sink’s internal status register for debugging. Using a controller allows

you to access additional DPCD locations that are not accessible in non-GPU mode. For details of the

supported DPCD locations with and without a controller, refer to the Table 10-52 Sink Supported DPCD

Locations in the DP user guide. Note that if the “Enable GPU control” parameter is turned on, the sink’s

Avalon-MM master interface to the on-chip EDID memory is not instantiated. The EDID memory should

be accessed through a controller.

The “Export MSA” parameter enables the DP sink to export the Main Stream Attribute (MSA) interface

to the top level port interface along with the transceiver recovered clock, allowing your design to access

the MSA and Vertical Blanking ID (VB-ID) values.

The “Support CTS test automation” parameter enables the DP sink to calculate the 16-bit CRC value of

each color component of the received video frames to facilitate the automated test process. The DP

simulation example in the DP user guide enables this feature to verify the CRC values of the sent and

received video frames.

Table below lists the sink’s DPCD locations that store the CRC values. Note that these locations are

supported in non-GPU mode.

Table 9. DP Sink DPCD locations for CRC values

DPCD Address


00240h-00241h

TEST_CRC_R_Cr: Stores the 16 bit CRC value of the R or Cr component. 00240h bits 7:0 = CRC value bits 7:0 00241h bits 7:0 = CRC value bits 15:8

Read Only

00242h-00243h

TEST_CRC_G_Y: Stores the 16 bit CRC value of the G or Y component. 00242h bits 7:0 = CRC value bits 7:0 00243h bits 7:0 = CRC value bits 15:8

Read Only

00244h-00245h

TEST_CRC_B_Cb: Stores the 16-bit CRC value of the B or Cb component. 00244h bits 7:0 = CRC value bits 7:0 00245h bits 7:0 = CRC value bits 15:8

Read Only

DP Sink Interfaces

The DP sink top level interfaces are as follows.

Controller Interface – Avalon-MM slave interface for the DP sink management

Transceiver Management Interface – Transceiver data rate reconfiguration

Video Interface – Video data and H/V sync information input

AUX Interfaces – AUX channel, optional AUX debug stream, and EDID memory interfaces

Secondary Stream and Audio Interfaces – These interfaces are optional and can be enabled in the DP

sink parameter editor


Debugging Interface – Link parameter and video stream output for debugging

MSA Interface – Allows user design to access the MSA and VB-ID parameters

The following section describes the port signals of the interfaces.

The controller interface allows you to control the sink from an external or on-chip controller, such as the

Nios II processor for debugging. The controller interface is an Avalon-MM slave that also gives access to

the sink’s internal status registers.

Table below lists the DP sink controller interface ports.

Table 10. DP Sink Controller Interface

Port From (Input) To (Output) Description

clk Clock source Clock for embedded controller

reset System reset Reset for embedded controller

rx_mgmt_address[8:0] Avalon-MM master (Nios II processor)

Address bus

rx_mgmt_chipselect Chip select

rx_mgmt_read Read request

rx_mgmt_write Write request

rx_mgmt_writedata[31:0] Write data

rx_mgmt_readdata[31:0]

Avalon-MM master (Nios II processor)

Read data

rx_mgmt_waitrequest Asserted when DP sink is unable to respond to a read or write request

rx_mgmt_irq Interrupt request. DP sink asserts an IRQ when an AUX transaction is received and DPRX_AUX_IRQ_EN register ENABLE bit is set.

Table below lists the transceiver management interface ports.

Table 11. DP Sink Transceiver Management Interface


xcvr_refclk[1:0] Transceiver PLL Transceiver PLL reference clocks: 162 MHz for RBR, and 270 MHz for HBR and HBR2.

xcvr_mgmt_clk Clock source Transceiver management clock. Typically 100~125 MHz.

rx_serial_data[m-1:0]* Pin Main link serial data input.

rx_link_rate[1:0] Reconfiguration mgmt FSM

RX link rate setting. 00: RBR, 01:HBR, 10:HBR2

rx_reconfig_req RX link rate reconfiguration request.

rx_reconfig_ack Reconfiguration mgmt FSM

RX link rate reconfiguration request is acknowledged.

rx_reconfig_busy RX link rate reconfiguration is in


progress.

reconfig_to_xcvr [m x 70-1:0]*

Transceiver Reconfiguration Controller IP

XCVR reconfiguration signals from the Reconfiguration Controller IP Core.

reconfig_from_xcvr [m x 46-1:0]*


XCVR reconfiguration signals to the Reconfiguration Controller IP Core.

* m is the number of RX lanes.

Table below lists the video output interface ports. In the design example, the DP sink sends video data

output to Clock Video Input (CVI) IP core. CVI H-sync and V-sync inputs are derived from delayed

versions of eol and eof signals. For details about the DP sink and CVI interface, refer to the Verilog code

example in the DisplayPort Sink Video Interface section of the DP core user guide.

Table 12. DP Sink Video Interface


rx_vid_clk Video PLL Video/pixel clock input

rx_vid_valid VIP suite CVI IP core

Video data valid

rx_vid_data[3v - 1:0] Video data output (v is the number of bits per color)

rx_vid_sol Synchronization pulse at the start of active lines

rx_vid_eol Synchronization pulse at the end of active lines

rx_vid_sof Synchronization pulse at the start of active frames

rx_vid_eof Synchronization pulse at the end of active frames

rx_vid_locked MSA is locked

Figure 8. DP Sink Video Output Timing Diagram


Table below lists the AUX channel interface ports. AUX channel uses Manchester-II coding at the

nominal bit rate of 1 Mbps.

Table 13. DP Sink AUX Channel Interface


aux_clk Clock source AUX clock input. 16MHz.

aux_reset System reset Reset for AUX clock domain

rx_aux_in AUX channel bidirectional buffer

AUX channel serial data input

rx_aux_out AUX channel bidirectional buffer

AUX channel serial data output

rx_aux_oe AUX channel output enable

rx_hpd Pin Hot Plug Detect (HPD) output

Table below lists the AUX debug interface ports. The AUX debug interface is instantiated if the Enable

AUX debug stream is turned on in the DP sink parameter editor. The interface is an Avalon-ST streaming

output that connects to an Avalon-ST FIFO in this design example.

Table 14. DP Sink AUX Debug Interface


rx_aux_debug_data[31:0]

Avalon-ST FIFO

AUX data bytes transmitted or received

rx_aux_debug_valid Qualifies all output signals

rx_aux_debug_sop Start of packet

rx_aux_debug_eop End of packet

rx_aux_debug_err Indicates an error in the current data byte

rx_aux_debug_cha Indicates the direction. 0: bytes received from AUX channel 1: bytes transmitted to AUX channel

Table below lists an Avalon-MM master interface to the on-chip EDID memory. If the Enable GPU

control is turned on in the DP sink parameter editor, this interface is not instantiated and the EDID

memory is accessed via a controller.

Table 15. DP Sink EDID Interface


rx_edid_address[7:0] On-chip EDID memory

Byte address for 256 byte EDID

rx_edid_read Read request

rx_edid_write Write request

rx_edid_writedata[7:0] Write data

rx_edid_readdata[7:0] On-chip EDID Read data


rx_edid_waitrequest memory Asserted when a read or write request needs to wait

Table below lists the DP sink MSA output signals that are bundled in the rx_msa[215:0] port. The rx_msa

port on the DP sink top level allows your design to access MSA and VB-ID parameters. The MSA

parameters are assigned to zero when the sink is not receiving valid video data.

Table 16. DP Sink MSA Interface

rx_msa Bit Signal Description

215 vbid_strobe 0 = VB-ID fields invalid, 1 = VB-ID fields are valid

214:209 vbid_vbid[5:0] VB-ID bit field: vbid[0] - VerticalBlanking_Flag vbid[1] - FieldID_Flag (for progressive video, this remains 0) vbid[2] - Interlace_Flag vbid[3] - NoVideoStream_Flag vbid[4] - AudioMute_Flag vbid[5] - HDCP SYNC DETECT

208:201 vbid_Mvid[7:0] Least significant 8 bits of the time stamp value M for the video stream

200:193 vbid_Maud[7:0] Least significant 8 bits of the time stamp value M for the audio stream

192 msa_Valid 0 = MSA fields are invalid or being updated, 1 = MSA fields are valid

191:168 msa_Mvid[23:0] Timestamp values M and N for the main video stream. Used for stream clock recovery from link symbol clock. 167:144 msa_Nvid[23:0]

143:128 msa_Htotal[15:0] Horizontal total of received video stream in pixel count

127:112 msa_Vtotal[15:0] Vertical total of received video stream in line count

111 msa_HSP Hsync polarity 0 = Active high pulse, 1 = Active low pulse

110:96 msa_HSW[14:0] Hsync width in pixel count

95:80 msa_Hstart[15:0] Horizontal active start from Hsync start in pixel count (Hsync width + Horizontal back porch)

79:64 msa_Vstart[15:0] Vertical active start from Vsync start in line count (Vsync width + Vertical back porch)

63 msa_VSP Vsync polarity 0 = Active high pulse, 1 = Active low pulse

62:48 msa_VSW[14:0] Vsync width in line count

47:32 msa_Hwidth[15:0] Active video width in pixel count

31:16 msa_Vheight[15:0] Active video height in line count

15:8 msa_MISC0[7:0] MISC0[7:1] and MISC1[7] fields indicate the color encoding


format. The color depth info is indicated in MISC0[7:5].

000 - 6 bits per color





For details about the encoding format, refer to DP 1.2

specification. 7:0 msa_MISC1[7:0]

For details about the other interfaces below, refer to the DP Sink Interface section in the DP user guide.

Secondary Stream Interface

Audio interface

Debugging interface

EDID Initialization File

This design example uses ‘edid_memory.hex’ file to initialize the on-chip EDID memory of DP sink. If you

need to edit the EDID content, you can open the .hex file in Quartus II by File > Open > Select ‘Memory

Files (*.mif *.hex)’ in Files of type.

Below is the Quartus II screenshot showing part of the ‘edid_memory.hex’ file.

Figure 9. Viewing EDID Memory Initialization File in Quartus II

Alternatively, you can read the EDID content from a monitor you’re interested in and convert it to

‘edid_memory.hex’ file.


For details about the EDID data format, refer to the VESA E-EDID Standard document.

DP Source

The DP source has the following features:

1, 2, or 4 lane operation

1.62, 2.7, and 5.4 Gbps per lane

16, 18, 20, 24, 30, 32, 36, or 48 bits per pixel color depths

RGB and YCrCb color modes

Embedded controller AUX channel operation

Accepts standard H-sync and V-sync RGB and YCrCb input video formats

Support for OpenCore Plus evaluation

o Allows you to evaluate the IP core before you purchase a license

DP Source Parameters

Figure below is the screenshot of the DP source parameter editor.


Figure 10. DP Source Parameter Editor

Table below describes the DP source parameters.

Table 17. DP Source Parameters

Parameter Description

Device family Targeted device family (Arria V, Arria V GZ, or Stratix V); matches the project device family.

Support DisplayPort source Enable DisplayPort source.

Maximum video input color depth Video input interface port bits per color (bpc). Determines top-level video input port width. 6,8,10,12, or 16 bpc.

TX maximum link rate Maximum link rate. 20 = 5.4 Gbps, 10 = 2.7 Gbps, 6 = 1.62 Gbps.

Maximum lane count Maximum lanes used (1, 2, or 4).


Enable AUX debug stream Send source AUX traffic output to an Avalon-ST port.

Import fixed MSA Used fixed MSA.


Interlaced input video Interlace the input video. Turn on for interlaced, turn off for progressive.

Support secondary data channel Enables secondary data.

Support audio data channel Enables audio packet encoding.

Number of audio data channels Number of audio channels supported.

Support CTS test automation Support CTS test automation.











Scrambler seed value Initial seed for scrambler block. Use 16’hFFFF for normal DP and 16’hFFFE for eDP.

Support analog reconfiguration Enable the analog reconfiguration interface if you are not using an external re-driver solution

Most of the DP source parameters are the same as the DP sink parameters except for the following:

The “Import fixed MSA” parameter enables the DP source to accept a fixed MSA value from an external

port, rather than calculating one from video input data. This feature is useful for embedded systems

that only use known resolutions and synchronous pixel clocks.

The “Support analog reconfiguration” parameter enables analog reconfiguration interface. This is used

to reconfigure the transceiver Vod and pre-emphasis settings. You have to enable this feature if you are

not using an external redriver. This is not enabled in the design example.

DP Source Interfaces

The DP source interface is similar to the DP sink interface. The DP source top level interface types are:

Controller Interface – Avalon-MM slave interface for DP source management

Transceiver Management Interface – Transceiver data rate and analog reconfiguration

Video Interface – Video data and H/V sync information input

AUX Interface – AUX channel and an optional AUX debug interface

Secondary Stream and Audio Interfaces – Secondary stream and audio data input. These interfaces

are enabled in the DP source parameter editor GUI

MSA Interface – MSA inputs for applications that use a known video source

Table below lists the controller interface ports.


Table 18. DP Source Controller Interface


clk Clock source Clock for embedded controller

reset System reset Reset for embedded controller

tx_mgmt_address[8:0] Avalon-MM Interconnect (Nios II processor)

Address bus

tx_mgmt_chipselect Chip select

tx_mgmt_read Read request

tx_mgmt_write Write request

tx_mgmt_writedata[31:0] Write data

tx_mgmt_readdata[31:0]

Avalon-MM Interconnect (Nios II processor)

Read data

tx_mgmt_waitrequest Asserted when DP source is unable to respond to a read or write request

tx_mgmt_irq Interrupt request. DP source asserts IRQ when an HPD event is received and an IRQ generation is enabled.

Table below list the transceiver management interface ports used for the transceiver reconfiguration.

Table 19. DP Source Transceiver Management Interface


xcvr_refclk[1:0] Transceiver PLL Transceiver PLL reference clocks: 162 MHz for RBR, and 270 MHz for HBR and HBR2.

xcvr_mgmt_clk Clock source Transceiver management clock. Typically 100~125 MHz.

tx_serial_data[m-1:0]* Pin Main link serial data output.

tx_link_rate[1:0] Reconfiguration mgmt FSM

TX link rate setting. 00: RBR, 01:HBR, 10:HBR2

tx_reconfig_req TX link rate reconfiguration request.

tx_reconfig_ack Reconfiguration mgmt FSM

TX link rate reconfiguration request is acknowledged.

tx_reconfig_busy TX link rate reconfiguration is in progress.

tx_vod[2m-1:0] Reconfiguration mgmt FSM

Two bit per lane vod setting

tx_emp[2m-1:0] Two bit per lane pre-emphasis setting

tx_analog_reconfig_req Vod and/or pre-emphasis analog reconfiguration request

tx_analog_reconfig_ack Reconfiguration mgmt FSM

Analog reconfiguration request is acknowledged

tx_analog_reconfig_busy Analog reconfiguration request is in progress


reconfig_to_xcvr [m x 70-1:0]*


XCVR reconfiguration signals from the Reconfiguration Controller IP core

reconfig_from_xcvr [m x 46-1:0]*


XCVR reconfiguration signals to the Reconfiguration Controller IP core

* m is the number of TX lanes.

Table below lists the video input interface ports.

Table 20. DP Source Video Interface


tx_vid_clk Video PLL Video/pixel clock input

tx_vid_data[3v - 1:0] VIP suite CVO IP core

Video data input (v is the number of bits per color)

tx_vid_v_sync Vsync input

tx_vid_h_sync Hsync input

tx_vid_f 0: field 0/progressive, 1: field 1

tx_vid_de Video data valid signal. Asserted when an active picture sample of video data is present on tx_vid_data bus

Table below lists the bidirectional AUX channel interface ports.

Table 21. DP Source AUX Channel Interface


aux_clk Clock source AUX clock input. 16MHz.

aux_reset System reset Reset for AUX clock domain

tx_aux_in AUX channel bidirectional buffer

AUX channel serial data input

tx_aux_out AUX channel bidirectional buffer

AUX channel serial data output

tx_aux_oe AUX channel output enable

tx_hpd Pin Hot Plug Detect (HPD) output

Table below lists the AUX debug interface ports.

The AUX debug interface is instantiated if the “Enable AUX debug stream” parameter is turned on in the

DP source parameter editor. The interface is an Avalon-ST streaming output that connects to an Avalon-

ST FIFO in this design example.


Table 22. DP Source AUX Debug Interface


tx_aux_debug_data[31:0]

Avalon-ST FIFO

AUX data bytes transmitted or received

tx_aux_debug_valid Qualifies all output signals

tx_aux_debug_sop Start of packet

tx_aux_debug_eop End of packet

tx_aux_debug_err Indicates an error in the current data byte

tx_aux_debug_cha Indicates the direction 0: bytes received from AUX channel 1: bytes transmitted to AUX channel

Table below lists the MSA signals.

For applications that use a known video source signal, the FPGA resource of video measurement path

can be removed. In this scenario, the DP Source uses the MSA values presented on the tx_msa[191:0]

signal bundle described in the following table.

Table 23. DP Source MSA Interface

tx_msa Bit Signal Description

191:168 Mvid[23:0] Timestamp values M and N for the main video stream

167:144 Nvid[23:0]

143:128 Htotal[15:0] Horizontal total of video stream in pixel count

127:112 Vtotal[15:0] Vertical total of video stream in line count

111 HSP Hsync polarity 0 = Active high pulse, 1 = Active low pulse

110:96 HSW[14:0] Hsync width in pixel count

95:80 Hstart[15:0] Horizontal active start from Hsync start in pixel count (Hsync width + Horizontal back porch)

79:64 Vstart[15:0] Vertical active start from Vsync start in line count (Vsync width + Vertical back porch)

63 VSP Vsync polarity 0 = Active high pulse, 1 = Active low pulse

62:48 VSW[14:0] Vsync width in line count

47:32 Hwidth[15:0] Active video width in pixel count

31:16 Vheight[15:0] Active video height in line count

15:8 MISC0[7:0] MISC0[7:1] and MISC1[7] fields indicate the color encoding

format. The color depth info is indicated in MISC0[7:5].







7:0 MISC1[7:0] For details about the encoding format, refer to DP 1.2

specification.

For the port signals of the secondary stream and audio interfaces, refer to the DP MegaCore user guide.

Video and Image Processing (VIP) Suite IP Cores

The following features are common to all of the VIP Suite IP cores:

Common Avalon Streaming (Avalon-ST) interface and Avalon-ST Video protocol

Avalon Memory-Mapped (Avalon-MM) interfaces for run-time control input and connections to

external memory blocks

IP functional simulation models for use in Altera-supported HDL simulators.

Support for OpenCore Plus evaluation that allows you to evaluate the VIP Suite IP cores in

simulation and in hardware before you purchase a license

The following section describes the Avalon-ST Video Protocol used for video paths of the VIP Suite IP

cores. For details about the Avalon Interfaces, refer to the Avalon Interface Specification document.

Avalon-ST Video Protocol

The Avalon-ST Video protocol is a packet-oriented way to send video and control data over Avalon-ST

connections. The protocol defines the following three pre-defined packet types:

Video data packet – Contains uncompressed video data. Video data is sent per pixel in a raster scan

order

Control data packet – Contains the control data such as the image dimension and interlacing info of

the video data packets that follow. It configures the cores for video data packets

Ancillary (non-video) data packet - Contains ancillary packets from the vertical blanking period of a

video frame

Figure below shows the Avalon-ST interface signals.

Figure 11. Avalon-ST Interface Signals

startofpacket

endofpacketdoutdin

ready

valid

data

startofpacket

endofpacket

ready

valid

data

clock

http://www.altera.com/literature/manual/mnl_avalon_spec.pdf


Table 24. Avalon-ST Interface Signal Description

Signal Width Direction Description

ready 1 Sink to Source

Asserted high to indicate that the sink can accept data. Used to backpressure the source.

valid 1 Source to

Sink Asserted by the source to qualify all other source to sink signals.

startofpacket 1 Source to

Sink Asserted by the source to mark the beginning of a packet.

endofpacket 1 Source to

Sink Asserted by the source to mark the end of a packet.

data bits per color sample X number of color samples transferred in parallel

Source to Sink

Data signal from the source to the sink

Figure below is the Avalon-ST timing diagram showing the video data packet transferring 24 bit RGB

pixel data in parallel.

The frame boundaries are delimited by the startofpacket and endofpacket signals.

Figure 12. Avalon-ST Timing Diagram Showing R'G'B' (8-bpc) Transferred in Parallel


For details about the Avalon-ST Video protocol, refer to the Interface chapter in Video and Image

Processing Suite User Guide.

The following section describes the VIP Suite IP cores used in the design example.

Clocked Video Input

The Clocked Video Input (CVI) MegaCore function receives clocked video data from the DP sink and

converts it to the flow controlled Avalon-ST Video protocol. The MegaCore function strips the incoming

clocked video of horizontal and vertical blanking, leaving only active picture data. Using this data with

the horizontal and vertical synchronization information creates the necessary Avalon-ST Video control

and active picture packets.

The CVI MegaCore function can detect the following different aspects of the incoming video stream:

Picture width (in samples) – Total number of samples per line, and the number of samples in the

active picture

Picture height (in lines) – Total number of lines per frame or field, and the number of lines in the

active picture

Interlaced / Progressive – Detects whether the incoming video is interlaced or progressive

The CVI MegaCore function provides a status interrupt that can be used to determine when the video

format changes or disconnected.

Figure below is the CVI parameter editor.

http://www.altera.com/literature/ug/ug_vip.pdf#performance_performancehttp://www.altera.com/literature/ug/ug_vip.pdf#performance_performance


Figure 13. CVI Parameter Editor

Below is the CVI video input timing diagram.

Figure 14. CVI Timing Diagram with Separate Synchronization Signals

For details about the interface between the CVI MegaCore function and DP Sink, refer to the DP Sink

Video Interface section of the DisplayPort MegaCore function User Guide.


Clocked Video Out

The Clocked Video Output (CVO) MegaCore function receives Avalon-ST Video data and converts it into

clocked video by inserting horizontal and vertical blanking and generating horizontal and vertical

synchronization information. The CVO clocked video output is connected to the DP source in the design

example.

The CVO MegaCore function provides a number of configuration registers that control the format of

video leaving the system (blanking period size, synchronization length, and interlaced or progressive

mode) and a status interrupt that can be used to determine when the video format changes. You can

configure up to 13 video formats via the CVO mode registers if “Use control port” parameter is turned

on.

Figure below is the CVO parameter editor.


Figure 15. CVO Parameter Editor

Frame Buffer

The Frame Buffer MegaCore function stores the video frames into external memory. This design

example uses triple buffering and stores three frames into external memory. The reader and the writer

components are always locking one buffer to respectively store input pixels to memory and read output

pixels from memory. The third frame buffer is a spare buffer that allows the input and the output sides


to swap buffers asynchronously. It handles the frame synchronization between DP sink and source in the

design example.

Mixer

The Mixer MegaCore function receives Avalon-ST Video from the Frame Buffer and mixes the buffered

image with the 1920x1200 background color bars from the Test Patter Generator IP core. The combined

image is then sent to the downstream Clocked Video Output IP core which converts the Avalon-ST Video

to the clocked video format for transmission over the DP source TX link.

Test Pattern Generator

The Test Pattern Generator MegaCore function generates the 1920x1200 background color bars for a

picture-in-picture image display.

Nios II Processor Sub-system

The Nios II processor is a softcore processor with Avalon-MM data and instruction masters. The Nios II

processor acts as a link policy maker in the design example. The software running on the processor

performs the DP source TX link management through the AUX channel. The following peripheral

components are instantiated for the Nios II embedded sub-system.

Table 25. Nios II System Peripheral IP Cores IP Core Function

On-Chip Memory Nios II program memory

Interval Timer Nios II system timer

System ID Unique ID for Nios II embedded system

PIO (Parallel I/O) Parallel I/O for User push-buttons and LEDs.

JTAG UART Allows Host PC and Nios II system communication via USB-

Blaster cable

The design example uses a minimum size Nios II configuration, which doesn’t require a license.


Software Description This design example provides software for DP source and sink instantiations as two C system libraries

(‘btc_dptx_syslib’ and ‘btc_dprx_syslib’, respectively). The design example software includes a sample

main program (‘main.c’ in dp_demo_src directory), which demonstrates basic system library use.

Library Use The main program initializes the system library as its first operation. Next, it initializes the instantiated

DP source. The main program initialize the DP sink only if BITEC_RX_GPUMODE flag is set to 1 in

‘config.h’ file. By default, BITEC_RX_GPUMODE is set to 0. In this step, the Interrupt Service Routines

(ISRs) to handle the DP source and sink IRQs are registered with the Nios II HAL Interrupt API function.

When the initialization is complete, it simply invokes the periodic library monitoring function.

Figure below shows the source and sink application library calls in this design example.

For details of the system library API function calls , refer to DisplayPort API Reference chapter in the DP

User Guide.

Sink and source interrupts can be enabled and disabled by using the following library macros:

BTC_DPTX_ENABLE_IRQ()

BTC_DPTX_DISABLE_IRQ()

BTC_DPRX_ENABLE_IRQ()

BTC_DPRX_DISABLE_IRQ()

Figure below shows the sequence of the DP source and sink library calls in the design example software.

Figure 16. Design Example Library Calls

btc_dptx_syslib_init(..);

BTC_DPTX_ENABLE_IRQ();

btc_dptx_syslib_monitor(..);

btc_dprx_syslib_init(..);

btc_dprx_dpcd_gpu_access(..);btc_dprx_edit_set(..);

BTC_DPRX_ENABLE_IRQ();

btc_dprx_syslib_monitor(..);

Sink application library calls(when BITEC_RX_GPUMODE is set to 1)

Source application library calls


Below is a DP sink ISR implementation in the design example.

Below is a DP source ISR implementation in the design example.

Using the Design Example

Obtaining the Design Example The design examples are available for download from Altera’s wiki website.

Design Example Content After you download the design example and extract the zip file contents, you will have the files defined

in Table 3. In the design example, file names have a prefix; is ‘sv’ for the Stratix V devices, and

‘av’ for the Arria V devices.

Table 26. Files for Design Example

File Type File Description

Verilog HDL

design files

_dp_demo.v Top-level design file for the design example

dp_mif_mappings.v Table translating MIF mappings for transceiver

reconfiguration

dp_analog_mappings.v Table translating VOD and pre-emphasis settings

reconfig_mgmt_hw_ctrl.v Reconfiguration manager top-level

reconfig_mgmt_write.v Reconfiguration manager FSM for a single write

http://www.alterawiki.com/wiki/DisplayPort_Design_Example_(RX_and_TX)


command

MegaWizard

files

_video_pll.v

_xcvr_pll.v

_aux_buffer.v

_xcvr_reconfig.v

IP cores and megafunctions

Qsys System _control.qsys Qsys system file

Scripts runall.tcl Script to run the setup project, generate the IP and

Qsys system, and compile.

assignments.tcl Top-level TCL file to create the project assignments

Miscellaneous _dp_demo.sdc Top-level timing constraint file

Software files

(in the

‘software’

directory)

batch_script.sh Master script to build BSP and application software, and

download the FPGA programming file (.sof) and Nios II

code file (.elf).

rerun.sh Script to program the device, and rerun the software

without rebuilding

dp_demo_src Directory containing the example application source

code

btc_dptx_syslib Directory containing DP source API system library

btc_dprx_syslib Directory containing DP sink API system library

Compiling the Design Example In this step you use a script to build and compile the FPGA design to generate the FPGA programming

file (.sof). Type the command:

quartus_sh -t runall.tcl

This script performs the following steps by executing the listed commands.

The is ‘sv’ for the Stratix V devices, and ‘av’ for the Arria V devices.

Load the required packages:

load_package flow

load_package misc

Regenerate the MegaWizard Plug-In Manager components:


qexec "qmegawiz -silent _video_pll.v"

qexec "qmegawiz -silent _xcvr_pll.v"

qexec "qmegawiz -silent _aux_buffer.v"

qexec "qmegawiz -silent _xcvr_reconfig.v"

Regenerate the Qsys system including the DP source and sink:

qexec "ip-generate --project-directory=./ \

--output-directory=./_control/synthesis/ \

--file-set=QUARTUS_SYNTH \

--report-file=sopcinfo:./_control.sopcinfo \

--report-file=html:./_control.html \

--report-file=qip:./_control/synthesis/_control.qip \

--component-file=./_control.qsys"

Create the project, overwriting any previous settings files:

project_new _dp_demo -overwrite

Add the assignments to the project:

source assignments.tcl

Compile the project:

execute_flow –compile

Clean up by closing the project:

project_close

Hardware Requirements The design was tested on Stratix V GX FPGA Development Kit and Arria V GX FPGA Development Kit with

the Bitec HSMC daughter card. However, the design example can be ported to any platform which has

the required clock sources.

The following is the list of hardware required to view the results:

Altera FPGA Development Kit

Desktop PC with a graphics card supporting DisplayPort and DVI-D outputs

DisplayPort Capable Monitor

Bitec HSMC Daughter Board

Others

- DisplayPort Cables (2)

- DVI-D Cable

- Power Supply for FPGA board

- JTAG Download Cable (USB-Blaster II or USB-Blaster)

http://www/products/devkits/altera/kit-sv-gx-host.htmlhttp://www/products/devkits/altera/kit-arria-v-gx.htmlhttp://www.bitec-dsp.com/hsmc_dp_daughtercard_product_brief.pdf


Hardware Setup Figure below shows the hardware setup. The FPGA board in the figure is the Stratix V GX FPGA

Development Kit.

Figure 17. Hardware Setup to View the Result

Software Requirements The design was tested using Altera Quartus II software v13.0 release.

Build, Load, and Run the Software In this step you build the software, load it into the device, and run the software.

Before you start, unplug DP RX and DP TX cables from the Bitec HSMC board.

1. In a Windows command prompt, navigate to the ‘software’ directory in the design example project

directory

2. Launch a Nios II command shell. You can launch it using several methods, for example, from the

Windows task bar or within the Qsys system. To run this command from the Windows command

prompt, use the command:

start "" %SOPC_KIT_NIOS2%\"Nios II Command Shell.bat"

3. From within the Nios II command shell, execute the following command to build the software,

program the device (.sof file), download the Nios II program (.elf file), and launch a nios2 terminal:

./batch_script.sh , or


./batch_script.sh , if there are multiple USB cables.

To find the USB cable number, type:

jtagconfig

The script also creates the dp_demo, and dp_demo_bsp subdirectories inside the software directory. If

you have already built the software, use the ‘rerun.sh’ script to program the device (.sof), download the

Nios II program (.elf), and launch the terminal:

./rerun.sh

Refer to Chapter 15: Nios II Software Build Tools Reference in the Nios II Software Developer’s

Handbook for a description of the commands used in these scripts.

http://www.altera.com/literature/lit-nio2.jsphttp://www.altera.com/literature/lit-nio2.jsp


Viewing the Results 1. Plug the DP monitor cable into Bitec HSMC board DP TX connector. After successful link training, the

following background color bars are displayed on the DP monitor.

Figure 18. Background Color Bars

2. Plug the host PC graphics card DP cable into Bitec HSMC board DP RX connector. After successful

link training, the host PC desktop image is overlaid on the background color bars as shown below.

Figure 19. Picture-In-Picture

3. Bring up the Control Panel > Display > Adjust Resolution on the host PC and adjust the screen

resolution of the 2nd Display ‘BITECDP01’. Observe the foreground image resolution change on the

DP monitor.


Document Revision History Revision 1.0 Sept 5, 2013 Initial Release

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