VLSI implementation of a 5-trit full adder H.T. Mouftah, B.Sc, M.Sc, Ph.D., Sen.Mem.I.E.E.E., and A.I. Garba, B.Eng. Indexing terms: Integrated circuits, Logic Abstract: The design and implementation of a 5-trit full adder is presented. Only enhancement-type CMOS transistors are used in the circuitry. The CMOS chip layout of the ternary full adder is presented, with the computer simulation results for all the circuits. 1 Introduction Several works have been reported on the realisation of 3- valued logic circuits using CMOS integrated circuits [1-9]. None of these circuits have been integrated using VLSI technology, simply because they either use resistors, which take up too much chip space and are difficult to imple- ment, are of complex design, with large numbers of tran- sistors, or have low performance, with high power consumption and a large delay. Thus, the prime objective here is to avoid using resistors, and to minimise the number of transistors in a design that would lead to lower power consumption and a shorter propagation delay. In this paper a new design methodology of 3-valued logic systems, using all-transistor enhancement-type CMOS circuits, is introduced. The application of this method in the design of basic cells of ternary inverters, cycling gates and T-gates is presented. An all-CMOS 5-trit full adder based on these basic cells is implemented, and its design and chip layout is described in detail. Circuit per- formances, studied using the SPICE 2G computer simula- tion package, are also reported. 2 Design methodology The positive ternary inverter (PTI) and negative ternary inverter (NTI) are the two basic ternary operators consti- tuting the main unit cell in this system. The PTI and NTI functions are defined by x l = i, if x = 0 -x, if x^O (1) where i takes the value of 1 for the PTI and 1 for the NTI operator, assuming that the lower, middle and upper levels are labelled logic 1,0, and 1, respectively. The main idea behind the design of the CMOS PTI and NTI circuits is the change in the geometry of the p- and n-channels of a standard binary inverter. By making one of the channels more resistive than the other (the n-channel for the PTI and the p-channel for the NTI), the output will take one of the upper or lower logic levels when the input is at the intermediate level. The drain/source current I ds in a MOS device is defined by [10] LD Then K L ds D IXE{V 9S -V T ) = R (2) (3) Paper C362G (E10, C2), first received 18th January and in revised form 15th May 1984 The authors are with the Department of Electrical Engineering, Queen's University, Kingston, Canada K7L 3N6 where R = device well resistance (Q) V ds = drain/source voltage (V) V gs = gate/source voltage (V) V T = device threshold voltage (V) L = channel length (/mi) W = channel width (/mi) D = thickness of insulator (/mi) pi = mobility of charge carriers e = permittivity of insulating material From eqn. 3 one can find that Therefore, to make a device more resistive, one has to increase L or decrease W. As design rules and technology set a minimum limit for W, one has to increase L to have a high enough resistance. The design rules followed in the circuit layouts are those of Northern Telecom Ltd. of Ottawa, set for its 'silicon foundry' custom integrated circuits fabrication, as our ternary full adder was to be submitted to this 'silicon foundry' for fabrication. For a standard binary inverter using the Northern Telecom CMOS IB 5 /mi process, the length-to-width ratio Z of the transistors, for minimum allowable dimensions, are given as Z p (p-device) = 5/9 Z n (rc-device) = 5/5 The difference in width of the two transistors is to compen- sate for the difference in carrier (electrons and holes) mobility in the devices. To find out how much one has to increase L, the inverter circuit has been simulated on a computer, using the SPICE 2G simulation package, for different values of L. The length and width values to be used in the chip layout are those that give the best switching speed, tran- sient response and saving in chip area. There is a trade-off between switching speed, transient response and device area. For these reasons, Z p and Z n are selected to be (5/9) and (25/5), respectively, for the PTI, and (25/9) and (5/5), respectively, for the NTI circuit. Fig. 1 shows the schematic diagram of the ternary inverter (PTI or NTI), and the parameters for the MOSFET models used in SPICE are given in Table 1. The simulation results show that both the PTI and NTI have fast transition times and low power consumption. The maximum speed that both PTI and NTI can accept without degrading their performance was found to be 2.5 GHz, while the rise and fall times were found to be 0.7 ns and 0.5 ns, respectively. Furthermore, for both circuits, the total power dissipation was found to be 10" 8 W. Through- out this study no loads have been used at the output of the simulated circuits. 214 IEE PROCEEDINGS, Vol. 131, Pt. G, No. 5, OCTOBER 1984
Transcript
VLSI implementation of a 5-trit full adderH.T. Mouftah, B.Sc, M.Sc, Ph.D., Sen.Mem.I.E.E.E., and A.I. Garba, B.Eng.
Indexing terms: Integrated circuits, Logic
Abstract: The design and implementation of a 5-trit full adder is presented. Only enhancement-type CMOStransistors are used in the circuitry. The CMOS chip layout of the ternary full adder is presented, with thecomputer simulation results for all the circuits.
1 Introduction
Several works have been reported on the realisation of 3-valued logic circuits using CMOS integrated circuits [1-9].None of these circuits have been integrated using VLSItechnology, simply because they either use resistors, whichtake up too much chip space and are difficult to imple-ment, are of complex design, with large numbers of tran-sistors, or have low performance, with high powerconsumption and a large delay. Thus, the prime objectivehere is to avoid using resistors, and to minimise thenumber of transistors in a design that would lead to lowerpower consumption and a shorter propagation delay.
In this paper a new design methodology of 3-valuedlogic systems, using all-transistor enhancement-typeCMOS circuits, is introduced. The application of thismethod in the design of basic cells of ternary inverters,cycling gates and T-gates is presented. An all-CMOS 5-tritfull adder based on these basic cells is implemented, and itsdesign and chip layout is described in detail. Circuit per-formances, studied using the SPICE 2G computer simula-tion package, are also reported.
2 Design methodology
The positive ternary inverter (PTI) and negative ternaryinverter (NTI) are the two basic ternary operators consti-tuting the main unit cell in this system. The PTI and NTIfunctions are defined by
xl =i, if x = 0
-x, if x ^ O (1)
where i takes the value of 1 for the PTI and 1 for the NTIoperator, assuming that the lower, middle and upper levelsare labelled logic 1,0, and 1, respectively.
The main idea behind the design of the CMOS PTI andNTI circuits is the change in the geometry of the p- andn-channels of a standard binary inverter. By making one ofthe channels more resistive than the other (the n-channelfor the PTI and the p-channel for the NTI), the output willtake one of the upper or lower logic levels when the inputis at the intermediate level.
The drain/source current Ids in a MOS device is definedby [10]
LD
Then
KL
ds D
IXE{V9S-VT)= R
(2)
(3)
Paper C362G (E10, C2), first received 18th January and in revised form 15th May1984The authors are with the Department of Electrical Engineering, Queen's University,Kingston, Canada K7L 3N6
whereR = device well resistance (Q)
Vds = drain/source voltage (V)Vgs = gate/source voltage (V)VT = device threshold voltage (V)L = channel length (/mi)
W = channel width (/mi)D = thickness of insulator (/mi)pi = mobility of charge carrierse = permittivity of insulating material
From eqn. 3 one can find that
Therefore, to make a device more resistive, one has toincrease L or decrease W. As design rules and technologyset a minimum limit for W, one has to increase L to have ahigh enough resistance.
The design rules followed in the circuit layouts are thoseof Northern Telecom Ltd. of Ottawa, set for its 'siliconfoundry' custom integrated circuits fabrication, as ourternary full adder was to be submitted to this 'siliconfoundry' for fabrication. For a standard binary inverterusing the Northern Telecom CMOS IB 5 /mi process, thelength-to-width ratio Z of the transistors, for minimumallowable dimensions, are given as
Zp (p-device) = 5/9
Zn (rc-device) = 5/5
The difference in width of the two transistors is to compen-sate for the difference in carrier (electrons and holes)mobility in the devices.
To find out how much one has to increase L, theinverter circuit has been simulated on a computer, usingthe SPICE 2G simulation package, for different values ofL. The length and width values to be used in the chiplayout are those that give the best switching speed, tran-sient response and saving in chip area. There is a trade-offbetween switching speed, transient response and devicearea. For these reasons, Zp and Zn are selected to be (5/9)and (25/5), respectively, for the PTI, and (25/9) and (5/5),respectively, for the NTI circuit.
Fig. 1 shows the schematic diagram of the ternaryinverter (PTI or NTI), and the parameters for theMOSFET models used in SPICE are given in Table 1. Thesimulation results show that both the PTI and NTI havefast transition times and low power consumption. Themaximum speed that both PTI and NTI can acceptwithout degrading their performance was found to be 2.5GHz, while the rise and fall times were found to be 0.7 nsand 0.5 ns, respectively. Furthermore, for both circuits, thetotal power dissipation was found to be 10" 8 W. Through-out this study no loads have been used at the output of thesimulated circuits.
214 IEE PROCEEDINGS, Vol. 131, Pt. G, No. 5, OCTOBER 1984
Fig. 2 shows the static characteristics of the PTI andNTI circuits, while Fig. 3 shows the dynamic character-istics for the same circuits when a triangular signal of 2.5MHz is applied at the input. Circuit layouts for the PTIand NTI circuits are shown in Fig. 4.
3 The ternary 7-gate
The ternary T-gate is used as the main building block inthe design of the ternary full adder described in this paper.The T-gate is defined [11] by
1 ( ; s) — (4)
where i = 1 if s = 1, 2 if s = 0 and 3 if s = 1.The block diagram of the T-gate is shown in Fig. 5a. It
is essentially composed of four inverters and four transmis-sion gates, called 'ternary switches' (TSs). Each TS consistsof one p-channel and one n-channel enhancement-typetransistor. The source of the p-channel is connected to thedrain of the n-channel, and vice versa. A control signal Vc
5.00 (i)
-5.000 60 120 180 240 300 360 420 480 540 600
timens a
)-4.00 -3.00-2.00 -1.00 0 100 200 300 4.00 5.00b
Fig. 2 Static characteristicsa PTI, b NTI
(i) Vin, (ii) Voul
- 5 0 0 - - • • i i
0 60 120 180 240 300 360 420 480 540 600time.ns b
Fig. 3 Dynamic characteristics
a PTI, b NTI(i) Input, (ii) Output
IEE PROCEEDINGS, Vol. 131, Pt. G, No. 5, OCTOBER 1984 215
is required for proper switch operation. This signal directlycontrols the n-channel, and the p-channel is controlled by
JT(x) = xT
device well
J0(x) = MxYAJ^x)1
(6)
(7)
(8)
Fig. 4 Ternary circuit layoutsa PTI, b NTI
1
1
1
1
L
r
j
-a
• 1
A."
V\ (or Fj). Both channels are biased on or off simulta-neously by the control signal Vc. When Vc is equal to thehigh level ( + 5 V), the switch will be on, and when Vc isequal to the low level ( - 5 V), the switch will be off. Thevalues of Vc for the four switches are controlled by thesignals JT and Ju and indirectly by the Jo signal. The JT,Jo and Jj signals are outputs of the JK(x) circuit, whichfunction is defined by [12]
1 if x = K1 if x±K (5)
where K can take the values of 1, 0 or 1.JT(x) is realised by an NTI, and J^x) by a PTI followed
by another PTI (or NTI). However, J0(x) is realised byapplying a logical AND operation to the inverse of boththe Jj and J\ signals. This is implemented by controllingthe two switches TS3 and TS4, connected in series, by theinverse of the JT and Jv signals. Thus, the three JK(x) func-tions realised are based on the following relationships:
216
where A is a logic operator defined by the minimum func-tion, and realised here by the two switches, TS3 and TS4,connected in series.
This T-gate implementation reduces the number oftransistors used in the whole circuit to only 16. Fig. 5bshows the schematic diagram of the T-gate. The value of sdetermines which of the switches will be on and, even-tually, which signal (xt, x2 or x3) will be displayed at theoutput. Simulation results show that the T-gate canoperate at a speed of 2.5 MHz, with a total power dissi-pation of 1.46 nW. The circuit layout of the T-gate isshown in Fig. 5c.
4 The ternary cycling gate
To further reduce the transistor count in the ternary fulladder chip layout, other cells, such as the cycling gate andthe inverse cycling gate, with fewer transistors than theT-gate, have been developed. The ternary cycling gate
IEE PROCEEDINGS, Vol. 131, Pt. G, No. 5, OCTOBER 1984
and inverse cycling gate functions are defined, respectively,by [2]
x' = (x + 1) mod 3 (9)
and
x" = (x - 1) mod 3 (10)
where + means an arithmetic addition and — an arith-metic subtraction.
The cycling gate is composed of three inverters and twoswitches, for a total of 10 enhancement-type MOS tran-sistors, connected as shown in Fig. 6. An NTI is control-ling a switch, TSl5 that has at its input a PTI, and the
inverse of the signal coming from the NTI is controllingthe other switch, TS2, that has its input kept at logic 0.TSj will be on when the input x is at logic 1 or 0, and theoutput x' will take the value_of the PTI output, 1 or 1.respectively. Only when x is 1 is TS2 on while TSj is off,forcing the output to be at logic 0.
By making the input of TS2 in the cycling gate circuit tobe at logic 1, and inserting another PTI (or NTI) at theoutput of the PTI, the circuit of the inverse cycling gate isrealised as shown in Fig. 7. Its operation is very similar tothat of the cycling gate.
5 The ternary full adder
The 1-trit ternary full adder is composed of a sum gener-ation and a carry generation section. The truth table forthe complete ternary full adder is presented in Table 2. Thesymmetric ternary number system is used in the design ofthe full adder. The full-adder sum-generation section iscomposed of two T-gates, two cycling gates and twoinverse cycling gates, connected as shown in Fig. 8.
IEE PROCEEDINGS, Vol. 131, Pt. G, No. 5, OCTOBER 1984 217
Table 2: Truth table for ternary full adder
0
T1
1
1
0
1
0
T
1
1
0
1
0
T
0
T1
1
0
T
0
T1
1
1
0
1
1
0
1
0
0
0
0
0
x\ 1
1
0
T
1
0
0
0
0
0
0
0
T
X \ i
1
0T
0
0
0
0
0
T
0
TT
I
I~LIT
B CFig. 8 1-tritfull adder sum generation block diagram
-5V
Zi
-5V
Fig. 7 Ternary inverse cycling gate
a Block diagramb Schematic diagram
The block diagram of the carry generation section isshown in Fig. 9. It is composed of 4 T-gates and 8 ternaryinverters, four of which are of the 'earthed logic' type [13].The 'earthed' PTI (EPTI) and 'earthed' NTI (ENTI) aredefined by
— fO if x = in if x 9* i (11)
where i can be 1 or 1 and Ex is for the EPTI and £T for theENTI.
The EPTI can be considered as a PTI followed by a'forward diode' operator (FD). The ENTI can be con-sidered to be an NTI followed by a 'reversed diode' oper-ator (RD) [13]. The FD and RD operators are defined by
218 1EE PROCEEDINGS, Vol. 131, Pt. G, No. 5, OCTOBER 1984
•Mr H-fc- H-E- H-lr
Fig. 11 5-tritfull adder circuit layout
t where i can be 1 or 1, K{ represents the FD operator (~i)and Kj the RD operator (r~).
v To keep in mind the main objective of this study, i.e.avoiding the use of resistors in order to make the VLSI
I implementation feasible, the EPTI and ENTI circuits havebeen designed as shown in Fig. 10. One may see from Fig.10a that the EPTI circuit is actually a standard binary
• inverter.
6 Circuit layout
The ternary full adder has been simulated successfully onthe computer, using the SPICE 2G simulation package.Simulation results show that a 1-trit full adder can operateat a speed of 2.5 MHz, with a total power dissipation of5.4 mW. The computer-aided design tool used for the tran-sistor layout is the Quich Caltech Intermediate Form
IEE PROCEEDINGS, Vol. 131, Pt. G, No. 5, OCTOBER 1984 219
(version 2.0). To simplify the layout and make intercon-nections between devices easy, the transistors are madeuniform. Fig. 11 shows the metalisation-layer circuit layoutof the 5-trit full adder.
7 Conclusions
The design and implementation of a 5-trit full adderCMOS chip is presented. Only enhancement-type CMOStransistors are used in all circuitry, so avoiding the use ofresistors. Computer simulation results prove that the per-formance of all circuitry is as good as the binary counter-part. Based on this design technique, a complete ternarymicroprocessor can be implemented.
8 References
1 MOUFTAH, H.T., and JORDAN, I.B.: 'Integrated circuits forternary logic'. Proceedings of international symposium on multi-valued logic, Morgan town, USA, May 1974, pp. 285-302
2 MOUFTAH, H.T., and JORDAN, I.B.: 'Design of ternaryCOS/MOS memory and sequential circuits', IEEE Trans., 1977,C-26, pp. 281-288
3 MOUFTAH, H.T., and JORDAN, I.B.: 'A design technique for anintegrable ternary arithmetic unit', Proceedings of ISMVL-75, Bloom-ington, USA, May 1975, pp. 359-372
4 HUERTAS, J.L., ACHA, J.I., and CARMONA, J.M.: 'Design andimplementation of tristables using CMOS integrated circuits', IEE J.Electron. Circuits & Syst., 1977, 1, (3), pp. 88-94
5 MOUFTAH, H.T.: 'Design and implementation of tristables usingCMOS integrated circuits', ibid., 1978, 2, (2), pp. 61-62
6 MOUFTAH, H.T., and SMITH, K.C.: Three-valued CMOS cyclinggates', Electron. Lett., 1978, 14, pp. 36-37
7 CARMONA, J.M., HUERTAS, J.L., and ACHA, J.I.: 'Realisation ofthree-valued CMOS cycling gates', ibid., 1978, 14, pp. 288-290
8 KOANANTAKOOL, H.T.: 'Implementation of ternary identity cellsusing CMOS integrated circuits', ibid., 1978,14, pp. 462-464
9 MOUFTAH, H.T., and SMITH, K.C.: 'Injected voltage low-powerCMOS for 3-valued logic', IEE Proc. G, Electron. Circuits & Syst.,1982, 129, (6), pp. 270-272
10 MEAD, C, and CONWAY, L.: 'Introduction to VLSI systems'(Addison-Wesley, Reading, Mass., 1980)
11 LEE, C.Y., and CHEN, W.H.: 'Several-valued combinational switch-ing circuits', Trans. Amer. Inst. Elect. Engrs., 1956, 75, pp. 278-283
12 ROSSER, J.B., and TURQUETTE, A.R.: 'Many-valued logics'(North-Holland, Amsterdam, 1952)
13 MOUFTAH, H.T.: 'A study of the implementation of three-valuedlogic', Proceedings of ISMVL-76, Logan, USA, May 1976, pp.123-126
H.T. Mouftah received the B.Sc. degreein electrical engineering, and the M.Sc.degree in computer science, from the Uni-versity of Alexandria, Alexandria, Egypt, in1969 and 1972, respectively, and the Ph.D.degree in electrical engineering from LavalUniversity, Quebec, Canada, in 1975. From1969 to 1972 he was an instructor at theUniversity of Alexandria, a research andteaching assistant at Laval University from1973 to 1975, a postdoctoral Fellow at the
University of Toronto for the academic year 1975-76, and seniordigital systems engineer, and then Chief engineer, at AdaptiveMicroelectronics Ltd., Thornhill, Ontario, from 1976 to 1977.From 1977 to 1979 he worked with the Data System PlanningDepartment at Bell-Northern research, Ottawa, on several pro-jects related to computer communication networks. In 1979 hejoined the Department of Electrical Engineering, Queen's Uni-versity at Kingston, Ontario, Canada, where he is presently anassociate professor. He has been consulted by government andindustry in the areas of computer communications and digitalsystems. He holds a number of patents, and has published a largenumber of technical articles in the areas of computer communica-tions, digital systems and multiple-valued logic.
Ado Isa Garba was born in Kano, Nigeria.He taught mathematics and physics at theGovernment College of Kaduna, Nigeria,in 1971, and from 1972 to 1974 took severalcourses in electrical engineering at theQueen's University of Belfast. Between
I" . 1979 and 1980 he worked as a service engi-
neer for Amapco Sierra Leone Ltd., andreceived his B.Eng. degree with honours
| from Fourah Bay College, Sierra Leone, in1981. Since 1983 he has been carrying out
research in the area of multiple-valued logic design and VLSIimplementation, in the Department of Electrical Engineering atthe Queen's University at Kingston, Canada.
220 IEE PROCEEDINGS, Vol. 131, Pt. G, No. 5, OCTOBER 1984
