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VLSI TestingF lt Si l ti
VLSI TestingF lt Si l tiFault SimulationFault Simulation
Virendra SinghI di I tit t f S iIndian Institute of Science
E0 286: Test & Verification of SoC Design
Jan 27, 2010 E0-286@SERC 1
Lecture - 7
Fault Simulation
Jan 27, 2010 E0-286@SERC 2
Simulation DefinedSimulation DefinedDefinition: Simulation refers to modeling of a design, its function and performance.A software simulator is a computer program; an emulator is a hardware simulator.Simulation is used for design verification:Simulation is used for design verification:
Validate assumptionsVerify logicVerify performance (timing)Verify performance (timing)
Types of simulation:Logic or switch levelTimingCircuitFault
Jan 27, 2010 E0-286@SERC 3
Simulation for VerificationSimulation for Verification
SpecificationSpecification
Synthesis
Design(netlist)
Responseanalysis
Designchanges ( )y g
True-valuesimulation Input stimuliComputed
responses
Jan 27, 2010 E0-286@SERC 4
Modeling LevelsModeling Levels
Circuitdescription
Signalvalues
TimingModelinglevel
Application
Programminglanguage-like HDL
Connectivity of
0, 1
0 1 X
Clockboundary
Zero-delay
Function,behavior, RTL
Logic
Architecturaland functionalverification
LogicConnectivity ofBoolean gates,flip-flops andtransistors
Transistor size
0, 1, Xand Z
0 1
Zero delayunit-delay,multiple-delay
Logic
S it h
Logicverificationand test
LogicTransistor sizeand connectivity,node capacitances
Transistor technology
0, 1and X
Analog
Zero-delay
Fine-grain
Switch
Timing
Logicverification
Timinggydata, connectivity,node capacitances
Tech. Data, active/passive component
gvoltage
Analogvoltage
gtiming
Continuoustime
Timing
Circuit
gverification
Digital timingand analog
Jan 27, 2010 E0-286@SERC 5
passive componentconnectivity
voltage,current
time gcircuitverification
True-Value Simulation Al ith
True-Value Simulation Al ithAlgorithmsAlgorithms
Compiled-code simulationpApplicable to zero-delay combinational logicAlso used for cycle-accurate synchronous sequential circuits for logic verificationgEfficient for highly active circuits, but inefficient for low-activity circuitsHigh-level (e.g., C language) models can be used
Event-driven simulationOnly gates or modules with input events are evaluated (event means a signal change)( g g )Delays can be accurately simulated for timing verificationEfficient for low-activity circuits
Jan 27, 2010 E0-286@SERC 6
Can be extended for fault simulation
Compiled-Code AlgorithmCompiled-Code Algorithm
Step 1: Levelize combinational logic and Step 1: Levelize combinational logic and encode in a compilable programming languageStep 2: Initialize internal state variables (flip-p ( pflops)Step 3: For each input vector
S t i i t i blSet primary input variablesRepeat (until steady-state or max. iterations)
Execute compiled codeExecute compiled codeReport or save computed variables
Jan 27, 2010 E0-286@SERC 7
Event-Driven AlgorithmEvent-Driven AlgorithmScheduledevents
Activitylist
2
2
a =1c =1 0
e =1
g =1
t = 0
1
c = 0 d, e
2
4
2d = 0
f 0
g2
3
d = 1, e = 0 f, g
ack
4b =1 f =04
5
g = 0
Tim
e st
aTime, t0 4 8
g 6
7
f = 1 g
T
Jan 27, 2010 E0-286@SERC 8
8 g = 1
Time Wheel (Circular Stack)Time Wheel (Circular Stack)
t=01
maxCurrenttimepointer Event link-list
2
3
4
56
7
Jan 27, 2010 E0-286@SERC 9
Efficiency of Event-driven Simulator
Efficiency of Event-driven Simulatordriven Simulatordriven Simulator
Simulates events (value changes) onlySimulates events (value changes) onlySpeed up over compiled-code can be ten times or more; in large logic circuits about g g0.1 to 10% gates become active for an input change
Large logicblock without
Steady 0Steady 0
( t) block withoutactivity0 to 1 event
(no event)
Jan 27, 2010 E0-286@SERC 10
Problem and MotivationProblem and Motivation
Fault simulation Problem: GivenA circuitA sequence of test vectorsA fault model
DetermineFault coverage - fraction (or percentage) of modeled faults detected by test vectorsySet of undetected faults
MotivationDetermine test quality and in turn product qualityDetermine test quality and in turn product qualityFind undetected fault targets to improve tests
Jan 27, 2010 E0-286@SERC 11
Fault simulator in a VLSI Design Process
Fault simulator in a VLSI Design ProcessDesign ProcessDesign Process
Verified design VerificationVerified designnetlist
Verificationinput stimuli
Fault simulator Test vectors
Modeledfa lt list
Testcompactor
Remove t t d f lt
Deletevectorsfault list
Test
compactor
Fault
tested faults vectors
Low Testgenerator
Faultcoverage
? Add vectorsLow
Adequate
Jan 27, 2010 E0-286@SERC 12
qStop
Fault Simulation ScenarioFault Simulation Scenario
Circuit model: mixed-levelMostly logic with some switch level for highMostly logic with some switch-level for high-impedance (Z) and bidirectional signalsHigh-level models (memory, etc.) with pin faults
Si l t t l iSignal states: logicTwo (0, 1) or three (0, 1, X) states for purely Boolean logic circuitsFour states (0, 1, X, Z) for sequential MOS circuits
TimingZero delay for combinational and synchronous Zero-delay for combinational and synchronous circuitsMostly unit-delay for circuits with feedback
Jan 27, 2010 E0-286@SERC 13
Fault Simulation ScenarioFault Simulation Scenario
FaultsMostly single stuck-at faultsSometimes stuck-open, transition, and path-delay faults; analog circuit fault simulators are not yet in faults; analog circuit fault simulators are not yet in common useEquivalence fault collapsing of single stuck-at faultsfaultsFault-dropping -- a fault once detected is dropped from consideration as more vectors are simulated; fault-dropping may be suppressed for diagnosisfault dropping may be suppressed for diagnosisFault sampling -- a random sample of faults is simulated when the circuit is large
Jan 27, 2010 E0-286@SERC 14
Fault Simulation AlgorithmsFault Simulation Algorithms
Serial
Parallel
Deductive
Concurrent
Jan 27, 2010 E0-286@SERC 15
Serial AlgorithmSerial AlgorithmAlgorithm: Simulate fault-free circuit and save responses Repeat following steps for each responses. Repeat following steps for each fault in the fault list:
Modify netlist by injecting one faultSimulate modified netlist, vector by vector, comparing responses with saved responsesIf response differs, report fault detection and suspend simulation of remaining vectors
Advantages:Easy to implement; needs only a true-value Easy to implement; needs only a true-value simulator, less memoryMost faults, including analog faults, can be simulated
Jan 27, 2010 E0-286@SERC 16
simulated
Serial AlgorithmSerial Algorithm
Disadvantage: Much repeated computation; CPU time prohibitive for VLSI circuitsCPU time prohibitive for VLSI circuitsAlternative: Simulate many faults together
Test vectors Fault-free circuit
Circuit with fault f1
Comparator f1 detected?
Circuit with fault f2
Comparator f2 detected?
Circuit with fault fn
Comparator fn detected?
Jan 27, 2010 E0-286@SERC 17
Parallel Fault SimulationParallel Fault Simulation
Compiled-code method; best with two-states (0 1)states (0,1)Exploits inherent bit-parallelism of logic operations on computer wordsStorage: one word per line for two-state simulationMulti-pass simulation: Each pass simulates p pw-1 new faults, where w is the machine word lengthSpeed up over serial method ~ w-1Speed up over serial method ~ w-1Not suitable for circuits with timing-critical and non-Boolean logic
Jan 27, 2010 E0-286@SERC 18
Parallel Fault SimulationParallel Fault SimulationBit 0: fault-free circuit
Bit 1: circuit with c s-a-0
1 1 1
Bit 2: circuit with f s-a-1
a
b e
1 1 1
1 1 1 1 0 11 0 1
1 0 1
c s-a-0 detected
c g 0 0 0
1 0 1s-a-0
d f s-a-1 0 0 1
Jan 27, 2010 E0-286@SERC 19
Deductive Fault SimulationDeductive Fault Simulation
One-pass simulationEach line k contains a list L of faults Each line k contains a list Lk of faults detectable on kFollowing true-value simulation of each
t f lt li t f ll t t t li vector, fault lists of all gate output lines are updated using set-theoretic rules, signal values, and gate input fault listsPO fault lists provide detection dataLimitations:
Set-theoretic rules difficult to derive for non-Set theoretic rules difficult to derive for nonBoolean gatesGate delays are difficult to use
Jan 27, 2010 E0-286@SERC 20
Deductive Fault SimulationDeductive Fault Simulation
Notation: Lk is fault list for line k
1 {a } L = L U L U {e0}
Notation: Lk is fault list for line kkn is s-a-n fault on line k
a
b e
1
1 11
{a0}
{b0 , c0}
Le = La U Lc U {e0}= {a0 , b0 , c0 , e0}
c
d f g
0
1{b0}
L = (L Lf ) U {g0}U
{b0 , d0}Lg = (Le Lf ) U {g0}
= {a0 , c0 , e0 , g0}
U
{b0 , d0 , f1}Faults detected by
the input vector
Jan 27, 2010 E0-286@SERC 21
the input vector
Concurrent Fault SimulationConcurrent Fault SimulationEvent-driven simulation of fault-free circuit and only those parts of the faulty circuit that differ in signal states from the fault free circuitsignal states from the fault-free circuit.A list per gate containing copies of the gate from all faulty circuits in which this gate differs. List
felement contains fault ID, gate input and output values and internal states, if any.All events of fault-free and all faulty circuits are yimplicitly simulated.Faults can be simulated in any modeling style or detail supported in true-value simulation (offers detail supported in true value simulation (offers most flexibility.)Faster than other methods, but uses most memory
Jan 27, 2010 E0-286@SERC 22
memory.
Conc. Fault SimulationConc. Fault Simulation
0 1 1 1a0 b0 c0 e0
a 1
11
0
10
10
01
00
1
10
b c e
g
1
0
1
1
11
10
1
d f 0
1 000
001
1 00
000
0
a0 b0 c0 e0
10
011
1 11
1
0 1 0 1 1 1b0 d0
d0 g f1f1
Jan 27, 2010 E0-286@SERC 23
0 1 0 1 1 1 00
1
Thank YouThank YouThank YouThank You
Jan 27, 2010 E0-286@SERC 24