Wafer level packaging development at HT€¦ · Huan Tian Technology Page 1 GSA Tech Forum November...

Huan Tian Technology Page 1 GSA Tech Forum November 2017

Wafer level packaging development at HT

Hong Xie

General Manager

Flip Chip International

Acknowledgement: Dr. Daquan Yu of HTKS and other HT contributors, Jan Vardaman of TechSearch International for the market and technology trends.


Agenda

• Overview of HT/FCI

• Trends of WLP

• HT WLP/3D roadmap

• eSIFO

• 3D WLP

• Summary


Overview of HT technology group

• Ranked #6 among OSAT’s globally by revenue.

• A total of 5 manufacturing sites in US and China.

• Offers a diverse packaging technology portfolio to customers


FCI/HT Offers the broadest bumping technology portfolio


WLP Market Growth

• WLP market: Significant growth over the past 10 years– ~12 billion units in 2007, now ~35 billion units

– Wafer-level packaging device shipments to overtake flip chip tech in 2018 (by The Information Network)

– FO-WLP market will see strong growth in 2019

• Capacity for WLP expanding for 200mm and 300mm– Fain-in 200mm in short supply

– FO-WLP expansion for 300mm

– Capacity expansion in advanced packaging, including bumping, fan-in WLP, FO-WLP continues

FC-CSP Fan-in WLP FO-WLP


WLP Count Increase in Phones

• Apple’s original iPhone contained 2 WLPs

• Apple’s iPhone 7 has 44 WLPs

• One is FO-WLP (TSMC’s InFO)

– Bottom package for the application processor in the package-on-package

– Top package contains memory (side-by-side)

• Additional 43 WLPs on main board plus WLPs in lightening cable, earbud etc.

• Almost all high-end smartphones have WLPs (as many as 15)

iPhone 7 includes WLPs in Lightning charge & sync cable and Lightning-

to-3.5mm audio adapter

iPhone2007

2 WLPs

iPhone 72016

44 WLPs


Changing Assembly Model: Processing at the Wafer Level

• Traditional model:

– Wafer is processed in fab

– Wafer sent to assembly facility for singulation, assembly, and test

• New/emerging model:

– Some wafers stay at the foundry for packaging and assembly

– Some OSATs install wafer processing equipment to create package on the wafer


Bumping technology Trend

HT FC/ Bumping for 16/14nm wafer is in volume production.


HT WLP/3D technology roadmap

2015 2017

Solder bumping

TSV-CIS

Vertical via

TSV-MEMS (SiP)RF MEMS

AA-CIS

mCSP

Copper pillar

CSP-CIS

TSV-MEMS

2016 2018 2019

3D SiP

IC

IC IC

Interposer

μ bump

PCBbump

BSI TSV-CISHigh end BSI -CIS

Accelerometer

Fan-out

High pixel-CIS

3D IC

Fingerprint

Imagesensor

MEMS

Bumping

WLP

2.5/3D

SSP

3D FO

Fingerprint

EBG

FI

Finer LS


embedded Si Fan-Out(eSiFO®)

KGDs embedded in silicon wafer; Micro-scale gap is filled by epoxy; Silicon surface as the FO area. Behaves like a piece of Si vs other

FO technologies

2.4

eWLB

Si substrate

Si fan-out

area

Molding

fan-out

area Molding compound

eSiFO

eSiFO cross section


Production Results

100um etch depth Pick & place accuracy ≤4um

Re-constructed Si wafer with known good die attachment

~2 layer RDL with 15um L/S

BGA with 400um pitch


eSiFO® Product examples

3.3x3.3mm package Reliability test package

Easy and smooth integration of current product to eSIFO WL-FO is a very good platform for SiP for integration of different Si

functions and technologies Lower cost due to its use of reclaimed wafer and existing and

depreciated bumping equipment.

RDL/BGA on 3.9x3.9

package

GaAs + ASIC


Time Samples Results

BAKE 125C 24h 49 Passed

SOAK (L3) 30C/60%RH 192h 49 Passed

Reflow(260C) 3x 49 Passed

THS(8C5/85RH) 1008h 21 Passed

T/C-B(-55C/125C) 1000 cycles 21 Passed

Unbiased AST(110C/85RH) 264h 21 Passed3.9x3.9mm package

Reliability results

BLR test vehicle

Samples (with underfill) passed 1000 cycles of board-level temperature cycles (-40/125℃)

Samples (without underfill) passed 800 cycles (-40/125℃), 3mmx3mm, 150um FO thickness.

More testing is in progress.


An example of using eSIFO for lower product cost

• Current product:

– 2mmx2mm. I/O driven due to bump count and bump pitch for board level assembly

– Die size can be 1.6x1.6mm if chip circuit function driven

– SMT mounted to a regular PCB SiP.

• Proposed eSIFO product:

– Product die size is 1.6mmx1.6mm, decreasing the die area by 36%.

– eSIFO is 2mmx2mm with the existing bump pattern and pitch

• Benefits:

– Product DPW increased by ~36% (depending on the wafer size)

– Significant product cost saving due to the FO wafer cost <<< product wafers

– eSiFO behaves like Si so it is a “drop-in” with the existing WLCSP products.

– Chip design flexibility with eSIFO for signal routing and distribution

Current product Proposed eSIFO product


3D WLP technology examples2.4

Chip (s) embedded into Si carrier High density vertical interconnect can be realized using via last TSVs 3D eSiFO-SiP can be used for many multi-chip applications:

Processor+ memory, sensor+ASIC, MEMS+ASIC

3D eSiFO 3D eSiFO (multi-chip)


T bond & Grind-Back

Litho & Etch

PECVD

Passivation

FC

Dicing & De-bondOxide etch

RDL

BGA

Process flow for 3D eSIFO


Cross-section View of the 3-D WLP2.4

Significant features, # of chips in a very small FF.


3D IC wafer level packaging2.5

Product trends in many markets, phones, medical devices,… continue todemand more and more functions with the same or decreasing volume.

3D WLP is the ideal technology to meet good performance, small formfactor and low cost requirements

TSV is a critical technology component for 3D WLP and via last TSV processis a low cost solution


(a) Forming Bump (b) Polymer & patterning

(C) Hybrid bonding(d) Backside grinding & TSV formation

Si Cu pillar SnAg RDL Dry film IMC Passivation BGA Silicon oxide

3D wafer to wafer bonding 2.5


Results of wafer to wafer Bonding process development

Voids free bonding interface and robust TSV process are the keys forsuccess for low cost 3D IC integration.

50 um interconnect pitch

2.5

No crack

(a) X-ray for hybrid wafer bonding (b) Cross-section of bonding interface

(c) TSV after etching and cleaning (d) Bonding wafer after TSV and PECVD


• Multi chip integration with ~1um width RDLS

• Fan-Out/2.5D interposer/bumping

• RDL for leading technology is 5/5um going to 1/1um

• Bumping for 10nm wafer

• Process, tools and materials

• Wafer level device integration

• Provide Value Add for system

• Complexity for WLP process

• Panel level packaging

• Process/tools/materials/cost/market

Future WLP technology Developments


Summary

• The fast growth of Intelligent Mobile devices, IoT, and wearable

device, brings more challenging requirements for WLP on FF, cost,

performance.

• With the Si node scaling reaching its physical and cost effectiveness

limit, packaging, especially WLP will play more and more important

roles in continuing to scale the semiconductor performance and cost.

• Continued innovation, technology investment are critical to the WLP

technology development: fine pitch bumping/RDL, micro scale

WLCSP, TSV, wafer level SiP using FOWLP, 3D IC.

• Closer collaborations between Si designs, Fab and WLP are critical to

develop the vertically optimized total solutions for the semiconductor

industry.

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