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Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
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WG-DPEC-1.0 (DFOG)WG-DPEC-1.0 (DFOG)
FPGA Firmware Design Do!men"
A!"#or(s)$ 3 4 PRASAD AU.4, PRASADA RA8.S 7anuary *, #015
Re%iewer(s)$ &'A&'A*T + A,T *A'AR
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%hi document cover the detail o irm!are imlemented in +PA on :(DP-6(1.0 2oard.:(DP-6(1.0 2oard act a data ac;uiition and inal rocein unit to achieve cloed loounctionality o +8. %he hae(error data i received throuh the P$N+-% outut o 6<+8 ytem, it idemodulated and ued to enerate hae(error(comenation inal to achieve cloed loo unctionality o the ytem. +PA i ued in interacin !ith variou comonent, erormin diital inal roceinunction and communicatin !ith uer interace.
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APPROVED3DRAFT
:A=-<-% R8UP All Riht Reerved
%he inormation and>or dra!in et orth in thi document and all riht in and to invention dicloed herein and atent !hich may2e ranted thereon dicloin or emloyin the material, method, techni;ue, or aaratu decri2ed herein are the ecluiveroerty o :A=-<-% R8UP.6ontent o the document are u2?ect to chane !ithout rior notice.
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Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
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Con"en"s
1. *TRODUCTO* ....................................................................................................................................... 4
1.1 PURPO&E.................................................................................................................................................. 41.5 &COPE...................................................................................................................................................... 41.6 L&T OF A77REVATO*&............................................................................................................................ 41.8 REFERE*CE&.......................................................................................................................................... 101.9 DOCU,E*T OVERVEW............................................................................................................................ 10
5. GE*ERAL DE&CRPTO* ...................................................................................................................... 11
5.1 PRODUCT PER&PECTVE........................................................................................................................... 11
5.5 E*D U&ER& PER&PECTVE........................................................................................................................ 155.6 A&&U,PTO*& A*D DEPE*DE*CE&..........................................................................................................15
6. DE&G* CO*&TRA*T& ........................................................................................................................ 16
6.1 &OFTWARE CO*&TRA*T&........................................................................................................................ 166.5 'ARDWARE CO*&TRA*T&....................................................................................................................... 16
8. R& A*D &&UE& ................................................................................................................................. 16
9. 'ARDWARE *TERFACE DETAL& ...................................................................................................... 18
9.1 *TERFACE DAGRA,............................................................................................................................... 189.5 CO,,U*CATO* PROTOCOL&..................................................................................................................1:5.#.1 UAR%.................................................................................................................................................. 1)9.6 DATA FOR,AT&....................................................................................................................................... 145.*.1 8++S-% $NAR +8RBA%....................................................................................................................... 195.*.# %:8’S 68BP<-B-N% +8RBA%................................................................................................................#0
;. DE&G* APPROAC' ............................................................................................................................. 51
<. TOP LEVEL DE&G* .............................................................................................................................. 56
<.1 ,A=OR CO,PO*E*T& DE*TFCATO*......................................................................................................58<.5 FU*CTO*& OF ,A=OR CO,PO*E*T&......................................................................................................58C.#.1 6<864 -N-RA%$8N B8DU<-................................................................................................................ #"C.#.# R A%- UPDA%- B8DU<-.......................................................................................................................... #"C.#.* R-+-R-N6- S$NA< R8B....................................................................................................................#"C.#." AD6 DA%A SABP<-R............................................................................................................................. #5C.#.5 D-B8DU<A%$8N BU<%$P<$-R.................................................................................................................. #5
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Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
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C.#. B8=$N A=-RA- +$<%-R...................................................................................................................... #5C.#.C A$N BU<%$P<$-R.................................................................................................................................. #5C.#.) D-AD(AND 68BP-NSA%8R................................................................................................................... #5C.#.9 S%-P(S$E- $N%-RA%8R........................................................................................................................ #5C.#.10 =#P$ 68N%R8< 63A$N......................................................................................................................... #
C.#.11 R ABP S$NA< -N-RA%$8N..................................................................................................................#C.#.1# $AS S$NA< -N-RA%$8N................................................................................................................... #C.#.1* S%-P S$E- A=-RA- B8DU<-.............................................................................................................. #
:. DE&G* DETAL& ................................................................................................................................... 5<
:.1 CLOC GE*ERATO* ,ODULE..................................................................................................................5<).1.1 $NPU% AND 8U%PU% S$NA< D-S6R$P%$8N..............................................................................................#)).1.# 68D- D-S6R$P%$8N.............................................................................................................................. #):.5 RATE UPDATE ,ODULE............................................................................................................................ 68).#.1 $NPU% AND 8U%PU% S$NA< D-S6R$P%$8N...............................................................................................*5).#.# 68D- D-S6R$P%$8N.............................................................................................................................. *5
:.6 REFERE*CE &G*AL RO,....................................................................................................................... 6:).*.1 $NPU% AND 8U%PU% S$NA< D-S6R$P%$8N...............................................................................................*9).*.# 68D- D-S6R$P%$8N.............................................................................................................................. *9:.8 ADC DATA &A,PLER............................................................................................................................... 81).".1 $NPU% AND 8U%PU% S$NA< D-S6R$P%$8N..............................................................................................."#).".# 68D- D-S6R$P%$8N.............................................................................................................................. "#:.9 DE,ODULATO* ,ULTPLER.....................................................................................................................89).5.1 $NPU% AND 8U%PU% S$NA< D-S6R$P%$8N..............................................................................................."5).5.# 68D- D-S6R$P%$8N.............................................................................................................................. ":.; ,OV*G AVERAGE FLTER........................................................................................................................ 8<)..1 $NPU% AND 8U%PU% S$NA< D-S6R$P%$8N..............................................................................................."))..# 68D- D-S6R$P%$8N.............................................................................................................................. "):.< GA* ,ULTPLER..................................................................................................................................... 95).C.1 $NPU% AND 8U%PU% S$NA< D-S6R$P%$8N...............................................................................................5*).C.# 68D- D-S6R$P%$8N.............................................................................................................................. 5*:.: DEAD-7A*D CO,PE*&ATOR.....................................................................................................................98).).1 68D- D-S6R$P%$8N.............................................................................................................................. 5":.4 &TEP-&>E *TEGRATOR........................................................................................................................... 99).9.1 $NPU% AND 8U%PU% S$NA< D-S6R$P%$8N...............................................................................................5).9.# 68D- D-S6R$P%$8N.............................................................................................................................. 5:.10 V5P CO*TROL C'A*............................................................................................................................ 9:).10.1 $NPU% AND 8U%PU% S$NA< D-S6R$P%$8N.............................................................................................59).10.# 68D- D-S6R$P%$8N............................................................................................................................ 59:.11 RA,P &G*AL GE*ERATO*.................................................................................................................... ;8).11.1 $NPU% AND 8U%PU% S$NA< D-S6R$P%$8N.............................................................................................5).11.# 68D- D-S6R$P%$8N............................................................................................................................ ):.15 7A& &G*AL GE*ERATO*..................................................................................................................... <1).1#.1 68D- D-S6R$P%$8N............................................................................................................................ C1:.16 &TEP-&>E AVERAGE ,ODULE................................................................................................................. <1).1*.1 68D- D-S6R$P%$8N............................................................................................................................ C1:.18 PCO7LA>E CO*TROLLER...................................................................................................................... <8).1".1 68D- D-S6R$P%$8N............................................................................................................................ C5:.19 7UCET 7RGADE FFO......................................................................................................................... <:).15.1 AS$6 +$+8 B8DU<-.......................................................................................................................... C)
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Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
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).15.# D-S6R$P%$8N 8+ +$+8 P8R%S............................................................................................................ C9).15.* +$+8 U++-R S$E$N.......................................................................................................................... )0).15." 68NS%RU6%$N ")F9 +$+8 US$N %3R-- 1F9 +$+8S&......................................................................)1:.1; UART TRA*&,TTER ? RECEVER..........................................................................................................:5).1.1 UAR% %RANSB$%%-R :$%3 1F9 U++-R............................................................................................)*
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4. ,E,OR@ ,A*AGE,E*T ..................................................................................................................... 41
10. T,*G A*D &EUE*CE DAGRA,& ................................................................................................ 45
10.1 T,*G C'ARACTER&TC& OF PCO7LA>E *PUT& A*D OUTPUT& WT' READ A*D WRTE &TRO7E&............4510.5 T,*G C'ARACTER&TC& OF UART TRA*&,TTER A*D RECEVER.........................................................4510.#.1 %$B$N 63ARA6%-R$S%$6S 8+ UAR% %F :3-N U++-R $S N8% +U<<......................................................9#10.#.# %$B$N 63ARA6%-R$S%$6S 8+ UAR% %F :3-N U++-R $S +U<<.............................................................9*
10.#.* %$B$N 63ARA6%-R$S%$6S 8+ UAR% RF :$%3 DA%A PR-S-N%...............................................................9*10.#." %$B$N 63ARA6%-R$S%$6S 8+ UAR% RF :3-N U++-R $S +U<<............................................................9*10.6 T,*G C'ARACTER&TC& OF ADC........................................................................................................4810.8 T,*G C'ARACTER&TC& OF DAC........................................................................................................48
11. DATA FLOW DAGRA, ........................................................................................................................ 49
15. REURE,E*T ,APP*G .................................................................................................................. 4;
16. APPE*DB ............................................................................................................................................ 4<
16.1 PCO7LA>E PROCE&&OR$....................................................................................................................... 4<1*.1.1 +-A%UR-S 8+ P$68<AE- PR86-SS8R&...............................................................................................9C1*.1.# P$68<AE- AND $%S PR8RAB R8B $N%-R+A6-&.................................................................................9C1*.1.* 46PSB* > P$68<AE- AR63$%-6%UR-&...............................................................................................9)1*.1." P$68<AE- B$6R868N%R8<<-R +UN6%$8NA< <864S&........................................................................9)1*.1.5 P$68<AE- $N%-R+A6- 68NN-6%$8NS................................................................................................1001*.1. P$68<AE- $N%-R+A6- S$NA< D-S6R$P%$8NS...................................................................................1011*.1.C P$68<AE- > 46PSB* $NS%RU6%$8N S-%.........................................................................................1011*.1.) %$B$N D$ARAB 8+ R-AD AND :R$%- S%R8-S...............................................................................10*1*.1.9 ASS-B<-R $NPU% G 8U%PU% +$<-S...................................................................................................10*16.5 EBTE*DED &CRATC' PAD PCO7LA>E$ (59; 7@TE &CRATC' PAD ,E,OR@)............................................10816.6 DEVCE UTL>ATO* OF FPGA (BC5V590-8C&188)............................................................................10<16.8 FPGA P* UTL>ATO*........................................................................................................................10:
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Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
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Lis" o ig!res+iure 1& locH diaram o ytem............................................................................................................... 11+iure #& Diaram ho!in all the interace o +PA on :(DP-6(1.0 2oard.........................................1"+iure *& +PA 2aed inal rocein....................................................................................................#1
+iure "& 6omonent identiication..............................................................................................................#*+iure 5& locH diaram o 6locH eneration module..................................................................................#C+iure & "B3@, #B3@ 6locH eneration lo!.............................................................................................*0+iure C& #0043@, 10043@ clocH eneration lo!.......................................................................................*#+iure )& locH diaram o Rate udate module.........................................................................................*"+iure 9& clH5003@ eneration lo!............................................................................................................ *+iure 10& locH diaram o Reerence inal R8B...................................................................................*)+iure 11& locH diaram o AD6 data amler..........................................................................................."1+iure 1#& AD6 Samle relacement loic lo!.........................................................................................."*+iure 1*& locH diaram o Demodulation multilier.................................................................................."5+iure 1"& locH diaram o movin averae ilter......................................................................................"C+iure 15& Synchronou +$+8 2aed +$R ilter dein lo!........................................................................."9+iure 1& locH diaram o ain multilier.................................................................................................5#
+iure 1C& locH diaram o Ste(i@e interator.........................................................................................55+iure 1)& locH diaram o =#i control chain...........................................................................................5)+iure 19& Alorithm or =#i error correction..............................................................................................0+iure #0& locH diaram o Ram(inal eneration module....................................................................."+iure #1& Alorithm or Ram inal eneration........................................................................................+iure ##& Pielined imlementation o ram inal eneration..................................................................C+iure #*& <864 D$ARAB o P$68<AE- imlementation 8+ UAR%...................................................C"+iure #"& 1 dee )(2it +$+8..................................................................................................................... C)+iure #5& :ater %anH Bodel o ucHet riade +$+8................................................................................)0+iure #& ")9 +$+8 uin three 1) +$+8 module...............................................................................)1+iure #C& UAR% tranmitter macro............................................................................................................. )*+iure #)& Architecture o UAR% tranmitter macro.....................................................................................)*+iure #9& %imin characteritic o UAR% % !hen 2uer i not ull...........................................................)5
+iure *0& %imin characteritic o UAR% % !hen 2uer i ull.................................................................)5+iure *1& UAR% receiver macro.................................................................................................................)+iure *#& Architecture o UAR% receiver macro.........................................................................................)+iure **& %imin characteritic o UAR% R !ith data reent.................................................................))+iure *"& %imin characteritic o UAR% R !hen 2uer i ull................................................................))+iure *5& Bater lave communication cheme........................................................................................)9+iure *& Accein Pico2la@e $nut and 8utut.......................................................................................9#+iure *C& %imin characteritic o UAR% % !hen 2uer i not ull...........................................................9#+iure *)& %imin characteritic o UAR% % !hen 2uer i ull.................................................................9*+iure *9& %imin characteritic o UAR% R !ith data reent.................................................................9*+iure "0& %imin characteritic o UAR% R !hen 2uer i ull................................................................9*+iure "1& AD6 data read timin................................................................................................................. 9"+iure "#& DA6 timin................................................................................................................................. 9"
+iure "*& Data lo! diaram...................................................................................................................... 95
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Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
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%a2le "& $nut and 8utut inal o 6locH eneration module....................................................................#)%a2le 5& $nut and 8utut inal o Rate(udate module...........................................................................*5%a2le & $nut and outut inal o Reerence inal R8B........................................................................ *9%a2le C& $nut and outut inal o AD6 data amler..............................................................................."#%a2le )& $nut and outut inal o Demodulation multilier....................................................................... "5%a2le 9& $nut and outut inal o Bovin averae ilter........................................................................... ")%a2le 10& $nut and outut inal o ain multilier................................................................................... 5*%a2le 11& $nut and outut inal o Ste(i@e interator........................................................................... 5%a2le 1#& $nut and outut inal o =#i control chain..............................................................................59%a2le 1*& $nut and 8utut inal o Ram(eneration module................................................................. 5%a2le 1"& +PA Bemory utili@ation.............................................................................................................91%a2le 15& Re;uirement main.................................................................................................................. 9%a2le 1& +PA reource utili@ation..........................................................................................................10C
%a2le 1C& +PA Pin detail........................................................................................................................ 109
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1.1 n"ro!"ion
1.1.1 P!rose
%hi document cover the detail o irm!are dein imlemented in =irte($$ +PA o :(DP-6(1.02oard !hich i ued in Diital 6loed <oo +i2er 8tic yro ytem.
1.1.5 &oe
%he coe o thi document cover the dein and develoment eort involved in +irm!are or 6loed<oo D+8. $t cover the ollo!in oint aociated !ith the intended ytem, Product erective,unctional decrition, end uer’ erective, roduct unction and eciication. $t then detail deincontraint and aumtion and deendencie.
1.1.6 Lis" o a//re%ia"ions
A66 Accelerometer AD6 Analo to Diital Converter
RAB 7locH Random Acce ,emory6< Coniura2le Loic 7locH6<+8 Cloed Loo Fi2er Otic GyroDA6 Diital to Analo Converter D6B Diital ClocH ,anaer D+8 Diital aroach Fi2er Otic GyroDP-6 Diital Phae Etimator CardDSP Diital &inal Proceor D=A Diitally controlled Varia2le Gain Amliier +DD Firm!are Dein Document++ Fli Flo+$+8 Firt n Firt Out+8 Fi2er Otic Gyro
+PA Field Proramma2le Gate Array$$6 J$#6K nter nterated(circuit Communication$N nut7%A =oint Tet Action Grou<U% LooH U Ta2le<=DS Lo! Voltae Dierential &inalNA *ot Alica2le8U% OututP6 Peronal Comuter P$N+-%RAB Random Acce ,emoryR8B Read Only ,emoryR6$ Reearch Centre marat
S<D &uer Luminecent DiodeSP$ &erial Periheral nteraceSRS &eciication Re;uirement &heet%D To 7e DicuedUAR% Univeral Aynchronou Receiver Tranmitter =3D< Very 3ih Seed $nterated 6ircuit 'ard!are Decritive Lanuae: Wavelet Grou
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1.1.8 Reerenes
• :(DP-6(1.0 SRS Document
• %echnical eciication manual o =$R%-F($$ +PA rom Filin
• Data heet o on(2oard comonent liHe AD6 JADS)"##K, DA6 J<%61)K
• Schematic o :(DP-6(1.0
• %echnical reerence aer rom R6$
1.1.9 Do!men" O%er%iew
:(DP-6(1.0 +PA +irm!are Dein Document cover the ollo!in
• Aumtion and deendencie
• +irm!are dein contraint
• %echnical eciication
• Dein decrition
• $mlementation detail
• -ternal, internal and uer interace
• Bemory Bain
FPGA Firmware Design Do!men"
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
Aroved y&
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6reated on& 7anuary #0, #010
1.5 Genera Desri"ion
1.5.1 Pro!" erse"i%e
:(DP-6(1.0 2oard act a data ac;uiition and inal rocein unit to achieve cloed loounctionality o +8. %hi !ill 2e ued or rotation rate comutation uin +8 a a enor.+8 !orH on the rincile o Sanac hae hit. %he outut o the +8 i characteri@ed 2y the e;uation&
@(") 1 os (R(") 7(")):here JtK i outut in term o Sanac hae hit in radian,
RJtK i rate o rotation in rad>ecJtK i 2iain inal
6<+8 i 2iaed !ith ;uare !ave inal o eriod e;ual to tranit time o the i2er(coil.%he P$N+-% convert otical o!er, !hich i outut o +8 to electrical inal. %hi outut i ;uare !avemodulated co(inuoidal inal.%he modulated Sanac Phae hit data i received throuh P$N+-% outut o 6<+8.8n(2oard 1(2it AD6 !ill receive the data rom P$N+-% and !ill 2e roceed to enerate the eed2acHinal or the hae modulator i iven throuh 1(2it DA6. %hi eed 2acH inal rereent hae(error(
comenation inal to achieve cloed loo unctionality o the ytem.+PA i ued in interacin !ith variou comonent, erormin diital inal rocein unction andcommunicatin !ith uer interace.
%he +PA irm!are mainly conit o ollo!in three ection&1K 6ontrol and clocH inal eneration#K Alorithm imlementation*K 6ommunication !ith eternal !orld JPreently UAR%K
+iure 1& locH diaram o ytem
WG-DPEC-1.0
Fiber
Optic
Gyroscope
HOST
FPGA Firmware Design Do!men"
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
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1.5.5 En !sers erse"i%e
1.5.6 Ass!m"ions an eenenies
Nil
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
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1.6 Design ons"rain"s
1.6.1 &o"ware ons"rain"s
• %he in ainment hould 2e accordin to the chematic and roer $8 tandard hould 2e et.
• :herever oi2le the loic !ill maHe ue o in 2uilt eature o +PA uch a 2locH RAB, D6B,
macro contructed !ith +PA rimitive etc
1.6.5 'arware ons"rain"s
• 6locH hould not contain litche.
• =oltae level at $>8 hould match !ith the interace.
• Po!er uly hould 2e rile ree.
1.8 Ris an ss!es
Nil
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
Aroved y&
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6reated on& 7anuary #0, #010
1.9 'arware in"erae e"ais
1.9.1 n"erae iagram
+iure #& Diaram ho!in all the interace o +PA on :(DP-6(1.0 2oard
&.*o Por" name Dire"ion Te ? wi"# Desri"ion
1 6<4 $N S%DL<8$6 50 B3@ clocH rom thecrytal ocillator
# UAR%L6<4 $N S%DL<8$6 1.)"*# B3@ clocH rom thecrytal ocillator
* R-S-%L%8PLN $N S%DL<8$6 3ard!are Reet to +PA
" AD6LDA%A $N S%DL<8$6L=-6%8RJ15D8:N%8 0K
1(2it data inut rom AD6
5 AD6LR-S-% 8U% S%DL<8$6 Reet control to AD6
AD6L6S 8U% S%DL<8$6 6hi(elect control to AD6
C AD6LUS $N S%DL<8$6 uy(tatu inut rom AD6
) AD6LPD# 8U% S%DL<8$6 Po!er(Do!n control to AD6
9 AD6LRD 8U% S%DL<8$6 Synchroni@ation ule to AD6 or arallel outut
10 AD6L68N=S% 8U% S%DL<8$6 6onvert(tart control to AD6
11 %DL%8P 8U% S%DL<8$6 %ranmit to RS#*# UAR% $61# RDL%8P $N S%DL<8$6 Receive rom RS#*# UAR%$6
1* %-S%1 8U% S%DL<8$6 8n(2oard tet oint
1" %-S%# 8U% S%DL<8$6 8n(2oard tet oint
15 DA61L6<4 8U% S%DL<8$6 6locH inal to DA61
1 DA%AL%8LDA61 8U% S%DL<8$6L=-6%8RJ15D8:N%8 0K
1(2it data to DA61
1C DA6#L6<4 8U% S%DL<8$6 6locH inal to DA6#
1) DA%AL%8LDA6# 8U% S%DL<8$6L=-6%8RJ15D8:N%8 0K
1(2it data to DA6#
FPGA Firmware Design Do!men"
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AD6JADS)"##K
FPGA(BC5V590-8C&188)
6rytal8cillator50 B3@
6rytal8cillator
1.)"*# B3@
JF6+0"SK6oniuration+lah>7%A
$nterace
Reetcircuit
DA61J<%61)K
DA6#J<%61)K
RS#*#>"##interace
JBAF*1#K
%em(eratureSenor
<=DS
Po!erSuly
$nterace to A66 2oard
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
Aroved y&
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6reated on& 7anuary #0, #010
%a2le 1& +PA $nut>8utut inal connection
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
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6reated on& 7anuary #0, #010
%he ollo!in =3D< code o +PA eciie the eternal inut G outut connection
-N%$% DP-6L%8P $S-N-R$6J
ilterLdeth & S%DL<8$6L=-6%8RJ1* D8:N%8 0K &M 11111001111111O=#iL6trlL+ioLdeth & S%DL<8$6L=-6%8RJ" D8:N%8 0K &M 10100
KO
P8R%J((((((((((( 6<4 G RS%LN (((((((((((
6<4 & $N S%DL<8$6OR-S-%L%8PLN & $N S%DL<8$6OUAR%L6<4 & $N S%DL<8$6O (( 1.)"*# B3@ 8c clH
(((((((((((((( AD6 (((((((((((((((( AD6LDA%A & $N S%DL<8$6L=-6%8RJ15 D8:N%8 0KO
AD6LR-S-% & 8U% S%DL<8$6O AD6L6S & 8U% S%DL<8$6O AD6LUS & $N S%DL<8$6O AD6LPD# & 8U% S%DL<8$6O AD6LRD & 8U% S%DL<8$6O AD6L68N=S% & 8U% S%DL<8$6O
((((((((((((( UAR% ((((((((((((((((%DL%8P & 8U% S%DL<8$6ORDL%8P & $N S%DL<8$6O
(((((((((( %et Point ((((((((((((%-S%1 & 8U% S%DL<8$6O (( %-S% <-D1
%-S%# & 8U% S%DL<8$6O (( %-S% <-D#
((((((((((((( DA6 (((((((((((((((((DA61L6<4 & 8U% S%DL<8$6ODA%AL%8LDA61 & 8U% S%DL<8$6L=-6%8RJ15 D8:N%8 0KO
DA6#L6<4 & 8U% S%DL<8$6ODA%AL%8LDA6# & 8U% S%DL<8$6L=-6%8RJ15 D8:N%8 0K
KO-ND DP-6L%8PO
FPGA Firmware Design Do!men"
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
Aroved y&
Preared 2y& 3 4 Praad a2u.4,Praada Rao.S, Amit Nahar
6reated on& 7anuary #0, #010
Desri"ion&
AD6 interace&1(2it arallel data received rom AD6. %hi data rereent the yro hae error. 6locH and reet to AD6i driven 2y +PA. Data read ynchroni@ation control i driven 2y +PA.
DA61 interace&1(2it arallel data outut rom +PA to DA6. %hi data rereent the hae error comenatin inal.6locH inal to DA6 i driven 2y +PA.
DA6# interace&1(2it arallel data outut rom +PA to DA6. %hi data rereent the 2ia ;uare !ave inal.6locH inal to DA6 i driven 2y +PA
RS#*#>RS"## interace&6ommunication !ith P6 alication ot!are i imlemented on UAR%. +PA actin a Bater o communication traner the deired data to P6. 6oniuration arameter rom P6 are received on theerial line.
6rytal 8cillator&50B3@ and 1.)"*#B3@ ocillator uly clocH inut to +PA. %hee mater clocH are ued urther toderive internal clocH ued in inal rocein 2y +PA eature.
6oniuration lah interace&8n(2oard Filin latorm erial lah i ued to coniure the +PA ater every o!er(on.
%emerature enor interace&$#6 2aed readin o temerature data J2oth 8n(2oard enor and other connectorK.
A66 2oard interace&SP$ 2aed data traner 2et!een :(DP-6(1.0 2oard and :(+8A66(#.0.
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
Aroved y&
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6reated on& 7anuary #0, #010
1.9.5 Comm!nia"ion ro"oos
1.9.5.1 UART
%he UAR% tranmitter>receiver macro i rovided 2y Filin. %hi i havin the ollo!incharacteritic&
1. 1 tart 2it#. ) data 2it*. 1 arity 2it". 1 to 2it.%hi macro alo contain a 1 2yte +$+8. %he +$+8 i@e can alo etenda2le 2y cacadin more
2ucHet 2riade +$+8.
An aynchronou tranmitter G receiver mean tranmitter G receiver are not [email protected]!ever they do 2oth utili@e a timin reerence !hich i o a uita2le tolerance to allo! the erial traner
o each 2yte o data.%he data tranmitted erially <S irt at a iven 2it rate JAUD rateK !hich i Hno!n 2y the
tranmitter and receiver. Since the tranmitter can tart endin data at any time, the receiver need amethod o identiyin !hen the irt J<SK i 2ein ent. %hi i achieved 2y the tranmitter endin anactive lo! tart inal or the duration o one 2it.
%he receiver ue the allin ede o the tart 2it to 2ein an internal timin circuit. %hi timin ithen ued to amle the value o the erial inut at a oint !hich i aroimately at the mid(oint o eachdata 2it. %hi i !here the data hould 2e mot ta2le. Ater the PAR$% 2it ha 2een amled, the receiver
checH to ee i the tranmitted to nit JhihK i the value eected !hich hel conirm correct oeration.
Since the receiver re(ynchroni@e Jtart the internal timin circuitK to the allin ede o eachtart 2it, the timin o the tranmitter and receiver only need to 2e the ame to a tolerance o a 2it eriodin every 10 2it eriod. %hi 5Q accuracy i really no iue to achieve in any diital ytem.
$n common !ith many UAR% olution, thee macro eect that a timin reerence 2e rovided in
the orm o an ena2le inal J‘enL1LL2aud’K, !hich i alied at 1 time the 2it rate.
%he normal tatu o UAR% erial line i active 3$3. $n thi !ay a ne! tart 2it i identiied 2y itallin ede.
FPGA Firmware Design Do!men"
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
Aroved y&
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6reated on& 7anuary #0, #010
1.9.6.5 Twos omemen" orma"
%he t!oI comlement o a 2inary num2er i deined a the value o2tained 2y u2tractin the num2er roma lare o!er o t!o Jeciically, rom # N or an N (2it t!oI comlementK. %he t!oI comlement o thenum2er then 2ehave liHe the neative o the oriinal num2er in mot arithmetic, and it can coeit !ithoitive num2er in a natural !ay. A t!oI(comlement ytem or t!oI(comlement arithmetic i a ytem in !hich neative num2er arerereented 2y the t!oI comlement o the a2olute valueO thi ytem i the mot common method o rereentin ined inteer on comuter. $n uch a ytem, a num2er i neated Jconverted romoitive to neative or vice veraK 2y comutin it t!oI comlement. An N(2it t!oI(comlement numeralytem can rereent every inteer in the rane #N1 to '#N11.%he t!oI(comlement ytem ha the advantae o not re;uirin that the addition and u2traction circuitryeamine the in o the oerand to determine !hether to add or u2tract. %hi roerty maHe theytem 2oth imler to imlement and caa2le o eaily handlin hiher reciion arithmetic. Alo, @eroha only a inle rereentation, o2viatin the u2tletie aociated !ith neative @ero, !hich eit in
oneI(comlement ytem.
TwoHs omemen" Deima
0111 C
0110
0101 5
0100 "
0011 *
0010 #
0001 1
0000 0
1111 11110 #
1101 *
1100 "
1011 5
1010
1001 C
1000 )
%a2le *& %!oI comlement uin a "(2it inteer
FPGA Firmware Design Do!men"
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
Aroved y&
Preared 2y& 3 4 Praad a2u.4,Praada Rao.S, Amit Nahar
6reated on& 7anuary #0, #010
1.; Design Aroa#
+iure *& +PA 2aed inal rocein
FPGA Firmware Design Do!men"
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Di%ie / #15 wi"# /i" see"ion("&15) "o re!e
"#e gain
Gain,!"iier
(&ign eI"ene "o 65 /i")Di%ie / 1; wi"# /i" see"ion (54$8) "o re!e
"#e gain
")
(&ign eI"ene)
Gain romUART
*#
CJ5,CJ5,
1
+$+8 o deth‘N’ amleNM1000
*0
(&ign eI"ene)
(&ign eI"ene)
*0
CJ5,
REG
*0
(&ign eI"ene)
*0
1
CJ5,
ADC Da"a(5s omemen" orma")
CJ5,
F1
REG
50I1;
RO,
+ied 8etrom UAR%*#
Dead2and 6omentaion Amlitude rom UAR%
-ected to 2e !ith in *# 2itrane
*#
&K!are wa%e$ 90 !" e anrogramma/e erio an ami"!e
or DEAD7A*D omensa"ion
Uer T#res#o
*#
*#
*#
RamGenera"or
*#
*#
Lower T#res#o
+ied Ste(i@erom UAR%
*#
BS
REG
ToDAC
1
C500 C500 *#
(&ign eI"ene)
(&ign eI"ene)
C500
**
REG
,UB
**
**
**
**
**
Ste(i@e electionrom UAR%
1
Uer 1;
/i"s(Di%ie/ 5M1;
"oeI"ra"1; /i")(61$1;)
REG
"C
(65$0)
C500
"C
#m uleJAync(6<-ARK
65 /i" Da"a "oPC o%er Uar"
(Di%ie / 5M4
as a!m!a"e800 "imes) (80$4)
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
Aroved y&
Preared 2y& 3 4 Praad a2u.4,Praada Rao.S, Amit Nahar
6reated on& 7anuary #0, #010
%he a2ove diaram i the rooed aroach to enerate the eed 2acH inal or comenatin thehae error o 6<+8 ytem.
%he rate data comin rom AD6 J1 2itK i demodulated and aed throuh +$R ilter. %he reult imultilied !ith ain actor Jreceived throuh UAR%K. %he multilier outut i interated !ith the tranit timereerence to enerate inal te i@e, !hich !ill 2e ued or eneration o ram. %hi ram inal and the2iain inal J;uare !ave o 100 43@ and eaH to eaH amlitude o i># voltK are ued a controlinal or 6<+8.
• ADC wi igi"iNe P*FET o!"!" wi"# saming reK!en o 5 ,'N gi%ing 50
sames er e.
• FR i"er (* sames a!m!a"or+ w#ere * is m!"ie o 50) is imemen"e
asY(n) = Y(n-1) + x(n) –x(n-N)
&o+ FFO is !se "o s"ore as" * sames an s!/seK!en" re"rie%e ea# o"#ose a"er * es.
* 1;000 or !rren" imemen"a"ion
• Dieren" FreK!enies genera"e insie FPGA
Crs"a Osia"or reK!en$ 90 ,'NDC, (Digi"a Co ,anager) o!"!" reK!en$
((9050) 3 59) 80 ,'NDACJCL 500 'N+ADCJCL 5 ,'N+F&&JUPDATE 500 'NFUART 1.:8 ,'N
FPGA Firmware Design Do!men"
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
Aroved y&
Preared 2y& 3 4 Praad a2u.4,Praada Rao.S, Amit Nahar
6reated on& 7anuary #0, #010
1.< To e%e esign
+iure "& 6omonent identiication
6locH eneration module
Data amlin clocH Uart clocH%ranit clocH
6locH eneration module
Data amlin clocH Uart clocH%ranit clocH
FPGA Firmware Design Do!men"
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Pae 1 o *
Demodulator
multilier
Raminalenera
tor
iainal
enerator
AD6Data
Reerence
S;uare:ave
Bovin Accumulation+ilter
ainBultili
er
Dead(2and
comenator
Rateintera
tor
<ooain
Dead(2and6omenation
Amlitude
Datato
DA6(#
Datato
DA6(1
Rateudatemodule
GUAR%
P$68(<AE-
PeaH(eaH
amlitude
DatatoP6
7/26/2019 WG-DPEC-1.0_FDD(DFOG)
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
Aroved y&
Preared 2y& 3 4 Praad a2u.4,Praada Rao.S, Amit Nahar
6reated on& 7anuary #0, #010
1.<.1 ,a2or omonen"s ien"iia"ion
%he ma?or comonent in the +PA dein are,1. 6locH eneration module,#. Rate udate module,*. Reerence inal R8B,". AD6 Data amler,5. Demodulation Bultilier,. Bovin Averae ilter,C. ain multilier,). Dead(2and comenator,9. Ste(i@e JrateK interator,10. =#i control chain,11. Ram inal eneration,1#. ia inal eneration,
1*. Ste(i@e averae module,1". Pico(2la@e controller,15. UAR% Receiver controller,1. UAR% %ranmitter controller G1C. $nterated to module.
1.<.5 F!n"ions o ,a2or Comonen"s
1.<.5.1 Co genera"ion mo!e
%hi dein module ulie the neceary clocH inal to all other dein module. $nut to thi module
i the clocH inal rom the 6rytal 8cillator. Uin +PA reource liHe D6B and ome mod(counter loicneceary clocH inal are derived.
1.<.5.5 Ra"e !a"e mo!e
%hi dein module enerate timin control inal ued to uload data to P6. aed on the timincontrol inal enerated, te(i@e data i averaed. $n the current dein, #m averaed data i ent toP6 uin thee control inal. 8ne o thee control inal i ued to enerate the comenation ;uare!ave inal ued in Dead(2and comenation.
1.<.5.6 Reerene signa RO,
%hi dein module enerate reerence inal ued or demodulatin data rom AD6. %hi module i amemory initiali@ed !ith *# 2it data rereentin '1 and (1 amle. %he memory i #0 dee and read atdata amlin clocH to ynchroni@e !ith AD6 data amlin. Addre to the R8B i enerated 2aed onBod(#0 U(counter rom the interated to module. 3al o the memory i initiali@ed !ith '1 amle andthe other hal !ith (1 amle Jrereentin a ;uare !ave reerence inalK.
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
Aroved y&
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6reated on& 7anuary #0, #010
1.<.5.8 ADC a"a samer
%hi module amle 1(2it data rom AD6 !ith data(amlin clocH J#B3@K. Samlin data i ena2led!ith counter 2aed control inal. $t i o2erved ome iHe occurrence in the P$N+-% outut data, inorder to avoid thee un!anted iHe amle, the AD6 outut amle around the iHe occurrence areinored and are relaced !ith the latet received valid data amle. %hi election o amle relacementi uer coniura2le. Uer can enter the amle num2er, 2y !hich the entered amle num2er and theollo!ed immediate # amle are relaced !ith the latet received valid data amle.
1.<.5.9 Demo!a"ion m!"iier
%he multilier ued here i +PA reource rimitive. $t i coniured to have ined 1(2it inut andined *#(2it outut. Bodulated data rom P$N+-% i received 2y +PA throuh AD6, then demodulateduin thi multilier !ith the reerence ;uare !ave amle. :ith thi multilier, AD6 amle aredemodulated over every u2e;uent t!o tranit(time !hich reult a the dierence 2et!een AD6amle o thoe t!o tranit(time. 8ver a eriod o t!o tranit(time, every irt 10 AD6 data amle are
multilied !ith 10 reerence inal ‘'1’ amle, net 10 AD6 data amle are multilied !ith 10reerence inal ‘(1’ amle.
1.<.5.; ,o%ing a%erage i"er
%he ilter i ued to mooth the cloed loo control ytem reone, !hich imrove the threhold andreolution characteritic o the ytem. %houh it i named i movin averain ilter, actualimlementation reult a Bovin accumulation ilter ollo!ed !ith 2inary diviion in # o!er.y thi ilterin the deviation in error can 2e minimi@ed.
1.<.5.< Gain m!"iier
%he multilier ued here i +PA reource. $t i ued to control the ain o the iltered outut error inalamlitude. ain i controlled 2y ractional multilication o inal. $t i a ined multilier. Uer can electthe ractional value over UAR% !ith !hich inal to 2e multilied. $t alo control the atne o the loocloure o the ytem.
1.<.5.: Dea-/an omensa"or
%he cloed loo oeration uer rom a locHu near rotation rate around @ero. %he locHu i aloreerred to a dead(2and, dead(@one, or a reion o inta2ility. $t i a rane o rate !here the enitivity o the yro reduce to @ero uch that yro no loner ene rotation rate.%hi dead(2and error can 2e eliminated 2y the addition o a eriodic comenation inal, at the inut tothe te(i@e interator.
1.<.5.4 &"e-siNe in"egra"or
%hi i an $nteral controller. %hi module interate the ain controlled error outut or every tranit time.%he interated outut !ill 2e ued or the hae error comenation inal eneration. $n a cloed looytem, !hen the error inut i o hih>lo! amlitude, the comenation inal o roortional amlitude!ill 2e enerated. 3ence thi interation at every tranit time never overlo!. %he interated outut i alouload to P6 over a elected eriod.
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
Aroved y&
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6reated on& 7anuary #0, #010
1.<.5.10 V5i on"ro #ain
%he value =#i correond to the eaH(eaH amlitude o the eed 2acH comenation inal JRaminalK. %he uroe o thi controller i to correct the error in thi amlitude at every ram(reet intance.
1.<.5.11 Ram signa genera"ion
%hi module i the eed2acH hae error comenation inal enerator. %he te(i@e data i interated!ith reerence to the uer and lo!er threhold and reult ram inal !hoe re;uency i roortionalto the te(i@e.
1.<.5.15 7ias signa genera"ion
S;uare !ave ia inal o 10043@ re;uency i enerated. %he 2ia inal amlitude i roortional tothe ram inal amlitude. %he 2ia inal time eriod i roortional to the tranit time eriod.
1.<.5.16 &"e siNe a%erage mo!e
%hi module accumulate the inal te(i@e data over a elective eriod 2y the uer, then averae andthi outut !ill 2e ed to Uart controller or tranmiion.
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Pae 1 o *
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
Aroved y&
Preared 2y& 3 4 Praad a2u.4,Praada Rao.S, Amit Nahar
6reated on& 7anuary #0, #010
1.: Design e"ais
1.:.1 Co genera"ion mo!e
%hi dein module ulie the neceary clocH inal to all other dein module. $nut to thi modulei the clocH inal rom the 6rytal 8cillator. Uin +PA reource liHe D6B and ome mod(counter loicneceary clocH inal are derived.
+iure 5& locH diaram o 6locH eneration module
-N%$% clHLmodule $SP8R% J
6<4 & $N S%DL<8$6OR-S-%L%8PLN & $N S%DL<8$6OclHL50B & 8U% S%DL<8$6OclHL"0B & 8U% S%DL<8$6OclHL#5B & 8U% S%DL<8$6OclHL"B & 8U% S%DL<8$6O
CJmo!e
6<4
R-S-%L%8PLN
6lHL50B
6lHL"0B
6lHL#5B
6lHL"B
6lHL#B
6lHL#004
6lHL1004
R-S-%L<864-DLN
FPGA Firmware Design Do!men"
C!s"omer$ RC+ 'era/a
Ei"ion 1
Pro2e"$ WG-DPEC-1.0 (Cose Loo DFOG)
Pae 1 o *
7/26/2019 WG-DPEC-1.0_FDD(DFOG)
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
Aroved y&
Preared 2y& 3 4 Praad a2u.4,Praada Rao.S, Amit Nahar
6reated on& 7anuary #0, #010
clHL#B & 8U% S%DL<8$6OclHL#004 & 8U% S%DL<8$6OclHL1004 & 8U% S%DL<8$6OR-S-%L<864-DLN & 8U% S%DL<8$6
KO
-ND clHLmoduleO
1.:.1.1 n!" an O!"!" signa esri"ion
&.*o Por" name Dire"ion Te ? wi"# Desri"ion
1 6<4 $N S%DL<8$6 50B3@ clocH inut rom6rytal 8cillator
# R-S-%L%8PLN $N S%DL<8$6 lo2al Reet inut Jactivelo!K
* 6lHL50B 8U% S%DL<8$6 uered 50B3@ oututclocH
" 6lHL"0B 8U% S%DL<8$6 "0B3@ outut clocH
5 6lHL#5B 8U% S%DL<8$6 6locH outut or Pico(2la@econtroller
6lHL"B 8U% S%DL<8$6 "B3@ clocH outut
C 6lHL#B 8U% S%DL<8$6 Data amlin rom AD6,Bovin averae ilter,
drivin 1(2it data to DA6are !orHin on data(
amlin clocH J#B3@K
) 6lHL#004 8U% S%DL<8$6 Ste(i@e interation, Rate(udate module, =#i control
chain are !orHin on the%ranit(clocH J#0043@K
9 6lHL1004 8U% S%DL<8$6 ia inal eneration i2aed on 10043@ clocH
inal
%a2le "& $nut and 8utut inal o 6locH eneration module
1.:.1.5 Coe esri"ion
$n thi module, intantiation o the D6B to enerate the deired clocH inal i ho!n here.%he lo2al reet inut to the +PA rom the 2oard i active(lo!. %he D6B reet inut olarity hould 2eactive(hih, hence the lo2al reet inut i inverted and ed a reet to D6B.%he clocH inut to the D6B i 50B3@ clocH rom the on(2oard crytal ocillator. 8utut o the D6B are"0B3@ and 2uered 50B3@ clocH.%he <864-DLS inal outut rom the D6B validate the outut clocH ta2ility o the D6B. %hi oututinal tate i initially lo! ater o!er(on, 2ecome hih !hen D6B ive ta2le clocH outut. %hi inalalon !ith lo2al reet inal i ued to enerate internal reet RS%L<64LNLint inal or all other module o the dein to enure 2etter erormance.
FPGA Firmware Design Do!men"
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
Aroved y&
Preared 2y& 3 4 Praad a2u.4,Praada Rao.S, Amit Nahar
6reated on& 7anuary #0, #010
((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((( D$$%A< 6<864 BANA-R(((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((
R-S-%L%8PLP TM N8% R-S-%L%8PLNO
$ntLclHLen& clHLenP8R% BAP J6<4$NL$N M 6<4, (( 50 B3@ 8c clHRS%L$N M R-S-%L%8PLP,6<4+FL8U% M clHL"0BLint, (( "0 B3@6<4$NL$U+L8U% M clHL50BLint, (( 50 B3@<864-DL8U% M <864-DLSKO(((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((clHL"0B TM clHL"0BLintOclHL50B TM clHL50BLintO
(((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((RS%L<64LNLint TM JR-S-%L%8PLN and <864-DLSKOR-S-%L<864-DLN TM RS%L<64LNLintO(((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((
%hee D6B outut clocH inal are ued to enerate the other deired re;uencie 2aed on Bod(counter.+rom 50B3@ clocH inal, #5B3@ i derived uin %ole(li(lo unctionality.
FPGA Firmware Design Do!men"
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
Aroved y&
Preared 2y& 3 4 Praad a2u.4,Praada Rao.S, Amit Nahar
6reated on& 7anuary #0, #010
+iure & "B3@, #B3@ 6locH eneration lo!
((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((( #5 B3@ eneration(((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((roceJclHL50BLint, RS%L<64LNLintK2ein
i RS%L<64LNLint M I0I thenclHL#5BLint TM I0IO
eli clHL50BLintIevent and clHL50BLint M I1I thenclHL#5BLint TM not clHL#5BLintO
D li lo
clHL50BLint
RS%L<64LNLint
clHL#5BLint
Bod(5counter
D li lo
clHL"0BLint
RS%L<64LNLint
clHL"BLint
clHL"0BLint
U+
clHL"BLU+
D li lo
clHL"BLU+
RS%L<64LNLint
clHL#BLintU+
clHL#BLU+
FPGA Firmware Design Do!men"
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Ei"ion 1
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
Aroved y&
Preared 2y& 3 4 Praad a2u.4,Praada Rao.S, Amit Nahar
6reated on& 7anuary #0, #010
end iOend roceO
clHL#5B TM clHL#5BLintO(((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((
((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((( " B3@ eneration(((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((roceJRS%L<64LNLint, clHL"0BLintK2ein
i RS%L<64LNLint M I0I thencntr1Lmod5 TMJother M I0IKOclHL"BLint TMI0IO
eli clHL"0BLintIevent and clHL"0BLint M I1I then(((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((
i cntr1Lmod5 M100 then
cntr1Lmod5 TMJother M I0IKOclHL"BLint TM not clHL"BLintO
elecntr1Lmod5 TM cntr1Lmod5 ' I1IO
end iO(((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((end iO
end roceO(((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((U+LU* & U+
ort ma J$ M clHL"BLint,8 M clHL"BLU+
KOclHL"B TM clHL"BLU+O(((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((
((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((( # B3@ eneration(((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((roceJRS%L<64LNLint, clHL"BLU+K2ein
i RS%L<64LNLint M I0I thenclHL#BLint TM I0IO
eli clHL"BLU+Ievent and clHL"BLU+ M I1I then
clHL#BLint TM not clHL#BLintOend iOend roceO(((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((U+LU & U+
ort ma J$ M clHL#BLint,8 M clHL#BLU+
FPGA Firmware Design Do!men"
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Pro2e"$ WG-DPEC-1.0 (Cose Loo DFOG)
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
Aroved y&
Preared 2y& 3 4 Praad a2u.4,Praada Rao.S, Amit Nahar
6reated on& 7anuary #0, #010
KOclHL#B TM clHL#BLU+O(((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((
+iure C& #0043@, 10043@ clocH eneration lo!
((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((( #00 43@ eneration(((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((roceJRS%L<64LNLint, clHL#BLU+K2ein
i RS%L<64LNLint M I0I thencntr#Lmod5 TM Jother M I0IKO
clHL#004Lint TM I0IOeli clHL#BLU+Ievent and clHL#BLU+ M I1I then
i cntr#Lmod5 M 100 thencntr#Lmod5 TM Jother M I0IKOclHL#004Lint TM not clHL#004LintO
elecntr#Lmod5 TM cntr#Lmod5 ' I1IO
end iO
Bod(5counter
D li lo
clHL#BLU+
RS%L<64LNLint
clHL#004Lint
clHL#BLU+
U+
clHL#004LU+
D li lo
clHL#004LU+
RS%L<64LNLint
clHL1004Lint
FPGA Firmware Design Do!men"
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Ei"ion 1
Pro2e"$ WG-DPEC-1.0 (Cose Loo DFOG)
Pae 1 o *
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
Aroved y&
Preared 2y& 3 4 Praad a2u.4,Praada Rao.S, Amit Nahar
6reated on& 7anuary #0, #010
end iOend roceO(((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((U+LU" & U+
ort ma J
$ M clHL#004Lint,8 M clHL#004LU+KO
clHL#004 TM clHL#004LU+O(((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((
((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((( 100 43@ eneration(((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((roceJRS%L<64LNLint, clHL#004LU+K2ein
i RS%L<64LNLint M I0I then
clHL1004Lint TM I0IOeli clHL#004LU+Ievent and clHL#004LU+ MI1I then
clHL1004Lint TM not clHL1004LintOend iO
end roceOclHL1004 TM clHL1004LintO(((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((
FPGA Firmware Design Do!men"
C!s"omer$ RC+ 'era/a
Ei"ion 1
Pro2e"$ WG-DPEC-1.0 (Cose Loo DFOG)
Pae 1 o *
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
Aroved y&
Preared 2y& 3 4 Praad a2u.4,Praada Rao.S, Amit Nahar
6reated on& 7anuary #0, #010
1.:.5 Ra"e !a"e mo!e
%hi dein module enerate timin control inal ued to uload data to P6. aed on the timincontrol inal enerated, te(i@e data i averaed. $n the current dein, #m averaed data i ent toP6 uin thee control inal. 8ne o thee control inal i ued to enerate the comenation ;uare!ave inal ued in Dead(2and comenation.
+iure )& locH diaram o Rate udate module
-N%$% RateLudateLmodule $SP8R% J
RS%LN & $N S%DL<8$6O
clHL#004 & $N S%DL<8$6OclHL#5B & $N S%DL<8$6ORateLUdateL=A< & $N S%DL<8$6L=-6%8RJ15 D8:N%8 0KOclHL5003@ & 8U% S%DL<8$6OuleL#Lm & 8U% S%DL<8$6
KO-ND RateLudateLmoduleO
Ra"e !a"e mo!e
RS%LN
RateLUdateL=A<
clHL5003@
uleL#Lm
clHL#004
clHL#5B
1
FPGA Firmware Design Do!men"
C!s"omer$ RC+ 'era/a
Ei"ion 1
Pro2e"$ WG-DPEC-1.0 (Cose Loo DFOG)
Pae 1 o *
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
Aroved y&
Preared 2y& 3 4 Praad a2u.4,Praada Rao.S, Amit Nahar
6reated on& 7anuary #0, #010
1.:.5.1 n!" an o!"!" signa esri"ion
&.*o Por" name Dire"ion Te ? wi"# Desri"ion
1 RS%LN $N S%DL<8$6 Reet to the rate(udatemodule
# clHL#004 $N S%DL<8$6 #00 43@ clocH inut
* clHL#5B $N S%DL<8$6 N8% US-D
" RateLUdateL=A< $N S%DL<8$6L=-6%8RJ15D8:N%8 0K
Uer Selective inut controlo rate udate duration
5 clHL5003@ 8U% S%DL<8$6 $nteral multile o 5003@re;uency outut ued or Dead(2and comenation
uleL#Lm 8U% S%DL<8$6 Pule outut once everyinteral multile o #m
ued to reet the roce o
accumulatin Ste(i@e data!hile uload to P6
%a2le 5& $nut and 8utut inal o Rate(udate module
1.:.5.5 Coe esri"ion
aed on the inut RateLUdateL=A< a counter i incremented at #0043@ clocH. 6ounter increment untilit value reache RateLUdateL=A< and then reet.%hi i done to derive lo! re;uency inal Jinteral multile o 143@ clocHK. A the RateLUdateL=A< i roramma2le 2y uer, the mod o the counter decide the deired lo!re;uency inal eneration JrateLudateLclHLtmK .
Uin thi interal multile o 143@ re;uency, interal multile o 50043@ re;uency are enerated othat te(i@e data to 2e uloaded to P6 at #m, "mV..Jinteral multile o #mK.
(((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((roceJclHL#004,RS%LNK2ein
i RS%LN MI0I thenrateLudateLcntr TM Jother M I0IKO
eli clHL#004Ievent and clHL#004 MI0I theni rateLudateLcntr M RateLUdateL=A< then
rateLudateLcntr TM Jother M I0IKOele
rateLudateLcntr TM rateLudateLcntr ' I1IOend iO
end iOend roceO(((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((
FPGA Firmware Design Do!men"
C!s"omer$ RC+ 'era/a
Ei"ion 1
Pro2e"$ WG-DPEC-1.0 (Cose Loo DFOG)
Pae 1 o *
7/26/2019 WG-DPEC-1.0_FDD(DFOG)
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
Aroved y&
Preared 2y& 3 4 Praad a2u.4,Praada Rao.S, Amit Nahar
6reated on& 7anuary #0, #010
+iure 9& clH5003@ eneration lo!
roceJclHL#004, RS%LNK2ein
i RS%LN MI0I thenrateLudateLclHLtm TMI0IO
eli clHL#004Ievent and clHL#004 MI0I theni rateLudateLcntr M RateLUdateL=A< then
rateLudateLclHLtm TMI0IOeli rateLudateLcntr M JI0I G RateLUdateL=A<J15 do!nto 1KK then
rateLudateLclHLtm TMI1IOend iO
end iOend roceO(((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((roceJrateLudateLclHLtm , RS%LNK2ein
i RS%LN MI0I then
Bod JRateLUdateL=A<
'1Kcounter
D li lo
clHL#004
RS%LN
rateLudateLclHLtm
clHL#004
D li lo
rateLudateLclHLtm
RS%LN
clHL5003@ Lint
1
FPGA Firmware Design Do!men"
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Ei"ion 1
Pro2e"$ WG-DPEC-1.0 (Cose Loo DFOG)
Pae 1 o *
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
Aroved y&
Preared 2y& 3 4 Praad a2u.4,Praada Rao.S, Amit Nahar
6reated on& 7anuary #0, #010
clHL5003@Lint TMI0IOeli rateLudateLclHLtmIevent and rateLudateLclHLtm MI0I then
clHL5003@Lint TM not clHL5003@LintOend iO
end roceO
clHL5003@ TM clHL5003@LintOuleL#Lm TM clHL5003@LintO(((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((
FPGA Firmware Design Do!men"
C!s"omer$ RC+ 'era/a
Ei"ion 1
Pro2e"$ WG-DPEC-1.0 (Cose Loo DFOG)
Pae 1 o *
7/26/2019 WG-DPEC-1.0_FDD(DFOG)
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
Aroved y&
Preared 2y& 3 4 Praad a2u.4,Praada Rao.S, Amit Nahar
6reated on& 7anuary #0, #010
1.:.6 Reerene signa RO,
%hi dein module enerate reerence inal ued or demodulatin data rom AD6. %hi module i amemory initiali@ed !ith *# 2it data rereentin '1 and (1 amle. %he memory i #0 dee and read atdata amlin clocH to ynchroni@e !ith AD6 data amlin. Addre to the R8B i enerated 2aed onBod(#0 U(counter rom the interated to module. 3al o the memory i initiali@ed !ith '1 amle andthe other hal !ith (1 amle Jrereentin a ;uare !ave reerence inalK.
+iure 10& locH diaram o Reerence inal R8B
-N%$% ReLSiLR8B iP8R% J
6lH & $N S%DL<8$6Oaddr & $N S%DL<8$6L=-6%8RJ" D8:N%8 0KODataout & 8U% S%DL<8$6L=-6%8RJ*1 D8:N%8 0KKO
-ND ReLSiLR8B O
Reerene signa RO,
addr
Dataout
6lH
5
*#
FPGA Firmware Design Do!men"
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
Aroved y&
Preared 2y& 3 4 Praad a2u.4,Praada Rao.S, Amit Nahar
6reated on& 7anuary #0, #010
1.:.6.1 n!" an o!"!" signa esri"ion
&.*o Por" name Dire"ion Te ? wi"# Desri"ion
1 6lH $N S%DL<8$6 Data amlin clocH inut toR8B to ynchroni@e
readin R8B !ith AD6 data
# Addr $N S%DL<8$6L=-6%8RJ"D8:N%8 0K
Addre inut to #0 deeR8B
* Dataout 8U% S%DL<8$6L=-6%8RJ*1D8:N%8 0K
Data outut rom the R8Bued to demodulate AD6
amle
%a2le & $nut and outut inal o Reerence inal R8B
1.:.6.5 Coe esri"ion
%he ollo!in code ho! initiali@ation o memory o deth #0. A ho!n here, 10 amle o memoryindicate '1 and the remainin 10 amle indicate (1 amle. 3ence thi R8B i ued to enerate thereerence ;uare !ave amle !hich !ill 2e ued to demodulate the AD6 data amle.locH memory reource o +PA i ued to enerate thi R8B.
attri2ute RABLS%<- & trinOattri2ute RABLS%<- o R8BLB-B& inal i <864O
((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((( R8B content
(((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((R8BLB-B TM
J11111111111111111111111111111111, ((1#11111111111111111111111111111111, ((1*11111111111111111111111111111111, ((1"11111111111111111111111111111111, ((1511111111111111111111111111111111, ((111111111111111111111111111111111, ((1C11111111111111111111111111111111, ((1)11111111111111111111111111111111, ((1911111111111111111111111111111111, ((#000000000000000000000000000000001, ((100000000000000000000000000000001, ((#00000000000000000000000000000001, ((*00000000000000000000000000000001, (("00000000000000000000000000000001, ((500000000000000000000000000000001, ((00000000000000000000000000000001, ((C00000000000000000000000000000001, (()00000000000000000000000000000001, ((9
FPGA Firmware Design Do!men"
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Ei"ion 1
Pro2e"$ WG-DPEC-1.0 (Cose Loo DFOG)
Pae 1 o *
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
Aroved y&
Preared 2y& 3 4 Praad a2u.4,Praada Rao.S, Amit Nahar
6reated on& 7anuary #0, #010
00000000000000000000000000000001, ((1011111111111111111111111111111111 ((11KO
%he addre inut rom the interated to module i reitered and ed to the R8B.
(((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((roce JclHK2ein
iJclHIevent and clH M I1IK thenrLaddr TM addrO
end iOend roceO
A thi i a R8B JRead only memoryK, rovidin addre inut to the R8B ive out the data amle. A the addre i enerated 2aed on the mod(counter, data i read continuouly rom R8B throuh outthe oeration.(((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((Dataout TM R8BLB-BJconvLinteerJrLaddrKKO
(((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((
FPGA Firmware Design Do!men"
C!s"omer$ RC+ 'era/a
Ei"ion 1
Pro2e"$ WG-DPEC-1.0 (Cose Loo DFOG)
Pae 1 o *
7/26/2019 WG-DPEC-1.0_FDD(DFOG)
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
Aroved y&
Preared 2y& 3 4 Praad a2u.4,Praada Rao.S, Amit Nahar
6reated on& 7anuary #0, #010
1.:.8 ADC a"a samer
%hi module amle 1(2it data rom AD6 !ith data(amlin clocH J#B3@K. Samlin data i ena2led!ith counter 2aed control inal. $t i o2erved ome iHe occurrence in the P$N+-% outut data, inorder to avoid thee un!anted iHe amle, the AD6 outut amle around the iHe occurence areinored and are relaced !ith the latet received valid data amle. %hi election o amle relacementi uer coniura2le. Uer can enter the amle num2er, 2y !hich the entered amle num2er and theollo!ed immediate # amle are relaced !ith the latet received valid data amle.
+iure 11& locH diaram o AD6 data amler
-N%$% AD6LdataLamler $SP8R% J
RS%LN & $N S%DL<8$6OclHL#B & $N S%DL<8$6O
tartLamleLnum & $N S%DL<8$6L=-6%8RJ* D8:N%8 0KO AD6LDA%A & $N S%DL<8$6L=-6%8RJ15 D8:N%8 0KOSamledLAD6LData & 8U% S%DL<8$6L=-6%8RJ15 D8:N%8 0K
KO-ND AD6LdataLamlerO
ADC a"a samer
RS%LN
tartLamleLnum
SamledLAD6LDataclHL#B
AD6LDA%A
"
1
1
FPGA Firmware Design Do!men"
C!s"omer$ RC+ 'era/a
Ei"ion 1
Pro2e"$ WG-DPEC-1.0 (Cose Loo DFOG)
Pae 1 o *
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
Aroved y&
Preared 2y& 3 4 Praad a2u.4,Praada Rao.S, Amit Nahar
6reated on& 7anuary #0, #010
1.:.8.1 n!" an o!"!" signa esri"ion
&.*o Por" name Dire"ion Te ? wi"# Desri"ion
1 RS%LN $N S%DL<8$6 Reet to the AD6 dataamler module
# clHL#B $N S%DL<8$6 # B3@ clocH inut or amlin AD6 data
* tartLamleLnum $N S%DL<8$6L=-6%8RJ*D8:N%8 0K
Uer elected amlenum2er to 2e relaced
" AD6LDA%A $N S%DL<8$6L=-6%8RJ15D8:N%8 0K
1(2it AD6 data inut
5 SamledLAD6LDA%A 8U% S%DL<8$6L=-6%8RJ15D8:N%8 0K
=alid 1(2it AD6 amle
%a2le C& $nut and outut inal o AD6 data amler
1.:.8.5 Coe esri"ion
AD6 data are amled !ith data(amlin clocH J#B3@K. A er the reent eciication o the ytem,tranit clocH re;uency i #0043@. 3ence or each tranit clocH, 10 amle o AD6 data can 2e received!hen amled !ith #B3@.
Bod(10 counter Jena2leLcounter K i ued or thi amle relacement unction. Uer elect articular amle num2er JtartLamleLnum K !hich need to 2e relaced !ith valid data.ena2leLadcLamle i the control enerated 2aed on !hich valid data !ill relace thee un!antedamle.:hen ena2leLadcLamle i lo!, the valid amle data relace the current inut AD6 amle.:hen ena2leLadcLamle i hih, AD6 outut amle are imly reitered JSamledLAD6LDataK.
(((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((roceJclHL#B, RS%LNK2ein
i RS%LN M I0I thenena2leLcounter TM Jother M I0IKO
eli clHL#BIevent and clHL#B M I0I theni ena2leLcounter M 1001 then
ena2leLcounter TM Jother M I0IKOele
ena2leLcounter TM ena2leLcounter ' I1IOend iO
end iOend roceO(((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((
FPGA Firmware Design Do!men"
C!s"omer$ RC+ 'era/a
Ei"ion 1
Pro2e"$ WG-DPEC-1.0 (Cose Loo DFOG)
Pae 1 o *
7/26/2019 WG-DPEC-1.0_FDD(DFOG)
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
Aroved y&
Preared 2y& 3 4 Praad a2u.4,Praada Rao.S, Amit Nahar
6reated on& 7anuary #0, #010
+iure 1#& AD6 Samle relacement loic lo!
ena2leLre TM I0I !hen Jena2leLcounter M tartLamleLnumK ele I1IO
roceJclHL#B, RS%LNK2ein
i RS%LN M I0I then
ena2leLreLdel TM Jother M I1IKOeli clHL#BIevent and clHL#B M I0I then
ena2leLreLdel TM ena2leLreLdelJ0K G ena2leLreOend iO
end roceO
ena2leLadcLamle TM ena2leLre AND ena2leLreLdelJ0K AND ena2leLreLdelJ1KO(((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((
D li lo
clHL#B
RS%LN
SamledLAD6LData
Bod (10counter
clHL#B"
"M
tartLamleLnum
ena2leLcounter
Dlilo
Dlilo
clHL#B clHL#B
1
AD6LData
11
FPGA Firmware Design Do!men"
C!s"omer$ RC+ 'era/a
Ei"ion 1
Pro2e"$ WG-DPEC-1.0 (Cose Loo DFOG)
Pae 1 o *
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
Aroved y&
Preared 2y& 3 4 Praad a2u.4,Praada Rao.S, Amit Nahar
6reated on& 7anuary #0, #010
roceJclHL#B, RS%LNK2ein
i RS%LN M I0I thenSamledLAD6LData TM Jother M I0IKO
eli clHL#BIevent and clHL#B M I0I then
i ena2leLadcLamle M I1I thenSamledLAD6LData TM AD6LDA%AO
end iOend iO
end roceO(((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((
FPGA Firmware Design Do!men"
C!s"omer$ RC+ 'era/a
Ei"ion 1
Pro2e"$ WG-DPEC-1.0 (Cose Loo DFOG)
Pae 1 o *
7/26/2019 WG-DPEC-1.0_FDD(DFOG)
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
Aroved y&
Preared 2y& 3 4 Praad a2u.4,Praada Rao.S, Amit Nahar
6reated on& 7anuary #0, #010
1.:.9 Demo!a"ion m!"iier
%he multilier ued here i +PA reource rimitive. $t i coniured to have ined 1(2it inut andined *#(2it outut.
+iure 1*& locH diaram o Demodulation multilier
Bodulated data rom P$N+-% i received 2y +PA throuh AD6, then demodulated uin thi multilier !ith the reerence ;uare !ave amle JD-B8DLR-+LiK.
:ith thi multilier, AD6 amle are demodulated over every u2e;uent t!o tranit(time !hich reult athe dierence 2et!een AD6 amle o thoe t!o tranit(time.
8ver a eriod o t!o tranit(time, every irt 10 AD6 data amle are multilied !ith 10 reerence inal‘'1’ amle, net 10 AD6 data amle are multilied !ith 10 reerence inal ‘(1’ amle.
1.:.9.1 n!" an o!"!" signa esri"ion
&.*o Por" name Dire"ion Te ? wi"# Desri"ion
1 6lH $N S%DL<8$6 #B3@ Data(amlin clocHinut
# A $N S%DL<8$6L=-6%8RJ15D8:N%8 0K
1(2it ined data inut.SamledLAD6LData iconnected to thi ort
* $N S%DL<8$6L=-6%8RJ15
D8:N%8 0K
1(2it ined data inut.
D-B8DLR-+Li iconnected to thi ort
" P 8U% S%DL<8$6L=-6%8RJ*1D8:N%8 0K
1(2it ined data outut,demodLmulLout i
connected to thi ort
%a2le )& $nut and outut inal o Demodulation multilier
Demo!a"ionm!"iier
SamledLAD6LData demodLmulLout
clHL#B
D-B8DLR-+Li
1
1
*#
FPGA Firmware Design Do!men"
C!s"omer$ RC+ 'era/a
Ei"ion 1
Pro2e"$ WG-DPEC-1.0 (Cose Loo DFOG)
Pae 1 o *
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
Aroved y&
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6reated on& 7anuary #0, #010
1.:.9.5 Coe esri"ion
3ere ho!n the intantiation o thi +PA reource in the to(level module,
$ntLdemodLmultilier & demodLmultilierP8R% BAP J
clH M clHL#B,a M SamledLAD6LData,2 M D-B8DLR-+LiJ15 do!nto 0K, M demodLmulLout
KO
A 1(2it AD6 data are multilied !ith '>(1 value, leat 1 2it o the outut roduct i the uicientinormation.
demodLmulLoutLint TM demodLmulLoutJ15 do!nto 0KO
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
Aroved y&
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6reated on& 7anuary #0, #010
1.:.; ,o%ing a%erage i"er
%he ilter i ued to mooth the cloed loo control ytem reone, !hich imrove the threhold andreolution characteritic o the ytem. %houh it i named i movin averain ilter, actualimlementation reult a Bovin accumulation ilter ollo!ed !ith 2inary diviion in # o!er.y thi ilterin the deviation in error can 2e minimi@ed.
+iure 1"& locH diaram o movin averae ilter
-N%$% BovinLAvL+ilter $SP8R% J
clH & $N S%DL<8$6ORS%LN & $N S%DL<8$6OilterLdeth & $N S%DL<8$6L=-6%8RJ1* D8:N%8 0KOdemodLmulLdata & $N S%DL<8$6L=-6%8RJ15 D8:N%8 0KO+$RL+ilterLout & 8U% S%DL<8$6L=-6%8RJ*1 D8:N%8 0K
KO-ND BovinLAvL+ilterO
,o%ing a%erage i"er
RS%LN
ilterLdeth
+$RL+ilterLoutclH
demodLmulLdata
1"
1
*#
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
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6reated on& 7anuary #0, #010
1.:.;.1 n!" an o!"!" signa esri"ion
&.*o Por" name Dire"ion Te ? wi"# Desri"ion
1 6lH $N S%DL<8$6 #B3@ Jdata(amlinK clocHinut
# RS%LN $N S%DL<8$6 Reet inut
* ilterLdeth $N S%DL<8$6L=-6%8RJ1*D8:N%8 0K
1"(2it data inut rom to(module indicatin the 2uer
i@e ued or ilterin
" demodLmulLdata $N S%DL<8$6L=-6%8RJ15D8:N%8 0K
1(2it Demodulated AD6data
5 +$RL+ilterLout 8U% S%DL<8$6L=-6%8RJ*1D8:N%8 0K
*#(2it +ilter outut data
%a2le 9& $nut and outut inal o Bovin averae ilter
1.:.;.5 Coe esri"ion
1(2it outut JdemodLmulLdataK rom the demodulation multilier i ed a inut to +$R tye Bovinaverae ilter module.%hi ilter i an accumulation circuit, !hich !ill um the redeined num2er o amle JNK deined in thecode 2y the arameter ilterLdeth J+io deth mut 2e reater than ilterLdethK. At any oint in the time the outut o the ilter i um o N mot recent amle. 3ere ilter i !orHin at#B3@ JData(amlin clocHK, o in order to et ummation o inteer num2er o !ave orm o 10043@ J#%ranit timeK, N i al!ay inteer multile o #0, and the maimum value o N i retricted 2y the +$+8deth. %he lo! diaram o ilter i ho!n 2elo!.
Y(n) = Y(n-1) + x(n) –x(n-N)
((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((( +$R JBovin AveraeK ilter (((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((RS%LP TM not RS%LNO
$ntLioLorLilter & ioLorLilterort ma J
clH M clH,rt M RS%LP,din M demodLmulLdata,!rLen M !rLenLio,rdLen M rdLenLtart,dout M demodLioLout,ull M 8P-N,emty M 8P-N
KO
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
Aroved y&
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6reated on& 7anuary #0, #010
(((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((
+iure 15& Synchronou +$+8 2aed +$R ilter dein lo!
&n#rono!sFFO
RS%LP rt
demodLmulLdata din
emty emty
dout demodLioLout
6lHL#B clH
!rLenLio !rLen
1
*0
ull ull
rdLen rdLenLtart
' R-
*0
*0
Sineteneded to *0
2it
Sin eteneded to*0 2it
6lHL#B
'
'(
AccumLDemodLout
Sineteneded to *#
2it
*0
R-
6lHL#B
# Men
'1
W11X
counterLorL!r
!rLenLio
R-
6lHL#B
1" Men
'1
+ilterLdeth
counterLorLrd
rdLenLio
#
1"
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
Aroved y&
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6reated on& 7anuary #0, #010
eneration o !rite ena2le to io i 2aed on thi counter. Until counter value i *, !rite ena2le to io ilo!, thi i the initial delay ied to 2alance the inut data ath delay.8nce !rite ena2le i et to hih, it remain continuouly hih.
enerateL!rLen&roceJclH, RS%LNK2ein
i RS%LN M I0I thencounterLorL!r TM Jother M I0IKO
eli clHIevent and clH M I1I theni !rLenLio M I0I then
counterLorL!r TM counterLorL!r ' 1Oend iO
end iOend roceO(((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((!rLenLio TM I1I !hen JcounterLorL!r M 11 K ele
I0IO(((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((
eneration o read ena2le to io i 2aed on thi counter. Read ena2le to io i initially lo!, once !riteena2le to io 2ecome hih and comlete !ritin o data location o eciied deth N, readin rom ioi ena2led.%hi i done to enure that 2eore averain, the entire N Jcorreond to dethK amle are !ritten toio.
enerateLrdLenLtart&roceJclH, RS%LNK2ein
i RS%LN M I0I thencounterLorLrd TM Jother M I0IKO
eli clHIevent and clH M I1I theni rdLenLtart M I0I and !rLenLio M I1I then
counterLorLrd TM counterLorLrd ' 1Oend iO
end iOend roceO(((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((rdLenLtart TM I1I !hen JcounterLorLrd M ilterLdethK ele
I0IO
(((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((
roceJclH, RS%LNK2ein
i RS%LN M I0I then AccumLDemodLout TM Jother M I0IKO
eli clHIevent and clH M I1I then AccumLDemodLout TM AccumLDemodLoutLtmO
end iOend roceO
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
Aroved y&
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6reated on& 7anuary #0, #010
((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((( A mentioned in the a2ove diaram, at every intance the ummation o every conecutive N amle icalculated in thi !ay. At JN'1K th clocH ede the outut o +$R ilter i, JSum o N'1 amleK Y Jirt amleK.
AccumLDemodLoutLtm TM AccumLDemodLout J#9 D8:N%8 0K 'JdemodLmulLdataJ15K G demodLmulLdataJ15K G demodLmulLdataJ15K G demodLmulLdataJ15K GdemodLmulLdataJ15K G demodLmulLdataJ15K G demodLmulLdataJ15K G demodLmulLdataJ15K GdemodLmulLdataJ15K G demodLmulLdataJ15K G demodLmulLdataJ15K G demodLmulLdataJ15K GdemodLmulLdataJ15K G demodLmulLdataJ15K G demodLmulLdataJ15 D8:N%8 0KK(JdemodLioLoutJ15K G demodLioLoutJ15K G demodLioLoutJ15K G demodLioLoutJ15K GdemodLioLoutJ15K G demodLioLoutJ15K G demodLioLoutJ15K G demodLioLoutJ15K G
demodLioLoutJ15K G demodLioLoutJ15K G demodLioLoutJ15K G demodLioLoutJ15K GdemodLioLoutJ15K G demodLioLoutJ15K G demodLioLoutJ15 D8:N%8 0KKO
(((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((
$t i o2erved the ytem ocillatin, hence to reduce the ain o the inal, thi iltered outut i divided 2y1 2y riht hitin " 2it.
+$RL+ilterLout TM AccumLDemodLoutJ#9K G AccumLDemodLoutJ#9K G AccumLDemodLoutJ#9K G AccumLDemodLoutJ#9K G AccumLDemodLoutJ#9K G AccumLDemodLoutJ#9K G AccumLDemodLoutJ#9 do!nto "KO
(((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((
FPGA Firmware Design Do!men"
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
Aroved y&
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6reated on& 7anuary #0, #010
1.:.< Gain m!"iier
%he multilier ued here i +PA reource. $t i ued to control the ain o the iltered outut error inalamlitude. ain i controlled 2y ractional multilication o inal. $t i a ined multilier. Uer can electthe ractional value over UAR% !ith !hich inal to 2e multilied.$t alo control the atne o the loo cloure o the ytem.
+iure 1& locH diaram o ain multilier
((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((( PR8P8R%$8NA< A$N BU<%$P<$-R(((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((%he ractional calin actor i coniured 2y the uer. 3ere ho!n the 4 value ained !ith Uart data.
H TM uLdata" G uLdata5O
$ntLmulLid & mulLidort ma J
clH M clHL#B,a M +$RL+ilterLoutLre, (( *# 2it2 M H, (( 1 2it Proortional ain J+or unit ain o rate, et or "dK; M roLout, (( ") 2it Proortional oututaclr M RS%LP
KO(((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((
Gain m!"iier
+$RL+ilterLoutLre a ; roLout
clHL#B clH
4 2
*#
1
")
RS%LP aclr
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
Aroved y&
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6reated on& 7anuary #0, #010
1.:.<.1 n!" an o!"!" signa esri"ion
&.*o Por" name Dire"ion Te ? wi"# Desri"ion
1 clH $N S%DL<8$6 #B3@ JData amlin clocHKclocH inut
# a $N S%DL<8$6L=-6%8RJ*1D8:N%8 0K
*#(2it ined +iltered data iconnected !hich need to
2e caled
* 2 $N S%DL<8$6L=-6%8RJ15D8:N%8 0K
1(2it unined roortionalain controlled 2y uer ued
to cale the iltered inal
" ; 8U% S%DL<8$6L=-6%8RJ"CD8:N%8 0K
")(2it ined roduct outut
5 aclr $N S%DL<8$6 Active hih reet inut iconnected
%a2le 10& $nut and outut inal o ain multilier
1.:.<.5 Coe esri"ion
%he 1(2it unined value H elected 2y the uer i one o the inut to the ain multilier. A thi i 1(2it!idth the rane o thi cale actor i Z0 to J#1(1K[.
+or the current imlementation, the averain ilter deth i ied to 1000 J$nteer multile o #0amleK.3ence accumulation o 1000 amle reult M 1000 time \ error inal.+ilter outut i divided 2y 1 to reduce the ain M J1000 time \ error inalK>1.
$n thi multilier, the ractional multilication i erormed to et error inal o le amlitude !hich !ill 2eued or net tae interation.
roLout i the ")(2it ined outut o the multilier. $n the net ae roLout J"do!nto 15K i ued orinteration. 3ence the ouut o multilier i urther divided 2y #15.
3ence,ain multilier eective outut i M J1000 time \ error inalK>1>J#15K
M J1000 \ error inal >J#19KK.
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
Aroved y&
Preared 2y& 3 4 Praad a2u.4,Praada Rao.S, Amit Nahar
6reated on& 7anuary #0, #010
1.:.: Dea-/an omensa"or
%he cloed loo oeration uer rom a locHu near rotation rate around @ero. %he locHu i aloreerred to a dead(2and, dead(@one, or a reion o inta2ility. $t i a rane o rate !here the enitivity o the yro reduce to @ero uch that yro no loner ene rotation rate.
%hi dead(2and error can 2e eliminated 2y the addition o a eriodic comenation inal, at the inut tothe te(i@e interator.
1.:.:.1 Coe esri"ion
Uer can elect the amlitude o the comenation over UAR%. %hi i ho!n in the ollo!in art o code.6omenation amlitude i *#(2it value.*#(2it +ied oet value can 2e elected over Uart, i re;uired can 2e added to thi comenationamlitude.
%he duration o comenation i elected 2aed on conideration o data uload rate to P6. At reent or every #m duration, te(i@e data need to 2e uload to P6. 3ence the eriod o dead(2and comenation hould alo 2e in roortion to that uload rate. 3ere the eriod o comenation i#m.
3ence a eriodic J#m eriod ( clHL5003@K ;uare !ave JDL6omLout K o elected amlitudeJUartLDLcomLamK i enerated.
((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((( Dead 2and error comenation uin +ied oet addition G(( u2traction !ith 8n(8 eriod o clHL5003@ inal.(((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((
UartLDLcomLam TM uLdata) G uLdata9 G uLdata10 G uLdata11O
(( iedLoet TM JuLdataLevenKOiedLoet TM Jother M I0IKODL6omLout TM JiedLoet ' UartLDLcomLam K !hen clHL5003@ M I1I ele
JiedLoet ( UartLDLcomLam KO(((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((
%he enerated ;uare !ave Jdead(2and comenator inalK i added to the ain multilier outut !hichi ed a inut to the net tae Ste(i@e interator.
dmodLerror TM JroLoutLint ' DL6omLoutKO
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
Aroved y&
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6reated on& 7anuary #0, #010
1.:.4 &"e-siNe in"egra"or
%hi i an $nteral controller. %hi module interate the ain controlled error outut or every tranit time.%he interated outut !ill 2e ued or the hae error comenation inal eneration. $n a cloed looytem, !hen the error inut i o hih>lo! amlitude, the comenation inal o roortional amlitude!ill 2e enerated. 3ence thi interation at every tranit time never overlo!. %he interated outut i alouload to P6 over a elected eriod.
+iure 1C& locH diaram o Ste(i@e interator
-N%$% tei@eLinterator $SP8R% J
(((((((((((((((((((((( 6<4 G RS%LN (((((((((((((((((((((((clHLtranit & $N S%DL<8$6ORS%LN & $N S%DL<8$6O(((((((((((((((((( $nut to interator ((((((((((((((((((+$FLRLA6%UA<LSSLS-< & $N S%DL<8$6L=-6%8RJ1 D8:N%8 0KOdmodLerror & $N S%DL<8$6L=-6%8RJ*1 D8:N%8 0KO+iedSteSi@e & $N S%DL<8$6L=-6%8RJ*1 D8:N%8 0KO
(((((((((((((((((((( Stei@e outut (((((((((((((((((((((teLi@e & 8U% S%DL<8$6L=-6%8RJ*# D8:N%8 0KKO
-ND tei@eLinteratorO
&"e-siNe in"egra"or
RS%LN
dmodLerror
teLi@e
clHLtranit
+$FLRLA6%UA<LSSLS-<
+iedSteSi@e
*#
*#
** #
FPGA Firmware Design Do!men"
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
Aroved y&
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6reated on& 7anuary #0, #010
1.:.4.1 n!" an o!"!" signa esri"ion
&.*o Por" name Dire"ion Te ? wi"# Desri"ion
1 clHLtranit $N S%DL<8$6 #0043@ clocH inut
# RS%LN $N S%DL<8$6 Active lo! Reet inut* +$FLRLA6%UA<LSSL S-<
$N S%DL<8$6J1 D8:N%80K
Uer election control or +ied>actual te(i@e inut
conideration or theinteration
" dmodLerror $N S%DL<8$6L=-6%8RJ*1D8:N%8 0K
6omenated ainmultilier outut
5 +iedSteSi@e $N S%DL<8$6L=-6%8RJ*1D8:N%8 0K
*#(2it +ied te(i@e dataelected 2y uer over UAR%
teLi@e 8U% S%DL<8$6L=-6%8RJ*# D8:N%8 0K
-ective Ste(i@e outut,!ill 2e ued or ram(
eneration and averaer.
%a2le 11& $nut and outut inal o Ste(i@e interator
1.:.4.5 Coe esri"ion
ain controlled error outut i *#(2it dmodLerror.aed on the uer election arameter +$FLRLA6%UA<LSSLS-< +ied te(i@e and actual te(i@e imultileed, !hich !ill 2e interated at every tranit(time. %he interated outut i teLi@e.
:hen +$FLRLA6%UA<LSSLS-< i W00X, actual inut error i interated to orm the te(i@e.:hen +$FLRLA6%UA<LSSLS-< i W10X, uer elected ied(te(i@e *#(2it value i interated to orm thete(i@e. %hi !ill 2e ued or ome tetin in oen loo condition.
(((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((teLi@eLtem TM dmodLerrorO(((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((!ith +$FLRLA6%UA<LSSLS-< elect teLi@eLtem1 TM
((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((( 100Q Stei@e $N%-RA%$8N(((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((JteLi@eLtemJ*1K G teLi@eLtemK ' teLi@eLint !hen 00,((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((( +ied Stei@e inut(((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((J+iedSteSi@eJ*1K G +iedSteSi@eK !hen 10,Jother M I0IK !hen otherO
(((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((
((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((( Ste(i@e interation ater every tranit(time o yro.(((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((
FPGA Firmware Design Do!men"
C!s"omer$ RC+ 'era/a
Ei"ion 1
Pro2e"$ WG-DPEC-1.0 (Cose Loo DFOG)
Pae 1 o *
7/26/2019 WG-DPEC-1.0_FDD(DFOG)
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
Aroved y&
Preared 2y& 3 4 Praad a2u.4,Praada Rao.S, Amit Nahar
6reated on& 7anuary #0, #010
roceJRS%LN, clHLtranitK2ein
i RS%LN M I0I thenteLi@eLint TM JotherM I0IKO
eli clHLtranitIevent and clHLtranit M I0I then
teLi@eLint TM teLi@eLtem1Oend iO
end roceO(((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((
teLi@e TM teLi@eLintO(((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((
FPGA Firmware Design Do!men"
C!s"omer$ RC+ 'era/a
Ei"ion 1
Pro2e"$ WG-DPEC-1.0 (Cose Loo DFOG)
Pae 1 o *
7/26/2019 WG-DPEC-1.0_FDD(DFOG)
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
Aroved y&
Preared 2y& 3 4 Praad a2u.4,Praada Rao.S, Amit Nahar
6reated on& 7anuary #0, #010
1.:.10 V5i on"ro #ain
%he value =#i correond to the eaH(eaH amlitude o the eed 2acH comenation inal JRaminalK. %he uroe o thi controller i to correct the error in thi amlitude at every ram(reet intance.
+iure 1)& locH diaram o =#i control chain
-N%$% =#iL6ontrolL6hain $SP8R% J
clHL#B & $N S%DL<8$6OclHL#004 & $N S%DL<8$6ORS%LN & $N S%DL<8$6OdemodLmulLoutLint & $N S%DL<8$6L=-6%8RJ15 D8:N%8 0KO=#iL6trlL+ioLdeth & $N S%DL<8$6L=-6%8RJ" D8:N%8 0KOainLval & $N S%DL<8$6L=-6%8RJ15 D8:N%8 0KOD-<ALS-<L6%R< & $N S%DL<8$6L=-6%8RJC D8:N%8 0KO
RamLReetLctrl & $N S%DL<8$6O=#iL-rrorLcomLval & 8U% S%DL<8$6L=-6%8RJ*1 D8:N%8 0K
KO-ND =#iL6ontrolL6hainO
V5i on"ro #ain
RS%LN
ainLval
RamLReetLctrl
=#iL-rrorLcomLval
clHL#004
clHL#B
D-<ALS-<L6%R<
1
)
*#demodLmulLoutLint
=#iL6trlL+ioLdeth
1
5
FPGA Firmware Design Do!men"
C!s"omer$ RC+ 'era/a
Ei"ion 1
Pro2e"$ WG-DPEC-1.0 (Cose Loo DFOG)
Pae 1 o *
7/26/2019 WG-DPEC-1.0_FDD(DFOG)
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
Aroved y&
Preared 2y& 3 4 Praad a2u.4,Praada Rao.S, Amit Nahar
6reated on& 7anuary #0, #010
1.:.10.1 n!" an o!"!" signa esri"ion
&.*o Por" name Dire"ion Te ? wi"# Desri"ion
1 clHL#B $N S%DL<8$6 #B3@ clocH inut
# clHL#004 $N S%DL<8$6 #00 43@ clocH inut* RS%LN $N S%DL<8$6 Active lo! reet inut
" demodLmulLoutLint $N S%DL<8$6L=-6%8RJ15D8:N%8 0K
Demodulation multilier outut
5 =#iL6trlL+ioLdeth $N S%DL<8$6L=-6%8RJ"D8:N%8 0K
Storae 2uer or the dataamle at the ram(reet
intance
ainLval $N S%DL<8$6L=-6%8RJ15D8:N%8 0K
Proortional ain inut or the =#i control chain
C D-<ALS-<L6%R< $N S%DL<8$6L=-6%8RJCD8:N%8 0K
Ram(reet ynchroni@ation!ith data !ill 2e done uin
thi control
) RamLReetLctrl $N S%DL<8$6 Ram(reet intance inut
rom ram inal enerationmodule
9 =#iL-rrorLcomLval 8U% S%DL<8$6L=-6%8RJ*1D8:N%8 0K
*#(2it outut !ith !hich=#i amlitude need to 2e
corrected
%a2le 1#& $nut and outut inal o =#i control chain
1.:.10.5 Coe esri"ion
V 5 Con"ro C#ain$
,o%ing A!m!a"ion Fi"er &
• $t i #0 amle movin accumulator.
• #0 amle correond to t!o tranit(time eriod o yro.
• #0(dee 2uer J+$+8K i ued to accumulate the hae error.
Gain ,!"iier &
• %hi i loo ain multilier o =#] control chain.
• ain o thi multilier i uer roramma2le.
V5 error in"egra"or &
• $t interate the =#] error once or every Ram(Reet intance.
• Ram(reet inal i enerated 2y ram inal enerator module !ith the hel o count overlo!.
• 8utut o error interator i ued to correct the =#] amlitude JUer and lo!er threholdK.
Ram T#res#o Corre"ion$
FPGA Firmware Design Do!men"
C!s"omer$ RC+ 'era/a
Ei"ion 1
Pro2e"$ WG-DPEC-1.0 (Cose Loo DFOG)
Pae 1 o *
7/26/2019 WG-DPEC-1.0_FDD(DFOG)
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
Aroved y&
Preared 2y& 3 4 Praad a2u.4,Praada Rao.S, Amit Nahar
6reated on& 7anuary #0, #010
• %he interated =#] error value i added to ied =#] value to et deired =#] amlitude.
• :hen the =#] amlitude i eceedin the rane, =#] amlitude i et to maimum.
%hi =#] amlitude i ued to derive uer and lo!er threhold o ram inal eneration.
+iure 19& Alorithm or =#i error correction
Demo!a"i
onm!"i
ier
RamT#res#o
Corre"ion
Ramsignagener a"or
7iassignagener a"or
AD6Data
ReerenceS;uare :ave
,o%ing
A!m!a"i
on
Fi"er
Gain,!"i
ier
V5Errorin"egr a"or
Ram(reet
aincontrol
V5 Con"ro C#ain
,o%ing
A!m!a"i
onFi"er
Gain,!"i
ier
Dea-/anomensa"
or
Ra"ein"egr a"or
<oo(ain
Dead(2and6omenation
Amlitude
Ra"e C#ain
FPGA Firmware Design Do!men"
C!s"omer$ RC+ 'era/a
Ei"ion 1
Pro2e"$ WG-DPEC-1.0 (Cose Loo DFOG)
Pae 1 o *
7/26/2019 WG-DPEC-1.0_FDD(DFOG)
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
Aroved y&
Preared 2y& 3 4 Praad a2u.4,Praada Rao.S, Amit Nahar
6reated on& 7anuary #0, #010
((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((( +$RJBovin AveraeK ilter to tore the amle ?ut 2eore and ater the ram reet intance((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((($ntLBovinLAvL+ilterL=#iLctrl& BovinLAvL+ilterL=#iLctrlP8R% BAP J
clH M clHL#B,RS%LN M RS%LN,ilterLdeth M =#iL6trlL+ioLdeth,demodLmulLdata M demodLmulLoutLint,+$RL+ilterLout M +$RL+ilterLout
KO
roceJRS%LN, clHL#BK2ein
i RS%LN M I0I then +$RL+ilterLoutLre TM JotherM I0IKO
eli clHL#BIevent and clHL#B M I0I then +$RL+ilterLoutLre TM +$RL+ilterLoutO
end iOend roceO(((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((
((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((( PR8P8R%$8NA< A$N BU<%$P<$-R(((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((RS%LP TM N8% RS%LNO
$ntLmulLainLctrl & mulLidort ma J
clH M clHL#B,
a M +$RL+ilterLoutLre, (( *# 2it2 M ainLval, (( 1 2it Proortional ain; M BulLout, (( ") 2it Proortional oututaclr M RS%LP
KO(((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((
((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((( Ste(i@e interation ater every tranit(timeJ#0043@K o yro.(((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((
$ntL=#iL-rrorLtem TM BulLoutJ* do!nto 5KO
(( $ntL=#iL-rrorLtem1 TM $ntL=#iL-rrorLtem ' $ntL=#iL-rrorO$ntL=#iL-rrorLtem1 TM $ntL=#iL-rrorLtemO
roceJRS%LN, clHL#BK2ein
i RS%LN M I0I thenRamLReetLctrlLd1 TM I0IORamLReetLctrlLd# TM I0IO
FPGA Firmware Design Do!men"
C!s"omer$ RC+ 'era/a
Ei"ion 1
Pro2e"$ WG-DPEC-1.0 (Cose Loo DFOG)
Pae 1 o *
7/26/2019 WG-DPEC-1.0_FDD(DFOG)
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
Aroved y&
Preared 2y& 3 4 Praad a2u.4,Praada Rao.S, Amit Nahar
6reated on& 7anuary #0, #010
RamLReetLctrlLd* TM I0IOeli clHL#BIevent and clHL#B M I0I then
RamLReetLctrlLd1 TM RamLReetLctrlORamLReetLctrlLd# TM RamLReetLctrlLd1ORamLReetLctrlLd* TM RamLReetLctrlLd#O
end iOend roceO
PR8L6N%L-N TMJN8% RamLReetLctrlLd*K AND RamLReetLctrlLd#O
(( SR<1L1& 1(2it hit reiter <U% oeratin on neede o clocHSR<1L1Lint1 & SR<1L1eneric ma J $N$% M F0000Kort ma J
^ M PR8L6N%L-NLD-<A1, (( SR< data outut A0 M D-<ALS-<L6%R<J0K, (( SelectZ0[ inut A1 M D-<ALS-<L6%R<J1K, (( SelectZ1[ inut A# M D-<ALS-<L6%R<J#K, (( SelectZ#[ inut
A* M D-<ALS-<L6%R<J*K, (( SelectZ*[ inut6<4 M clHL#B, (( 6locH inutD M PR8L6N%L-N (( SR< data inut
KO
SR<1L1Lint# & SR<1L1eneric ma J $N$% M F0000Kort ma J
^ M PR8L6N%L-NLD-<A#, (( SR< data outut A0 M D-<ALS-<L6%R<J0K, (( SelectZ0[ inut A1 M D-<ALS-<L6%R<J1K, (( SelectZ1[ inut A# M D-<ALS-<L6%R<J#K, (( SelectZ#[ inut A* M D-<ALS-<L6%R<J*K, (( SelectZ*[ inut
6<4 M clHL#B, (( 6locH inutD M PR8L6N%L-NLD-<A1 (( SR< data inut
KO
roceJD-<ALS-<L6%R<J"K, PR8L6N%L-NLD-<K2ein
iJD-<ALS-<L6%R<J"K M I0IK then$ntL-N TM PR8L6N%L-NLD-<A1O
ele$ntL-N TM PR8L6N%L-NLD-<A#O
end iOend roceO
roceJRS%LN, clHL#BK2ein
i RS%LN M I0I then$ntL=#iL-rror TM JotherM I0IKO
eli clHL#BIevent and clHL#B M I0I theniJ$ntL-N M I1IK then
$ntL=#iL-rror TM $ntL=#iL-rrorLtem1O
FPGA Firmware Design Do!men"
C!s"omer$ RC+ 'era/a
Ei"ion 1
Pro2e"$ WG-DPEC-1.0 (Cose Loo DFOG)
Pae 1 o *
7/26/2019 WG-DPEC-1.0_FDD(DFOG)
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
Aroved y&
Preared 2y& 3 4 Praad a2u.4,Praada Rao.S, Amit Nahar
6reated on& 7anuary #0, #010
end iOend iO
end roceO
=#iL-rrorLcomLval TM $ntL=#iL-rrorO
N8%- & Still urther tudy o =#i variation !ith rotation rate at the ram(reet i need.
FPGA Firmware Design Do!men"
C!s"omer$ RC+ 'era/a
Ei"ion 1
Pro2e"$ WG-DPEC-1.0 (Cose Loo DFOG)
Pae 1 o *
7/26/2019 WG-DPEC-1.0_FDD(DFOG)
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
Aroved y&
Preared 2y& 3 4 Praad a2u.4,Praada Rao.S, Amit Nahar
6reated on& 7anuary #0, #010
1.:.11 Ram signa genera"ion
%hi module i the eed2acH hae error comenation inal enerator. %he te(i@e data i interated!ith reerence to the uer and lo!er threhold and reult ram inal !hoe re;uency i roortionalto the te(i@e.
+iure #0& locH diaram o Ram(inal eneration module
entity RamLen iortJRS%LN & $N S%DL<8$6OramLenLclH & $N S%DL<8$6OclHL#B & $N S%DL<8$6ORamL= & $N S%DL<8$6L=-6%8RJ*1 D8:N%8 0KOteLi@e & $N S%DL<8$6L=-6%8RJ*# D8:N%8 0KO
RamLReetLctrl & 8U% S%DL<8$6OramLout & 8U% S%DL<8$6L=-6%8RJ15 D8:N%8 0K
KOend RamLenO
Ram genera"ion mo!e
RS%LN
RamL=
RamLReetLctrl
ramLout
ramLenLclH
clHL#B
teLi@e
*#
**
1
FPGA Firmware Design Do!men"
C!s"omer$ RC+ 'era/a
Ei"ion 1
Pro2e"$ WG-DPEC-1.0 (Cose Loo DFOG)
Pae 1 o *
7/26/2019 WG-DPEC-1.0_FDD(DFOG)
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
Aroved y&
Preared 2y& 3 4 Praad a2u.4,Praada Rao.S, Amit Nahar
6reated on& 7anuary #0, #010
1.:.11.1 n!" an o!"!" signa esri"ion
&.*o Por" name Dire"ion Te ? wi"# Desri"ion
1 RS%LN $N S%DL<8$6 Reet to the ram(eneration module
# ramLenLclH $N S%DL<8$6 #00 43@ clocH inut
* clHL#B $N S%DL<8$6 # B3@ clocH inut or reiterin the ram(inal
" RamL= $N S%DL<8$6L=-6%8RJ*1D8:N%8 0K
PeaH(eaH amlitude o ram(inal
5 teLi@e $N S%DL<8$6L=-6%8RJ*#D8:N%8 0K
Ste(i@e data
RamLReetLctrl 8U% S%DL<8$6 Ram(reet intance outut
C ramLout 8U% S%DL<8$6L=-6%8RJ15D8:N%8 0K
1(2it ram(inal to DA6
%a2le 1*& $nut and 8utut inal o Ram(eneration module
FPGA Firmware Design Do!men"
C!s"omer$ RC+ 'era/a
Ei"ion 1
Pro2e"$ WG-DPEC-1.0 (Cose Loo DFOG)
Pae 1 o *
SUL8U%1 MBodJSte i@eK(=L#iL*#
BodJSte i@eK=L#iL*#
ye
no
SUL8U%1 MBodJSte i@eK
SUL8U%1 MBodJSte i@e#K(=L#iL*#
BodJStei@e#K =L#iL*#
ye
no
SUL8U%1 MBodJSte i@e#K
Stei@e
Poitive Neative
Stei@e
Poitive Neative
RamLintL MRamLintL ' SUL8U%1( =L#iL*#
RamLintL MRamLintL ' SUL8U%1
J=LU%hr(
ramLintL K TMSUL8U%1
ye
no
RamLintL MRamLintL ( SUL8U%1' =L#iL*#
RamLintL MRamLintL ( SUL8U%1
JramLint L (
=L<o!%hrK TMSUL8U%1
ye
no
7/26/2019 WG-DPEC-1.0_FDD(DFOG)
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
Aroved y&
Preared 2y& 3 4 Praad a2u.4,Praada Rao.S, Amit Nahar
6reated on& 7anuary #0, #010
+iure #1& Alorithm or Ram inal eneration
FPGA Firmware Design Do!men"
C!s"omer$ RC+ 'era/a
Ei"ion 1
Pro2e"$ WG-DPEC-1.0 (Cose Loo DFOG)
Pae 1 o *
++1 ++# ++* ++"
Ste i@e
Ste i@e#
= #i *#
Eero SUL1
SULA1
Ste i@e del1 J*#K Ste i@e del* BS
SUL8U%1
**
*#
*#
#
*#
*#
*#
Ste i@e J*#K
*#
*#
#
SUL8U%1
Ste i@e del* BS
=LUL%hr
=L<o!L%hr
= #i *#
Eero
Ram intL
*#
*#
*#
**
*#
*# *#
*#
*#
*#
*#
7/26/2019 WG-DPEC-1.0_FDD(DFOG)
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
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6reated on& 7anuary #0, #010
+iure ##& Pielined imlementation o ram inal eneration
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
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1.:.11.5 Coe esri"ion
%he ollo!in art o =3D< code ive the detail o the imlementation o ram(inal eneration.Ram(inal eaH(eaH amlitude i coniured 2y the uer uin P6 alication. %hi i alo reerred toa =#] JRamL=K. Uer and lo!er threhold o the ram(inal are derived rom =#].
A RamL= i *#(2it value, midL*#2it rereent hal o the manitude o a *#(2it value. Uin theet!o arameter, uer and lo!er threhold value are calculated a ho!n.
midL*#2it TM 01111111111111111111111111111111O=LU%hr TM midL*#2it ' JI0I G RamL=J*1 do!nto 1KKO (( Uer threhold=L<o%hr TM not J=LU%hrKO
Ste(i@e i rotation(rate deendent arameter. Ste(i@e value i in %!o’ comlement ormat, itmanitude i ued or ram(inal interation.Since the DA6 ued or ram(inal outut accet data in 8et 2inary ormat, ram(inal hould 2e inoet 2inary rereentation. %he manitude o te(i@e i etracted 2aed on it in 2it.$ te(i@e i oitive, the manitude o te(i@e i the te(i@e itel.$ te(i@e i neative, the manitude o te(i@e i it %!o comlemented value.%!o’ comlemented value o actual te(i@e data i teLi@eL#Lcm. Ram inal i enerated 2y theinteration o the te(i@e manitude.
teLi@eL#Lcm TM Jnot teLi@e K ' 1O
AL6BP%R TM teLi@eJ*1 do!nto 0K !hen JteLi@eJ*#K M I0IKele teLi@eL#LcmJ*1 do!nto 0KO
%he manitude o te(i@e J AL6BP%RK i comared !ith the ram(inal eaH(eaH amlitude J*#(2it=#]K. aed on the comarator reult reective control SULelLctrl1 are et a ollo!
$ te(i@e i oitive and reater than =#], SULelLctrl1 value i W00X.$ te(i@e i oitive and le than or e;ual =#], SULelLctrl1 value i W01X.$ te(i@e i neative and reater than =#], SULelLctrl1 value i W10X.$ te(i@e i neative and le than or e;ual =#], SULelLctrl1 value i W11X.
%he leat iniicant 2it o SULelLctrl1 i enerated 2aed on comarator.%he mot iniicant 2it o SULelLctrl1 i enerated uin the in o te(i@e. %hi i done to reduceone multileer uae.
roceJRS%LN, ramLenLclHK
2ein i RS%LN M I0I thenSULelLctrl1 TM Jother M I0IKOteLi@eLdel1 TM Jother M I0IKOteLi@eL#Ldel1 TM Jother M I0IKO
eli ramLenLclHIevent and ramLenLclH M I1I theni JAL6BP%R RamL=J*1 do!nto 0KK then
SULelLctrl1J0K TM I0IOele
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
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SULelLctrl1J0K TM I1IOend iOSULelLctrl1J1K TM teLi@eJ*#KOteLi@eLdel1 TM teLi@eOteLi@eL#Ldel1 TM teLi@eL#LcmO
end iOend roceO
$ te(i@e i oitive and reater than =#], SULelLctrl1 value i W00X then the dierence 2et!een te(i@e JmanitudeK and =#] i calculated, !hich !ill 2e ued to enerate ram(inal.
$ te(i@e i oitive and le than or e;ual =#], SULelLctrl1 value i W01X then the ame te(i@eJmanitudeK !ill 2e ued to enerate ram(inal.
$ te(i@e i neative and reater than =#], SULelLctrl1 value i W10X then the dierence 2et!eente(i@e JmanitudeK and =#] i calculated, !hich !ill 2e ued to enerate ram(inal.
$ te(i@e i oitive and le than =#], SULelLctrl1 value i W11X then the ame te(i@e JmanitudeK
!ill 2e ued to enerate ram(inal.
roceJRS%LN, ramLenLclHK2ein
i RS%LN M I0I thenSULA1 TM Jother M I0IKOSUL1 TM Jother M I0IKOteLi@eLdel#LBS TM I0IO
eli ramLenLclHIevent and ramLenLclH M I1I thencae SULelLctrl1 i
!hen 00 MSULA1 TM teLi@eLdel1J*1 do!nto 0KOSUL1 TM RamL=J*1 do!nto 0KO
!hen 01 MSULA1 TM teLi@eLdel1J*1 do!nto 0KOSUL1 TM Jother M I0IKO
!hen 10 MSULA1 TM teLi@eL#Ldel1J*1 do!nto 0KOSUL1 TM RamL=J*1 do!nto 0KO
!hen other MSULA1 TM teLi@eL#Ldel1J*1 do!nto 0KOSUL1 TM Jother M I0IKO
end caeOteLi@eLdel#LBS TM teLi@eLdel1J*#KO
end iOend roceO
roceJRS%LN, ramLenLclHK2ein
i RS%LN M I0I thenSUL8U%1 TM Jother M I0IKOteLi@eLdel*LBS TM I0IO
eli ramLenLclHIevent and ramLenLclH M I1I thenSUL8U%1 TM SULA1 ( SUL1O
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
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teLi@eLdel*LBS TM teLi@eLdel#LBSOend iO
end roceO
%he reult o the a2ove u2traction eciie 2y ho! much te(i@e manitude eceed eaH(eaH
amlitude o ram(inal. %hi !ill 2e ued a the eective te to 2e added to the current level o ram(inal.%he addition o the te to the ram(inal i done 2aed on the in o the te(i@e and uer>lo!er threhold limit.$ Ste(i@e i oitive then reent level o ram(inal i comared !ith uer threhold value, !hileinteration.$ Ste(i@e i neative then reent level o ram(inal i comared !ith lo!er threhold value, !hileinteration.:hile interation !ith te(i@e, once the ram(inal data reach the threhold value, it reet. %hicondition i ued to enerate RamLReetLctrl !hich !ill 2e ued or ram(inal amlitude error controllin.$ AL6BP%R# TM SUL8U%1 then it indicate that the interation o ram(inal !ith te(i@e manitude!ill lead to cro the eaH(eaH amlitude o ram(inal. 3ence their dierence i calculated and ram(
inal i enerated. %hi i ena2led !ith the in conideration o the te(i@e.
AL6BP%R# TM J=LU%hr ( ramLintLK !hen JteLi@eLdel*LBS M I0IK eleJramLintL ( =L<o%hrKO
roceJRS%LN, ramLenLclHK2eini RS%LN M I0I then
ramLintL TM midL*#2itORamLReetLctrl TM I0IO
eli ramLenLclHIevent and ramLenLclH M I1I theni JteLi@eLdel*LBS M I0IK then
i AL6BP%R# TM SUL8U%1 then
ramLintL TM ramLintL ' SUL8U%1 ( RamL=J*1 do!nto 0KORamLReetLctrl TM I1IO
eleramLintL TM ramLintL ' SUL8U%1ORamLReetLctrl TM I0IO
end iOele
i AL6BP%R# TM SUL8U%1 thenramLintL TM ramLintL ( SUL8U%1 ' RamL=J*1 do!nto 0KORamLReetLctrl TM I1IO
eleramLintL TM ramLintL ( SUL8U%1ORamLReetLctrl TM I0IO
end iOend iO
end iOend roceO
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
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1.:.15 7ias signa genera"ion
S;uare !ave ia inal o 10043@ re;uency i enerated. %he 2ia inal amlitude i roortional tothe ram inal amlitude. %he 2ia inal time eriod i roortional to the tranit time eriod.
1.:.15.1 Coe esri"ion
%he amlitude o the 2ia inal can 2e coniured 2y uer over Uart. A ho!n in the code, over a clocH 10043@, the ;uare !ave i enerated.
((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((( ia ;uare !ave eneration(((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((
S;LU%hr TM uLdata#0 G uLdata#1OS;L<o%hr TM uLdata## G uLdata#*OS^L:A=-L12it TM S;LU%hr !hen clHL1004 M I1I ele S;L<o%hrO
(((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((
%hi 1(2it data !ill 2e ed a inut to DA6
1.:.16 &"e-siNe a%erage mo!e
%hi module accumulate the inal te(i@e data over a elective eriod 2y the uer, then averae andthi outut !ill 2e ed to Uart controller or tranmiion.
1.:.16.1 Coe esri"ion
$t i ho!n here the accumulator or the te(i@e. 8ver a eriod o #m the data i accumulated and ater every #m thi accumulator content i reet.
((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((( Averain o the Ste i@e over # m(((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((LavLadder & Lavort ma J
A M teLi@e, M LavL,^ M LavL,6<4 M clHL#004, A6<R M SSLavLclrLule
KO(((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((
%he interal multile o #m 2aed control ule rom the rate(udate module i ued to reet thiaccumulator and to initiate the tranmiion o averaed te(i@e data to P6.
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
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uartLtLel i the control arameter elcetd 2y the uer over uart, 2aed on thi control the roceed dataat dierent tae o thi control chain can 2e uload to P6.
uartLtLel TM uLdata#"J# do!nto 0KO
Selective oet value u2traction rom the te(i@e data 2eore uload to P6. %hi i done to eliminateoet in the data !hile tetin the linearity o the ytem.
teLi@eLtoLUartLintTM LavLJ"0 do!nto 9K (J uLdata#JCK G uLdata#JCK G uLdata#JCK G uLdata#JCK G uLdata#JCK G uLdata#JCK G
uLdata#JCK G uLdata#JCK G uLdata#JCK G uLdata#JCK G uLdata#JCK G uLdata#JCK GuLdata#JCK G uLdata#JCK G uLdata#JCK G uLdata#JCK G uLdata# G uLdata#C
KO
%hi i the multilein loic 2aed on the control uartLtLel.Uin thi multileer, AD6 demodulated data, Ste(i@e o #m averaed data, =#i amlitude data andother re;uired value can 2e uload to P6.
((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((( %hi i UAR% data elector BUF.(((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((
!ith uartLtLelJ# do!nto 0K elect teLi@eLtoLUart TM
(( teLi@eJ*# do!nto 1K !hen 000, (( Deault 5 u(( =J*1 do!nto 0K !hen 000, (( 6hecHin =#i value
=#iL-rrorLcomLval !hen 000, (( =#i error (( D-B8DLR-+Li !hen 001, (( 6hecHin Re(!aveorm
LavLJ"0 do!nto 9K !hen 001,(( # m(( teLi@eLtoLUartLint !hen 001,(( # m
LavLJ"1 do!nto 10K !hen 010,(( " mLavLJ"# do!nto 11K !hen 011, (( ) mLavLJ"* do!nto 1#K !hen 100, (( 1 mLavLJ"" do!nto 1*K !hen 101, (( *# m
(( LavLJ"5 do!nto 1"K !hen 110, (( " mroLoutLint !hen 110, ((LavLJ" do!nto 15K !hen otherO(( 1#) m
(((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((
%hi i the ynchroni@ation loic to enerate the reet ule to the accumulator mentioned a2ove andinitiate trier ule or Uart tranmitter.
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
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:hen rate udate module end #m control inal, uin thi inal a reet(control J SSLavLclrLuleKand trier(control Jtei@eLudateLuleK are enerated.%hi i to enure that the accumulator !ill 2e reet once every #m, only ater it accumulated data i
reitered and then reet !ill 2e iued.
(((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((roceJclHL#B, RS%LNK2ein
i RS%LN M I0I thenuleL#LmLre1 TM I0IOuleL#LmLre# TM I0IOuleL#LmLre* TM I0IOuleL#LmLre" TM I0IO
eli clHL#BIevent and clHL#B M I1I thenuleL#LmLre1 TM uleL#LmOuleL#LmLre# TM uleL#LmLre1OuleL#LmLre* TM uleL#LmLre#OuleL#LmLre" TM uleL#LmLre*O
end iOend roceO
tei@eLudateLule TM uleL#LmLre1 AND JN8% uleL#LmLre#KOSSLavLclrLule TM uleL#LmLre* AND JN8% uleL#LmLre"KO
roceJclHL#B, RS%LNK2ein
i RS%LN M I0I thenteLi@eLtoLUartLre TM Jother M I0IKO
eli clHL#BIevent and clHL#B M I1I then$ Jtei@eLudateLule M I1IK then
teLi@eLtoLUartLre TM teLi@eLtoLUartO
end iO end iOend roceO(((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
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1.:.18 Pio/aNe on"roer
%hi module ued to communicate !ith uer interace over Uart.
+iure #*& <864 D$ARAB o P$68<AE- imlementation 8+ UAR%
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$NP8R%
8U%P8R%
P8R%$D
1
R8B
$N<
A%63
D A %
AL
8 U %
D A % A L $
N
$N%R
ADD Z9&0[DA%A Z1C&0[
0[
P8R%$D1
6BD<
A%631
6S>
A1 A0 A#
RD>:->
>
RFD
%FD
D6B
6%SR%SDSR
D%RSR$
D6D D6D
P8R%$D1#%8#
UDA%A0
%8
UDA%A*1
R-S-%
#5 B3@1.)"*# B3@
$N%R
RFD
6<4
: 7T DATA 7U&
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
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1.:.18.1 Coe esri"ion
UAR% receive data erially rom P6 on RFD inal o +PA.%he received data i availa2le in receive2uer reiter o UAR%.%he Pico 2la@e roceor checH any ne! data availa2le in UAR%.:hen ever ne!data availa2le in UAR% then roceor ?um $SR routine.
&R$
$n interrut ervice routine roceor read tatu reiter o UAR% 2y eecutin read command andoututtin the command on 68BBANDL<A%63L1 inal throuh outK ort inal. and checH !hether DA%A R-AD $% JDR $%K i one or not .:hen ever DR $% i one it read data rom receive 2uer reiter o UAR% throuh $NL<A%63L1 inal in addre decodin loic o roceor imlemented inide+PA.Proceor tore data one o internal reiter named a UAR%LDA%ALR-ADLDA%A.
Proess insie roessor a"er &R$Deendin on ortLid in addre decodin loic o roceor inide +PA outut data to internal inalinide data.
y uin a2ove loic !e enterin *# 2yte data rom P6 to UAR% and roceor oututtin *# 2yte o data on to *# internal inal named a ULDA%A0 to ULDA%A*1.
Proceor and addre decodin loic in +PA and UAR% reiter addre(decodin loic !orHin at #5B3@ clocH re;uency.
Addre Decodin <oic&
roceJRS%LN, cl41K2ein i JrS%LN M I1IK then
commandLlatchL1 TM 11111111O inLort TM 00000000O uLdata0 TM 00000000O uLdata1 TM 00000000O uLdata# TM 00000000O uLdata* TM 00000000O uLdata" TM 00000000O uLdata5 TM 00000000O uLdata TM 00000000O uLdataC TM 00000000O
uLdata) TM 00000000O uLdata9 TM 00000000O uLdata10 TM 00000000O
uLdata11 TM 00000000O uLdata1# TM 00000000O uLdata1* TM 00000000O uLdata1" TM 00000000O uLdata15 TM 00000000O
uLdata1 TM 00000000O uLdata1C TM 00000000O uLdata1) TM 00000000O uLdata19 TM 00000000O
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
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uLdata#0 TM 00000000O uLdata#1 TM 00000000O uLdata## TM 00000000O uLdata#* TM 00000000O
uLdata#" TM 00000000O
uLdata#5 TM 00000000O uLdata# TM 00000000O uLdata#C TM 00000000O uLdata#) TM 00000000O uLdata#9 TM 00000000O uLdata*0 TM 00000000O uLdata*1 TM 00000000O R-S-% TMI0IO
eli JclH1 M I1I and clH1IeventK then i J!riteLtro2e M I1IK then
cae ortLid i
!hen 00000001 M commandLlatchL1 ToutLortO!hen 00001100 M uLdata0 TM outLortO
!hen 00001101 M uLdata1 TM outLortO !hen 00001110 M uLdata# TM outLortO !hen 00001111 M uLdata* TM outLortO !hen 00010000 M uLdata" TM outLortO !hen 00010001 M uLdata5 TM outLortO !hen 00010010 M uLdata TM outLortO
!hen 00010011 M uLdataC TM outLortO !hen 00010100 M uLdata) TM outLortO !hen 00010101 M uLdata9 TM outLortO !hen 00010110 M uLdata10 TM outLortO !hen 00010111 M uLdata11 TM outLortO
!hen 00011000 M uLdata1# TM outLortO !hen 00011001 M uLdata1* TM outLortO !hen 00011010 M uLdata1" TM outLortO !hen 00011011 M uLdata15 TM outLortO !hen 00011100 M uLdata1 TM outLortO !hen 00011101 M uLdata1CTM outLortO !hen 00011110 M uLdata1) TM outLortO !hen 00011111 M uLdata19 TM outLortO !hen 00100000 M uLdata#0 TM outLortO !hen 00100001 M uLdata#1 TM outLortO !hen 00100010 M uLdata## TM outLortO !hen 00100011 M uLdata#*TM outLortO
!hen 00100100 M uLdata#" TM outLortO !hen 00100101 M uLdata#5 TM outLortO !hen 00100110 M uLdata# TM outLortO !hen 00100111 M uLdata#C TM outLortO !hen 00101000 M uLdata#) TM outLortO !hen 00101001 M uLdata#9 TM outLortO !hen 00101010 M uLdata*0 TM outLortO !hen 00101011 M uLdata*1 TM outLortO
FPGA Firmware Design Do!men"
C!s"omer$ RC+ 'era/a
Ei"ion 1
Pro2e"$ WG-DPEC-1.0 (Cose Loo DFOG)
Pae 1 o *
7/26/2019 WG-DPEC-1.0_FDD(DFOG)
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
Aroved y&
Preared 2y& 3 4 Praad a2u.4,Praada Rao.S, Amit Nahar
6reated on& 7anuary #0, #010
!hen other M nullOend caeO
eli JreadLtro2e M I1IK then cae ortLid i
!hen 00000001 M inLort TM inLlatchL1O
!hen other M nullO end caeO
elecommandLlatchL1 TM commandLlatchL1O
end iO end iOend roceO
$n a2ove loic ollo!in are Proessor signas are8utLort& )(2it vector. %hi i ued or outut data rom roceor to internal data inal and to oututcommand inal to UAR%.
inLort& ) 2it vector. +or inut data and tatu o UAR% to roceor orm UAR%.
PortLid& )(2it vector. %hi i ued to elect internal inal to !hich data hould !rite rom outLort o roceor.
:riteLtro2e& inle 2it .%o ive roceor !rite command. Active hih inal.
ReadLtro2e& inle 2it .%o ive roceor read command. Active hih inal.
UART signas&
$nLlacthL1& )(2it vector. Ued to roceor read data or tatu o UAR% throuh thi inal deendin onortLid W00000001X.
6ommandLlatchL1& )(2it vector. Ued to roceor !rite command to UAR% throuh thi inal deendinon ortLid W0000000XO.
Genera signas&
6lH1& i oeratin at #5 B3@.
RtLn& i to reet the decodin loic.
O"#er signas&ULDA%A0 to ULDA%A*1 are ued to tore data enter throuh P6.
Deendin on the ortLid inal any one o ULDA%A inal i elected to tore data
FPGA Firmware Design Do!men"
C!s"omer$ RC+ 'era/a
Ei"ion 1
Pro2e"$ WG-DPEC-1.0 (Cose Loo DFOG)
Pae 1 o *
7/26/2019 WG-DPEC-1.0_FDD(DFOG)
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
Aroved y&
Preared 2y& 3 4 Praad a2u.4,Praada Rao.S, Amit Nahar
6reated on& 7anuary #0, #010
1.:.19 7!e" /rigae FFO
1.:.19.1 7asi FFO mo!e
+iure #"& 1 dee )(2it +$+8
(((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((Fie name $ //ioJ1;I:.%#,o!e $ //ioJ1;I:Use as $ 1; /"e a"a s"orage /!er 3 FFO(((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((68BP8N-N% 22ioL1) i P8R% J dataLin & $N tdLloicLvectorJC do!nto 0KO dataLout & 8U% tdLloicLvectorJC do!nto 0KO reet & $N tdLloicO
!rite & $N tdLloicOread & $N tdLloicO
ull & 8U% tdLloicO halLull & 8U% tdLloicO dataLreent & 8U% tdLloicO clH & $N tdLloicKO -ND 68BP8N-N%O(((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((
1.:.19.5 Desri"ion o FFO or"s
a"aJin $%he Parallel 2yte data to 2e tored in 2uer. %he data !ill 2e catured 2y the 2uer J+$+8K on the
riin ede o the clH durin !hich I!riteI i active.a"aJo!"$
%he Parallel 2yte data !hich ha 2een received. %hi data i valid !hen IdataLreentI i active.rese"$
FPGA Firmware Design Do!men"
C!s"omer$ RC+ 'era/a
Ei"ion 1
Pro2e"$ WG-DPEC-1.0 (Cose Loo DFOG)
Pae 1 o *
7/26/2019 WG-DPEC-1.0_FDD(DFOG)
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
Aroved y&
Preared 2y& 3 4 Praad a2u.4,Praada Rao.S, Amit Nahar
6reated on& 7anuary #0, #010
An active 3$3 inut caue the 2uer to 2e reet and hence all data currently in 2uer to 2e lot.wri"e$
An active 3$3 indicate that the data currently 2ein alied to the IdataLinI ort i to 2e !rittento the internal 2uer on the net riin ede o IclHI. A !rite oeration !ill taHe lace on every riin ede o IclHI on !hich thi inal i active. 3ence thi inal i uled 3$3 or one clocH cycle only, unle ne!
data i alied to IdataLinI every clocH cycle or a 2urt !rite. %he 2uer !ill inore data hould it 2ecomeull.rea$
An active 3$3 indicate that the data rovided at the IdataLoutI ort ha 2een read Jor !ill 2eread on the net riin ede o the ‘clH’K and that 2uer hould maHe the net data availa2le. %he IreadIinut may 2e active or conecutive clocH cycle to erorm a I2urt o dataI. Any attemt to read data !henIdataLreentI i inactive !ill have no eect, 2ut thi illeal cae hould 2e avoided !hen oi2le.!$
:hen the 2uer i ull thi outut 2ecome 3$3. %he hot ytem hould not attemt to !rite untilit return <8:. Any attemt to !rite data !ill mean that ne! data i inored.#aJ!$
:hen 2uer i illed hal or more than hal thi outut 2ecome 3$3. %hi i ueul indication tothe hot ytem that the 2uer i aroachin a ull condition and that it !ould 2e !ie to reduce the rate
at !hich data i 2ein !ritten to the macro.a"aJresen"$
:hen the 2uer contain one or more 2yte o received data thi inal !ill 2ecome active 3$3and valid data !ill 2e availa2le at the IdataLoutI ort.$
Ued 2y all ynchronou element o the macro, thi inal hould 2e rovided via one o thelo2al lo!(He! clocH net!orH and all other inal hould 2e alied and read ynchronouly to thiclocH.
1.:.19.6 FFO /!er siNing
Wa"er "an moe o 7!e" /rigae FFO$%he oeration o a +$+8 can 2e rereented 2y a !ater tanH. Ne! !ater i added at the to, and
the oldet !ater i drained rom the 2ottom. %he i@e o the tanH Jor 2ucHetK mut 2e lare enouh o that itdoe not overlo! at time !hen more !ater i 2ein added at the to than i 2ein drained rom the2ottom. 82viouly !hen a tanH i emty nothin can 2e drained rom the 2ottom. A oon a any !ater iadded at the to then that !ater i availa2le to 2e drained rom the 2ottom.
FPGA Firmware Design Do!men"
C!s"omer$ RC+ 'era/a
Ei"ion 1
Pro2e"$ WG-DPEC-1.0 (Cose Loo DFOG)
Pae 1 o *
7/26/2019 WG-DPEC-1.0_FDD(DFOG)
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
Aroved y&
Preared 2y& 3 4 Praad a2u.4,Praada Rao.S, Amit Nahar
6reated on& 7anuary #0, #010
$t ha 2ecome common ractice or eole to imlement +$+8’ a a inle 2locH o memory o anade;uate i@e to revent overlo!. 3o!ever, ?ut a !ith !ater tanH, uch a techni;ue can oten reult inlare Jor heavyK unit that are diicult to manae and connect u.
+iure #5& :ater %anH Bodel o ucHet riade +$+8
A ‘ucHet riade’ +$+8 i contructed in a orm that i imilar to a erie o maller !ater tanH!hich are connected in a cacaded arranement.
1.:.19.8 Cons"r!"ing 8:I4 FFO !sing "#ree 1;I4 FFOs$
$t i alo called a ")9 2ucHet 2riade +$+8.
FPGA Firmware Design Do!men"
C!s"omer$ RC+ 'era/a
Ei"ion 1
Pro2e"$ WG-DPEC-1.0 (Cose Loo DFOG)
Pae 1 o *
7/26/2019 WG-DPEC-1.0_FDD(DFOG)
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
Aroved y&
Preared 2y& 3 4 Praad a2u.4,Praada Rao.S, Amit Nahar
6reated on& 7anuary #0, #010
+iure #& ")9 +$+8 uin three 1) +$+8 module
1.:.1; UART "ransmi""er ? reei%er
UART maro$
FPGA Firmware Design Do!men"
C!s"omer$ RC+ 'era/a
Ei"ion 1
Pro2e"$ WG-DPEC-1.0 (Cose Loo DFOG)
Pae 1 o *
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
Aroved y&
Preared 2y& 3 4 Praad a2u.4,Praada Rao.S, Amit Nahar
6reated on& 7anuary #0, #010
%he UAR% tranmitter>receiver macro i rovided 2y Filin. %hi i havin the ollo!incharacteritic&
1. 1 tart 2it#. ) data 2it*. 1 arity 2it
". 1 to 2it.%hi macro alo contain a 1 2yte +$+8. %he +$+8 i@e can alo etenda2le 2y cacadin more
2ucHet 2riade +$+8.
7a! ra"e "iming$%hee macro derive the tranmiion and receive timin rom a reerence inal ‘enL1LL2aud’.
A the name uet, thi inal hould 2e alied to the macro at a rate !hich i 1 the deired 2itrate.
Since the inal i ued a a clocH ena2le !ithin the macro, it hould 2e rovided ynchronou tothe clocH and have a ule duration o one clocH cycle only Junle the maimum communication rate o clH>1 i re;uiredK.
-amle&%he 2aud rate re;uired i 19#003@ and the availa2le ytem clocH i 50.#5B3@. %hi can 2e
achieved 2y 50,#5,000 > J1 19#00K M 1".C9"9. %he nearet inteer o 15 i !ell in ece o there;uired tolerance Je;uivalent 2aud rate o 191C3@ !hich i ?ut 0.1#Q lo!K. Any thin !ith in 1Qtolerance i oin to !orH.
((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((( aud %imer eneration or UAR% %F and RF(( 50.#5 B3@ > J1 \ 19#00 2audK M 1".C9 _M 15(( audLcnt& rane 0 to 1". J000 to 0A"K(((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((
PR86-SS JSSL6<4K
-$N$+ JSSL6<4Ievent and SSL6<4 M I1IK %3-N
$+ J2audLcnt M A"K %3-N2audLcnt TM Jother M I0IKOenL1LL2aud TM I1IO
-<S-2audLcnt TM 2audLcnt ' 01OenL1LL2aud TM I0IO
FPGA Firmware Design Do!men"
C!s"omer$ RC+ 'era/a
Ei"ion 1
Pro2e"$ WG-DPEC-1.0 (Cose Loo DFOG)
Pae 1 o *
7/26/2019 WG-DPEC-1.0_FDD(DFOG)
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
Aroved y&
Preared 2y& 3 4 Praad a2u.4,Praada Rao.S, Amit Nahar
6reated on& 7anuary #0, #010
-ND $+O-ND $+O
-ND PR86-SSO
1.:.1;.1 UART Transmi""er wi"# 1;I4 /!er
+iure #C& UAR% tranmitter macro
%hi UAR% tranmitter macro !ill receive arallel data J) data 2it and 1 arity 2itK rom hot andthi data !ill 2e ent erially on ‘erialLout’ line o the macro.
n"erna ar#i"e"!re o UART "ransmi""er$
+iure #)& Architecture o UAR% tranmitter macro
68BP8N-N% uartL19LtP8R% J
dataLin & $N tdLloicLvectorJ) do!nto 0KO!riteL2uer & $N tdLloicO
FPGA Firmware Design Do!men"
C!s"omer$ RC+ 'era/a
Ei"ion 1
Pro2e"$ WG-DPEC-1.0 (Cose Loo DFOG)
Pae 1 o *
7/26/2019 WG-DPEC-1.0_FDD(DFOG)
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
Aroved y&
Preared 2y& 3 4 Praad a2u.4,Praada Rao.S, Amit Nahar
6reated on& 7anuary #0, #010
reetL2uer & $N tdLloicOenL1LL2aud & $N tdLloicOerialLout & 8U% tdLloicO2uerLull & 8U% tdLloicO2uerLhalLull & 8U% tdLloicO
clH & $N tdLloicKO
-ND 68BP8N-N%O
1.).1.1.1 Pin decrition o UAR% tranmitter macro&
Da"aJin$%he arallel data J)(2it data and 1(arity 2itK to 2e tranmitted erially. %he data !ill 2e catured 2y
the +$+8 2uer on ariin ede o the ‘6lH’ durin !hich ‘!riteL2uer’ i active.Wri"eJ/!er$
An active 3$3 indicate that the data currently 2ein alied to the ‘dataLin’ ort i to 2e !rittento the internal 2uer on the net riin ede o ‘6lH’. A !irte oeration !ill taHe alce on every riin clocHede on !hich thi inal i active. 3ence thi inal hould 2e uled 3$3 or one clocH cycle only,unle ne! data alied to ‘dataLin’ every clocH cycle or a ‘2urt !rite’. %he +$+8+ !ill inore data houldit 2ecome ull.Rese"J/!er$
An active 3$3 inut caue the 1(2yte internal 2uer to 2e reet and hence all data currently inthe 2uer to 2e lot. 8eration o thi inal durin erial data tranmiion !ill otentially reult incorruted data.EnJ1;JIJ/a!$
Provide the timin reerence or the erial tranmiion. %hi hould 2e uled 3$3 or one clocHcycle duration only and at a rate !hich i 1 time Jor aroimately 1 timeK the rate at !hich the erialdata tranmiion i to taHe lace. Alternatively, thi inal may 2e et continuouly 3$3 uch that erialdata tranmiion taHe lace at the maimum rate o clH>1 2it er econd.&eriaJo!"$
%hi i the erial data conormin to 1 tart 2it, ) data 2it J<S irtK, 1 arity 2it G 1 to 2it. $naccordance !ith normal UAR% oeration, thi inal i 3$3 in the idle Jno data to tranmitK condition.Serial data tranmiion commence a oon a there i data in the 2uer and continuou !ithoutinterrution Jtart 2it immediately ollo! to 2itK until the 2uer i emty.7!erJ!$
:hen 1(2yte +$+8 2uer i ull, thi outut 2ecome active 3$3. %he hot ytem hould notattemt to !rite any ne! data until the erial tranmiion ha 2een a2le to create a ace Jindicated 2y‘2uerLull’ returnin lo!K. Any attemt to !rite data !ill mean that the ne! data i inored.7!erJ#aJ!$
:hen 1(2yte +$+8 2uer hold eiht or more 2yte o data !aitin to 2e tranmitted, thi outut2ecome active 3$3. %hi i a ueul indication to the hot that the +$+8 2uer i aroachin a ullcondition, and that it !ould 2e !ie to reduce the rate at !hich ne! data i 2ein !ritten to the macro.C$
Ued 2y all ynchronou element o the macro, thi inal hould 2e rovided via one o thelo2al lo!(He! clocH net!orH and all other inal hould 2e alied and read ynchronouly to thiclocH.
1.).1.1.# %imin diaram to !rite data to UAR% tranmit 2uer&
W#en /!er is no" !$
FPGA Firmware Design Do!men"
C!s"omer$ RC+ 'era/a
Ei"ion 1
Pro2e"$ WG-DPEC-1.0 (Cose Loo DFOG)
Pae 1 o *
7/26/2019 WG-DPEC-1.0_FDD(DFOG)
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
Aroved y&
Preared 2y& 3 4 Praad a2u.4,Praada Rao.S, Amit Nahar
6reated on& 7anuary #0, #010
%he +$+8 2uer i ued to accet data or tranmiion !hen !ritten to macro. %he 2uer iautomatically read 2y the ‘Hcuart9Lt’ circuit to a the data to the erial line. Data i !ritten to the 2uer on the riin ede o clocH !hen ‘!riteL2uer’ inal i active. Data can 2e !ritten in iolation, or in a 2urto everal 2yte.
+iure #9& %imin characteritic o UAR% % !hen 2uer i not ull
W#en /!er is !$
:hen the +$+8 2uer 2ecome ull, the ‘2uerLull’ inal !ill 2e aerted. %hi inal !ill remainaerted until the arity 2it o the currently 2ein tranmitted data i comlete Ji.e. once the net to 2it i2ein tranmittedK. No data can 2e !ritten to the 2uer !hen it i ull.
+iure *0& %imin characteritic o UAR% % !hen 2uer i ull
FPGA Firmware Design Do!men"
C!s"omer$ RC+ 'era/a
Ei"ion 1
Pro2e"$ WG-DPEC-1.0 (Cose Loo DFOG)
Pae 1 o *
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
Aroved y&
Preared 2y& 3 4 Praad a2u.4,Praada Rao.S, Amit Nahar
6reated on& 7anuary #0, #010
1.:.1;.5 UART Reei%er wi"# 1;I4 /!er$
+iure *1& UAR% receiver macro
%hi UAR% receiver macro !ill receive erial data J) data 2it and 1 arity 2itK rom erial line. %hereceived 9 2it data !ill 2e availa2le on ‘dataLout’ ort throuh a 1(2yte +$+8 2uer.
n"erna ar#i"e"!re o UART reei%er$
+iure *#& Architecture o UAR% receiver macro
68BP8N-N% uartL19LrP8R% J
erialLin & $N tdLloicOdataLout & 8U% tdLloic Lvector J) do!nto 0KreadL2uer & $N tdLloicOreetL2uer & $N tdLloicOenL1LL2aud & $N tdLloicO2uerLdataLreent & 8U% tdLloicO
2uerLull & 8U% tdLloicO2uerLhalLull & 8U% tdLloicOclH & $N tdLloicKO
-ND 68BP8N-N%O
1.).1.#.1 Pin decrition o UAR% tranmitter macro
FPGA Firmware Design Do!men"
C!s"omer$ RC+ 'era/a
Ei"ion 1
Pro2e"$ WG-DPEC-1.0 (Cose Loo DFOG)
Pae 1 o *
7/26/2019 WG-DPEC-1.0_FDD(DFOG)
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
Aroved y&
Preared 2y& 3 4 Praad a2u.4,Praada Rao.S, Amit Nahar
6reated on& 7anuary #0, #010
&eriaJin$%hi i the erial data conormin to 1 tart 2it, ) data 2it J<S irtK, 1 arity 2it G 1 to 2it. $n
accordance !ith normal UAR% oeration thi inal i 3$3 in the idle condition. %he allin edeaociated !ith a tart 2it i ued to identiy the 2einnin o a erial tranmiion and the ‘enL1LL2aud’
i ued to determine the timin o the traner. 8nce a comlete erial traner ha 2een received !ith avalid to 2it, it i automatically !ritten to the +8++8 2uer Junle the 2uer i ullK.Da"aJo!"$
%he arallel data J9(2itK, !hich ha 2een received. %hi data i valid !hen ‘2uerLdataLreent’ iactive.ReaJ/!er$
An active 3$3 inut indicate that the data rovided at the ‘dataLout’ ort ha 2een read Jor !ill2e read on the net riin ede o ‘clH’K and that the +$+8 hould maHe the net availa2le data availa2le.%he ‘readL2uer’ inut may 2e active or conecutive clocH cycle to erorm a ‘2urt’ o data. Any attemtto read data !hen ‘2uerLdataLreent’ i inactive !ill have no eect, 2ut thi illeal cae hould 2eavoided !hen oi2le.Rese"J/!er$
An active 3$3 inut caue the 1(2yte internal 2uer to 2e reet and hence all data currently in
the 2uer to 2e lot.EnJ1;JIJ/a!$
Provide the timin reerence or the erial tranmiion. %hi hould 2e uled 3$3 or one clocHcycle duration only and at a rate !hich i 1 time Jor aroimately 1 timeK the rate at !hich the erialdata tranmiion i to taHe lace. Alternatively, thi inal may 2e et continuouly 3$3 uch that erialdata tranmiion taHe lace at the maimum rate o clH>1 2it er econd.7!erJa"aJresen"$
:hen the internal 2uer contain one or more 2yte o received data thi inal !ill 2ecome 3$3and valid data !ill 2e availa2le at the ‘dataLout’ ort. 7!erJ!$
:hen 1(2yte +$+8 2uer i ull, thi outut 2ecome active 3$3. %he hot ytem hould raidlyreond to thi condition 2y readin ome data rom the 2uer o that urther erial data i not lot.7!erJ#aJ!$
:hen 1(2yte +$+8 2uer hold eiht or more 2yte o data !aitin to 2e read, thi outut2ecome active 3$3. %hi i a ueul indication to the hot ytem that the +$+8 2uer i aroachin aull condition, and that it !ould 2e !ie to read ome data in the very near uture.C$
Ued 2y all ynchronou element o the macro, thi inal hould 2e rovided via one o thelo2al lo!(He! clocH net!orH and all other inal hould 2e alied and read ynchronouly to thiclocH.
1.).1.#.# %imin diaram to read data rom UAR% receive 2uer&
FPGA Firmware Design Do!men"
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
Aroved y&
Preared 2y& 3 4 Praad a2u.4,Praada Rao.S, Amit Nahar
6reated on& 7anuary #0, #010
Wi"# a"a resen"$:hen data i reent J‘2uerLdataLreent’ M 1K, individual or 2urt read can 2e made rom the
+$+8 2uer.
+iure **& %imin characteritic o UAR% R !ith data reent
W#en /!er is !$%he +$+8 2uer i automatically !ritten 2y the ‘Hcuart9Lr’ circuit a each valid erially tranmitted
‘character’ i catured 2y the receiver. Data i !ritten to the 2uer a oon a the to 2it ha 2eenconirmed a 2ein hih, 2ut only i the 2uer i not ull.
+iure *"& %imin characteritic o UAR% R !hen 2uer i ull
$t can 2e een a2ove that !hen the +$+8 2uer 2ecome ullO it doen’t actually revent the net‘character’ rom 2ein received. %hereore the hot ytem ha the time aociated !ith eleven erial 2itto read at leat one 2yte rom the +$+8 2eore data i actually mied.
FPGA Firmware Design Do!men"
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
Aroved y&
Preared 2y& 3 4 Praad a2u.4,Praada Rao.S, Amit Nahar
6reated on& 7anuary #0, #010
1.:.1;.6 Uoaing 6-aIes ro"a"ion ra"e a"a "o PC !sing singe UART
+iure *5& Bater lave communication cheme
Comm!nia"ion /e"ween "#ree /oars ? PC&%o uload *(ae data uin inle UAR%, !e are uin mater>lave communication techni;ue. 3ere *(
ae data mean, data rom three :(DP-6(1.0 2oard. Amon thee three, one 2oard i ued a mater and the other a lave. A ho!n in the a2ove iure, mater 2oard i havin one Pico2la@e roceor to
communicate !ith lave and P6 throuh UAR%.
Design e"ais o mas"er omm!nia"ion&
FPGA Firmware Design Do!men"
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Ei"ion 1
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Pae 1 o *
Pico 2la@eRdLtro2e
:rLtro2e
8utLort$nLort
) )) )
)
)
)
)
)
)
)
Slv1Ldata
Slv#Ldata
BaterLdataL0
BaterLdataL1
BaterLdataL#
BaterLdataL*
SlvLdatareentPortLid
SyncLule
uartLtLdata
UAR%R
J19+$+8K
Slv1LRD Slv1Ldata
SlvLdatareentJ0K
audLenLule
UAR%R
J19+$+8K
Slv#LRD Slv#Ldata
SlvLdatareentJ1K
audLenLule
)
$nterrutPortLid Decoder
6e1
6e#
6e1
6e#
UAR%%
J19+$+8K
uartL%DUartLtLdata
)audLenLule
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
Aroved y&
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6reated on& 7anuary #0, #010
%he mater 2oard !ill communicate !ith the other t!o lave 2oard uin t!o UAR% ort. %!o 19 +$+82aed UAR% R module are ued to communicate !ith t!o lave and one 19 +$+8 2aed UAR% %module to end *(ae rotation rate data to P6. A ynchroni@in ule !ill 2e iued to t!o lave 2oard toynchroni@e the data communication 2et!een mater and lave 2oard.
+unctionality o Pico2la@e&1. # mec ule enerated 2y the mater !ill 2e ued a interrut to the Pico2la@e.#. Pico2la@e !ill end rotation rate data o mater and lave in the ollo!in ormat.
3eader JAAhK Bater data J"2yteK Slave(1 dataJ"2yteK
Slave(# dataJ"2yteK
*. :ith every interrut Pico2la@e !ill end a header JAAhK to P6 throuh UAR% % and then materand lave data J"(2yte eachK.
". :hile endin mater data to P6, Pico2la@e !ill read *#(2it J"(yteK rotation rate data rom it’inut ort and ent to P6 throuh UAR% %.
5. Ater endin mater data to P6, Pico2la@e !ill read lave(1 data rom one o t!o UAR% Rmodule and thi data !ill 2e ent to P6.
. Similarly, lave(# data !ill alo ent to P6.
C. :hile readin data rom lave, Pico2la@e !ill read the tatu o UAR% R 2uer to checH thereence o data. Readin WSlvLdatareentX inut ort o Pico2la@e !ould do thi.
). UAR% R 2uer o t!o lave !ill have 5(2yte o data i.e. header and "(2yte o rotation ratedata. :hile readin Pico2la@e !ill irt read the header o thoe ive 2yte. $ the header i 0AAthen Pico2la@e !ill end the remainin "(2yte to P6.
9. $ the header i not 0AA, then, Pico2la@e !ill end "(2yte o @ero to P6 or that articular lave. Ater endin @ero, the UAR% R 2uer !ill 2e luhed out until it’ data reent inal 2ecome@ero.
10. Ater endin *(ae data to P6, Pico2la@e JBaterK !ill iue a ynchroni@ation ule to it’ t!olave to re;uet net rotation rate data to 2e ent to P6.
FPGA Firmware Design Do!men"
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
Aroved y&
Preared 2y& 3 4 Praad a2u.4,Praada Rao.S, Amit Nahar
6reated on& 7anuary #0, #010
1.4 ,emor managemen"
& *o F!n"ion &iNe o memor(e"# I /i"s)
Te o memor
1 Demodulation reerence inal #0 *# locH ram coniured a R8B
# Uart tate machine loic #4 ) +inite State Bachine laced inlocH ram
* 1000 amle torae +$+8 o Bovin averae ilter ection
14 1 locH ram
" #0 amle torae +$+8 o =#icontrol chain
14 1 locH ram
5 Uart tranmitter +$+8 1 9 <U% ram
Uart receiver +$+8 1 9 <U% ram
C Proram memory o Pico(2la@econtroller
14 1) locH ram
%a2le 1"& +PA Bemory utili@ation
FPGA Firmware Design Do!men"
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
Aroved y&
Preared 2y& 3 4 Praad a2u.4,Praada Rao.S, Amit Nahar
6reated on& 7anuary #0, #010
1.10 Timing an seK!ene iagrams
1.10.1 Timing #ara"eris"is o Pio/aNe in!"s an o!"!"s wi"# rea an wri"e s"ro/es
+iure *& Accein Pico2la@e $nut and 8utut
1.10.5 Timing #ara"eris"is o UART "ransmi""er an reei%er
1.10.5.1 Timing #ara"eris"is o UART TI w#en /!er is no" !
+iure *C& %imin characteritic o UAR% % !hen 2uer i not ull
FPGA Firmware Design Do!men"
C!s"omer$ RC+ 'era/a
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
Aroved y&
Preared 2y& 3 4 Praad a2u.4,Praada Rao.S, Amit Nahar
6reated on& 7anuary #0, #010
1.10.5.5 Timing #ara"eris"is o UART TI w#en /!er is !
+iure *)& %imin characteritic o UAR% % !hen 2uer i ull
1.10.5.6 Timing #ara"eris"is o UART RI wi"# a"a resen"
+iure *9& %imin characteritic o UAR% R !ith data reent
1.10.5.8 Timing #ara"eris"is o UART RI w#en /!er is !
+iure "0& %imin characteritic o UAR% R !hen 2uer i ull
FPGA Firmware Design Do!men"
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
Aroved y&
Preared 2y& 3 4 Praad a2u.4,Praada Rao.S, Amit Nahar
6reated on& 7anuary #0, #010
1.10.6 Timing #ara"eris"is o ADC
+iure "1& AD6 data read timin
1.10.8 Timing #ara"eris"is o DAC
+iure "#& DA6 timin
FPGA Firmware Design Do!men"
C!s"omer$ RC+ 'era/a
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
Aroved y&
Preared 2y& 3 4 Praad a2u.4,Praada Rao.S, Amit Nahar
6reated on& 7anuary #0, #010
1.11 Da"a ow iagram
+iure "*& Data lo! diaram
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Demo!a"or ,!"iier
FR ,o%ingA%erage
Fi"er
&"e-siNen"egra"or
RamGenera"or
DACADC
7iasing&igna
Genera"or
DAC
ReerenesK!are wa%e
UARTTI3RI
'O&T
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
Aroved y&
Preared 2y& 3 4 Praad a2u.4,Praada Rao.S, Amit Nahar
6reated on& 7anuary #0, #010
1.15 ReK!iremen" maing
& *o ReK!ire seiia"ion ,ae "o FDD
1 ia inal eneration. 10043@;uare !ave
ia inal eneratorJReer to the Section).1#K
# Ram inal eneration. 0(10043@.
Ram inaleneration JReer tothe Section ).11K
* and!idth o 150 3@ at # m oututudate rate
Rate udate moduleJReer to the Section
).#K" %emerature enor outut
5 Synchroni@ation ule romnaviation 2oard
%a2le 15& Re;uirement main
FPGA Firmware Design Do!men"
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
Aroved y&
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6reated on& 7anuary #0, #010
1.16 AeniI
1.16.1 Pio/aNe roessor$
1.16.1.1 Fea"!res o Pio/aNe roessor$
• 1 2yte(!ide eneral(uroe data reiter.
• 14 intruction o roramma2le on(chi roram tore, automatically loaded durin +PA
coniuration.
• yte(!ide Arithmetic <oic Unit JA<UK !ith 6ARR and E-R8 indicator la.
• "(2yte internal cratchad RAB. $t i etenda2le u to #5 2yte.
• #5 inut and #5 outut ort or eay eanion and enhancement.
• Automatic *1(location 6A<<>R-%URN tacH.
• Predicta2le erormance, al!ay t!o clocH cycle er intruction, u to "" B$PS in Sartan(*
+PA.
• +at interrut reoneO !ort(cae 5 clocH cycle.• 8timi@ed or Filin Sartan(*, =irte($$, and =irte($$ Pro +PA architecture`?ut9 lice and
0.5 to 1 2locH RAB.
• Aem2ler, intruction(et imulator uort.
1.16.1.5 Pio/aNe an i"s rogram RO, in"erae$
46PSB* i a very imle )(2it R$S6 microcontroller rimarily or the Sartan(* device. Althouhit could 2e ued or rocein o data, it i mot liHely to 2e emloyed in alication re;uirin a comle,2ut non(time critical tate machine. 3ence it ha the name o WJ4K contant 6oded Proramma2le StateBachineX. %hi 46PSB* re;uire ?ut 9 lice o +PA. %oether !ith thi mall amount o loic, a inle2locH RAB i ued to orm a R8B tore or a roram o u to 10#" intruction. -ven !ith uch i@econtraint, the erormance i reecta2le at aroimately "* to B$PS deendin on device tye andeed rade.
FPGA Firmware Design Do!men"
C!s"omer$ RC+ 'era/a
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
Aroved y&
Preared 2y& 3 4 Praad a2u.4,Praada Rao.S, Amit Nahar
6reated on& 7anuary #0, #010
%he Pico2la@e microcontroller core i totally em2edded !ithin the taret +PA and re;uire no eternalreource. %he Pico2la@e microcontroller i etremely lei2le. %he 2aic unctionality i eaily etendedand enhanced 2y connectin additional +PA loic to the microcontroller’ inut and outut ort.
%he Pico2la@e microcontroller i delivered a ynthei@a2le =3D< ource code, the core i uture(roo and can 2e mirated to uture +PA architecture, eectively eliminatin roduct o2olecence
ear. ein interated !ithin the +PA, the Pico2la@e microcontroller reduce 2oard ace, dein cot,and inventory.
1.16.1.6 CP&,6 3 Pio/aNe ar#i"e"!re$
1.16.1.8 Pio/aNe ,iroon"roer F!n"iona 7os$
1.1*.1.".1 eneral(Puroe Reiter&
• 1 2yte(!ide.
• Deinated a reiter s0 throuh sF.
• %hey can 2e renamed uin an aem2ler directive or 2etter roram clarity.
•
All reiter oeration are comletely interchanea2le.
• No reiter are reerved or ecial taH or have riority over any other reiter
• %here i no dedicated accumulatorO each reult i comuted in a eciied reiter.
1.1*.1.".# 1,0#"($ntruction Proram Store&
• -ecute u to 1,0#" intruction rom memory !ithin the +PA.
• -ach Pico intruction i 1) 2it !ide, comiled !ithin the +PA dein and automatically loaded
durin the +PA coniuration roce.
FPGA Firmware Design Do!men"
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
Aroved y&
Preared 2y& 3 4 Praad a2u.4,Praada Rao.S, Amit Nahar
6reated on& 7anuary #0, #010
1.1*.1.".* Arithmetic <oic Unit JA<UK&
• aic arithmetic oeration uch a addition and u2traction.
• it!ie loic oeration uch a AND, 8R, and F8R.
• Arithmetic comare and 2it!ie tet oeration.
•6omrehenive hit and rotate oeration.
• Reiter F contain irt oerand and or an )(2it immediate contant HH contain the econd
oerand, the reult i tored in the reiter F.
1.1*.1."." +la&
• A<U oeration aect the E-R8 and 6ARR la.
• E-R8 la indicate !hen the reult o the lat oeration reulted in @ero.
• %he 6ARR la indicate variou condition, deendin on the lat intruction eecuted.
• %he $N%-RRUP%L-NA<- la ena2le the $N%-RRUP% inut.
1.1*.1.".5 "(yte Scratchad RAB&
• $t i directly or indirectly addrea2le rom the reiter ile uin the S%8R- and +-%63
intruction.
• %he S%8R- intruction !rite the content o any o the 1 reiter to any o the " RAB
location.
• %he comlementary +-%63 intruction read any o the " memory location into any o the 1
reiter.
1.1*.1.". $nut>8utut&
• Suort u to #5 inut ort.
• P8R%L$D outut rovide the ort addre.
• Durin an $NPU% oeration, the Pico2la@e microcontroller read data rom the $NLP8R% ort to a
eciied reiter, F.
• Durin an 8U%PU% oeration, the Pico2la@e microcontroller !rite the content o a eciied
reiter, F, to the 8U%LP8R% ort.
1.1*.1.".C Proram 6ounter JP6K&
• P6 al!ay oint to the net intruction to 2e eecuted.
• P6 al!ay increment to the net intruction unle encountered 2y 7UBP, 6A<<, R-%URN, and
R-%URN$ intruction or $nterrut and reet event.
• 10(2it P6 uort a maimum code ace o 1,0#" intruction J000 to *++ heK.
• $ the P6 reache the to o the memory at *++ he, it roll over to location 000.
1.1*.1.".) Proram +lo! 6ontrol&
• Any deault eecution e;uence o the roram can 2e modiied uin conditional and non(
conditional roram lo! control intruction.• 6A<< and R-%URN intruction rovide u2routine acilitie or commonly ued ection o code.
• 7UBP intruction eciy an a2olute addre any!here in the 1,0#"(intruction roram ace.
• 6A<< intruction eciie the a2olute tart addre o a u2routine, !hile the return addre i
automatically reerved on the 6A<<>R-%URN tacH.
• $ the interrut inut i ena2led, an $nterrut -vent alo reerve the addre o the reemted
intruction on the 6A<<>R-%URN tacH !hile the P6 i loaded !ith the interrut vector, *++ he.
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
Aroved y&
Preared 2y& 3 4 Praad a2u.4,Praada Rao.S, Amit Nahar
6reated on& 7anuary #0, #010
• R-%URN$ intruction intead o the R-%URN intruction i ued to return rom the interrut ervice
routine J$SRK.
1.1*.1.".9 6A<<>R-%URN StacH&
•
6A<<>R-%URN hard!are tacH tore u to *1 intruction addree, ena2lin neted 6A<<e;uence u to *1 level dee.
• Since the tacH i alo ued durin an interrut oeration, at leat one o thee level hould 2e
reerved !hen interrut are ena2led.
• %he tacH i imlemented a a earate cyclic 2uer.
• :hen the tacH i ull, it over!rite the oldet value. No roram memory i re;uired or the tacH.
1.1*.1.".10$nterrut&
• Pico2la@e B6U ha an otional $N%-RRUP% inut, allo!in the B6U to handle aynchronou
eternal event. Aynchronou event reer to interrut occurrin at any time durin theintruction cycle.
• enerally, all inut to Pico2la@e are ynchroni@ed uin clocH inut.
1.1*.1.".11Reet&
• %he Pico2la@e microcontroller i automatically reet immediately ater the +PA coniuration
roce comlete.
• Ater coniuration, the R-S-% inut orce the roceor into the initial tate.
• %he P6 i reet to addre 0, the la are cleared, interrut are dia2led, and the
6A<<>R-%URN tacH i reet.
• %he data reiter and cratchad RAB are not aected 2y Reet.
1.16.1.9 Pio/aNe n"erae onne"ions
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
Aroved y&
Preared 2y& 3 4 Praad a2u.4,Praada Rao.S, Amit Nahar
6reated on& 7anuary #0, #010
1.16.1.; Pio/aNe n"erae &igna Desri"ions
1.16.1.< Pio/aNe 3 CP&,6 ns"r!"ion &e"
1.1*.1.C.1 Proram 6ontrol rou
7UBP aaa
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
Aroved y&
Preared 2y& 3 4 Praad a2u.4,Praada Rao.S, Amit Nahar
6reated on& 7anuary #0, #010
7UBP E, aaa7UBP NE, aaa7UBP 6, aaa7UBP N6, aaa
6A<< aaa6A<< E, aaa6A<< NE, aaa6A<< 6, aaa6A<< N6, aaa
R-%URNR-%URN ER-%URN NER-%URN 6R-%URN N6
1.1*.1.C.# Arithmetic rou
ADD F, HH ADD6 F, HHSU F, HHSU6 F, HH68BPAR- F, HH
ADD F, ADD6 F, SU F, SU6 F, 68BPAR- F,
1.1*.1.C.* <oical rou<8AD F, HH AND F, HH8R F, HHF8R F, HH%-S% F, HH
<8AD F, AND F, 8R F, F8R F, %-S% F,
1.1*.1.C." Shit and Rotate rou
SR0 FSR1 FSRF FSRA FRR F
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
Aroved y&
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6reated on& 7anuary #0, #010
S<0 FS<1 FS<F FS<A FR< F
1.1*.1.C.5 $nterrut rou
R-%URN$ -NA<-R-%URN$ D$SA<-
-NA<- $N%-RRUP%D$SA<- $N%-RRUP%
1.1*.1.C. Storae rou
S%8R- F, S%8R- F, JK+-%63 F,
+-%63 F, JK
1.1*.1.C.C $nut>8utut rou
$NPU% F, $NPU% F, JK8U%PU% F, 8U%PU% F, JK
Note that call and return uort u to a tacH deth o *1.
1.16.1.: Timing Diagram o Rea an Wri"e &"ro/es
1.16.1.4 Assem/er in!" ? o!"!" ies
$t ha our inut ile and 15 outut ile.
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
Aroved y&
Preared 2y& 3 4 Praad a2u.4,Praada Rao.S, Amit Nahar
6reated on& 7anuary #0, #010
+urther more detail o Pico2la@e roceor reer U1#9, ulied 2y Filin.
1.16.5 EI"ene sra"# a Pio/aNe$ (59; /"e sra"# a memor)
Pico2la@e roceor ha 1)(2it intruction lenth. -ach command !ill it into thee 1)(2it. S%8R-
G +-%63 intruction are ued to acce cratch ad memory. 8(code orani@ation o S%8R- G +-%63intruction are a ollo!&
+rom the a2ove iure it i clear that th G C th 2it are not ued in S%R8- and +-%63 command,a it re;uire only (2it to acce "(2yte cratch ad RAB. $ thee t!o 2it alo ued to acce thecratch ad RAB a #5 2yte cratch ad RAB can 2e accei2le 2y the Pico2la@e.
%o do thi a ecial aem2ler i needed. %hi aem2ler i ulied 2y Filin.
46PSB* code i havin only " 2yte cratch ad memory. %he ollo!in art o 46PSB*.vhdcode i to orm a " 2yte cratch ad memory.
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
Aroved y&
Preared 2y& 3 4 Praad a2u.4,Praada Rao.S, Amit Nahar
6reated on& 7anuary #0, #010
(((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((A ;8I1 RA, is !se wi"# Qgenera"e s"a"emen"+ "o ge" a ;8I: sra"# a RA,.(((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((toreLloo& or i in 0 to C enerate ((
(( Attri2ute to deine RAB content durin imlementation(( %he inormation i reeated in the eneric ma or unctional imulation
((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((( attri2ute $N$% & trinOattri2ute $N$% o memoryL2it & la2el i 0000000000000000O(((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((
2ein memoryL2it& RAB"F1S ((ynthei tranlateLo eneric maJ$N$% M F0000000000000000K ((ynthei tranlateLon ort ma J D M JiK, :- M memoryLena2le,
:6<4 M clH, A0 M econdLoerandJ0K, A1 M econdLoerandJ1K, A# M econdLoerandJ#K, A* M econdLoerandJ*K, A" M econdLoerandJ"K, A5 M econdLoerandJ5K, 8 M memoryLdataJiKKO ((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((( toreLlo& +D ort ma J D M memoryLdataJiK, ^ M toreLdataJiK, 6 M clHKO
((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((( end enerate toreLlooO(((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((
%he ollo!in modiication are needed to the 46PSB*.vhd module to increae the cratch adi@e. A #5) RAB i re;uired or thi.(((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((A 59;I1 RA, !sing is"ri/!"e ogi reso!res. Deare "#is omonen".(((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((comonent 46PSBLcratchL#5F1SenericJ$N$%& 2itLvectorJ#55 do!nto 0K&M JotherMI0IKKOort J
D & in tdLloicO
:- & in tdLloicO:6<4 & in tdLloicO A0 & in tdLloicO A1 & in tdLloicO A# & in tdLloicO A* & in tdLloicO A" & in tdLloicO A5 & in tdLloicO
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
Aroved y&
Preared 2y& 3 4 Praad a2u.4,Praada Rao.S, Amit Nahar
6reated on& 7anuary #0, #010
A & in tdLloicO AC & in tdLloicO8 & out tdLloicKO
end comonentO
(((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((-- C#ange oowing moiia"ions "o "#e CP&,6 oe. n ar#i"e"!re /o.(((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((toreLloo& or i in 0 to C enerate((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((( Attri2ute to deine RAB content durin imlementation(( %he inormation i reeated in the eneric ma or unctional imulation(((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((attri2ute $N$% & trinOattri2ute $N$% o memoryL2it & la2el i0000000000000000000000000000000000000000000000000000000000000000O(((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((2ein
(((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((memoryL2it& 46PSBLcratchL#5F1S((ynthei tranlateLo eneric maJ$N$% M F0000000000000000000000000000000000000000000000000000000000000000K((ynthei tranlateLonort ma JD M JiK,
:- M memoryLena2le,:6<4 M clH, A0 M econdLoerandJ0K, A1 M econdLoerandJ1K, A# M econdLoerandJ#K, A* M econdLoerandJ*K, A" M econdLoerandJ"K,
A5 M econdLoerandJ5K, A M econdLoerandJK, AC M econdLoerandJCK,8 M memoryLdataJiK KO(((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((
toreLlo& +D ort ma J D M memoryLdataJiK,
^ M toreLdataJiK,6 M clHKO
(((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((end enerate toreLlooO
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
Aroved y&
Preared 2y& 3 4 Praad a2u.4,Praada Rao.S, Amit Nahar
6reated on& 7anuary #0, #010
1.16.6 De%ie !"iiNa"ion o FPGA (BC5V590-8C&188)
De%ie U"iiNa"ion &!mmar
Logi U"iiNa"ion Use A%aia/e U"iiNa"ion
To"a *!m/er &ieRegis"ers 1,#* *,0C# "0Q
Num2er ued a +li +lo 1,#*#
Num2er ued a <atche "
Num2er o " inut <U% 1,"0 *,0C# 5*Q
Logi Dis"ri/!"ion
Num2er o occuied Slice 1,1)) 1,5* CCQ
Num2er o Slicecontainin only related
loic 1,1)) 1,1)) 100QNum2er o Slicecontainin unrelated loic 0 1,1)) 0Q
To"a *!m/er o 8 in!"LUTs 1,C1# *,0C# 55Q
Num2er ued a loic 1,51
Num2er ued a a route(thru C#
Num2er ued or Dual PortRAB 1
Num2er ued or *#1RAB 5#
Num2er ued a Shitreiter 11
Num2er o 2onded $8
Num2er o 2onded * 9# )Q
$8 +li +lo 1
Num2er o RAB1 19 #" C9Q
Num2er o BU<%1)F1) 5 #" #0Q
Num2er o U+BUF ) 1 50Q
Num2er o D6B 1 ) 1#Q
Num2er o RPB macro *
%a2le 1& +PA reource utili@ation
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WAVELET GROUP
Unit No. 10, Plot No. 59, ‘Amchi’ colony,Survey No. 1, NDA Road, a!dhan, Pune "11
0#1, $ND$A%el& '91(#0(##9519)*,##9519)", ##9519)5+a& '91(#0(##95190"-(mail& ino/!aveletrou.com
Aroved y&
Preared 2y& 3 4 Praad a2u.4,Praada Rao.S, Amit Nahar
6reated on& 7anuary #0, #010
1.16.8 FPGA Pin !"iiNa"ion
&igna name Pin name
Co signas6<4 A
UAR%L6<4 DC
Rese" signa
R-S-%L%8PLN 4C
Tes" signas
%-S%1 <#
%-S%# <*
Uar" signas
%FDL%8P 4"
RFDL%8P B"
ADC in"erae signas
AD6LR-S-% A" AD6LUS D5
AD6L6S A5
AD6LPD# D
AD6LRD 6
AD6L68N=S%
AD6LDA%AT0 D*
AD6LDA%AT1 D#
AD6LDA%AT# D1
AD6LDA%AT* -"
AD6LDA%AT" -*
AD6LDA%AT5 -#
AD6LDA%AT +"
AD6LDA%ATC +#
AD6LDA%AT) +1
AD6LDA%AT9 1
AD6LDA%AT10 *
AD6LDA%AT11 "
AD6LDA%AT1# *
AD6LDA%AT1* A*
AD6LDA%AT1" 6"
AD6LDA%AT15 "
DAC1 in"erae signas
DA61L6<4 ACDA%AL%8LDA61T0 41#
DA%AL%8LDA61T1 <1*
DA%AL%8LDA61T# 411
DA%AL%8LDA61T* 410
DA%AL%8LDA61T" 71*
DA%AL%8LDA61T5 41*
DA%AL%8LDA61T 311
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DA%AL%8LDA61TC 710
DA%AL%8LDA61T) 1#
DA%AL%8LDA61T9 1*
DA%AL%8LDA61T10 11
DA%AL%8LDA61T11 31#DA%AL%8LDA61T1# +1#
DA%AL%8LDA61T1* -1*
DA%AL%8LDA61T1" 10
DA%AL%8LDA61T15 +11
DAC5 in"erae signas
DA6#L6<4 C
DA%AL%8LDA6#T0 -11
DA%AL%8LDA6#T1 -10
DA%AL%8LDA6#T# D1#
DA%AL%8LDA6#T* D1*
DA%AL%8LDA6#T" D10
DA%AL%8LDA6#T5 610DA%AL%8LDA6#T D11
DA%AL%8LDA6#TC 61*
DA%AL%8LDA6#T) A10
DA%AL%8LDA6#T9 10
DA%AL%8LDA6#T10 69
DA%AL%8LDA6#T11 D9
DA%AL%8LDA6#T1# D)
DA%AL%8LDA6#T1* 6)
DA%AL%8LDA6#T1" A)
DA%AL%8LDA6#T15 )
%a2le 1C& +PA Pin detail
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