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Wild Circuits
Investigating the Limits of MIN/MAX/AVG Circuits
Brendan Juba
Faculty Advisor: Manuel BlumGraduate Mentor: Ryan Williams
Definitions: MIN/MAX/AVG Circuits
We are given a circuit, C, with feedback, operating on real numbers from the closed interval [0,1].
C contains MIN, MAX, or AVG gates with two inputs “Inputs” to the circuit that are hard-wired to
either 0 or 1. |C| denotes the number of gates of C
Here, |C| = 3 When the output of a gate is the
appropriate function of its inputs, we say that the gate is satisfied
MAX
AVG
MIN
1 0
0
0
0
unsatisfied
satisfied
satisfied
Definitions: MIN/MAX/AVG Circuits
Settings of the gate outputs from the interval [0,1] are value vectors A value vector for C, v [0,1]|C|
The ith entry, vi, is the output of the ith gate. This is an implicit ordering of the gates of C
We may also consider an update function, F: [0,1]|C| [0,1]|C|
A single-gate update function replaces the output of a single designated gate with the correct output value.
We will call iterating over the single gate update functions “gate-by-gate update”
MAX
AVG
MIN
1 0
Definition: Stable Circuit Problem A vector v is stable iff every gate is satisfied. (F(v) = v) Gate-by-gate update from the vector 0 obtains a stable vector in the
limit. This is the minimum stable solution We wish to find the minimum stable solution
MAX
AVG
MIN
1 0
1/2
1/2
0
MAX
AVG
MIN
1 0
1/2
0
0
stable unstable
Definition: STABLE CIRCUIT (Decision Problem) We are given a circuit C, and some designated ith gate.
In the minimum stable solution of C, s, “is si ≥ 1/2?” If we can efficiently solve this decision problem, we can
efficiently solve the function problem: we can find 2|C| bits of any si, which may be shown to be sufficient. Inductively suppose we know
the first k-1 bits of si to be v Modify C:
(1-1/2k-v) requires k gates In the minimum stable solution, this new AVG gate’s output is above 1/2 iff
the kth bit of si is a 1, so the decision problem tells us the kth bit of si Ex: Suppose v = .011010, si = .0110101… (k = 7) then
AVG(si,1-1/2k-v) = (.0110101… + .1001011)/2 = .10000000… If si = .0110100… then
AVG(si,1-1/2k-v) = (.0110100… + .1001011)/2 = .01111111…
AVGith gate
(1-1/2k-v)
Previously, on STABLE CIRCUIT
STABLE CIRCUIT is in NPco-NP (Condon, 1992) We can modify our circuits to have a unique
solution that is identical to the minimum stable solution up to the 2|C|th bit
This unique solution can be guessed and checked
STABLE CIRCUIT is P-hard MONOTONE CIRCUIT is a special case
Observations and Motivations
Our original motivation was to show STABLE CIRCUIT was hard for some class beyond P
If we apply gate-by-gate update to arbitrary starting value vectors, we can obtain “interesting” circuits We do not necessarily obtain stable configurations of our
circuits -- this is not Stable Circuit If we apply gate-by-gate update to the value vector 0,
can we still obtain “interesting” circuits? If so, the minimum stable solution is the configuration of the
device after an unbounded amount of time!
Can we obtain “interesting” circuits starting from 0?
YES
“Leapfrog” circuits
We assign each wire a “threshold” wire and interpret its value relative to that threshold Above threshold: T Below threshold: F
It is already clear that we still have AND and OR There is also a construction for NOT (next slide)
If there are W wires which we wish to interpret relative to the same threshold, this gadget takes Θ(W) gates
NB: The circuits are still monotone! As we update, a value may seem to rise or fall, as we follow it
across different wires through the circuit The value on any particular wire only rises as the gates of the
circuit are updated
NOT Gadget
AVG
AVG
MAX
MIN MIN
MAX
MIN
MAX
th x0 x1 x2
~x0th x1 x2
AVGAVG
MAXMAX
MINMIN MINMINMINMIN
MAXMAX MAXMAX
AVGAVG
th x0 x1 x2
Caveats
Assumptions:1. All values above [below] threshold are equal2. th has a value distinct from all other inputs3. We may specify the update order for the gates of the circuit
Take each in turn:1. Everything starts from zero and the property is preserved by
our AND, OR, and NOT gates2. We can push th above zero by means of an AVG gate
With feedback, we must also pass the other wires through AVG gates to preserve relative values
3. Update order doesn’t change the solution we approach
Two-bit Counter Circuit
MAX
MIN MIN
AVG
AVGAVG
NOT
NOT
1
1 1
x0 x1 th
0
1
x0 x1 th
AVGAVG
MINMIN MINMIN
MAXMAX
AVGAVG AVGAVG
AVG
Two-bit Counter Circuit
MAX
MIN MIN
AVG
AVGAVG
NOT
NOT
1
1 1
x0 x1 th
1/2
17/32
x0 x1 th
MINMIN MINMIN
MAXMAX
Two-bit Counter Circuit
MAX
MIN MIN
AVG
AVGAVG
NOT
NOT
1
1 1
x0 x1 th
195/256
781/ 1024
x0 x1 th
MINMIN MINMIN
MAXMAX
Two-bit Counter Circuit
MAX
MIN MIN
AVG
AVGAVG
NOT
NOT
1
1 1
x0 x1 th
28867/32768
7217/8192
x0 x1 th
MINMIN MINMIN
MAXMAX
Serving Suggestions
The counter generalizes to n bits easily The n-bit counter takes Θ(n2) ga
tes, due to the size of the NOT gadgets
We now have our counter We next investigate the powe
r of Leapfrog circuits, using the counter…
First, we will need to make precise what we mean by “Leapfrog circuits”
NOT
NOT
MIN MIN MIN
MAX
carry-in xi
xi
carry-out
Definition: LEAPFROG
Let LEAPFROG be the following problem:
Given a circuit C and designated gates i and th, consider the sequence of vectors v1, v2, … obtained during gate-by-gate update of C from 0 in the order of the gate indices of C:
“Is there an index t such that vti > vt
th?”
LEAPFROG captures our notion of what Leapfrog circuits “compute”
LEAPFROG vs. STABLE CIRCUIT
NB: Not the same problem!! But, STABLE CIRCUIT obviously reduces to
LEAPFROG (include a gate that outputs constant 1/2-1/22|C|…)
Is LEAPFROG hard? YES -- we will see in a moment
Does LEAPFROG reduce to STABLE CIRCUIT? If “yes,” then STABLE CIRCUIT is also hard.
LEAPFROG is hard! (NP-hard)
Let any boolean formula be given…
Ex: (x1~x2x3) (~x1~x2x3)
Since we have AND, OR, and NOT gates, formulas easily translate into circuits.
NOT
NOT
MIN
MAX
MAX
MAX
MAX
x1 x2 x3 th, etc.
(x1~x2x3)(~x1~x2x3)
If we attach xi to the ith bit of the counter, we try all possible assignments, allowing us to reduce SAT to LEAPFROG.
The number of gates in these SAT circuits is quadratic in the length of the formula.
LEAPFROG is really hard! (PSPACE-hard) We can still do better: using the counter, we will
decide whether quantified boolean formulas are valid (Reducing TQBF to LEAPFROG)
Assume WLOG that the quantifiers alternate: odd variables are universal, even ones are existential
Leaves in this tree correspond to assignments The counter walks along the leaves, left to right
At the bottom we evaluate the quantifier-free part of the formula on the specified assignment.
x1
x0 x0
00 01 10 11
Each level of the tree has one bit of memory for the left branch Set it to T when the branch is T, reset it to F when leaving that subtree.
Pass T up the tree when we see T at either branch at an level T at the right branch of a level with the left branch bit already set to T.
T is passed up from the top of the tree iff we have a TQBF.
Quantifier Circuit: xi (xi-1 A)
Axi Carry-out: xivi
0
NOT
NOT
MIN
MIN
MIN
MIN
MAX
xi vi0
xi xi-1 A
• IH: the wire A will be T iff the shorter formula with alternating quantifiers, A, is satisfied by the assignment to xn,…,xi-1 from the counter
• vi0 is our bit of memory storing the value of (A|
xi = F) (the left branch) under the fixed assignment to xn,…,xi+1
• When there is a carry out of xi, xi+1 has altered, so we reset vi
0 to F
• If vi0 = (A|xi = F) = T and (A|xi = T) = T (on the
right branch), then the wire labeled xixi-1 A is set to T. Otherwise, the wire remains F.
• Notice we try both settings of xi-1 for each bran
ch. The wire xi xi-1 A is T iff xi xi-1 A is satisfied by the assignment to xn,…,xi+1, so the Inductive Hypothesis is satisfied
MINMIN
MINMIN
MINMIN
MINMIN
MAXMAX
End of the Line: Thwarted by PSPACE Recall: finding values in the limit (the minimum st
able solution) is known to be in NPco-NP Answers to PSPACE-hard problems (TQBF) ma
y be encoded on the wires as we update Since circuits of AND/OR/NOT gates can be evalua
ted in PSPACE, we would need to drastically alter our model to solve anything harder
Hence, unless NP = PSPACE, LEAPFROG does not reduce to STABLE CIRCUIT
Thus, in general, Leapfrog circuits (specifically, our counter) cannot be “stopped”
Open problems
How hard is STABLE CIRCUIT? We had also succeeded in placing the function
version in PLS, but still no hardness results Is Stable Circuit PLS-complete? Is STABLE CIRCUIT in P?
How hard is LEAPFROG, actually? Trivially RE, but this says rather little Is LEAPFROG decidable?