Work in Progress --- Not for Publication1 ERD WG 1/15/09

ERD TWG Emerging Research Devices

Telecon Meeting No. 3

Jim Hutchby - FacilitatingThursday, January 15, 2009

9:00 am – 10:30 Eastern US Time

ERD WG Telecon January 15, 2009

Pacific US Central US Eastern US Europe Taiwan Japan/Korea

6am 8am 9am 3pm 10pm 11pm

Work in Progress --- Not for Publication2 ERD WG 1/15/09

Jan. 15, 2009 ERD Telecon Meeting Objectives

Review structure and content of 2007 ERD Logic Section tables

Review and discuss Japan ERD proposal for a new structure for the 2009 ERD Logic Section tables.

Work in Progress --- Not for Publication3 ERD WG 1/15/09

January 15, 2009 ERD Telecon Meeting Agenda

9:00 am Check in & review meeting Hutchby Objectives/Agenda

9:10 Review 2007 ITRS/ERD Logic Table Bourianoff structure

9:30 Present the Japan ERD Proposal for Hiramoto-san the 2009 ERD Logic Table structure

9:50 Discuss 2009 ERD Logic Table Bourianoff structure Hiramoto-san

10:30 Adjourn Meeting

Work in Progress --- Not for Publication4 ERD WG 1/15/09

Device

FET ExtensionFET [A] 1D structures Channel

replacementSET Molecular Ferromagnetic

logicSpin

transistorTypical example devices Si CMOS CNT FET

NW FET

NW hetero-structures

Nanoribbon transistors with

graphene

III-V compound semiconductor and Ge channel

replacement

SET Crossbar latch

Molecular transistor

Molecular QCA

Moving domain wall

M: QCA

Spin Gain transistor

Spin FET

Spin Torque

Transistor

Cell Size (spatial

pitch) [B]

Projected 100 nm 100 nm [D] 300 nm [I] 40 nm [O] 10 nm [U] 140 nm [Y] 100 nm [C]

Demonstrated

590 nm ~1.5 m [E] 1700 nm [J] ~200 nm [K, L] ~2 m [V]250 nm [Z,

AA]100 m [AB]

Density (device/cm2)

Projected 1E10 4.5E9 6.1E9 6E10 1E12 5E9 4.5E9Demonstrate

d2.8E8 4E7 3.5E7 ~2E9 2E7 1.6E9 1E4

Switch SpeedProjected 12 THz 6.3 THz [F] >1 THz 10 THz [Q] 1 THz [W] 1 GHz [Y] 40 GHz [AC]

Demonstrated

1.5 THz 200 MHz [G] >300 GHz 2 THz [R] 100 Hz [V] 30 Hz [Z, AA] Not known

Circuit SpeedProjected 61 GHz 61 GHz [C] 61 GHz [C] 1 GHz [O] 1 GHz [U] 10 MHz [Y] Not known

Demonstrated

5.6 GHz 220 Hz [H]Data not available

1 MHz [P] 100 Hz [V] 30 Hz [Z] Not known

Switching Energy, J

Projected 3E-18 3E-18 3.00E-181×10–18 [O]

[>1.5×10–17 ] [S]5E-17 [X] ~1E-17 [Z] 3E-18

Demonstrated

1E-16 1E-11 [H] 1E-16 [J]8×10–17 [T]

[>1.3×10–14] [S]3E-7 [V] 6E-18 [AA] Not known

Binary Throughput, GBit/ns/cm2

Projected 238 238 61 10 1000 5E-2 Not known

Demonstrated

1.6 1E-8Data not available

2E-4 2E-9 5E-8 Not known

Operational Temperature RT RT RT RT [M, N] RT RT RT

Materials System Si

CNT,

Si, Ge, III-V,

In2O3, ZnO, TiO2, SiC,

InGaAs, InAs, InSb

III-V, Si, Ge,Organic

moleculesFerromagnetic

alloys

Si, III-V, complex metals oxides

Research Activity [AD] 379 62 91 244 32 122

Table ERD7a Emerging Research Logic Devices—Demonstrated and Projected Parameters

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Resonant Tunneling Diodes

Multi-ferroic Tunnel Junctions

Single Electron Transistors

Molecular Devices

Ferro-Magnetic Devices

Frequency Coherent Spin Devices

State Variable Charge

Dielectric and magnetic domain polarization

ChargeMolecular conformation

Ferromagnetic polarization

Precession frequency

Response Function

Negative differential resistance

Four resistive states

Staircase I/V from Coulomb blockade

Hysteretic Nonlinear Nonlinear

Class—Example

Multi-ferroic tunnel junction

Voltage tunable transfer function

CMOL, cross bar latch

Amplifiers, buses, switches

Spin torque oscillator

Architecture Heterogeneous MorphicHeterogeneous,morphic

MQCA, morphic

Morphic

ApplicationElements in hybrid magneto electric circuits

Analog pattern matching

Associative processing , NP complete,

Elements in hybrid magneto-electric circuits

Microwave power, tunable rectifiers

CommentsAdditionalfunctionality

Density, functionality

Density, cost functionality

Radiation hard, environmental rugged

RF functionality

Status Demo Demo Demo Demo Simulation

Material Issues Stray charge RT DMS

Table ERD7b Alternative Information Processing Devices

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Logic Table

2007 Version2 + 1 Table

(1) Emerging Logic(General Purpose)

(2) Alternative Info. Processing Devices

Transition Table

2009 Version (Proposed)3 + 1 Table

(1) CMOS Extension

(2) Beyond CMOS (CMOS Supplement)

Transition Table

(3) Pure Beyond CMOS (CMOS replacement)

Classified byOperation Principles

Classified byPrinciples and Materials

T. Hiramoto, Dec. 14, 2009.

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Beyond CMOS

Elements

ERD-WG in Japan

Existing technologies

New technologies

Evolution of Extended CMOS

CMOS Extension

CMOS Supplement

CMOS Replacement

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(1) CMOS Extension Table

Purpose

Dim.No

ImpuritSelf

Assembl

Materials Ge III-V Graphene Si Ge III-V CNT GNRMolecularTunnel IMOSFD

SOI?CNT

PerformancePowerSize??

Smaller variabiityCMOS Extension

1D Sub-60mV2D

Higher Ion Smaller Ioff

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(2) Beyond CMOS (CMOS Supplement)

- Spin MOSFET (Including STT)- SET (including Molecular SET)- CMOL

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(3) Beyond CMOS (CMOS Replacement)

- Spin Wave- Domain Wall- NEMS- Electrochemical (Atom Switch, Memoristor?)- Molecular Computing Devices- Spin Transistor

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Operation Principles and Materials

2D 1DSub-60mV

SpinMOSFE

SET

CMOLSpinWave

DomainWall

NEMSElectro-

chemical

Si x x x x x xGe x x x xIII-V xCNT xx x xGraphene x x xxMolecular x

(1) CMOS Extension(2) CMOS Supplement (3) CMOS Replacement