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Getting Started with Xilinx (ISE):

PC users, start ISE from Start menu by

selecting• Start• Programs• Xilinx ISE 6.xi

• Project Navigator.

Note: Your start-up path is set during theinstallation process and may differ from

the one above.

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Source Window : To List All

Created Sources of Projects& maintaining their HirarchyAutomatically

Process Window :Displays list Proc-esses required forselected Source

Menu Bar

Tool Bar

Editor : Display &Edit of selectedSource Details

Transcript Window : DisplaysOn Going Process Reports

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Creating a New Project:

A project in ISE is a collection of all files necessary tocreate and download a design to the selected device.

1. To create a new project:• Select File• New Project.

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2. In the New Project Wizard dialog box, type the desired location in the ProjectLocation field, or browse to the directory under which you want to create your newproject directory using the browse button next to the Project Location field.

3. Use the pull-down arrow to select HDL from the Top-Level Module Type field.Click in the field to access the pull-down list.

4. Click Next

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5. In the New Project Wizard Device and Design Flow dialog box, use the pull-down arrow to

select the Value for each Property Name. Click in the field to access the pull down list.Change the values as follows:

• Device Family: Spartan II• Device: XC2S 100

• Package: TQ 144

• Speed Grade: -5

• Synthesis Tool: XST (VHDL/ Verilog)

• Simulator: Modelsim

• Generated Simulation Language: VHDL

6. Click Next.

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7. Click New Source in the New Project Wizard Create a New Source Dialog boxto add one new source to your project.

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8. In the New Source dialog box, selectVHDL Module as the source type.

9. Type in the file name ‘exp1_gates’.

10. Click Next.

11. Click Next in the Define VHDL Source dialog box.

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Note: You have the option of defining andadding ports from this dialog box. In thisexample, you will use pre-defined portssupplied in the Language Template.Click Next.

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Click Next.

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Click Next in the New Project Wizard

Add Existing Sources dialog box.

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Click Finish in the New Project

Wizard Summary dialog box.

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ISE creates and displays the new project in the Sources in Projectwindow, and opens the exp1_gates.vhd file in ISE TextEditor.Write the VHDL Code

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Save The VHDL File &

Check the Syntax

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Synthesize the Program

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CLICK “View Synthesis Report” from Synthesis Optionin Process Window to see detailed synthesis report.

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CLICK “View RTL Schematic” from Synthesis Option inProcess Window to see schematic equivalent of your code

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CLICK “Create New Source” in Process Window to openNew Source dialog box and Select Test Bench WaveFormtype the file name and Click Next

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Select the Source for which the testbench waveform to be generated fromselect window and click next

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click Finish

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Click OK to accept the default timing constraints.

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HDL Bencher opens within the ProjectNavigator framework.

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Set the input values for your project by clicking on inputwaveforms by making them low or high. Save the file andclose the waveform editor.

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1. Select Test_Gates.tbw in the Sources in Project window.2. In the Processes for Source window, click the + beside

ModelSim Simulator to expand the hierarchy.3. Double-click Simulate Behavioral Model.

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SIGNAL WINDOW : Displaysall I/Os of your project

Waveform Window : Displays outputwaveforms for verification

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CLICK “Create New Source” in Process Window to openNew Source dialog box and Select ImplementationConstraints File, type the file name and Click Next

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Select the Source for which the ImplementationConstraint File to be written, from select windowand click next

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click Finish

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1. Select Gates_UCF.ucf in the Sourcesin Project window.

2. In the Processes of Process window,click the + beside User Constraints toexpand the hierarchy.

3. Double-click Edit Constraints (Text).

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Write User Constraint File as above & Save:Assign Pin Locations to Inputs & Outputs basedon targetted Device [FPGA & CPLD]

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Double Click Implement Designin the Process Window to im-plement the Project

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1. Select exp1_gates-behavioral(exp1_gates.vhdl)from Sources in Project window.

2. In the Processes of Process window, click the +

beside Place &Routeto expand the hierarchy.3. Double-click Place & Route or Pad Report orGenerate Post-Route & Route Static Timing

to see their respective detailed report4. Double Click to explore additional advanced

special features of ISE software if you want

Additonal Advanced Features : 

Floor Planner - To view & edit Placed DesignFPGA Editor - To view & edit routed DesignXPower - Power Estimation of implemented DesignEtc.

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PAD REPORT

PLACE & ROUTE REPORT

STATIC TIMINGANALYSIS REPORT

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1. Right Click on Generate Programming File in side the Process Window2. Double Click on Properties to open Process Properties Dialog Box

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Then Double Click Generate ProgrammingFile inside the Process Window

Select Startup OptionsChoose Value JTAG Clock underProperty Name  FPGA Start-Up ClockClik OK

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Double Click onConfigure Device [IMPACT] insidethe Process Window to openConfigure Device Dialog Box

Select Boundary-Scan Mode

Click Next

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Click Finish

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Right Mouse Click

Select / Click Add Xilinx Deviceto open Add Device Dialog Box

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Browse & Select the Program bit file with .bit

extention from Add Device Dialog Box

exp1_Gates.bit

[generated & saved when Generate ProgrammingFile from Process window was double clicked]

Click Open

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Right Click on Xilinx Device as shown

Select / Click Program to down loadyour design to the target device ondemo board

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Your Design will get downloadedsuccessfully to the targetted device ifthe demo board is connected properlyto your system through parallel portusing downloading cable