Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis 8.1 EE4800 CMOS Digital IC Design & Analysis...

Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis

8.8.11

EE4800 CMOS Digital IC Design & Analysis

Lecture 8 Spice SimulationZhuo Feng


8.8.22

Outline■Introduction to SPICE■DC Analysis■Transient Analysis■Subcircuits■Optimization■Power Measurement■Logical Effort Characterization


8.8.33

Introduction to SPICE■ Simulation Program with Integrated Circuit

Emphasis► Developed in 1970’s at Berkeley► Many commercial versions are available► HSPICE is a robust industry standard

▼ Has many enhancements that we will use

■ Written in FORTRAN for punch-card machines► Circuits elements are called cards► Complete description is called a SPICE deck


8.8.44

Writing Spice Decks■ Writing a SPICE deck is like writing a good

program► Plan: sketch schematic on paper or in editor

▼ Modify existing decks whenever possible

► Code: strive for clarity▼ Start with name, email, date, purpose▼ Generously comment

► Test:▼ Predict what results should be▼ Compare with actual▼ Garbage In, Garbage Out!


8.8.55

Example: RC Circuit* rc.sp* [email protected] 2/2/03* Find the response of RC circuit to rising input

*------------------------------------------------* Parameters and models*------------------------------------------------.option post

*------------------------------------------------* Simulation netlist*------------------------------------------------Vin in gnd pwl 0ps 0 100ps 0 150ps 1.8 800ps 1.8R1 in out 2kC1 out gnd 100f

*------------------------------------------------* Stimulus*------------------------------------------------.tran 20ps 800ps.plot v(in) v(out).end

R1 = 2K

C1 =100fF

Vin

+Vout

-


8.8.66

Result (Textual)legend: a: v(in) b: v(out) time v(in) (ab ) 0. 500.0000m 1.0000 1.5000 2.0000 + + + + + 0. 0. -2------+------+------+------+------+------+------+------+- 20.0000p 0. 2 + + + + + + + + 40.0000p 0. 2 + + + + + + + + 60.0000p 0. 2 + + + + + + + + 80.0000p 0. 2 + + + + + + + + 100.0000p 0. 2 + + + + + + + + 120.0000p 720.000m +b + + a+ + + + + + 140.0000p 1.440 + b + + + + + a + + + 160.0000p 1.800 + +b + + + + + +a + 180.0000p 1.800 + + b + + + + + +a + 200.0000p 1.800 -+------+------+b-----+------+------+------+------+a-----+- 220.0000p 1.800 + + + b + + + + +a + 240.0000p 1.800 + + + +b + + + +a + 260.0000p 1.800 + + + + b + + + +a + 280.0000p 1.800 + + + + b+ + + +a + 300.0000p 1.800 + + + + +b + + +a + 320.0000p 1.800 + + + + + b + + +a + 340.0000p 1.800 + + + + + b + + +a + 360.0000p 1.800 + + + + + b + +a + 380.0000p 1.800 + + + + + +b + +a + 400.0000p 1.800 -+------+------+------+------+------+--b---+------+a-----+- 420.0000p 1.800 + + + + + + b + +a + 440.0000p 1.800 + + + + + + b + +a + 460.0000p 1.800 + + + + + + b+ +a + 480.0000p 1.800 + + + + + + b +a + 500.0000p 1.800 + + + + + + +b +a + 520.0000p 1.800 + + + + + + +b +a + 540.0000p 1.800 + + + + + + + b +a + 560.0000p 1.800 + + + + + + + b +a + 580.0000p 1.800 + + + + + + + b +a + 600.0000p 1.800 -+------+------+------+------+------+------+---b--+a-----+- 620.0000p 1.800 + + + + + + + b +a + 640.0000p 1.800 + + + + + + + b +a + 660.0000p 1.800 + + + + + + + b +a + 680.0000p 1.800 + + + + + + + b +a + 700.0000p 1.800 + + + + + + + b+a + 720.0000p 1.800 + + + + + + + b+a + 740.0000p 1.800 + + + + + + + b+a + 760.0000p 1.800 + + + + + + + b+a + 780.0000p 1.800 + + + + + + + ba + 800.0000p 1.800 -+------+------+------+------+------+------+------ba-----+- + + + + +


8.8.77

Result (Graphical)

t(s)0.0 100p 200p 300p 400p 500p 600p 700p 800p 900p

0.0

0.5

1.0

1.5

2.0 v(in)

v(out)


8.8.88

Sources■DC Source

Vdd vdd gnd 2.5

■Piecewise Linear SourceVin in gnd pwl 0ps 0 100ps 0 150ps 1.8 800ps 1.8

■Pulsed SourceVck clk gnd PULSE 0 1.8 0ps 100ps 100ps 300ps 800ps

PULSE v1 v2 td tr tf pw per

v1

v2

td tr tfpw

per


8.8.99

SPICE Elements

Letter ElementR ResistorC CapacitorL InductorK Mutual InductorV Independent voltage sourceI Independent current sourceM MOSFETD DiodeQ Bipolar transistorW Lossy transmission lineX SubcircuitE Voltage-controlled voltage sourceG Voltage-controlled current sourceH Current-controlled voltage sourceF Current-controlled current source


8.8.1010

Units

Letter Unit Magnitude

a atto 10-18

f fempto 10-15

p pico 10-12

n nano 10-9

u micro 10-6

m mili 10-3

k kilo 103

x mega 106

g giga 109

Ex: 100 femptofarad capacitor = 100fF, 100f, 100e-15


8.8.1111

DC Analysis* mosiv.sp

*------------------------------------------------* Parameters and models*------------------------------------------------.include '../models/tsmc180/models.sp'.temp 70.option post

*------------------------------------------------ * Simulation netlist*------------------------------------------------*nmosVgs g gnd 0Vds d gnd 0M1 d g gnd gnd NMOS W=0.36u L=0.18u

*------------------------------------------------* Stimulus*------------------------------------------------.dc Vds 0 1.8 0.05 SWEEP Vgs 0 1.8 0.3.end

Vgs Vds

Ids

4/2


8.8.1212

I-V Characteristics

Vds

0.0 0.3 0.6 0.9 1.2 1.5 1.8

Ids(A)

0

50

100

150

200

250

Vgs = 1.8

Vgs = 1.5

Vgs = 1.2

Vgs = 0.9

Vgs = 0.6

■NMOS I-V►Vgs dependence

►Saturation


8.8.1313

MOSFET ElementsM element for MOSFET

Mname drain gate source body type

+ W=<width> L=<length>

+ AS=<area source> AD = <area drain>

+ PS=<perimeter source> PD=<perimeter drain>


8.8.1414

Transient Analysis* inv.sp

* Parameters and models*------------------------------------------------.param SUPPLY=1.8.option scale=90n.include '../models/tsmc180/models.sp'.temp 70.option post

* Simulation netlist*------------------------------------------------Vdd vdd gnd 'SUPPLY'Vin a gnd PULSE 0 'SUPPLY' 50ps 0ps 0ps 100ps 200psM1 y a gnd gnd NMOS W=4 L=2 + AS=20 PS=18 AD=20 PD=18M2 y a vdd vdd PMOS W=8 L=2+ AS=40 PS=26 AD=40 PD=26

* Stimulus*------------------------------------------------.tran 1ps 200ps.end

a y

4/2

8/2


8.8.1515

Transient Results

(V)

0.0

1.0

t(s)0.0 50p 100p 150p 200p

v(a)

v(y)

tpdr = 15pstpdf = 12ps

tf = 10ps

tr = 16ps

0.36

1.44

1.8

■ Unloaded inverter► Overshoot► Very fast edges


8.8.1616

Subcircuits■ Declare common elements as subcircuits

■ Ex: Fanout-of-4 Inverter Delay► Reuse inv► Shaping► Loading

.subckt inv a y N=4 P=8M1 y a gnd gnd NMOS W='N' L=2 + AS='N*5' PS='2*N+10' AD='N*5' PD='2*N+10'M2 y a vdd vdd PMOS W='P' L=2+ AS='P*5' PS='2*P+10' AD='P*5' PD='2*P+10'.ends

a b c d eX1 X2 X3 X4

1

2

4

8

16

32

64

128 fX5

256

512

Shape input

DeviceUnderTest Load

Load onLoad


8.8.1717

FO4 Inverter Delay* fo4.sp

* Parameters and models*----------------------------------------------------------------------.param SUPPLY=1.8.param H=4.option scale=90n.include '../models/tsmc180/models.sp'.temp 70.option post

* Subcircuits*----------------------------------------------------------------------.global vdd gnd.include '../lib/inv.sp'

* Simulation netlist*----------------------------------------------------------------------Vdd vdd gnd 'SUPPLY'Vin a gnd PULSE 0 'SUPPLY' 0ps 100ps 100ps 500ps 1000psX1 a b inv * shape input waveformX2 b c inv M='H' * reshape input waveform


8.8.1818

FO4 Inverter Delay Cont.X3 c d inv M='H**2' * device under testX4 d e inv M='H**3' * loadx5 e f inv M='H**4' * load on load

* Stimulus*----------------------------------------------------------------------.tran 1ps 1000ps.measure tpdr * rising prop delay+ TRIG v(c) VAL='SUPPLY/2' FALL=1 + TARG v(d) VAL='SUPPLY/2' RISE=1.measure tpdf * falling prop delay+ TRIG v(c) VAL='SUPPLY/2' RISE=1+ TARG v(d) VAL='SUPPLY/2' FALL=1 .measure tpd param='(tpdr+tpdf)/2' * average prop delay.measure trise * rise time+ TRIG v(d) VAL='0.2*SUPPLY' RISE=1+ TARG v(d) VAL='0.8*SUPPLY' RISE=1.measure tfall * fall time+ TRIG v(d) VAL='0.8*SUPPLY' FALL=1+ TARG v(d) VAL='0.2*SUPPLY' FALL=1.end


8.8.1919

FO4 Results

(V)

0.0

0.5

1.0

1.5

2.0

t(s)0.0 200p 400p 600p 800p 1n

a

b

c

d

e

ftpdf = 66ps tpdr = 83ps


8.8.2020

Optimization■ HSPICE can automatically adjust parameters

► Seek value that optimizes some measurement

■ Example: Best P/N ratio► We’ve assumed 2:1 gives equal rise/fall delays► But we see rise is actually slower than fall► What P/N ratio gives equal delays?

■ Strategies► (1) run a bunch of sims with different P size► (2) let HSPICE optimizer do it for us


8.8.2121

P/N Optimization* fo4opt.sp

* Parameters and models*----------------------------------------------------------------------.param SUPPLY=1.8.option scale=90n.include '../models/tsmc180/models.sp'.temp 70.option post

* Subcircuits*----------------------------------------------------------------------.global vdd gnd.include '../lib/inv.sp'

* Simulation netlist*----------------------------------------------------------------------Vdd vdd gnd 'SUPPLY'Vin a gnd PULSE 0 'SUPPLY' 0ps 100ps 100ps 500ps 1000psX1 a b inv P='P1' * shape input waveformX2 b c inv P='P1' M=4 * reshape inputX3 c d inv P='P1' M=16 * device under test


8.8.2222

P/N Optimization

X4 d e inv P='P1' M=64 * loadX5 e f inv P='P1' M=256 * load on load

* Optimization setup*----------------------------------------------------------------------.param P1=optrange(8,4,16) * search from 4 to 16, guess 8.model optmod opt itropt=30 * maximum of 30 iterations.measure bestratio param='P1/4' * compute best P/N ratio

* Stimulus*----------------------------------------------------------------------.tran 1ps 1000ps SWEEP OPTIMIZE=optrange RESULTS=diff MODEL=optmod.measure tpdr * rising propagation delay+ TRIG v(c)VAL='SUPPLY/2' FALL=1 + TARG v(d) VAL='SUPPLY/2' RISE=1.measure tpdf * falling propagation delay+ TRIG v(c) VAL='SUPPLY/2' RISE=1+ TARG v(d) VAL='SUPPLY/2' FALL=1 .measure tpd param='(tpdr+tpdf)/2' goal=0 * average prop delay.measure diff param='tpdr-tpdf' goal = 0 * diff between delays.end


8.8.2323

P/N Results■ P/N ratio for equal delay is 3.6:1

► tpd = tpdr = tpdf = 84 ps (slower than 2:1 ratio)

► Big pMOS transistors waste power too► Seldom design for exactly equal delays

■ What ratio gives lowest average delay?

.tran 1ps 1000ps SWEEP OPTIMIZE=optrange RESULTS=tpd MODEL=optmod

► P/N ratio of 1.4:1

► tpdr = 87 ps, tpdf = 59 ps, tpd = 73 ps


8.8.2424

Power Measurement■HSPICE can measure power

► Instantaneous P(t)►Or average P over some interval

.print P(vdd)

.measure pwr AVG P(vdd) FROM=0ns TO=10ns

■Power in single gate►Connect to separate VDD supply

►Be careful about input power


8.8.2525

Logical Effort■ Logical effort can be measured from

simulation► As with FO4 inverter, shape input, load output

X1 X2X3 X4

X5

a bc d

efM=1

M=h M=h2M=h3

M=h4

Shape input

DeviceUnderTest Load

Load onLoad


8.8.2626

Logical Effort Plots■ Plot tpd vs. h

► Normalize by ► y-intercept is parasitic delay► Slope is logical effort

■ Delay fits straight linevery well in any processas long as input slope isconsistent

0

20

40

60

80

100

120

140

160

180

0 2 4 6 8 10

h

dabs

= 15 ps


8.8.2727

Logical Effort Data■ For NAND gates in TSMC 180 nm process:

■ Notes:► Parasitic delay is greater for outer input► Average logical effort is better than estimated


8.8.2828

Comparison


8.8.2929

■SPICE overview►N equations in terms of N unknown Node voltages►More generally using modified nodal analysis

G(v)i 1v2v

3v

4v

C

R

v


8.8.3030

Time Domain Equations at node 1:

If we do this for all N nodes:

N dimensional vector of unknown node voltages

vector of independent sources

nonlinear operator

0)()()(

12

4131

vvGR

vv

dt

vvdC

0))(),(),(( tutxtxF

Xx )0(

)(tx

)(tu

F


8.8.3131

■ Closed form solution is not possible for arbitrary order of differential equations

■ We must approximate the solution of:

■ This is facilitated in SPICE via numerical solutions

0))(),(),(( tutxtxF

Xx )0(


8.8.3232

■Basic circuit analyses►(Nonlinear) DC analysis

▼Finds the DC operating point of the circuit▼Solves a set of nonlinear algebraic eqns

►AC analysis▼Performs frequency-domain small-signal analysis▼Require a preceding DC analysis▼Solves a set of complex linear eqns

►(Nonlinear) transient analysis▼Computes the time-domain circuit transient response▼Solves a set of nonlinear different eqns▼Converts to a set nonlinear algebraic of eqns using

numerical integration


8.8.3333

■ SPICE offers practical techniques to solve circuit problems in time & freq. domains

► Interface to device models▼ Transistors, diodes, nonlinear caps etc

► Sparse linear solver

► Nonlinear solver – Newton-Raphson method

► Numerical integration

► Convergence & time-step control


8.8.3434

■Circuit equations are usually formulated using

►Nodal analysis ▼N equations in N nodal voltages

►Modified analysis▼Circuit unknowns are nodal voltages & some branch

currents▼Branch current variables are added to handle

– Voltages sources– Inductors– Current controlled voltage source etc

■Formulations can be done in both time and frequency


8.8.3535

How do we set up a matrix problem given a list oflinear(ized) circuit elements?

Similar to reading a netlist for a linear circuit:

*Element Name From

To Value

3

2

1

1

R

R

R

I

2

1

1

0

0

2

0

1

100

5

10

1mA


8.8.3636

The nodal analysis matrix equations are easily constructed via KCL at each node:

1I 1R

2R

3R

mA1

5

10010

1 2

0

JvY


8.8.3737

■ Naïve approach► a) Write down the KCL eqn for each node► b) Combine all of them to a get N eqns in N node voltages

■ Intuitive for hand analysis

■ Computer programs use a more convenient “element” centric approach

► Element stamps


8.8.3838

Instead of converting the netlist into a graph and writing KCL eqns, stamp in elements one at a time:

Stamps: add to existing matrix entries

RR

RR11

11 Fromrow

Torow

Fromcol.

Tocol.

j

i

i j

i

j

RY


8.8.3939

RHS of equations are stamped in a similar way:

I

Ii

jI

From row

Torow

i

j

J


8.8.4040

Stamping our simple example one element at a time:

10002

521

1001

110

3

2

1

1

R

R

R

mAI

01

2

1

322

221 I

V

V

GGG

GGG


8.8.4141

We know that nonlinear elements are first converted to linear components, then stamped

EQI EQG


8.8.4242

For 3 & 4 terminal elements we know that the linearized models have linear controlled sources

Gdsv

D DG

S S

gsv

gsmvg dsr

We can stamp in MOSFETs in terms of a complete stamp, or in terms of simpler element stamps


8.8.4343

Voltage controlled current source

kv 0I

k

kmvgi

p

q

Voltmeter

mm

mm

gg

gg

k

p

qrow

row

colcol

Large value that does not fall on diagonal of Y!


8.8.4444

All other types of controlled sources include voltage sources

Voltage sources are inherently incompatible with nodal analysis

Grounded voltages sources are easily accommodated

1

0

v2

21

2

1

v

v


8.8.4545

But a voltage source in between nodes is more difficult

Node voltages and

are not independentk

k


8.8.4646

We no longer have N independent node voltage variables

So we can potentially eliminate one equation and one variable (section 2.3 of reference [1])

But the more popular solution is modified nodal analysis (MNA)

i

Vk

Create one extra variable and one extra equation


8.8.4747

Extra variable: voltage source current

Allows us to write KCL at nodes

and

Extra equation

Advantage: now have an easy way of printing current results - - ammeter

Vvvk

k


8.8.4848

Voltage source stamp:

Vi011

1

1

row

row

row

col colcol

k

k

1N

1N


8.8.4949

Current-controlled current source (e.g. BJT) has to stamp in an ammeter and a controlled current source

12 ii 1i


8.8.5050

In general, we would not blindly build the matrix from an input netlist and then attempt to solve it

Various illegal ckts are possible:

Cutsets of current sources


8.8.5151

Loops of voltage sources

Dangling nodes


8.8.5252

■ Once we efficiently formulate MNA equations, an efficient solution to is even more important

■ For large ckts the matrix is really sparse► Number of entries in Y is a function of number of elements

connected to the corresponding node

■ Inverting a sparse matrix is never a good idea since the inverse is not sparse!

■ Instead direct solution methods employ Gaussian Elimination or LU factorization

JvY

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Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis 8.1 EE4800 CMOS Digital IC Design & Analysis...

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