26 th NATIONAL RADIO SCIENCE CONFERENCE, NRSC'2009 Future university, 5 th Compound, New Cairo, Egypt, March 17-19, 2009 1 26 th NATIONAL RADIO SCIENCE CONFERENCE (NRSC2009) jj D18 March 17-19, 2009, Faculty of Engineering, Future Univ., Egypt A Novel Low-Power and High-Speed Dynamic CMOS Logic Circuit Technique Sherif M. Sharroush 1 , Yasser S. Abdalla 2 , Ahmed A. Dessouki 3 , and El-Sayed A El-Badawy 4 1 Dept of Elect Eng, Fac. of Eng., Port Said, Suez Canal Univ., Egypt. EM: [email protected]2 Dept of Electricity, Fac. of Industrial Edu., Suez, Suez Canal Univ., Egypt. EM: [email protected]3 Dept of Elect Eng, Fac. of Eng., Port Said, Suez Canal Univ., Egypt. EM: [email protected]4 Alex Higher Inst. of Eng. & Tech. / Fac. of Eng., Alex. Univ., Alexandria, Egypt. EM: [email protected]Abstract Domino CMOS logic finds a wide variety of applications due to their high speed and low device count. In conventional CMOS domino logic, either the dynamic-node capacitor, C L is precharged to V DD during the precharge phase or predischarged to 0 V. The first precharging scheme is more suitable when logic “0” occurrence is more probable at the output due to the large saving in power consumption. On the other hand, the second predischarging scheme is more suitable when logic “1” is more probable at the output. In this paper, we will propose a novel technique to speed up the operation and minimize power consumption when there is an equal probability of occurrence of logic "0" and logic "1". This technique depends on precharging the dynamic node to V DD /2 instead of V DD during the precharge phase. Then, during the evaluation phase, the dynamic-node voltage will be either increased to V DD or decreased to 0 V depending on the state of the inputs. This, of course, saves much of the time and power consumption because discharging the dynamic node from V DD /2 to 0 V is much faster and consumes less power consumption than discharging it from V DD to 0 V. Also, the discharging process and noise margin will be enhanced by virtue of the fact that the time interval during which the keeper combats the discharging process is relatively very small. The proposed technique will be simulated for the 0.13 μm technology with V DD =1.2 V. Simulation results show that about 75% was shaved from the cycle time for the case of “0” and “1” outputs at the expense of an additional silicon area. Key Words: dynamic logic, low power, high speed, noise immunity. 1. Introduction Due to their high speed and low device count especially compared to complementary CMOS, dynamic-logic circuits are used in a wide variety of applications including microprocessors, digital signal processors [1], and dynamic memory. The basic dynamic domino logic gate is shown in Fig. 1 [2]. As shown in the figure, it consists of a pull-down network (PDN) that realizes the desired logic function and there are two switches in series that are periodically operated by the clock signal CLK whose waveform is shown in Fig. 2. C L denotes the total parasitic capacitance between the dynamic node and ground. When CLK is low, Q P is turned on, and the circuit is in the precharge phase where the dynamic node charges to V DD . Also, during precharge, the inputs are allowed to change and settle to their proper values. Because Q e is off, no path to ground exists. When CLK is high, Q P is off and Q e turns on, and the circuit is in the evaluation phase. During the evaluation phase; there are two possibilities for the dynamic-node voltage. If the input combination is one that corresponds to a low output, the dynamic-node voltage will be maintained at the supply voltage, V DD . On the other hand, if the input combination is one that corresponds to a high output, the dynamic-node voltage will be discharged to ground through the conducting NMOS transistors of the PDN.
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26th NATIONAL RADIO SCIENCE CONFERENCE, NRSC'2009 Future university, 5th Compound, New Cairo, Egypt, March 17-19, 2009
1 26thNATIONAL RADIO SCIENCE CONFERENCE (NRSC2009) jj D18
March 17-19, 2009, Faculty of Engineering, Future Univ., Egypt
A Novel Low-Power and High-Speed Dynamic CMOS Logic Circuit Technique
Sherif M. Sharroush1, Yasser S. Abdalla2, Ahmed A. Dessouki3, and El-Sayed A El-Badawy4 1Dept of Elect Eng, Fac. of Eng., Port Said, Suez Canal Univ., Egypt.
EM: [email protected] 2Dept of Electricity, Fac. of Industrial Edu., Suez, Suez Canal Univ., Egypt.
EM: [email protected] 3Dept of Elect Eng, Fac. of Eng., Port Said, Suez Canal Univ., Egypt.
EM: [email protected] 4Alex Higher Inst. of Eng. & Tech. / Fac. of Eng., Alex. Univ., Alexandria, Egypt.
Domino CMOS logic finds a wide variety of applications due to their high speed and low device count. In conventional CMOS domino logic, either the dynamic-node capacitor, CL is precharged to VDD during the precharge phase or predischarged to 0 V. The first precharging scheme is more suitable when logic “0” occurrence is more probable at the output due to the large saving in power consumption. On the other hand, the second predischarging scheme is more suitable when logic “1” is more probable at the output. In this paper, we will propose a novel technique to speed up the operation and minimize power consumption when there is an equal probability of occurrence of logic "0" and logic "1". This technique depends on precharging the dynamic node to VDD/2 instead of VDD during the precharge phase. Then, during the evaluation phase, the dynamic-node voltage will be either increased to VDD or decreased to 0 V depending on the state of the inputs. This, of course, saves much of the time and power consumption because discharging the dynamic node from VDD/2 to 0 V is much faster and consumes less power consumption than discharging it from VDD to 0 V. Also, the discharging process and noise margin will be enhanced by virtue of the fact that the time interval during which the keeper combats the discharging process is relatively very small. The proposed technique will be simulated for the 0.13 µm technology with VDD=1.2 V. Simulation results show that about 75% was shaved from the cycle time for the case of “0” and “1” outputs at the expense of an additional silicon area. Key Words: dynamic logic, low power, high speed, noise immunity. 1. Introduction
Due to their high speed and low device count especially compared to complementary CMOS, dynamic-logic circuits are used in a wide variety of applications including microprocessors, digital signal processors [1], and dynamic memory. The basic dynamic domino logic gate is shown in Fig. 1 [2]. As shown in the figure, it consists of a pull-down network (PDN) that realizes the desired logic function and there are two switches in series that are periodically operated by the clock signal CLK whose waveform is shown in Fig. 2. CL denotes the total parasitic capacitance between the dynamic node and ground. When CLK is low, QP is turned on, and the circuit is in the precharge phase where the dynamic node charges to VDD. Also, during precharge, the inputs are allowed to change and settle to their proper values. Because Qe is off, no path to ground exists. When CLK is high, QP is off and Qe turns on, and the circuit is in the evaluation phase.
During the evaluation phase; there are two possibilities for the dynamic-node voltage. If the input combination is one that corresponds to a low output, the dynamic-node voltage will be maintained at the supply voltage, VDD. On the other hand, if the input combination is one that corresponds to a high output, the dynamic-node voltage will be discharged to ground through the conducting NMOS transistors of the PDN.
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D Dw eak keeper
out
inputs
C LK
PD N
D D
PQ
Q e
dynam ic node
CL
Fig. 1 Basic structure of domino-logic circuit [2].
EvaluatePrecharge
VDD
t0
CLK
Fig. 2 Waveform of the clock needed to operate domino-logic circuit.
The conventional problem that arises during the evaluation phase is the inevitable leakage through the PDN when all the inputs are zeros. This leakage is due to the subthreshold current in the NMOS transistor when its gate-to-source voltage is less than its threshold voltage, the BTBT (band-to-band-tunneling) current, and gate tunneling current. These all add to the charge sharing that may occur between the dynamic-node capacitor and the internal capacitances of the NMOS transistors of the PDN. One solution to the problem of the leakage through the pull-down network (PDN) is to use a PMOS keeper [3] (refer to Fig. 1). This keeper acts to compensate for the leakage current and thus enhancing the noise immunity of the circuit. However, during the evaluation phase, if one of the transistors of the PDN is activated acting to discharge the dynamic node, the contention current supplied by the PMOS keeper slows down the discharging process. So, this keeper must be weak in order not to slow down the operation of the circuit. When the dynamic-node voltage decreases below the threshold voltage of the inverter, the weak keeper turns off and thus saving the power consumption and not fighting the discharging current of the PDN.
The remainder of this paper is organized as follows; Section II presents the problem to be solved in this paper, specifically, the time taken by the dynamic-node capacitor, CL to either discharge to ground during the evaluation phase in the precharged scheme or the time taken by CL to charge to VDD during the evaluation phase in the predischarged scheme. Section III presents our proposed solution where the dynamic-node capacitor, CL will be precharged to VDD/2 during the precharge phase instead of charging it to VDD, thus saving much of the time and power consumption. During the evaluation phase, CL will be either charged to VDD or discharged to 0 V depending on the state of the inputs. This will be achieved by a comparator whose output is connected to the gate of the PMOS keeper. This comparator compares between the dynamic-node voltage, VCL and a reference voltage, Vref. Simulation results will be presented and discussed in Section VI. Finally, the paper will be concluded in Section V.
2. Problem Statement
In the previous Section, we presented the most commonly used CMOS domino logic scheme in which the
dynamic node is precharged to VDD during the precharge phase, then deciding whether to keep the charge of CL intact or discharge it through the PDN during the evaluation phase. This scheme, of course, has relatively small power consumption in case the dynamic node must provide logic “1”. One other domino logic scheme is to predischarge the dynamic-node capacitor, CL to 0 V during the predischarge phase by an NMOS transistor, then
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deciding whether to charge it through the PUN (pull-up network) during the evaluation phase or to keep it discharged [4]. This scheme is shown in Fig. 3 with the CLK signal shown in Fig. 4.
out
L
inputs PUN
Qe
CLK
dynamic node
PQ
VDD
Cweak keeper
Fig. 3 The CMOS domino logic using the predischarge scheme [4].
0 t
Evaluate
CLK
DDVPredischarge
Fig. 4 The CLK signal according to the CMOS domino logic using the predischarge scheme.
The latter scheme has relatively small power consumption in case the dynamic node must provide logic “0”. The keeper according to this scheme will be an NMOS transistor in order to leak the leakage current and charge sharing through the pull-up network. The gate of the NMOS keeper is connected to the output node so that the keeper will shut down if the dynamic node is precharged during the evaluation phase through the PUN, thus saving power consumption.
Now, what about a novel scheme that precharges the dynamic node to VDD/2 instead of VDD or predischarging it to ground? Note that VDD/2 is neither a good “1” nor a good “0”, so a way must be provided to either charge CL to VDD or discharge it to 0 V. In the next Section, this technique will be discussed in detail. 3. Proposed Solution
In this section, we will present our proposed technique for speeding up the operation of the circuit. The
rationale behind this scheme is as follows. Refer to Fig. 5 for illustrating the proposed technique. During the precharge phase, the CLK signal will be zero, thus activating the header transistor, QP and charging CL to VDD/2. During the same time interval, the transistor, Qe will be deactivated. The comparator compares between the dynamic-node voltage, VCL and the reference voltage, Vref which will be chosen to be slightly smaller than VDD/2. Then, the CLK signal will be one beginning the evaluation phase when the dynamic-node voltage reaches VDD/2. So, the comparator output will be one as long as VCL is smaller than Vref, thus deactivating the keeper during this time interval. When VCL reaches Vref, the comparator output will be zero, thus activating the PMOS keeper, MP.
26th NATIONAL RADIO SCIENCE CONFERENCE, NRSC'2009 Future university, 5th Compound, New Cairo, Egypt, March 17-19, 2009
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During the evaluation phase, if the PDN doesn't provide a path for CL to discharge, then the dynamic-node voltage will be larger than Vref. So, the comparator output will be zero. The PMOS keeper will be activated, thus completing the charging of CL from VDD/2 to VDD.
Qe
CLK
Lc
comparatorrefV
keeper
out
VDDDDV
V CL
PDN
inputs
MP
QP
2
Fig. 5 The dynamic CMOS logic circuit according to the proposed scheme.
On the other hand, if the state of the inputs is such that there is a path to ground through the PDN, then CL will be discharged to a voltage that is less than Vref. So, the comparator output will be one, thus deactivating the PMOS keeper. The time saved by this technique is obviously due to two factors; the first one is the discharging of the dynamic-node capacitor, CL from VDD/2 to ground instead of discharging it from VDD to ground. The second factor is the deactivation of the PMOS keeper in case the dynamic-node capacitor, CL must be discharged, thus inhibiting the contention current from the keeper. Finally, the comparator may be realized by a differential amplifier, the output of which is taken single endedly and then fed to the gate of the PMOS keeper.
Qualitative Description of Differential Amplifier Operation
In this section, the operation of the differential amplifier will be discussed qualitatively. Refer to Fig. 6 for the circuit schematic of the differential amplifier adopted in this scheme.
MV CL
DD
1 M2
M3 4M
out1v v out2
V ref
C 1
C 2
Fig. 6 The circuit schematic of the differential amplifier used as a comparator.
In this circuit, the two input voltages to be compared by the differential amplifier are the dynamic-node voltage, VCL and the reference voltage, Vref. If VCL is larger than Vref, then the transistor, M1 conducts a larger current than that of M2 with the result that the output capacitor, C1 at vout1 will discharge faster than C2 at vout2. So, the PMOS transistor, M4 will be activated and conducts a larger current than that of M3. So, the output
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capacitor, C2 at vout2 will charge, thus acting to deactivate the PMOS transistor, M3 with the result that the current of M3 trying to charge C1 will decrease. This process is called positive feedback in that the discharging of the capacitor, C1 acts to charge C2 further and the charging of C2 acts to discharge C1 further. This process continues until the output voltage, vout1 decreases to 0 V and the output voltage, vout2 raises to VDD. The opposite occurs if Vref is larger than VCL. 4. Simulation Results and Discussion
The proposed technique will be simulated for the 0.13 µm technology with a power-supply voltage of 1.2 V. All transistors are assumed to be minimum-sized unless otherwise specified. The temperature is set at 27 °C in the simulation setup. The output capacitance is set at 2 fF. The aspect ratio of the NMOS transistors in the PDN along with the footer transistor is chosen to be 5. The fall time of any waveform is defined as the time between the 90% and 10% points of the waveform. We will run the simulation for an AND gate with two inputs, where there are two serially connected NMOS transistors in the PDN.
Refer to Fig. 7 for the dynamic-node voltages of the conventional and proposed methods for three values of the reference voltage, Vref= 0.7 V, 0.33 V, and 0.32 V. It is obvious that when the reference voltage decreases from 0.7 V to 0.33 V, the discharging process slows down slightly. This is because the differential amplifier output will be at logic "0" for a longer interval of time, thus activating the keeper and slowing down the operation.
However, when Vref= 0.32 V, the dynamic-node voltage will not discharge to 0 V due to the relatively large contention current from the keeper with the result that the noise margin degrades considerably (assuming that the noise margin is measured from VDD/2 to the steady-state value of Vref). The minimum value of the reference voltage, Vrefmin is thus 0.33 V.
(a)
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(b)
(c)
Fig. 7 The dynamic-node voltage according to the conventional and proposed schemes in case the dynamic-node voltage must be at logic “0” for three different values of Vref; (a) 0.7 V, (b) 0.33 V, and (c)
0.32 V.
Now, Figs. 8 (a) and (b) show the dynamic-node voltage for the case the dynamic-node voltage is to be at logic "1" during the evaluation phase for Vref=0.7 V and Vref=0.33 V with the keeper minimum-sized. The dynamic-node voltage will reach VDD at approximately 950 nS for Vref=0.7 V and at approximately 900 nS for Vref=0.33 V. This is a slight enhancement in speed. The keeper size can instead be increased to speed up the charging process of CL. Fig. 8 (c) shows VCL for Vref=0.33 V and with aspect ratio of the keeper=6. The dynamic-node voltage reaches VDD at approximately 700 nS. However, in case the dynamic-node voltage must be at logic "0" during the evaluation phase, the discharging speed and the noise margin degrade considerably as shown in Fig. 9 for the aspect ratio of the keeper=6. Thus, the process requires a suitable selection of Vref and the size of the keeper in order to obtain the minimum discharging time and the maximum noise margin in the two cases; logic "0" and logic "1" for VCL. This requires solving an optimization problem in a two-dimensional design space for selecting Vref and the aspect ratio of the keeper.
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(a)
(b)
(c)
Fig. 8 The dynamic-node voltage according to the conventional and proposed schemes in case the
dynamic-node voltage must be at logic “1” for: (a) Vref = 0.7 V with minimum-sized keeper, (b) Vref = 0.33 V with minimum-sized keeper, and (c) Vref = 0.32 V with the aspect ratio of the keeper = 6.
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Fig. 9 The dynamic-node voltage according to the conventional and proposed schemes in case the
dynamic-node voltage must be at logic “0” for Vref = 0.7 V and the aspect ratio of the keeper = 6. Note the obvious degradation in the
discharging speed and noise margin.
5. Conclusions
Optical communications systems are increasingly used nowadays especially for communicating throughout the world using the internet [5]. These types of systems have electronic parts for the transmitter, receiver, and repeaters among others. Of course, light is much faster than the electron, so the maximum speed of these types of systems is determined by their electronic parts. For these systems, the speed of the electronic systems is thus of paramount importance and the optical communications engineers still cry "speed up your electronic equipments". In this paper, a novel technique for increasing the speed of CMOS domino logic was proposed and compared with the conventional scheme for the two cases of the output. The proposed technique depends on precharging the dynamic node to VDD/2 instead of charging it to VDD, thus saving much of the precharge and evaluation times. During the evaluation phase, the dynamic node will be either increased to VDD or discharged to ground depending on the inputs’ status. This can be accomplished by a comparator which compares the dynamic-node voltage to a voltage that is slightly lower than VDD/2. Using this technique will save approximately 75% of the cycle time in case the dynamic node must be at logic “0” at the cost of an additional silicon area.
References
[1] H. L. Yeager et al, "Domino Circuit Topology," U. S. Patent 6784695, Aug. 31, 2004. [2] A. S. Sedra and K. C. Smith, Microelectronic Circuits, Fourth Edition, New York: Oxford, 1998. [3] L. Ding and P. Mazumder, "On Circuit Techniques to Improve Noise Immunity of CMOS Dynamic Logic," IEEE Transactions on Circuits and Systems, 2004. [4] S. M. Kang and Y. Leblebici, CMOS Digital Integrated Circuits, Analysis and Design, Second Edition, McGraw-Hill, 1999. [5] Y. S. Abdalla, "Design of High Speed MUX/DMUX Using a New All-Time-On Single-Ended CMOS Logic", Ph. D. Thesis, University of Waterloo, Waterloo, Ontario, Canada, 2006.
