Intermodulation Distortion in CMOS Attenuators and Switches

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 3, MARCH 2007 529

Intermodulation Distortion in CMOSAttenuators and Switches

Hakan Dogan, Student Member, IEEE, and Robert G. Meyer, Fellow, IEEE

Abstract—Gain control elements are widely used in communica-tion systems both to limit the incident power to the circuitry andto control the amplitude of the transmitted signal. Attenuators areone way of controlling the signal amplitude. The distortion perfor-mance of common CMOS attenuator topologies is investigated inthis work. CMOS device equations that model the device in dif-ferent regions of operation and which also model short channeleffects are used for calculating distortion performance. Calculateddistortion is compared with simulation results and experimentaldata, and qualitative explanations of the distortion curves as well asthe deviation between different sources of data are given. Potentialimprovements in linearity performance of attenuators via circuitdesign techniques have also been discussed.

Index Terms—Attenuators, CMOS, distortion, harmonic bal-ance, Pi-network, switches, T-network, Volterra.

I. INTRODUCTION

GAIN-CONTROL elements are widely used in moderncommunication systems. Although variable gain ampli-

fiers (VGAs) have been the traditional way of implementinggain control, linearity and power handling requirements resultin very high power dissipation in these active blocks. FETdevices in their resistive linear region on the other hand canbe used as variable resistors to design attenuators with higher1 dB compression point and lower power dissipation. The lowcost and availability of CMOS makes it an attractive choice oftechnology to implement wideband multi-purpose attenuators,which can be integrated on chip in a system design.

Design parameters for attenuators can be summarized as min-imum insertion loss, maximum isolation, satisfactory sourceand load matching, linearity and noise performance. A goodattenuator is expected to have a very small signal loss when itis in the minimum attenuation setting, high isolation when itis in the maximum attenuation setting, good source and loadmatching for maximum power transfer, be highly linear andgenerate very small noise. Especially the first three parametersare highly correlated with each other and usually improving onedegrades the others. This paper solely focuses on the distortionperformance of the attenuators, and the readers should refer tovarious other publications regarding all the design parametersof attenuators [1]–[3], [10], [11].

Manuscript received April 26, 2006; revised August 28, 2006. This work wassupported by the U.S. Army Research Office under grant DAAD19-00-1-0550.

H. Dogan is with Atheros Communications, Santa Clara, CA 95054 USA(e-mail: [email protected]).

R. G. Meyer is with the Department of Electrical Engineering and ComputerScience, University of California, Berkeley, CA 94720 USA.

Digital Object Identifier 10.1109/JSSC.2006.891445

Attenuator blocks can be used in front of a constant gain am-plifier to limit the incident power to the amplifier. If the atten-uator is highly linear, this approach is superior to applying thesignal to a VGA that incorporates some sort of attenuation cir-cuitry, since the signal is attenuated before it is applied to theactive block. On the contrary, in a VGA, the signal is attenuatedin the amplifier by means of current diverting or signal shuntingvia CMOS resistor devices in differential applications. Theseimplementations have many design challenges. Firstly, the VGAneeds to be able to handle very high input power by means ofhigher power dissipation since the signal is not attenuated be-fore being applied to the amplifier. Secondly, transistors in theirpassive region have much better power handling then when theyare used as active amplifiers. Apart from these reasons, there aremany other challenges that the designers face during the designprocess, which are beyond the scope of this paper and there-fore are not explained here. Consequently, standalone attenua-tors should be considered as a good candidate for gain controlin transceiver chains. Despite the importance of these circuits,little has been published on the linearity performance of CMOSattenuators. In this paper we derive equations for the distortionperformance of CMOS attenuators and compare the theoreticalresults with measured values.

Fig. 1 shows two types of resistor networks commonly usedto design attenuators, namely the -Network [1], [2] and theT-Network [2], [3].

The MOS transistors in these networks are used in their re-sistive triode region to realize voltage controllable resistors. Ofthe two topologies, the topology has the broadest frequencyresponse. The series devices in both topologies are made largeto achieve minimal insertion loss. The shunt devices in theconfiguration are mainly used for matching to the source andload impedances, whereas in the T configuration, the shunt de-vice is used to make the internal node a low impedance to signalground. Therefore, for higher attenuation, shunt devices in thelatter configuration are made larger and this limits the frequencyresponse compared to a topology.

II. DEVICE EQUATIONS

In both the and T configurations, the transistors operatein strong inversion, moderate inversion and weak inversion atany given time, depending on the attenuation value. Existingmodels that divide the operation into multiple regions with dif-ferent equations become troublesome in calculating distortionin attenuators since, in this case, the operation region of eachtransistor need to be determined first and the circuit has to besolved for each condition separately. Therefore, a single equa-tion, which models the transistor in different regions of opera-tion, is desirable.

0018-9200/$25.00 © 2007 IEEE

530 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 3, MARCH 2007

Fig. 1. Attenuator networks. (a) �. (b) T.

MOS models with continuous equations have been presentedpreviously in [4] and [5]. In this work, similar equations incor-porating continuous transition between different regions of op-eration will be used. The deviation from square law due to shortchannel dimensions will be modeled to the first order. The draincurrent for the transistors as a function of gate-source anddrain-source voltage is modeled in this paper by [4]–[6]

(1)where

(2)

(3)

(4)

In the equations above, is the threshold voltage, isthe thermal voltage . is a well known technology con-stant, which is a function of the mobility of the carriers, gateoxide thickness, transistor channel length and width. modelsthe drain and source resistances, mobility degradation and othershort channel effects. The exponential increase of the drain cur-rent with value in the subthreshold region is modeled bythe parameter .

Equation (1) reduces to the well-known strong inversion andweak inversion equations of MOS devices in the triode regiondepending on the operating conditions. When isconsiderably larger than , given that is small, theexponential term dominates the 1 term in the logarithmic paren-

thesis and and reduces to and, respectively. The drain current then reduces to

(5)

Similarly, when is considerably smaller than, again given that is small, the exponential term be-

comes very small compared to 1 term and and reduceto and re-spectively. Therefore, the drain current reduces to

(6)

Now, given that the last term in parenthesis in (6) can be ig-nored because the exponential term is fairly small compared tounity, the current equation collapses down to the well-knownexponential weak inversion equation of MOS devices. In thetransition region (weak inversion to strong inversion) of mod-erate inversion, (1) models the drain current of MOS deviceswell enough for hand analysis purposes.

The parameters and need to be chosen carefully for accu-rate modeling of the transistors in different regions of operation.For this purpose, a 10 m wide and minimum length (0.13 m)nMOS device has been tested and the drain current, , versusdrain-source voltage, was measured for different gate volt-ages . Using the measured data, and parameters wereextracted for different regions of operation. varies from 1.4 inweak inversion (corresponding to ) to 0.7 in stronginversion (corresponding to ). on the other handvaries from 5 in weak inversion to around 1 in strong inver-sion for a best fit using the least squares fit algorithm. Theseparameters were extracted for different operating conditions ofthe transistor that depend on the gate voltages, using measure-ments taken from a transistor test structure. Linear interpolationwas used to get the and values for different operating pointsdepending on the attenuation setting and corresponding oper-ating condition of the device.

The test structures used to extract the model parameters wereon the same die as the attenuator structures. The bulk of the diewas grounded strongly by extensive use of taps to preventany significant signal leakage to the substrate node of the tran-sistors. Provided that the bulk is strongly grounded in the tran-sistor, the drain to source voltage is swept from negative valuesto positive values in order to obtain drain current as a functionof drain-source voltage and the equation in (1) is then fit to thisdata. Following this procedure assures that any drain current de-pendence with the source-bulk voltage or drain-bulk voltage forgrounded bulk terminal is taken into account in the equation. Ex-plicitly, the data points used to fit the (1) has body effect and thisis modeled in the equation by means of parameters as a result.

III. ATTENUATOR DISTORTION CALCULATIONS

A. CMOS Drain Current Expansion

Before deriving the distortion equations, we need to expandthe large signal current equation of a CMOS device into its har-monics. In this way, we will be able to write the signal com-ponents of the drain current as a sum of all the harmonics as

DOGAN AND MEYER: INTERMODULATION DISTORTION IN CMOS ATTENUATORS AND SWITCHES 531

Fig. 2. Large signal harmonic interpretation of a CMOS device.

given in Fig. 2. Subsequently, we can use the Harmonic Bal-ance method to find the amplitude of any of the harmonics at agiven node [7]–[9].

The signal components at the two terminals of the MOS re-sistor are given as and . The gate is assumed to bemodulated with a fraction ( and ) of each of the drain andsource signals as a result of bootstrapping due to the parasiticgate overlap and oxide capacitors. In the presence of a signalacross the device, and consist of harmonics of theinput excitation to the circuit , therefore can be written as

(7)

(8)

Equation (1) can be written as the combination of three func-tions as

(9)

where

(10)

(11)

(12)

The signal components in , and are due to signalswing across the gate-source and the drain-source terminals ofthe CMOS device and can be written as

(13)

(14)

Using the Taylor Series expansion, we now can expand eachof , , and around zero to get the harmonic representation

of these functions. Given that and consist of har-monics of the input voltage , the drain current of the CMOSdevice can also be represented as a function of the harmonics of

. If we denote the first, second and third derivatives ofwith respect to at zero with , , and , respec-tively, and similarly the derivatives of with respect to atzero with , , and and the derivatives of with re-spect to at zero with , , and , we can write thesignal current through the MOS device as

(15)

Given that the drain-source bias voltage is zero in the ana-lyzed attenuator circuits, the derivatives of the functions and

at zero will be equal. Now, if we represent as a function ofthe harmonics of as

(16)

then , and can be derived from (15) as

(17)

(18)

(19)

Using (16) for the drain current of MOS devices in triode, wenow can analyze the distortion in attenuator circuits, which isshown in the next section.

B. Distortion Calculations

1) -Network: Fig. 3 gives the schematic of a -Attenuatorwith the currents in each branch. The attenuation is achieved inthis network by increasing the resistance of the series deviceby means of decreasing its gate voltage. Simultaneously, thegate voltages of the shunt devices are increased to decrease thechannel resistance of these devices, therefore compensate for in-creased resistance at the input and output ports of the attenuator


Fig. 3. �-Network with source and load resistors.

network. The quiescent bias voltages at the input and output ofthe network are set to ground in order to achieve minimum onresistance from the devices. As a result, there is no quiescentcurrent but only signal current in the network. In order to solvefor distortion, we can write Kirchoff’s Current Equations at eachnode and solve for the current components for each harmonic ofthe input signal frequency. In this analysis, only the feedthroughcapacitor is considered as a frequency dependent compo-nent. This capacitor consists of the oxide and overlap capacitorsfrom gate to drain and source, and it was assumed constant overdifferent operating points for the device. A large gate resistorconnected from the control voltage to the gate of bypassesthese parasitic capacitors from drain to source, and thereforecreates a feedthrough path from input to the output. These ca-pacitors have two main effects on the circuit. Firstly, they limitthe maximum attenuation at higher frequencies and secondly,they cause the gate to be modulated with a fraction of the drainand source voltages. That is, they determine the values of and

in (13) and (14). All the other capacitors from the nodesand to ground are ignored in this analysis since these capac-itors in a -network are fairly small and they have very minoreffect at the frequencies of interest.

and in Fig. 3 can be expressed as a function of theinput voltage harmonics. Since, there is a frequency de-pendent element in the circuit, we need to represent andwith Volterra Series coefficients as

(20)

(21)

The operator “ ” stands for multiplication in Volterra seriesand denotes multiplication of the amplitude of each frequencycomponent and shift of the phase with the appropriate value.

We can write the KCL equations for Fig. 3 as

(22)

(23)

Equations (22) and (23) can be expressed in terms of the ter-minal voltages as

(24)

(25)

Now that we have the equations for the sum of the currentsat each node in Fig. 3, we can solve for each of the currentharmonics going in or out of each node using the HarmonicBalance Method. Explicitly, the equations for the first harmoniccan be written as (A1) and (A2) given in the Appendix.

The term in (A1) and (A2) represents theexpression in (17) for the MOS transistor . Similarly,and represent the same expression for the transistorsand respectively and are equal in value since andare identical in size and have the same quiescent operatingcondition.

Given that is equal to , solving (A1) and (A2) for, we get

(26)

Similarly, we can also write the current equations for thesecond-order products as given in (A3) and (A4). Solving theseequations we get as shown in (27) at the bottomof the page.

The terms denote the sum of all terms for transistor“n” after the first term in (18), which has and in it.Since and are already solved for,becomes a known value in the solution for and

.Lastly, current equations for the third-order products can be

written as given in (A5) and (A6). Solving these equations for, we get (28), shown at the bottom of the next

page.The terms denote the sum of all terms for transistor

“n” after the first term in (19), which has and in it.Since , , andare already solved for, becomes a known quantity in thesolution for and .

The and products at the output node at frequencyand , respectively, can now be calcu-

lated using the Volterra series coefficients and

(27)


. Given these solutions, we now can solve forintermodulation distortion assuming that two tones with equalamplitudes and close frequencies are applied to the network atthe input port as

(29)

For calculation, input frequencies are set toand , whereas for calculation, input frequenciesare set to and . and can becalculated as [4], [7]

(30)

(31)

Setting these equations equal to unity gives the amplitude ofthe input signal that results in equal amount of signal and dis-tortion terms at the output. Using these amplitude values, corre-sponding intercept points can be easily calculated to be

(32)

(33)

Figs. 4 and 5 give the calculated, simulated and measured dis-tortion performance in terms of second and third-order input-in-tercept points for a single stage -attenuator for low frequencyinput signals. The -attenuator analyzed consists of a 150 mseries device and 10 m shunt devices with minimum channellength of 0.13 m. The series device size was chosen arbitrarilyto achieve less then 1 dB insertion loss. The shunt device sizeswere chosen to achieve 50 on-resistance for good matchingwhen the gate voltage is equal to 1.2 V. At the minimum attenu-ation setting, the series device is turned on by applying 1.2 Vto the gate of this device. The shunt devices are kept off byapplying zero volts to their gates. In this setting, the sourceimpedance of the preceding stage matches to the sum of theon resistance of the series device and the load impedance andvice versa. As the attenuation is increased by reducing the gatevoltage of the series device, therefore increasing its resistance,the shunt devices are turned on gradually to accommodate forthe increasing input impedance due to the increasing channelresistance of the series device, therefore to achieve sufficientmatching. At the maximum attenuation setting, the series deviceis turned off and the shunt device is turned on completely. Theon-resistances of the shunt devices match to the source and loadimpedances in this setting. At high frequencies, the matching at

Fig. 4. IIP2 results for two tones at 99–100 MHz for the �-Network.

the input and output deviate from ideal as a result of parasitic ca-pacitances from the devices and the interconnections. However,it has been shown in literature that these networks are quite wideband and can achieve better than 10 dB S11 at frequencies ashigh as 10 GHz. [11] The quiescent voltages at the drain andsources of these devices are set to 0 V in order to minimize theon resistance as mentioned previously. Each gate in this networkhas a very large resistance in series for isolation and bootstrap-ping purposes. As a result of these gate resistances and parasiticgate-drain and gate-source capacitors, bootstrapping is achievedat the gates of the transistors.

The measurements were made by applying the control volt-ages and two tone signals by probing. Control voltagesand were supplied from a voltage source via DC probes.Adequate matching to source and load were achieved by meansof careful choice of control voltages along the attenuationrange. Two HP signal generators along with a Mini-Circuitspower combiner were used to combine two tones to apply atthe input port of the attenuator via Cascade high-frequencyprobes. The output was observed with a HP spectrum ana-lyzer. Signal frequencies of 99–100 MHz were chosen forlow frequency testing since these frequencies are within theCable TV operation bandwidth. For high frequency testing,1.799–1.8 GHz were used since these are cellular frequencies.These frequencies were chosen arbitrarily and the results canbe extrapolated to different bands of operation. For simulatedresults, Spectre simulator was used.

It is evident from Figs. 4 and 5 that the attenuator is highlylinear when it is in the minimum attenuation settings. This re-sult is not surprising since in the minimum attenuation setting,

(28)


Fig. 5. IIP3 results for two tones at 99–100 MHz for the �-Network.

the shunt devices are off, not generating any distortion and theseries device is on with a very large overdrive voltage and smallon-resistance. Consequently, the signal amplitude across the se-ries device is small and the device is highly linear because ofthe large gate voltage, resulting in the high intercept points.

As the shunt devices start turning on with increasing attenua-tion, they start contributing to distortion, therefore the interceptpoints start decreasing sharply. As the attenuation increases fur-ther, the gate overdrive voltage of the shunt devices gets largerand the linearity of these devices improve. This gives the rise inthe intercept points in the graphs. However, further attenuationresults in the gate voltage of the series device to drop to sub-threshold regions, degrading the linearity of this device. Conse-quently, the linearity metrics given by Figs. 4 and 5 settle downto values less than 0 dBm.

Figs. 6 and 7 give the second-order and third-order input inter-cept points for two input tones at 1.799 GHz and 1.8 GHz. Thesecurves have the same trend as the low-frequency curves, how-ever the absolute values are improved for the high-frequencydistortion results. This result is mainly due to better modula-tion of the gate of the devices via capacitive bootstrapping ofsource and drain to the gate. It has been shown in the litera-ture that bootstrapped devices have better linearity performancecompared to their grounded counterparts.

It is also observed in the high-frequency curves that the max-imum attenuation in these is smaller than in the low-frequencycurves. This is a direct result of feedthrough from input to theoutput caused by capacitor in Fig. 3. As the channel resis-tance of the series device increases, it eventually becomes largerthan the impedance of this feedthrough capacitor. Consequently,the attenuation cannot be increased appreciably even though thegate voltage of the series device is decreased further. However,reducing this gate voltage tends to completely turn off the seriesdevice. Accordingly, the distortion generated by the series de-vice decreases as it turns off further even though the attenuationstays the same. This results in the improvement in distortion to-wards the end of the attenuation curve, as shown in the last partof the curves in Figs. 6 and 7.

Fig. 6. IIP2 results for two tones at 1.799–1.8 GHz for the �-Network.

Fig. 7. IIP3 results for two tones at 1.799–1.8 GHz for the �-Network.

2) T-Network: Fig. 8 gives the schematic of a T-Attenuatorwith the current components at each node. In a manner similar tothe analysis of the -Attenuator, we can write Kirchoff’s Cur-rent Equations for each node and solve for the branch currentsthat are harmonics of the input signal frequency. In this anal-ysis, unlike the -Attenuator, we will include the total parasiticcapacitors from each node to ground, namely , , and ,since the devices in a T-Network are considerably larger than the

-Network, therefore resulting in larger total parasitic capaci-tors. These capacitors mainly consist of the junction capacitorsfrom the drain and source to the bulk node, and they were as-sumed constant over different operating conditions of the devicefor the sake of simplicity. The gate capacitors are bypassed fromdrain to source using large gate resistors. They were omitted inthis analysis in view of the fact that the series devices have anequivalent resistor of or smaller at all operating conditions,therefore minimizing the effect of the bypass capacitors. Theironly role in this analysis is defining the values of and in (13)


Fig. 8. T-Network with source and load resistors.

and (14). Gate capacitors of are lumped in since they arein series and terminate at ground. Furthermore, the resistorsand are included in the schematic to view the effects of thesein the distortion performance. Setting and equal toforces the series devices to turn off at the maximum attenuationfor adequate impedance matching.

, , and in Fig. 8 can be expressed as a function ofthe input voltage harmonics. Since, there is a frequencydependent element in the circuit, we need to represent ,and with Volterra Series coefficients as

(34)

(35)

(36)

We can write the KCL equations for Fig. 8 as

(37)

(38)

(39)

Equations (37), (38), and (39) can be expressed in terms ofthe terminal voltages as

(40)

(41)

(42)

We now can solve for each of the current harmonics at eachnode using these equations. Equations for the harmonics can bewritten similar to given in the Appendix for the -Network. De-vices and are equal in size and have the same quiescentoperating condition, therefore and are equal in value.Capacitors and represent the junction capacitors forand as explained above and are equal in size. Assumingis equal to and is equal to , we get

(43)

where , and are given as

(44)

(45)

(46)

Similarly, we can also write the current equations for thesecond-order products and solve for

(47)

where , and are given in (44), (45) and (46) respectively,and are given as

(48)

(49)

Finally, current equations for the third-order products can bewritten and solved to get

(50)

where , , , , and are given as (44), (45), (46), (48),and (49), respectively, and and are given as

(51)

(52)

Figs. 9 and 10 give the input intercept point plots for thesecond-order and third-order distortion terms. The T attenuatoranalyzed for these results consists of 250 m devices both forthe series and shunt devices with minimum channel length of0.13 m. The series device sizes were chosen arbitrarily to giveless than 1 dB insertion loss. The shunt device was chosen ar-bitrarily large enough to give 25–30 dB attenuation when it isentirely on. At the minimum attenuation setting, the shunt de-vice is off and the source impedance matches to the sum of theon-resistances of the two series devices and the load impedance.Attenuation is achieved by turning on the shunt device, there-fore shunting the signal to the ground via this path. The seriesdevice resistance is increased simultaneously to accommodatefor the decreasing input and output impedances as a result of


Fig. 9. IIP2 results with two tones at the input for the T-Network.


the smaller resistance of the shunt device. At the maximum at-tenuation setting, the shunt device is turned on completely andthe series device resistance is set to slightly less than 50 . Thesource approximately matches to the sum of the series deviceresistance and the small shunt device resistance of 1–2 inthis setting. Parasitic capacitances in the circuit deteriorate thematching at high frequencies, however it has been shown previ-ously by the same authors that very wideband T-attenuators withadequate matching can be designed [10] The operating condi-tions and the measurement setup are similar to the -Attenu-ator setup as explained in the previous section. The shapes ofthe curves in Figs. 9 and 10 are similar to the -Network plotswith small differences. At minimum attenuation, the attenuatoris highly linear since the series devices are completely on withsmall resistances and the shunt device is off. In order to increaseattenuation, the shunt device starts turning on and generating



distortion, therefore the curve goes down as the attenuation in-creases. Just like the -Network, as the shunt device turns onfurther with larger gate control voltage, the linearity of this de-vice improves. Nevertheless, larger attenuation settings reducethe gate voltage of the series device and consequently the lin-earity of the attenuator degrades further.

It is evident from Figs. 9 and 10 that the linearity of the T-Net-work is better than the -Network at higher attenuation settings.This can be explained by realizing that even at the highest atten-uation setting, the series devices in the T-Network have equiva-lent impedances of . Therefore, the overdrive voltages at thegates of these devices drop to around the threshold voltage evenat the highest attenuation. This limits the degradation on the lin-earity of the attenuator circuit, therefore the distortion curvesbelow are slightly better than the previous case.

Simulations and calculations show that the distortion perfor-mance of the T-Network is quite independent of frequency aslong as the bootstrapping at the gate is in effect. This result is


expected since each node in this network has at most an equiv-alent resistance of under all operating conditions. Con-sequently, distortion generation has very minor dependence onfrequency within the useful operation band of the attenuator.This result has also been verified through measurement results.

Figs. 11 and 12 show the effect of placing a resistor in shuntwith the series device as shown in Fig. 8. The size of this resistoris picked up to be equal to the values of the source and load resis-tances. In the minimum attenuation setting, small series deviceresistance dominates the parallel combination. However, as theattenuation setting moves towards maximum attenuation, theseresistors require the series device to turn off so that the input andoutput matching is achieved by the series combination of the re-sistors in shunt with the series device and small on-resistance ofthe shunt device. Consequently, the series device turns off com-pletely and does not contribute to the distortion generation inthe circuit. Given that the shunt device is completely on with alarge gate overdrive voltage, this device is also highly linear. Asa result, the distortion performance of the T-Network improvesat higher attenuations as shown in the Figs. 11 and 12.

This conclusion is very important in the sense that improvinglinearity at higher attenuation settings is highly desirable. Atten-uation in the receiver chains is usually required in order to limitlarge incoming signal amplitudes. Therefore, higher attenuationsettings correspond with higher input power levels. Since thedistortion terms increase with the square and cube of the inputsignal power, distortion generation in the attenuator block in-creases dramatically with increasing signal power. Thus, if thelinearity of the attenuator block improves at higher attenuationsettings, distortion generation can be limited even with highersignal amplitudes.

IV. CONCLUSION

This paper uses a device equation that is valid in differentregions of operations to solve for intermodulation distortion inpassive CMOS attenuators. The calculated results are comparedto simulated and measured results for verification.

The results given above show a general trend for distortiongeneration in CMOS attenuators. Attenuators in general arehighly linear in the minimum attenuation setting for the reasonsgiven in the previous sections. As the attenuation increases,the linearity of the attenuators worsens due to turn on of shuntdevices in the networks since they start contributing distortion.Increasing the attenuation further results in lower gate voltagefor the series devices, and this gives rise to even more non-linearity. Overall, we can easily conclude that the linearity ofattenuators in general degrades with increasing attenuation.

It has also been shown that the linearity of the attenuators canbe improved with increasing attenuation by forcing devices inthe network to either turn on or off completely with increasingattenuation. This can be done by inserting resistors in shuntwith these devices as shown in the above sections. These linearphysical resistors can be made to dominate the MOS devicesas the attenuation increases and consequently, the linearity ofthe network can be made to improve [10]. A similar approachcan be used in the -network by placing a large shunt resistor

( 1–2 ) with the series devices. At the maximum attenua-tion, these physical resistors dominate the equivalent resistanceand the distortion introduced by the series device can be mini-mized. However, it is important to realize that the introduced re-sistor will degrade the maximum attenuation achievable by thenetwork since this is a direct function of the series resistancevalue.

It is important to conclude from the analysis given in thispaper that the T-network is more linear than the -network.Given the fact that the gain control elements are desired to bemore linear at higher attenuation settings, the superiority of theT-network is much more pronounced. While the IIP2 of the net-works can be improved greatly with a differential approach, thethird-order products will be untouched for both of the networks.The -network settles around 5 dBm and 0 dBm IIP3 in low-frequency and high-frequency measurements, respectively, atthe highest attenuation settings. The same measurements show13 dBm and 18 dBm IIP3 respectively for the T-networks withand without the resistors in shunt with the series devices. Thelowest measured IIP3 for these networks is around 8 dBm. How-ever, these values occur at lower attenuation settings and thesesettings are for smaller input power levels. Consequently, gener-ated IM3 products are going to be lower as a result of less inputpower at these attenuation points. We can easily conclude thatthe worst case linearity for the attenuators in test is at highestattenuation settings.

Although the linearity of attenuators has dips in the attenua-tion range, it is very important to notice that the overall linearitystays relatively high in the whole operation range. In both typesof attenuators, measured worst case IIP2 and IIP3 are slightlyless than 0 dBm. This performance is generally higher than whatis expected from most wireless application gain control blocks.Given that these attenuators can be implemented on-chip withvery small static power dissipation, use of these linear blocks atthe input of a receiver chain will have a direct impact on the lin-earity and power dissipation of the whole system, since they willrelax the design constraints for the rest of the circuitry. Highlylinear CMOS attenuator designs have been shown in the litera-ture [10], [11].

There is also need to comment on how well the plots givenin this paper match to each other. The plots show that the cal-culated and measured results match each other better than thesimulated results. This is mainly due to the fact that BSIM3 hasbeen known to be problematic for distortion simulations of cir-cuit blocks that have devices with drain-source voltages of zero.Given that BSIM3 does not provide a symmetric model andit chooses the lower potential side of the device as the sourceterminal, whenever the drain-source voltage swings to nega-tive values, the simulator switches the drain and the source sideabruptly, resulting in a discontinuity in the drain current. Thisintroduces additional distortion in the circuits such as attenua-tors, switches etc., which makes it very difficult to predict thedistortion with simulation. This problem has been addressed inthe EKV or more recent BSIM4 modeling [12]. These modelswere not available to the authors, therefore the EKV and BSIM4results were omitted in this work.


The mismatch in measured and calculated results has threesources. One is as a result of poor modeling of the networkfor calculations, namely, the limited representation of the ac-tual transistor characteristics by the device equation used in cal-culations and poor bootstrapping at the gates of the devices asa result of the finite value gate resistors used. The other is thelimitation in measurements. This error is especially pronouncedat the regions where the attenuator is highly linear and the at-tenuation is somewhat high. This is mainly because the inputreferred distortion generation is already small in these regionsand the distortion becomes even smaller when measured at theoutput, as a result of the attenuation. In order to view measur-able distortion, the input power applied had to be increased tomore than 5 dBm in some cases and this invalidates the as-sumption of our analysis that the input is a small signal source.Hence, there is additional deviation from small-signal estima-tion due to large-signal effects. Lastly, the attenuation curvesof the attenuators have many nulls in the attenuation curve as aresult of distortion cancellation between the devices in the net-work. These nulls are functions of the operating DC voltages ofeach transistor. In this analysis, simulation results were used todetermine the control voltages in the networks and these volt-ages were used to generate the distortion plots for all measured,simulated and calculated results. Consequently, the curves andthe nulls shift from each other since the three curves assumedifferent device dynamics. In some cases as in Fig. 11, thereis discrepancy in excess of 20 dB as a result of these nulls ap-pearing in one of the curves but not the others. However, thetrend in the distortion curves rather than specific points shouldbe heeded for good understanding of the performance of the net-works investigated.

APPENDIX

First-order harmonic equations for the -Network is given as

(A1)

(A2)

Similarly, second-order harmonic equations for the same net-work are

(A3)

(A4)

Finally, third-order harmonic equations for the same networkare

(A5)

(A6)

ACKNOWLEDGMENT

The authors would like to thank ST Microelectronics for chipfabrication.

REFERENCES

[1] D. Fisher and D. Dobkin, “A temperature-compensated linearizingtechnique for MMIC attenuators utilizing GaAs MESFETs asvoltage-variable resistors,” in IEEE MTT-S Dig., May 1990, pp.781–784.

[2] R. Kaunisto, P. Korpi, J. Kiraly, and K. Halonen, “A linear-controlwideband CMOS attenuator,” in Proc. IEEE ISCAS, 2001, vol. 4, pp.458–461.

[3] H. Kondoh, “DC-50 GHz MMIC variable attenuator with a 30 dB dy-namic range,” in IEEE MTT-S Dig., Jun. 1988, pp. 499–502.

[4] M. T. Terrovitis and R. G. Meyer, “Intermodulation distortion in cur-rent-commutating CMOS mixers,” IEEE J. Solid-State Circuits, vol.35, no. 10, pp. 1461–1473, Oct. 2000.

[5] Y. Tsividis, K. Suyama, and K. Vavelidis, “Simple reconciliationMOSFET model valid in all regions,” Electron. Lett., pp. 506–508,Mar. 1995.

[6] Y. Tsividis, Operation and Modeling of the MOS Transistor. NewYork: McGraw-Hill, 1999.

[7] K. L. Fong and R. G. Meyer, “High-frequency nonlinearity analysis ofcommon-emitter and differential pair transconductance stages,” IEEEJ. Solid-State Circuits, vol. 33, no. 4, pp. 548–555, Apr. 1998.

[8] R. G. Meyer, “Intermodulation in high-frequency bipolar transistor in-tegrated-circuit mixers,” IEEE J. Solid-State Circuits, vol. SC-21, no.4, pp. 534–537, Aug. 1986.

[9] W. M. C. Sansen and R. G. Meyer, “Distortion in bipolar transistorvariable-gain amplifiers,” IEEE J. Solid-State Circuits, vol. SC-8, no.4, pp. 275–282, Aug. 1973.

[10] H. Dogan, R. G. Meyer, and A. M. Niknejad, “A DC-2.5 GHz wide-dy-namic-range attenuator in 0.13 �m CMOS technology,” in Proc. VLSICircuits Symp., 2005, pp. 90–93.

[11] ——, “A DC-10 GHz linear-in-dB attenuator in 0.13 �m CMOS tech-nology,” in Proc. IEEE Custom Integrated Circuits Conf., 2004, pp.609–612.

[12] “BSIM3 Version 3 Manual, Final Version,” BSIM Research Group,Dept. Elec. Eng. Comput. Sci., Univ. California, Berkeley [Online].Available: http://www-device.EECS.Berkeley.EDU/~bsim3

[13] R. Bayruns et al., “The Bootstrapped Gate FET (BGFET)—a new con-trol transistor,” in Proc. IEEE GaAs IC Symp., 1995, pp. 136–139.

[14] R. H. Caverly, “Linear and nonlinear characteristics of the siliconCMOS monolithic 50- microwave and RF control element,” IEEE J.Solid-State Circuits, vol. 34, no. 1, pp. 124–126, Jan. 1999.

[15] R. G. Meyer and P. R. Gray, Analysis and Design of Analog IntegratedCircuits, 3rd ed. New York: Wiley, 1993.

[16] S. W. Son, “High dynamic range CMOS mixer design,” Ph.D. disser-tation, Univ. California, Berkeley, 2002.


[17] H. J. Sun and J. Ewan, “A 2–18 GHz monolithic variable attenuatorusing novel triple-gate MESFETs,” in IEEE MTT-S Dig., 1990, pp.777–780.

[18] K. Vavelidis, Y. Tsividis, F. O. Eynde, and Y. Papananos, “Six terminalMOSFETs: modeling and applications in highly linear, electronicallytunable resistors,” IEEE J. Solid-State Circuits, vol. 32, no. 1, pp. 4–12,Jan. 1997.

Hakan Dogan (S’00) was born in Malatya, Turkey,on June 6, 1976. He received the B.S. degree in elec-trical engineering from the University of SouthernCalifornia, Los Angeles, in 1999, and the M.S. andPh.D. degrees in electrical engineering from theUniversity of California, Berkeley, in 2001 and 2005,respectively.

He is currently with Atheros CommunicationsInc., Santa Clara, CA, where he is involved with dualband wireless-LAN transceiver chipset design. In thesummer of 2000, he worked in HP Labs, where he

was involved with the design of clock and data recovery circuits for high speedserial data links. During the two consecutive summers, in 2001 and 2002, hewas with Maxim Integrated Circuits, where he was involved with the design ofcable modem tuners and satellite receivers.

Dr. Dogan is a member of various honor societies. He is the recipient of theAnalog Devices Outstanding Student Designer Award and the Philip S. BieglerExcellence in Electrical Engineering Award from the University of SouthernCalifornia.

Robert G. Meyer (S’64–M’68–SM’74–F’81) wasborn in Melbourne, Australia, on July 21, 1942. Hereceived the B.E., M.Eng. Sci., and Ph.D. degreesin electrical engineering from the University ofMelbourne in 1963, 1965, and 1968, respectively.

In 1968, he was an Assistant Lecturer in electricalengineering at the University of Melbourne. SinceSeptember 1968, he has been with the Departmentof Electrical Engineering and Computer Sciences,University of California, Berkeley, where he is nowProfessor Emeritus and Professor in the Graduate

School. His research interests are high-frequency analog integrated-circuitdesign and device fabrication. He has acted as a consultant on electronic circuitdesign for numerous companies in the electronics industry. He is coauthorof the book Analysis and Design of Analog Integrated Circuits (Wiley, 1977,1984, 1993, 2001), editor of the book Integrated Circuit Operational Amplifiers(IEEE Press, 1978), and co-editor of the book Integrated Circuits for WirelessCommunications (IEEE Press, 1999).

Dr. Meyer was President of the Solid-State Circuits Council and was an As-sociate Editor of the IEEE JOURNAL OF SOLID-STATE CIRCUITS and the IEEETRANSACTIONS ON CIRCUITS AND SYSTEMS.

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Intermodulation Distortion in CMOS Attenuators and Switches

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