1 Copyright ' 2001 by ASME Proceedings of IPACK’01: The Pacific Rim/ASME International Electronic Packaging Technical Conference and Exhibition July 8-13, 2001, Kauai, Hawaii, USA INTERPACK2001 - 15780 LAP: LOW COST LARGE AREA PANEL PROCESSING OF MCM-D SUBSTRATES AND PACKAGES ACHIEVEMENTS AND RESULTS M. Scheffler * , D. Cottet. J. Grzyb, G. Trster, ETH Zurich, Electronics Lab, Switzerland N. Ammann, W. Preyss, J. Baumbach, tyco electronics, Germany K. Delaney, NMRC, Ireland P. Poyet, G. Tessier, Thales Microwave, France P. Bod, P. Leisner, M. Karlsson, Acreo AB, Sweden U. Wahlstrm, S.-T. Persson, L. Ljungqvist, Strand Interconnect AB, Sweden W. Wendel, R. Epple, Hirschmann Rheinmetall, Germany T. Centro, F. Catarsi, CAEN Microelettronica, Italy and P. Demmer SIEMENS ZT, Germany ABSTRACT The paper describes the results of the EU research project LAP that had the target to develop and to demonstrate a low- cost high-density substrate manufacturing technology for 1 st - level die assemblies. The cost target of 1/in 2 had to be obtained by increasing toadys 4x4in 2 panel sizes to panels up to 24x24in 2 . The results focus on RF characterization (integrated antennas up to 83GHz, inductors up a Q value of 50), novel packaging strategies (integration of substrate and package), and cost achievements (approaching the cost target). The technology capabilities have been demonstrated with a 9:4 satellite switch operating up to 2.4GHz and readout electronics for physics experiments. INTRODUCTION High-density substrates have gained more and more interest recently, not only to achieve size reduction required for todays demanding consumer electronics, but also to provide high-density escape routing as present in chip- size/scale packages (CSPs). The costs of these types of substrates have always appeared to be a showstopper. To overcome this obstacle, in 1998 the EU consortium LAP (Low Cost Large Area Panel Processing of MCM-D Substrates and Packages) has formed to bring down the cost for thin-film substrates from ranges of 25US$/in 2 , nothing uncommon in the 1990s, to the range of 1US$/in 2 (≈ 1/in 2 ). The way to achieve this goal is to increase the manufacturing panel size from actual 4x4in 2 lines using existing semiconductor equipment to panel sizes of 8in diameter, 12x12in 2 , 16x16in 2 , and 24x24in 2 , based on dedicated LAP equipment. * Gloriastrasse 35, 8092 Zurich, Switzerland, [email protected]This paper presents • the LAP processes established during the project by the various partners, • the demonstrators used to verify the technical performance of the LAP processes with emphasis on high-density integration and high-frequency behavior, and • the results of the LAP cost benchmarking. THE LAP CONSORTIUM Companies and universities from eight European countries teamed in the LAP consortium to meet its targets [1]. • tyco electronics EM (former SIEMENS EC division, Munich, Germany): general contractor and responsible for the set-up of a 16x16in 2 line and a telecommunication demonstrator, • Thomson-CSF Microelectronique (TCM, Paris, France, now Thales Microwave), responsible for the set-up of a 12x12in 2 line, • ACREO (merger of the former IMC and IOF, Norrkping, Sweden), responsible for the set-up of a 24x24in 2 line, • Strand Interconnect (Norrkping, Sweden), responsible for the set-up of an 8in wafer line, • Electronics Lab ETH Zurich (Zurich, Switzerland), responsible for technology characterization and cost benchmarking, • NMRC (Cork, Ireland), responsible for reliability characterization, • Hirschmann Rheinmetall (Neckartenzlingen, Germany), providing a communication demonstrator operating up to 2.4GHz,
Proceedings of IPACK'01: The Pacific Rim/ASME International Electronic Packaging
Technical Conference and Exhibition July 8-13, 2001, Kauai, Hawaii, USA
INTERPACK2001 - 15780
LAP: LOW COST LARGE AREA PANEL PROCESSING OF MCM-D SUBSTRATES AND PACKAGES � ACHIEVEMENTS AND RESULTS
M. Scheffler*, D. Cottet. J. Grzyb, G. Tröster,
ETH Zurich, Electronics Lab, Switzerland N. Ammann, W. Preyss, J. Baumbach,
tyco electronics, Germany K. Delaney,
NMRC, Ireland P. Poyet, G. Tessier,
Thales Microwave, France P. Bodö, P. Leisner, M. Karlsson,
Acreo AB, Sweden U. Wahlström, S.-T. Persson, L. Ljungqvist,
Strand Interconnect AB, Sweden W. Wendel, R. Epple,
Hirschmann Rheinmetall, Germany T. Centro, F. Catarsi,
CAEN Microelettronica, Italy and P. Demmer
SIEMENS ZT, Germany
ABSTRACT The paper describes the results of the EU research project
LAP that had the target to develop and to demonstrate a low-cost high-density substrate manufacturing technology for 1st-level die assemblies. The cost target of 1�/in2 had to be obtained by increasing toady�s 4x4in2 panel sizes to panels up to 24x24in2. The results focus on RF characterization (integrated antennas up to 83GHz, inductors up a Q value of 50), novel packaging strategies (integration of substrate and package), and cost achievements (approaching the cost target). The technology capabilities have been demonstrated with a 9:4 satellite switch operating up to 2.4GHz and readout electronics for physics experiments.
INTRODUCTION
High-density substrates have gained more and more interest recently, not only to achieve size reduction required for today�s demanding consumer electronics, but also to provide high-density escape routing as present in chip-size/scale packages (CSPs). The costs of these types of substrates have always appeared to be a showstopper.
To overcome this obstacle, in 1998 the EU consortium LAP (Low Cost Large Area Panel Processing of MCM-D Substrates and Packages) has formed to bring down the cost for thin-film substrates from ranges of 25US$/in2, nothing uncommon in the 1990s, to the range of 1US$/in2 (≈ 1�/in2). The way to achieve this goal is to increase the manufacturing panel size from actual 4x4in2 lines using existing semiconductor equipment to panel sizes of 8in diameter, 12x12in2, 16x16in2, and 24x24in2, based on dedicated LAP equipment.
This paper presents • the LAP processes established during the project by the
various partners, • the demonstrators used to verify the technical performance
of the LAP processes with emphasis on high-density integration and high-frequency behavior, and
• the results of the LAP cost benchmarking.
THE LAP CONSORTIUM Companies and universities from eight European countries teamed in the LAP consortium to meet its targets [1].
• tyco electronics EM (former SIEMENS EC division, Munich, Germany): general contractor and responsible for the set-up of a 16x16in2 line and a telecommunication demonstrator,
• Thomson-CSF Microelectronique (TCM, Paris, France, now Thales Microwave), responsible for the set-up of a 12x12in2 line,
• ACREO (merger of the former IMC and IOF, Norrköping, Sweden), responsible for the set-up of a 24x24in2 line,
• Strand Interconnect (Norrköping, Sweden), responsible for the set-up of an 8in wafer line,
• Electronics Lab ETH Zurich (Zurich, Switzerland), responsible for technology characterization and cost benchmarking,
• NMRC (Cork, Ireland), responsible for reliability characterization,
• Hirschmann Rheinmetall (Neckartenzlingen, Germany), providing a communication demonstrator operating up to 2.4GHz,
• and finally CAEN Microelettronica (Viareggio, Italy), providing an instrumentation demonstrator.
Strand 8� wafer commercial line
Process Setup Complexity
Com
mer
cial
expl
oita
tion
TCM 12�x12�/tyco 16�x16� panelprototyping line / verified process
acreo 24�x24� panelfeasibility study
Figure 1: Setup Complexity vs. Exploitation Level
In order to account for the increasing challenge in setting up such processes, a �staggered� approach has been selected increasing both panel size and complexity continuously. The result is also a �staggered� level of commercial exploitation for the various partners (Figure 1).
Base Material
Dielectric
CuInterconnect
Figure 2: LAP layer stack-up
TECHNOLOGIES Since no single valid solution exists to accomplish Large
Area Processing, we give an overview on possible materials, processes, and packaging concepts.
Materials In the first phase of the project, a selection of materials
has been investigated for applicability. Among them were • Base materials: laminates (FR4, LinLam and high-Tg),
metals and metal alloys, ceramics, silicon; • Dielectrics: PI, Ormocer, PBO, BCB, SU-8 • Interconnection: Cu (and Al).
Table 1: Decision matrices for base and dielectric materials
DIE
LEC
TRIC
M
ATER
IALS
CTE
*
Cos
t
tan
δ
Cur
ing
tem
pera
ture
Rem
arks
Sele
cted
BCB 2 + ++ > 200°C Various formulations Yes
Ormocer 2 +/- + ~150°C No high quantities! No
PBO 3 + - > 200°C Yes
PI 1 - - + > 200°C High moisture uptake No
SU-8 2 ++ # 130°C MEMS material Yes
*: positive or negative depends on the base material, therefore only the rank is given
#: currently, there is no information on SU-8�s tan δ
+: positive property, as desired -: negative property
The base materials have been characterized according to their properties of LAP size availability, surface finish, cost, filled vias (required for packaging and thermal issues), and other advantages. For the dielectric materials, mainly the physical properties (CTE), cost, dielectric losses (tan δ), and curing temperature were of interest, focusing on photosensitive materials.
The decision matrices for the base and the dielectric materials are shown in Table 1. Si/BCB, ceramics+high-Tg-laminates/BCB, FR-4/SU-8, and Alloy/PBO have been chosen for implementation.
Processes The principal LAP layer stack-up is shown in Figure 2,
and Table 2 details the general processing steps. The processing starts with a primary substrate cleaning step, followed by iterative dielectric and metal processing, according to the number of interconnect layer required. Finally, a top metal layer is processed to enable soldering or wire bonding. Then, the panel is cut down for subsequent back end processing steps including testing and the connection of the substrate to the next interconnect level (2nd level packaging). Important manufacturing issues to be addressed are: • Dielectric deposition, • Metal deposition, • Lithography, and • 1st and 2nd level assembly.
For dielectric deposition, next to spin coating, also curtain, spray and meniscus coating are an option. The three latter processes have a higher material effectiveness, compared to spin coating, thus reducing the material cost. On the other hand, these methods are dedicated high-volume processes, requiring a number of set-up runs, before they yield the desired quality and effectiveness. Spin coating is less complicated, has superior thickness uniformity, and also the equipment is easier to obtain. Since the LAP project is confined to prototyping only, spin coating has been chosen for dielectric deposition. Once production volume is justified, the more material-effective methods will be considered.
The metal deposition can be either accomplished by an additive process (plating), or by a subtractive process (sputtering/etching). While the subtractive process demands for expensive sputter equipment with rather low throughput, it offers a higher level of precision, as mandatory for RF applications [2]. On the other hand, the additive process of plating allows a higher overall line throughput and comes with lower cost. Both methods are employed in the project.
Since the cost, handling, and exposure precision of lithography masks scales with their size, at a certain size the exposure mechanism has to be changed from �single exposure� to �step & repeat�. On the other hand, �step & repeat� slows down the exposure throughput. Therefore, for the smaller panel sizes (see Figure 1), �single exposure� has
been used, whereas for the largest size �step & repeat� was selected.
Table 2: General LAP Process Steps Substrate Cleaning Cleaning Dielectric Spin coating Dielectric
Lithography Wet etching Plasma cleaning
Metal Level Sputtering Spin coating resist Lithography Wet etching Hard bake Plasma cleaning
Top Metal Level Sputtering Spin coating photo Lithography Wet etching Hard bake Plasma cleaning Metal electroplating
Finishing Steps S/O test/ visual Singularization
For the 1st and 2nd level assembly, three different
approaches have been chosen (Figure 3), with the same relation of exploitation and complexity. Package A is the standard approach for MCM-D-on-Silicon substrates. This package offers a qualified approach and is used for the demonstrators. However, package A suffers from additional wire bond interconnects acting as parasitics and requires a laminate as an underlying carrier connecting to the BGA solder balls. Package B eliminates these shortcomings and allows in principle panel-level packaging. Filled vias in the base material provide the connection from the topside to the bottom side where the solder balls are attached. Suitable base materials are ceramics with punched vias and laminates with through-hole connections. Package B is now in the prototyping stage. Package C goes one step further, rendering also the interconnection through the base material superfluous. Using metals or alloys as base material and etching them back after chip attach and overmolding, an ultra-thin package with a thickness down to 0.8mm has been developed.
LaminateBase Material
DieGlob TopThinfilm
DieGlob TopThinfilmBase Material w/ filled vias
DieGlob TopThinfilm
Evolution of the LAP packaging
a) stacked package A b) integrated package B c) ultra thin package C
DEMONSTRATORS In order to verify the LAP technologies, application
demonstrators were fabricated during the project. Among them are • a direct broadcast switch for satellite TV subscribers,
operating up to 2.4GHz [3], • and a module for a data acquisition chain located inside a
particle physics experiment at CERN, Geneva.
Direct Broadcast Satellite (DBS) Switch Satellite TV today has a certain share of TV supply, next
to conventional cable TV, and is gaining more and more interest. Especially the new markets in Middle and Eastern Europe obtain easy access to a vast choice of channels without building an expensive infrastructure network. This increasing number of customers also drives the need for integration of underlying subsystems. Market forecasts are ranging from 0.5 to one million units per year for Europe. Due to a targeted quantity of 100.000 units per year and the cost sensitivity of the product, volume capabilities and low cost substrates are mandatory.
Figure 4: Schematic of the DBS
An existing PCB contains a DBS 5:4 multi switch operating at 2.4GHz. DBS 5:4 stands for Direct Broadcast Satellite Switch, making four satellite plus one terrestrial TV signals available to four subscribers at the same time. Extending this subsystem to a 9:4 format would be desirable, but impossible due to the large area consumption of coplanar lines required to connect two ASICs. Therefore, the LAP MCM-D technology was chosen to reduce the area required for coplanar interconnects. Moreover, due to the closer neighborhood of the two analog switches (3mm instead of 10mm in PCB technology), there would be no need for RF
coupling structures to match λ/4. The schematic of the 9:4 switch module can be found in Figure 4.
In total, the DBS system contains seven dies (two analog switch ASICs, four digital switch controls and one inverter). Additionally, 12 pull-up resistors and 8 capacitors for DC decoupling had to be positioned as close as possible to the ICs.
Data Acquisition Chain (DAC) In the Large Hadron Collider (LHC) accelerator
experiment at CERN (Geneva), the readout system for calorimetric measures is responsible for selecting a small number of interesting events out of 800 million events generated every second by 80'000 detectors for off-line analysis. Therefore, an MCM has been developed that is part of the LHC read out chain, featuring two types of custom ASICs (see Figure 5). The MCM is located in the Data Acquisition and Trigger path.
The data arrives at 40MHz rate compressed and digitized. In a first step, the data is linearized (in the LIN stage) including an adder for offset correction and a multiplier for gain adjustment. Next, the data is stored in a pipeline stage (PIPE) during first-level trigger loop latency. Then, if triggered, it is written to a so-called derandomizer (DER) event buffer. A subsequent filter (LVL2) contains FIR filters and statistic operators. In the trigger path the data from different channels are first applied to an adder circuit (ADDER) and then to another filter ASIC (LVL1) which extracts the energy and Bunch Crossing information formatting the signal according to the trigger system requirements (trigger primitives). As the Trigger path is more dedicated to a special experiment, the ADDER and LVL1 ASIC are located outside the MCM to increase the reusability.
Figure 5: Schematic of the DAC
In total, the DAC subsystem contains six dies with over 380 I/Os, operating at 40MHz. Due to the use of the LAP technology, the subsystem requires the same area as if realized in an FPGA, while having order of magnitude lower power consumption. This lower power consumption reduces in turn the cooling efforts for the overall detector.
From left to right: top Strand 8in wafer, bottom: TCM 12x12in2 panel, tyco 16x16in2 panel, ACREO 24x24in2 panel
ACHIEVEMENTS In this section we present the results of the project. The
section is divided into processes, technology, demonstrators, and cost issues.
C09
C10
Figure 7: Close-up of inductors integrated on a 12x12in2 panel
-5
0
5
10
15
20
25
30
35
40
45
50
55
60
65
0 0.5 1 1.5 2 2.5 3 3.5 4
Q-f
acto
r
Frequency [GHz]
Q-factor of 20nH spiral inductor
TV1...TV6
Figure 8: Variation of the Q factor over six test vehicles
Processes Generally, the consortium has met its targets according to
Figure 1. Strand AB has set up a fully operational line and is commercially active (design rules 30/30/40µm1). TCM and tyco have completed the prototyping stage and have verified their technology. Moreover, with these processes also integrated resistors and capacitors are available. ACREO has currently finished the first feasibility studies on the 24x24in2 panels (see Figure 6).
Technology During the development of the LAP technology, special
attention has been put on the RF capabilities of the processes. In order to assess these capabilities properly, dedicated RF test vehicles have been designed, containing transmission lines, integrated inductors, filters, couplers, and antennas. For the inductors, Q factors up to 50 at fQmax ≈ 2GHz for inductances from 15nH to 45nH have been measured (examples Figure 7, Figure 8). Based on simulations and measurements, a much deeper understanding of integrated inductors could be developed, leading to a �cook book� for inductor design [4]. Investigations on process variations have been conducted, showing that in general the reproducibility of the processes is good. Figure 9 and Figure 10 show examples for the sheet resistance and the dielectric thickness, driving inductor Q factors values and microstrip impedances.
Figure 9: Variations of sheet resistance on top metal layer
M4 (12x12in2 panel with 14x14 test vehicles)
Figure 10: Variations of dielectric thickness on ISO1 layer
M1/M2 (12x12in2 panel with 14x14 test vehicles)
-50
-45
-40
-35
-30
-25
-20
-15
-10
-5
0
30 40 50 60 70 80 90 100 110
[dB
]
Frequency [GHz]
Band Pass Filters @ 90GHz (Al2O3-PBO, plated Cu)
BPF4 S11BPF4 S21
Figure 11: 3rd order Chebyshev bandpass filter at 80-90GHz
-32-30-28-26-24-22-20-18-16-14-12-10
-8-6-4-20
81 81.5 82 82.5 83 83.5 84 84.5 85
S11
[dB
]
Frequency [GHz]
Measured process tolerances on patch antenna @ 83GHz
measured on tv1measured on tv2measured on tv3
simulation (HFSS)
Figure 12: Patch antenna with fres = 83GHz
More advanced structures, such as filters, show that the performance of the LAP technology is even applicable to mm-wave structures [5]. A Chebyshev bandpass filter of the 3rd order at 80-90GHz has been designed on M1(GND)/M3(signal), implemented as four sections of coupled lines. The S11 and S21 parameters of the measured PBO based band-pass filter are shown in Figure 11. The achieved insertion loss is �4dB and return loss below �15dB in the pass-band.
Also patch antennas have been produced, and a good coincidence of measurement and simulation has been found (Figure 12, fres=83GHz). Process variations led to minor shifts < ±1% of the resonance frequency, while more affecting the loss. Current work focuses on better antenna geometries for thinfilm geometries.
Demonstrators Both demonstrators, DBS and DAC, have been fabricated.
The DBS (Figure 14) has been evaluated and complies with the specifications. A redesign will replace the integrated capacitors by higher-value dielectrics (Ta2O5) or SMD components to save valuable substrate real estate. The DAC demonstrator is currently under evaluation.
Cost Issues In order to validate the cost target of 1�/in2, we conducted a continuous cost benchmarking throughout the project. In a first step, cost parameters such as • Machine cost, • Equipment up time, • Operator time for process, • Process time, • Process material cost, • Working days per year, • Shift composition, • Overhead cost, • Depreciation period,
• Operator cost, • Mass consumables cost, • Lot sizes, have to be collected.
These parameters are translated to the cost contributors labor, material, equipment, and overhead. Moreover, the utilization (percentage of available resources that are truly used) of labor and equipment is monitored. From these internal parameters two figures-of-merit can be extracted: • The activity cost (sum of all cost required to manufacture a
product); • The cost to be returned (sum of all cost spent).
The difference between these two figures is a measure for
the resource efficiency. Whereas the cost to be returned is primarily of actual economical interest, the activity cost gives a hint on the process capability and optimization potentials. Since all product- or process-non-idealities are subtracted, this figure is preferred to compare different process set-ups.
Figure 15 and Figure 16 show a typical distribution of cost contributors: the highest contributors are the materials (panel, the dielectrics, and the top layer Au finish) followed by the equipment cost (sputter and testing machines), as can be seen in Figure 16. Therefore, materials and equipment depreciation contribute over 50% of the cost to be returned (Figure 15). Next to the overhead, the depreciation penalty (for unused equipment time) adds significantly to this cost. Figure 17 gives the overall cost achievements for the LAP project: as one can see, all manufacturers have reduced their cost significantly, almost reaching the 1�/in2-target. Future cost reduction activities will focus on the material consumption.
CONCLUSIONS In this paper we have presented the results of the EU
Esprit project LAP. The LAP consortium partners have set up four different large-area panel production sites and have demonstrated the large-area feasibility.
The technology features high interconnect density, allows for multi-chip or ultra-thin chip-scale packages, with additional integration of passive components. RF structures up to 90GHz have been implemented and measured successfully. Demonstrators using the LAP technology were fabricated for instrumentation and communication applications.
Regarding cost, the project has achieved an important reduction of the per-area cost, coming close to the target of 1�/in2.
Upcoming activities comprise the further exploitation of the RF capabilities of the LAP technology.
ACKNOWLEDGMENTS The EU 4th framework program ESPRIT has supported
this work under contract 26261. The Swiss Federal Office for Education (BBW), under project 97.0286, and the Swedish Nutek, under P9760, partially funded this work. The authors would like to thank their colleagues from the LAP consortium, the EU project officer, and the reviewers for their contributions and help.
REFERENCES [1] �Low cost Large Area Panel Processing of MCM-D
substrates and packages�, EU ESPRIT Project 26261, www.ife.ee.ethz.ch/hdp/lap, 1998-2000.
[2] �Does Low Cost Large Area Panel Processing mean Low Performance?�, Michael Scheffler, Didier Cottet, Gerhard Tröster, Proc. IMAPS Annual, Symposium 2000, Boston MA, USA, September 2000, p. 217-222.
[3] �A 9:4 Satellite Receiver Switch in MCM-C/D Technology�, Etienne Hirt, Michael Scheffler, Gerhard Tröster, Geert Bernaerts, Wolfgang Wendel, Ralf Epple, Proc. HD International, Denver CO, USA, April 25-28, 2000, p.542-546.
[4] �Experimental Analysis of Design Options for Spiral Inductors Integrated on Low Cost MCM-D Substrates�, D. Cottet, J. Grzyb, M. Scheffler, G. Tröster, to appear in Proc. ECTC2001.
[5] �Distributed Elements and MM-Wave Characterization of Low Cost MCM-D Substrates�, J. Grzyb, D. Cottet, G. Tröster, to appear in Proc. HDI2001.
