Multiple State EFN Transistors Gideon Segev, Iddo Amit, Andrey Godkin, Alex Henning and Yossi Rosenwaks School of Electrical Engineering, Tel Aviv University, Israel Abstract Electrostatically Formed Nanowire (EFN) based transistors have been suggested in the past as gas sensing devices. These transistors are multiple gate transistors in which the source to drain conduction path is determined by the bias applied to the back gate, and two junction gates. If a specific bias is applied to the side gates, the conduction band electrons between them are confined to a well-defined area forming a narrow channel- the Electrostatically Formed Nanowire. Recent work has shown that by applying non-symmetric bias on the side gates, the lateral position of the EFN can be controlled. We propose a novel Multiple State EFN Transistor (MSET) that utilizes this degree of freedom for the implementation of complete multiplexer functionality in a single transistor like device. The multiplexer functionality allows a very simple implementation of binary and multiple valued logic functions. 1. Introduction Electrostatically Formed Nanowires (EFN) based transistors have been recently suggested as robust sensing[1] and memory devices [2]. The EFN device is based on the silicon-on- insulator (SOI) four gate field-effect transistor (G 4 -FET) developed in 2002 [3], [4] which emerged from the volume inversion SOI MOSFET[5]. The G 4 -FET combines MOSFET and junction gate field-effect transistor (JFET) principles as it consists of a top MOS gate (V TG ), a bottom substrate gate (V BG ) and is enclaved between by two lateral junction gates (V JG1 , V JG2 ). The four gate transistor can be naturally adapted to CMOS technology scaling and manufactured in conventional silicon-on-insulator (SOI) processes with a low cost and high volume manufacturing. In EFN devices the top gate is removed in order to allow
Transcript
Multiple State EFN Transistors
Gideon Segev, Iddo Amit, Andrey Godkin, Alex Henning and Yossi Rosenwaks
School of Electrical Engineering, Tel Aviv University, Israel
Abstract
Electrostatically Formed Nanowire (EFN) based transistors have been suggested in the
past as gas sensing devices. These transistors are multiple gate transistors in which the source
to drain conduction path is determined by the bias applied to the back gate, and two junction
gates. If a specific bias is applied to the side gates, the conduction band electrons between
them are confined to a well-defined area forming a narrow channel- the Electrostatically
Formed Nanowire. Recent work has shown that by applying non-symmetric bias on the side
gates, the lateral position of the EFN can be controlled. We propose a novel Multiple State
EFN Transistor (MSET) that utilizes this degree of freedom for the implementation of
complete multiplexer functionality in a single transistor like device. The multiplexer
functionality allows a very simple implementation of binary and multiple valued logic
functions.
1. Introduction
Electrostatically Formed Nanowires (EFN) based transistors have been recently suggested
as robust sensing[1] and memory devices [2]. The EFN device is based on the silicon-on-
insulator (SOI) four gate field-effect transistor (G4-FET) developed in 2002 [3], [4] which
emerged from the volume inversion SOI MOSFET[5]. The G4-FET combines MOSFET and
junction gate field-effect transistor (JFET) principles as it consists of a top MOS gate (VTG), a
bottom substrate gate (VBG) and is enclaved between by two lateral junction gates (VJG1,
VJG2). The four gate transistor can be naturally adapted to CMOS technology scaling and
manufactured in conventional silicon-on-insulator (SOI) processes with a low cost and high
volume manufacturing. In EFN devices the top gate is removed in order to allow
functionalization of the top surface, for example for gas sensing as suggested in [6]. If a
specific bias is applied to the side gates, the conduction band electrons between them are
confined to a well-defined area forming a narrow channel, the electrostatically-formed
nanowire[7]. Figure 1 (a) shows a schematic illustration of such a transistor and the formation
of the EFN. Figure 1 (b) illustrates the formation of the EFN in a cross section view.
Glazman et al. proposed the lateral position control of an electron channel with a split-
gate FET[8]. Shalev et al.[1] have shown in 3D electrostatic simulations that by applying
non-symmetric bias on the side gates, the position of the EFN can be moved towards one of
the gates.
We propose here novel Multiple State EFN Transistors (MSET) that exploits the EFN
lateral movement in order to form a single transistor multiplexer. In this device the drain is
split into several isolated individual drains and the MSET output is defined by a thin
conduction channel between a specific drain and the source. The multiplexer functionality
allows implementation of any logical operation within its inputs and outputs range.
Furthermore, since it supports multiple well defined conduction states, it can perform multiple
valued logic (MVL) operations as well. Since this device is based on simple SOI concepts, it
can be integrated into current technology relatively easily. To the best of our knowledge, this
is the first CMOS compatible transistor for MVL large-scale circuits to be suggested.
Although this work focuses on utilizing the MSET for logic applications, it is clear that it can
be used in many other fields as well.
Figure 1, 3D view of the 3 gate EFN transistor (a), cross section and formation of the EFN (b).
2. Operation
2.1. Two Gates MSET
The basic MSET configuration closely resembles the transistor illustrated in Figure 1 with
one important difference- the drain is split into several isolated drain inputs, labeled d1..dn,
where each drain is connected to a specific voltage, labeled Vd,1..Vd,n, according to the
required functionality. A known combination of side gate voltages brings the EFN next to one
of the drains, defining a single conduction path between a single drain and the source. For
logic applications as discussed below, the bottom gate can be removed. Figure 2 shows an
illustration of a two-drain MSET device embedded in a circuit which allows definition of
voltage based states. When V1 is applied to one of the gates and 0 is applied to the other, the
conduction channel will be next to the drain close to the latter gate. In Figure 2, the applied
biases are VG,1=V1 and VG,2=0 such that the EFN is next to d2. Since the resistance of the
conduction path between d2 and the source is significantly lower than the resistance of the
serial resistor R, the output voltage is Vs=Vd,2. In a similar fashion, applying opposite
voltages, VG,1=0 and VG,2=V1 yields Vs=Vd,1. When both gates are at voltage V2 the entire
region between the two gates is completely depleted. As a result, the resistance between the
source and the two drains is higher than R and Vout is 0. When both gates are at 0 there is
VD
VG,1
VG,2
(a) (b)
EFN
conduction between both drains and the state is undefined. When one gate is at V1 and the
other is at V2 the output voltage can be between 0 and the corresponding drain voltage
depending on the specific device engineering. These intermediate states can increase the
device functionality considerably but may result in high currents between the drains and high
power consumption. Table 1 shows the truth table for the MSET based circuit described in
Figure 2. It should be noted that as in CMOS configurations, the proposed configuration
possesses very low current flow through the device once the state is determined. In order to
further reduce the source current, the resistor in Figure 2 can be replaced with transistors that
will conduct or isolate the path between Vout and the ground according to the desired
functionality.
Figure 2, two drains MSET device in device in an exemplary circuit which allows definition of voltage
based states.
Vg1 Vg2 Vout
0 0 --
0 V1 Vd,1
V1 0 Vd,2
V2 V2 0 Table 1, 2 drains MSET truth table.
The addition of a third drain to the MSET will greatly increase its functionality. Having
three possible conduction states, this device can perform ternary based logical operations. We
assume a circuit similar to that shown in Figure 2 with a 3 drain MSET replacing the 2 drain
R
VO
VD1VG,1
VG,2
VD2
MSET. In this case, conduction through drain 1 is possible when Vg,1=0 and Vg,2=V2.
Conduction through the middle drain is possible when both gates are at V1 and conduction
through drain 3 is possible when Vg,2=0 and Vg,1=V2. When both gates are at V2 there is no
conduction through any of the drains and the output is 0. V1 and V2 in this example do not
necessarily have the same values as V1 and V2 in the previous example. Table 2 shows the
truth table for this configuration.
Vg,1 Vg,2 Vout
0 V2 Vd,1
V1 V1 Vd,2
V2 0 Vd,3
V2 V2 0 Table 2, basic 3 drain MSET truth table.
2.2. Four Gates, Three Dimensional Architecture
In order to add degrees of freedom to the MSET a three dimensional architecture is
proposed. The basic mode of operation is two dimensional movement of the channel, and the
conduction path is determined by 4 independent gates. The drains are isolated islands between
the gates and the source is located beneath the drains. In this case, instead of 2 gates which
determine the chosen drain, two side gates voltages (Vg,E and Vg,W respectively) determine
the chosen drain column and the other two gates voltages (Vg,N and Vg,S respectively)
determine the chosen row. We denote Vd,i,j the drain in the ith row and j
th column. Figure 3
shows a schematic illustration of such a device (a) and a cross sectional view along with
voltage based state circuit (b). In this example VJG,s>VJG,n and VJG,e>VJG,w and the EFN forms
a conduction path between d1 and the source. The device shown has 4 input channels VJG,s,
VJG,n, VJG,e, VJG,w. If the device output is determined by the source voltage and V1 and V2 are
defined as the 2 drain MSET above, 4 outputs Vd,1,1, Vd,1,2, ,Vd,2,1 and Vd,2,2 are possible.
Table 3 shows a truth table for a 3D MSET with 4 drains. As above, in order to allow a
voltage based output in which little power is dissipated in the device, only specific
combinations of inputs are allowed. Choosing combinations other than those in Table 3 can
add to the number of possible states but may cause high currents to pass between the drains
leading to high power consumption. As in the 2 gates configuration, adding more drains will
increase the device functionality significantly and allow realization of non binary logic.
Assuming voltages V1 and V2 as in the 3 drain MSET example above, the truth table of a 4
gates, 9 drain MSET is given in Table 4.
Figure 3, a three dimensional, 4 drain MSET device, 3D view (a) and cross section in a voltage based
The advantages of the MSET can be easily demonstrated by realizing a 2 control 4 inputs
multiplexer. The 4 gates, 4 drains multiplexer as shown in section 2.2 can be used to select
one of its 4 inputs. However, the need for 4 different gates voltages is somewhat
cumbersome. Hence, there is a need for a circuit that translates the multiplexer control inputs
to the appropriate gate voltages. We refer to this circuit as the State to Gate (S2G) circuit. As
seen in Table 3, conduction through the first column requires voltages of 0 and V1 on JGE and
JGW respectively. On the other hand, in order to conduct from the second column, JGE and
JGW should be V1 and 0 respectively. Hence, the voltage on JGW is always the inverse of JGE
and the S2G circuit can be realized with a simple NOT gate. Figure 4 shows an illustration of
a 2 control 4 inputs multiplexer realized with a 4 gates 4 drains MSET and two not gates. It
should be noted that a similar nonrestoring multiplexer realized in CMOS consists of 16
transistors[9].
Figure 4, an illustration of a two control 4 inputs multiplexer realized with a single MSET and two not
gates.
a1
a0
Vout
In order to realize complex logical several devices must be connected in series. Hence,
the MSET output voltage (source voltage) must be of the same sign and magnitude as the
input voltage (gates and drain voltage). However, in order to avoid forward biasing between
the gates-drains p-n junction the drain voltages must be non negative and the gate voltages
must be non positive. This contradiction can be removed in several ways: addition of a
voltage shifting circuit, addition of a voltage inverting circuit or alternating p-n design. The
first two circuits can be realized together with the S2G component in order to reduce the
number of transistors used in the circuit. Using an alternating p-n design requires that the
drain voltages of the n type MSET will be exactly the required gate input of p type MSETs
and vies-versa. Obviously, this layer is not required when the output of one MSET is
connected to the drain of another.
4. Simulation
In order to demonstrate the basic MSET concept of operation, a proof-of-concept two-
drains MSET was simulated with Sentaurus TCAD. The MSET device in these simulations is
the same as in the previous section coupled with a 10MΩ resistor which is placed between the
source and the ground. The drain voltages Vd,1 and Vd,2 are 1.5V and 1V respectively, the rest
of the MSET parameters are listed in Table 5. The simulated circuit including the MSET
device, resistor and voltage sources is as in Figure 2. The source voltage as a function of the
two gate voltages is shown in Figure 6. When there is a high voltage on one of the side gates
the conduction path is pushed away from it forming a single connection between the opposite
drain and the source. As a result, when Vg,2 is more negative than -1.5V and Vg,1 is close to
0V, the output voltage is exactly Vd,1. Similarly, when Vg,1 is below -1.5 and Vg,2 is close to
zero, the output voltage is exactly Vd,2. Last, when both gates are close to -3V, there is no
conduction through the device and the output is close to 0V. Hence, three different states can
be defined for this device: S0- where Vo=0, S1 where Vo=Vd,1 and S2 where Vo=Vd,2. From
Figure 6 it can be seen that input voltages of -3V and 0V are sufficient to switch between the
three states. Furthermore, since the output and input are of the same order of magnitude,
device concatenation is possible simply by shifting the voltage output by -3V. Table 6 shows
a truth table of the simulated circuit summarizing the different MSET states.
Table 5, two gates, 2 drains MSET simulation parameters.
Parameter Symbol Size (nm)
SOI width W 600[nm]
SOI length L 1000[nm]
SOI thickness T 145[nm]
Buried Oxide thickness TB 5[nm]
Drains length and width LD,WD 100[nm]
Drains thickness TD 145[nm]
Source width WS 400[nm]
Source length LS 100[nm]
Source thickness TS 145[nm]
Gates length LG 1000[nm]
Gates width WG 5[nm]
Gates thickness TG 145[nm]
Oxide buffer length LB 300[nm]
Oxide buffer width WB 160[nm]
Oxide buffer thickness TB 145[nm]
Drain 1 voltage VD,1 100[mV]
Drain 2 voltage VD,2 200[mV]
Bulk Doping Nd,0 1017
[cm-3
], Arsenic
Drains Doping Nd,D 1019
[cm-3
], Arsenic
Source Doping Nd,S 1019
[cm-3
], Arsenic
Gates Doping Na,G 1019
[cm-3
], Boron
Figure 5, 2 gates MSET simulation parameters
WD
WS
LD
LB
WG
LG
WB
LS
W
L
Top ViewFront View
Side View
TG
TDTB
T
TBOX
Back View
TS
Figure 6, two gates, two drains MSET source voltage as a function of the Vg,1 and Vg,2. The circuit is as
in Figure 2 and the MSET parameters are listed in Table 5. The drain voltages Vd,1 and Vd,2 are 1.5V and 1V
respectively and R=10MΩ.
Vg,1 Vg,2 Vo State
0 -1.5 Vd,1 S1
-1.5 0 Vd,2 S2
-3 -3 0 S0
Table 6, 2 drain MSET truth table.
As discussed above increasing the number of drains can increase the device functionality
significantly. However, since these devices are larger than the two drain devices presented
above, larger areas must be depleted leading to higher required gates voltages. In order to
reduce the area that has to be depleted and the gate voltages, the silicon oxide drain separators
can be replaced with highly doped p type gates, each connected to the near side gate. Figure
7(a) shows a schematic design for a two gates, three drains MSET with such active drain
separators. Table 7 lists all the device parameters. The source voltage as a function of the two
side gates voltages is shown in Figure 7(b). As in the previous simulation, the different states
can be easily distinguished.
Table 7, two gates, three drains MSET simulation parameters.
Vg,1
[V]
Vg,2
[V
]
Vs [V]
-3 -2.5 -2 -1.5 -1 -0.5 0
-3
-2.5
-2
-1.5
-1
-0.5
0
0.2
0.4
0.6
0.8
1
1.2
1.4S0
S2
S1
Parameter Symbol Value
Device width L,W 500 nm
Device length L 800 nm
Drains length and width LD,WD 50 nm
Source width WS 400 nm
Source length LS 100 nm
Gates length LG 400 nm
Gates width WG 50 nm
Oxide buffer length LB 300 nm
Oxide buffer width WB 50 nm
Drain 1 voltage VD,1 600mV
Drain 2 voltage VD,2 400mV
Drain 3 voltage VD,3 200mV
Resistor R 1TΩV
Bulk Doping Nd,0 2∙1017[cm
-3], Arsenic
Drains Doping Nd,D 1019
[cm-3
], Arsenic
Source Doping Nd,S 1019
[cm-3
], Arsenic
Gates Doping Na,G 1019
[cm-3
], Boron
Figure 7, (a) the simulated two gates, three drains MSET. (b) Source voltage as a function of the Vg,1
and Vg,2. The circuit is as is Figure 2 and the MSET parameters are as in Table 7. The drain voltages Vd,1,
Vd,2 and Vd,3 are 0.6V, 0.4V and 0.2V respectively
5. Conclusion
A new device capable of performing multiple valued operation with an inherent
multiplexer functionality is suggested. Wide spread implementation of MSET based circuits
in ASIC and FPGA chips relies on the ability to fabricate them in appropriate magnitudes
with low power consumption at sufficient frequency. As discussed above, an MSET based 4
Vg,1
[V]
Vg,2
[V]
-2.5 -2 -1.5 -1 -0.5 0
-2.5
-2
-1.5
-1
-0.5
00.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
1.1S0 S1
S3
S2
s
d1 d2 d3
g2
g2g1
g1
(a) (b)
inputs multiplexer can be realized with a single MSET and 4 MOSFET transistors, far less
than any current technology. Hence, even if a 4 gates, 4 drains MSET is 12 times less
efficient than current transistors in terms of magnitude, power consumption and speed, the
suggested MSET based circuit may still be significantly more attractive. Although we have
discussed using MSETs for implementation of logic operations, this transistor may prove
beneficial in many analog and digital applications where simple multiplexing circuits are
required.
Since the MSET operation is based on depletion, the gates and drains voltages must differ
in sign which may lead to device concatenation difficulties. This issue can be solved in the
suggested 2 drain MSETs by using a level shifter. However, in more complex devices such as
the 4 gates MSET or the 3 drains MSET, further optimization is required in order to allow
concatenation. Furthermore, in these devices the conduction channel has to have a larger
range of motion and higher gate voltages are required. Reducing the magnitude of the drains
and buffers along with detailed optimization of the device geometry and doping profiles can
reduce these issues considerably.
In order to fully exploit the functionality of MSET devices the number of states (drains)
should be maximized. This number is limited by the fabrication process and the range of
motion of the conduction channel for a specific range of gates voltages. Since the number of
possible inputs of a 4 Gates MSET is the square of the number of drains, there is great
motivation to increase the amount of drains to larger numbers than the numbers that were
discussed in this work.
References
[1] G. Shalev, G. Landman, I. Amit, Y. Rosenwaks, and I. Levy, “Specific and label-free
femtomolar biomarker detection with an electrostatically formed nanowire biosensor,” NPG Asia Mater, vol. 5, p. e41, Mar. 2013.
[2] G. Shalev, A. Doron, and A. Cohen, “Virtual semiconductor nanowire, and methods of using same,” US Pat. 8,318,505, vol. 2, no. 12, 2012.
[3] B. J. Blalock, S. Cristoloveanu, B. M. Dufrene, F. Allibert, and M. M. Mojarradi, “The multiple-gate MOS-JFET transistor,” Int. J. high speed Electron. Syst., vol. 12, no. 02,
pp. 511–520, 2002.
[4] S. Cristoloveanu, B. Blalock, F. Allibert, B. M. Dufrene, and M. M. Mojarradi, “The four-gate transistor,” in Solid-State Device Research Conference, 2002, pp. 323–326.
[5] F. Balestra, S. Cristoloveanu, M. Benachir, J. Brini, and T. Elewa, “Double-gate
silicon-on-insulator transistor with volume inversion: A new device with greatly
enhanced performance,” Electron Device Lett. IEEE, vol. 8, no. 9, pp. 410–412, 1987.
[6] A. Henning, N. Swaminathan, A. Godkin, G. Shalev, and I. Amit, “Tunable Diameter Electrostatically-formed Nanowire for High Sensitivity Gas Sensing,” pp. 1–17.
[7] B. Dufrene, K. Akarvardar, S. Cristoloveanu, B. J. Blalock, R. Gentil, E. Kolawa, and
M. M. Mojarradi, “Investigation of the four-gate action in G< sup> 4</sup>-FETs,” Electron Devices, IEEE Trans., vol. 51, no. 11, pp. 1931–1935, 2004.
[8] L. I. Glazman and I. A. Larkin, “Lateral position control of an electron channel in a
[9] “CMOS VLSI Design: A Circuits and Systems Perspective (4th Edition): Neil Weste, David Harris: 9780321547743: Amazon.com: Books.” [Online]. Available:
