BCD TO 7 SEGMENT DECODER(COMMON ANODE 7-SEGMENT DISPLAY)
Abanes, Rionle M.
Alvarez, Jann Terence L.
Castillo, Gian Carlo V.
De Ocampo, Eljon R.
Reyes, John Carlo R.
OBJECTIVES
This design activity aims to develop a BCD-to-7-segment decoder through VHDL coding implemented using Altera DE2 FPGA board. The activity also aims:
• To develop and simplify a logic function that will implement the decoder using a common anode 7 segment LED display
• To familiarize a common anode 7 segment LED display and explore more functions of the Altera DE2 FPGA board
• To observe the output of the 7 segment LED display when inputs are don’t cares
INTRODUCTION
Digital Design is concerned with the design of digital electronic circuits. Digital design is also known by other names as logic design, digital logic, switching circuits and digital systems.
Altera DE2 Development and Educational board provides the ideal vehicle for learning about digital logic, computer organization, and FPGA’s. It uses the state-of-the-art technology in both hardware and CAD tools to expose students and professionals to a wide range of topics.
The project is a constructed Verilog Hardware Definition Language code using Quartus II which supports all stages of the design process for logic circuits, including design entry, synthesis, and placement and routing, simulation, and device programming.
INTRODUCTION
A binary coded decimal (BCD) to 7-segment display decoder such as the TTL 74LS47 or 74LS48, have 4 BCD inputs and 7 output lines, one for each LED segment. This allows a smaller 4-bit binary number (half a byte) to be used to display all the denary numbers from 0 to 9.
The 7-segment display consists of seven LEDs arranged in a rectangular fashion. In the common anode display, all the anode connections of the LED segments are joined together to logic “1”. The individual segments are illuminated by applying a ground, logic “0” or “LOW” signal.
CIRCUIT OPERATION
DESIGN SPECIFICATIONS
Common anode 7 segment LED display
3.3 Volt VCC Supply
Input connections:
A = pin SW[3]
B = pin SW[2]
C = pin SW[1]
D = pin SW[0]
DESIGN SPECIFICATIONS
Output connections (FPGA to 7 segment LED display):
pin GPIO_0[0] to pin a
pin GPIO_0[1] to pin b
pin GPIO_0[2] to pin c
pin GPIO_0[3] to pin d
pin GPIO_0[4] to pin e
pin GPIO_0[5] to pin f
pin GPIO_0[6] to pin g
pin GPIO_0[7] to pin dp (decimal point)
pin GPIO_0[10] to common anode
LIST OF MATERIALS
Altera DE2 board
7 segment LED display
Breadboard
Connecting wires
Laptop with Quartus II
LOGIC FUNCTIONS
Truth Table
a = A’B’C’D + BC’D’
b = BC’D + BCD’
c = B’CD’
d = BC’D’ + BCD + A’B’C’D
e = D + BC’
f = B’C + CD + A’B’D
g = A’B’C’ + BCD
dp = 0
Binary Input 7-segment Output
A B C D a b c d e f g dp
0 0 0 0 0 0 0 0 0 0 1 0
0 0 0 1 1 0 0 1 1 1 1 0
0 0 1 0 0 0 1 0 0 1 0 0
0 0 1 1 0 0 0 0 1 1 0 0
0 1 0 0 1 0 0 1 1 0 0 0
0 1 0 1 0 1 0 0 0 0 0 0
0 1 1 0 0 1 0 0 0 0 0 0
0 1 1 1 0 0 0 1 1 1 1 0
1 0 0 0 0 0 0 0 0 0 0 0
1 0 0 1 0 0 0 0 1 0 0 0
1 0 1 0 X X X X X X X X
1 0 1 1 X X X X X X X X
1 1 0 0 X X X X X X X X
1 1 0 1 X X X X X X X X
1 1 1 0 X X X X X X X X
1 1 1 1 X X X X X X X X
3.3 V
A B C D E F G
CA
H
A B C D
SCHEMATIC DIAGRAM
DATA AND RESULTS
Multisim SimulationFor ABCD = 0000 For ABCD = 0001
3.3 V
A B C D E F G
CA
H
A B C D
3.3 V
A B C D E F G
CA
H
A B C D
DATA AND RESULTS
Multisim SimulationFor ABCD = 0010 For ABCD = 0011
3.3 V
A B C D E F G
CA
H
A B C D
3.3 V
A B C D E F G
CA
H
A B C D
DATA AND RESULTS
Multisim SimulationFor ABCD = 0100 For ABCD = 0101
3.3 V
A B C D E F G
CA
H
A B C D
3.3 V
A B C D E F G
CA
H
A B C D
DATA AND RESULTS
Multisim SimulationFor ABCD = 0110 For ABCD = 0111
3.3 V
A B C D E F G
CA
H
A B C D
3.3 V
A B C D E F G
CA
H
A B C D
DATA AND RESULTS
Multisim SimulationFor ABCD = 1000 For ABCD = 1001
3.3 V
A B C D E F G
CA
H
A B C D
3.3 V
A B C D E F G
CA
H
A B C D
DATA AND RESULTS
Multisim SimulationFor ABCD = 1010 For ABCD = 1011
3.3 V
A B C D E F G
CA
H
A B C D
3.3 V
A B C D E F G
CA
H
A B C D
DATA AND RESULTS
Multisim SimulationFor ABCD = 1100 For ABCD = 1101
3.3 V
A B C D E F G
CA
H
A B C D
3.3 V
A B C D E F G
CA
H
A B C D
DATA AND RESULTS
Multisim SimulationFor ABCD = 1110 For ABCD = 1111
3.3 V
A B C D E F G
CA
H
A B C D
3.3 V
A B C D E F G
CA
H
A B C D
FUNCTIONAL SIMULATION
REGISTERED TRANSFER LOGIC
FPGA IMPLEMENTATION
Decimal Input (Binary) Actual Simulation
0 0000
FPGA IMPLEMENTATION
Decimal Input (Binary) Actual Simulation
1 0001
FPGA IMPLEMENTATION
Decimal Input (Binary) Actual Simulation
2 0010
FPGA IMPLEMENTATION
Decimal Input (Binary) Actual Simulation
3 0011
FPGA IMPLEMENTATION
Decimal Input (Binary) Actual Simulation
4 0100
FPGA IMPLEMENTATION
Decimal Input (Binary) Actual Simulation
5 0101
FPGA IMPLEMENTATION
Decimal Input (Binary) Actual Simulation
6 0110
FPGA IMPLEMENTATION
Decimal Input (Binary) Actual Simulation
7 0111
FPGA IMPLEMENTATION
Decimal Input (Binary) Actual Simulation
8 1000
FPGA IMPLEMENTATION
Decimal Input (Binary) Actual Simulation
9 1001
FPGA IMPLEMENTATION
Decimal Input (Binary) Actual Simulation
10 1010
FPGA IMPLEMENTATION
Decimal Input (Binary) Actual Simulation
11 1011
FPGA IMPLEMENTATION
Decimal Input (Binary) Actual Simulation
12 1100
FPGA IMPLEMENTATION
Decimal Input (Binary) Actual Simulation
13 1101
FPGA IMPLEMENTATION
Decimal Input (Binary) Actual Simulation
14 1110
FPGA IMPLEMENTATION
Decimal Input (Binary) Actual Simulation
15 1111
CONCLUSION Development of a BCD to 7 segment decoder is implemented using
the Altera DE2 FPGA Board.
In developing the design, the group members constructed a truth table that would represent the input and output of a BCD-to-7-segment decoder.
For the common anode 7 segment LED display used in the design, pins 3 and 7 are the pins for common anode which will be connected to a high logic voltage. Furthermore, pins 4, 5, 9, 7, 6, 2, 1 and 10 correspond to the cathode of segments a, b, c, d, e, f, g, and decimal point respectively.
Lastly, for the outputs of the 7 segment LED display where inputs are don’t cares (10 to 15), their outputs are observed as if inputs are decimals 2 to 7 respectively.
RECOMMENDATION
For don’t care inputs, it is recommended that there should be an indicator that the seven segment display cannot show the don’t care inputs.
For output aesthetics and dynamic display, the Altera DE2 board’s LCD panel should be used.
Simulate the circuits using available integrated circuits to compare and confirm the results of different simulations.
VHDL CODES