Copyright © 1997 Altera Corporation
Designing with MAX+PLUS II
Copyright © 1997 Altera Corporation
Class Agenda
MAX+PLUS II Design Environment MAX+PLUS II Design Methodology
– Design Entry– Compilation– Simulation– Timing Analysis– Device Programming
Review and Support
Copyright © 1997 Altera Corporation
MAX+PLUS IIDesign Environment
Copyright © 1997 Altera Corporation
MAX+PLUS II IS...
A fully integrated CPLD development system– Provides an architecture-independent design environment
• Supports ALL Altera devices (one Library for all devices)
– Supports broad range of design needs
• Design Entry
• Synthesis
• Place & Route (fitting)
• Simulation
• Timing Analysis
• Device Programming
– Provides extensive on-line help
– Supports multiple platforms ( PC, Workstation )
– Supports multiple EDA vendors and standards
Copyright © 1997 Altera Corporation
MAX+PLUS II Can...
Operate in a self-contained environment
Design Entry Design Compilation Verification & Programming
EDIFLPMOthers
EDIFVerilogVHDLSDF
Standard EDADesign Entry:
Standard EDADesign Verification:
CadenceMentor GraphicsLogic ModellingSynopsysViewlogicOthers
CadenceMentor GraphicsOrCADSynopsysViewlogicOthers
MAX+PLUS II Compiler
GraphicDesign Entry
Text Design Entry(AHDL, VHDL, Verilog HDL)
WaveformDesign Entry
HierachicalDesign Entry
FloorplanEditing
Design-RuleChecking
Logic Synthesis &Fitting
Multi-DevicePartitioning
AutomaticError Location
Timing-DrivenCompilation
TimingSimulation
FunctionalSimulation
Multi-DeviceSimulation
TimingAnalysis
DeviceProgramming
Copyright © 1997 Altera Corporation
Or...
Operate seamlessly with other EDA tools
MAX+PLUS II
Altera Gate ArrayConversion Kit
Verilog HDL &VHDL Design Files
Standard EDASimulator
Verilog HDLVHDLEDIFSDF
Standard EDAHDL Files
Standard EDASchematics
EDIF
LMF TDF
MAXFLEX
Classic
Copyright © 1997 Altera Corporation
MAX+PLUS II Operating Environment
MAX+PLUS II Manager– Start-up window
Toolbar provides shortcuts for commonly used functions
Status bar provides a brief description of selected menu command and toolbar button
MAX+PLUS II menugives you access to all MAX+PLUS II functions
Help menu gives you access to on-line help
Project Directory andProject name
Copyright © 1997 Altera Corporation
Questions about MAX+PLUS II?
MAX+PLUS II On-Line Help has the answers– Contains the complete up-to-date information on MAX+PLUS II– Provides tips on how to effectively work with MAX+PLUS II tools– Provides answers and examples
Digital Library CD-ROM
Copyright © 1997 Altera Corporation
MAX+PLUS IIDesign Methodology
Copyright © 1997 Altera Corporation
System Production
Design Specification
Design Compilation
Functional Verification
Timing Verification
Device Programming
In-System Verification
Design Modification
Design Entry
Copyright © 1997 Altera Corporation
Design Entry
Multiple design entry methods– MAX+PLUS II
• Graphic design entry• Text design entry
– AHDL, VHDL– 3rd party EDA tools
• EDIF– FPGA-Express
• OrCAD schematics, Xilinx (XNF) files
Files can be mixed and matched in a hierachical project Use LPM and Megafunctions to accelerate design entry
– Megawizard is an easy to use interface
Copyright © 1997 Altera Corporation
Design Entry Files
MAX+PLUS IIGraphic Editor
MAX+PLUS IIText Editor
MAX+PLUS IISymbol Editor
MAX+PLUS IIFloorplan Editor
Top-Level File
.gdf
Top-level design files can be .gdf, .tdf, .vhd, .sch, or .edf
.wdf .vhd .sch .edf .xnf
GraphicFile
WaveformFile
TextFile
GraphicFile
TextFile
TextFile
Imported from other EDA tools
OrCAD
Synopsys,ViewLogic,Mentor Graphics,etc...
XilinxGenerated within MAX+PLUS II
VHDL/Verilog
Waveform
Schematic
.tdf
TextFile
AHDL
Copyright © 1997 Altera Corporation
Set up a new project Draw schematic
– Enter symbols– Connect wires– Type in signal names
Save and check the design– The file extension is .gdf– Correct any errors with the aid of Message Processor
Create symbol or include file
Graphic Design Entry
Copyright © 1997 Altera Corporation
Set Up A New Project
Every design must have a project name Project name must match design file name
Project Name
Project Directory
Copyright © 1997 Altera Corporation
Open New File & Enter Symbols
Open a new .gdf file in Graphic Editor Double click in Graphic file to enter symbol
Type in symbol nameor click on symbol name
Symbol libraries
Symbols in the selected library
Open new file
Double click in Graphic Editor
Copyright © 1997 Altera Corporation
Available Libraries
prim ( Altera primitives )– Basic logic building blocks
mf ( Macrofunction )– 7400 family logic
mega_lpm ( LPMs, Megafunctions and MegaCores )– Library of Parameterized Modules ( LPMs )
• High-level building blocks– Megafunctions are high level function module
• busmux, csdpram, csfifo, parallel_add, etc...– MegaCores are IP models you can try before purchase
• UARTs, FFT, etc…
AMPP ( Altera Megafunction Partners Program )– Partners providing PCI, DSP, uControllers, etc...
Copyright © 1997 Altera Corporation
Using LPM & Megafunctions
Select ports Set parameters
Set desired ports by clicking on Port Name and set Port Status to Used or Unused
Set desired parameters by clicking on Parameter Name and set the desired value in the Parameter Value field
Click on the Help button to get information about the LPM or Megafunction
Copyright © 1997 Altera Corporation
Add User Libraries
Access user created libraries– Add user library directories– Set priorities
Select the library directorythen click on Add
Library search priority can be changed.
The Project directory has the highest priority, followed by the User Libraries, then by the Altera Libraries
Copyright © 1997 Altera Corporation
Making Connections
Wire– Single bit line
Bus– Multi-bit line
Signal name– Matching name– Attached to wire
Bus -Bus signal names required for LPM module busesWire
Wire to Bus Connection
Drawing tool shortcuts
Copyright © 1997 Altera Corporation
Graphic Editor Options
Font, Text Size– Text Control
Line Style– Select Wire or Bus
Display Assignments– Turns display on or off
Guideline Control– Controls grid lines
Rubberbanding– Wires move with symbols
Copyright © 1997 Altera Corporation
Save & Check the Design
Save & check the design file with .gdf extension Correct any errors with the aid of Message Processor
Design File Name
Project Directory
Copyright © 1997 Altera Corporation
Message Processor
Lists all Info, Warning and Error messages– Info messages are general information– Warning messages are possible problems– Error messages indicate Compiler is unable to complete
compilation process
Provides help on the messages Locates source of message in design file
Messages
Go to next or previous message
Information about message
Locate source in design file
Copyright © 1997 Altera Corporation
Generate Symbols and Include Files
Create symbol for higher-level schematic capture Create include file for AHDL function prototype
Create symbol
Create include file
Copyright © 1997 Altera Corporation
Symbol Editor
Symbols can be modified with the Symbol Editor
Copyright © 1997 Altera Corporation
Example Section
(LAB 1)
Copyright © 1997 Altera Corporation
Demo 1 (Basic Graphic design Entry)
Design flow of the circuit
Print out
Copyright © 1997 Altera Corporation
Demo 2
(1) Draw the following circuit(2) Use the Save & Check Option(3) Use the Error Message to Locate the Error(4) Correct the Error
Copyright © 1997 Altera Corporation
Demo 2 (use Save & Check Option)
Build the following circuit from the provided library
VHDL
Viewlogic EDIF
AHDL
LPM
GDF
Sel[1..0]
Copyright © 1997 Altera Corporation
Set up a new project– Same as Graphic Design Entry
Enter text description– AHDL– VHDL
Save & check the design– Similar to Graphic Design Entry– The file extension is .tdf or .vhd
Text Design Entry
Copyright © 1997 Altera Corporation
AHDL
Altera Hardware Description Language High-level hardware behavior description language Uses Boolean equations, arithmetic operators, truth
tables, conditional statements, etc. Especially well-suited for large or complex state
machines All described behavior is implemented concurrently Use Insert AHDL Template in the Text Editor
Learn more about AHDL in the customer training class:Designing with MAX+plus II Using AHDL
Copyright © 1997 Altera Corporation
VHDL
VHSIC Hardware Description Language IEEE standard High-level hardware behavior description language Especially well-suited for large or complex designs Use Insert VHDL Template in the Text Editor
Learn more about VHDL in the customer training class:Designing with MAX+plus II Using VHDL
Copyright © 1997 Altera Corporation
Imported Design
Top-level Design– Some top-level designs can be read directly by the compiler
• EDIF Netlist files• VHDL Netlist files• Xilinx Netlist files
– Save top-level OrCAD schematics as .gdf file in Graphic Editor
Subdesigns (lower level modules)– EDIF, VHDL, OrCAD schematics, Xilinx files
• Create symbols and include files• Embed symbols or include files in Graphic or Text Editor
– Other proprietary files• JEDEC, ABEL, PALASM• Conversion ultilities exist in Altera ftp site
Copyright © 1997 Altera Corporation
MAX+PLUS II Hierachy Display
Displays current design files as a hierachy tree– Traverse the hierachy tree with ease
Displays all files associated with the current project– Open and close files directly ( click on right button of mouse )
Copyright © 1997 Altera Corporation
Design Entry Recommendations
Use LPM/Megafunction whenever possible Use hierarachical design methodology Use Hierarachy Display for fast access to design file
at any level Use Message Processor to locate source of error in
design file
Copyright © 1997 Altera Corporation
DesignFiles
SupportFiles
Design Entry Summary
MAX+PLUS IIGraphic Editor
MAX+PLUS IIText Editor
MAX+PLUS IISymbol Editor
MAX+PLUS IIWaveform Editor .gdf
.tdf .vhd
.sch
.edf
.xnf
MAX+PLUS II
3rd Party EDATools
.sym
.inc
User
.wdf
.lmf
Copyright © 1997 Altera Corporation
System Production
Design Specification
Design Entry
Simulation
Device Programming
In-System Verification
Design Modification
Compilation
Timing Analysis
Copyright © 1997 Altera Corporation
MAX+PLUS II Compiler
Process all design files associated with the project– Files can be created with MAX+PLUS II or 3rd party EDA Tools
Checks for syntax errors and common design pitfalls Performs logic synthesis and place & route
– According to assignments in .acf file
Generates files for simulation and timing analysis– Files can be used by MAX+PLUS II or 3rd party EDA Tools
Generates files for programming targeted devices
Copyright © 1997 Altera Corporation
Assign target device Set logic synthesis controls Set place & route controls Select functional compilation or timing compilation Run the compilation Consult the report file (.rpt) or the Floorplan Editor for
device utilization summaries and synthesis and place & route results
Compiling a Project
Copyright © 1997 Altera Corporation
Compiler Input and Output Files
MAX+PLUS IIDesign Files(.gdf, .tdf, .vhd)
MAX+PLUS II CompilerCompiler Netlist
Extractor (includesall netlist readers
Functional, Timing,or Linked SNF
Extractor
EDIF, VHDL &Verilog Netlist
Writers
DatabaseBuilder
Partitioner
DesignDoctor
LogicSynthesizer
Fitter
Assembler
3rd Party EDADesign Files(.edf, .sch, .xnf)
Functional SNFFiles(.snf)
Timing SNFFiles(.snf)
ProgrammingFiles
(.pof, .sof, .jed)
3rd Party EDASimulation/Timing Files
(.edo, vo, vho, sdo)
Mapping Files(.lmf)
Assignments(.acf)
Copyright © 1997 Altera Corporation
Compiler Input Files
Design files– MAX+PLUS II
• Graphics file (.gdf), AHDL file (.tdf), VHDL file (.vhd)
– 3rd Party EDA Tools
• EDIF file (.edf)
– Select Vendor in EDIF Netlist Reader Settings
– Library Mapping File (.lmf) required for vendors not listed
• OrCAD file (.sch), Xilinx file (.xnf)
Assignment and Configuration File (.acf)– Controls the Compiler’s synthesis and place & route operations
– Automatically generated when user enter assignments
– Automatically updated when user changes assignments or backannotes project
Copyright © 1997 Altera Corporation
Compiler Output Files
Design verification files– MAX+PLUS II
• Simulation Netlist File (.snf)– 3rd Party EDA Tools
• VHDL netlist file (.vho)• EDIF netlist file (.edo)• Verilog netlist file (.vo)• Standard Delay Format SDF file (.sdo)
Programming files– Programmer Object file (.pof)– SRAM Object file (.sof)– JEDEC file (.jed)
Copyright © 1997 Altera Corporation
Assignments
Assignments are used to control logic synthesis and place & route operations
Assignments are generally made after the compilation process to resolve fit or performance issues
Examples of assignments are:– Device assignment– Synthesis Logic Options– Timing Requirements– Pin/Location/Chip– Clique
Assignments are stored in the .acf file
Copyright © 1997 Altera Corporation
Making Device Assignment
Select Device– Specific device– Auto
• MAX+PLUS II chooses smallest and fastest device the design fits into
Selectdevice Family
Autodevice selection
Specificdevice selection
Copyright © 1997 Altera Corporation
Controlling Logic Synthesis
The logic synthesis operation is a trade-off between area, speed, and ease-of-fit
MAX+PLUS II gives users the control Two levels of controlling logic synthesis:
– Individual logic level• Localized effect• Affects only the selected nodes, pins and logic blocks
– Global logic level• Global effect• Affects all nodes, pins and logic blocks
Recommendation: use the logic synthesis controls only after design analysis of first compilation
Copyright © 1997 Altera Corporation
Individual Logic Level Control
Highlight node, pin or logic block Choose Assign menu then Logic Options Two ways of making individual logic level assignment:
– Individual Logic Options assignment– Synthesis Styles assignment
Copyright © 1997 Altera Corporation
Individual Logic Option Assignment
Provides controls to turn individual architectural features and synthesis algorithms on or off Gray or Default (default): set by higher level or global setting
Check or Auto: enable feature
Blank or Ignore: disable feature
Copyright © 1997 Altera Corporation
Synthesis Style Assignment
Predefined frequently used groups of logic options– None (default): set by higher level or global setting– FAST: enable features– NORMAL: disable features– WYSIWYG: implement design as is
User can customize own styles
Copyright © 1997 Altera Corporation
Global Logic Level Control
Choose Assign then Global Project Logic Synthesis Select from predefined synthesis style
– NORMAL (default), FAST or WYSIWYG
Or create user taylored settings
Copyright © 1997 Altera Corporation
More Methods of Controlling Synthesis
Making Timing Requirements assignment
(FLEX devices only) Specifies desired speed performance Use after performing timing analysis to improve specific
timing path Localized control
– Highlight Pin
– Choose Assign then Timing Requirements
– Assign desired tpd, tco, tsu, fmax values
Global control– Chosse Assign then Global Project Timing Requirements
– Assign desired tpd, tco, tsu, fmax values
Copyright © 1997 Altera Corporation
Controlling Place & Route
Recommendation: Give MAX+PLUS II the freedom to place pins and logic cells– Do not make Pin/Location/Chip assignments unless
absolutely necessary– Use Pin/Location/Chip assignments to solve specific
performance/fit problems found in design analysis
If needed, Pin/Location/Chip assignments can be made from design source file or the Floorplan Editor
Assignments can only be made to “hard” nodes or lower-level designs that contains hard nodes– Hard nodes are objects that translates directly into objects in
silicon e.g. flipflop, LCELL and I/O pins
Copyright © 1997 Altera Corporation
From Design Source File
Making Pin/Location/Chip Assignment Highlight node in graphics or text source file Make Pin/Location/Chip assignment
Highlight node and choose Assign Pin/Location/Chip
Node name automatically entered in the Node Name field
Choose pin or LCELL location then click on Add to enter assignment(Note: You must choose a specific device prior to this step)
Copyright © 1997 Altera Corporation
From Floorplan Editor
Making Pin/Location/Chip Assignment Select LAB View and Current Assignments Floorplan
– must Save & Check the project first
All nodes & pins are listed in the Unassigned Nodes & Pins field
Drag and drop to make assignments to specific locations
Nodes and pins can also be assigned to general areas like LAB, row or column
Copyright © 1997 Altera Corporation
More Controlling Place & Route
Making Clique Assignment Locate group of logic to be placed close together
– Highlight logic in design file or Floorplan Editor and assign clique
Use to reduce delay through the cliqued logic
Highlight logic block
Create or add to clique
Copyright © 1997 Altera Corporation
More Controlling Place & Route
Making Global Project Device Options Assignment Choose Assign then Global Project Device Options Used to control device utilization
– FLEX• Reserve I/O pin and LCELL resources• Select configuration method• Assign dual-use configuration pins in FLEX devices• Control device-wide reset and oe pins (FLEX 10K only)
– Others• Reserve I/O pin and LCELL resources• Set security bit
Copyright © 1997 Altera Corporation
Compiler Processing Options
Functional– Compilation generates file for Functional Simulation
• Functional SNF file (.snf)
Timing– Compilation generates user selectable files for
• Timing Simulation and Timing Analysis– Timing SNF file (.snf)
• 3rd party EDA Simulation– Verilog file (.vo)– VHDL file (.vho)– SDF file (.sdo)
• Device Programming– Altera Programmer file (e.g. .pof, .sof)
Copyright © 1997 Altera Corporation
The Functional Compilation Process
Compiler Netlist Extractor builds the .cnf netlist file and checks for syntax errors
Database Builder constructs the node name database Functional SNF Extractor build .snf file for functional
simulation
Copyright © 1997 Altera Corporation
The Timing Compilation Process
Compiler Netlist Extractor and Database Builder build netlist database and check for syntax errors
Logic Synthesizer performs logic synthesis/minimization Design Doctor checks for design violations Partitioner and Fitter executes place & route algorithm
and builds the .rpt file on device implementation Timing SNF Extractor builds .snf file for simulation and
timing analysis Assembler builds files for programming the device
Copyright © 1997 Altera Corporation
More Compiler Processing Options
Design Doctor– Checks for common design errors
Fitter Settings– Set place & route options
Smart Recompile– Faster compilation time
Total Recompile– Recompile every file
Copyright © 1997 Altera Corporation
Compile the Design
Start Button starts compilation process Messages are displayed by the Message Processor
– Info– Warning– Error
Start Compilation
Messages
Copyright © 1997 Altera Corporation
The Report File
Project summary– Device assignments– Error summary– Device pin-out diagram (useful for PCB layout)
Resource ultilization– Pin– LCELL– Equations
Compiler resources– Compilation time– Memory usage Open report file by double
clicking on the rpt icon
Copyright © 1997 Altera Corporation
Floorplan Editor
Graphical user interface for creating/viewing resource assignments– Pins– Logic cells– Cliques– Logic options
Drag-and-drop capability for assigning pins/logic cells Graphical view of current assignments as well as last
compilation results LAB view or external chip view
Copyright © 1997 Altera Corporation
Floorplan Editor
Last Compilation Floorplan Full Screen LAB View with Report File Equation Viewer
Fan-in and Fan-out
Highlighted LCELL
LCELL equation
Display control
Copyright © 1997 Altera Corporation
Floorplan Editor
Last Compilation Floorplan Device View
Pin number
Pin name
Color Legenddefinition
Copyright © 1997 Altera Corporation
Back-Annotation
Lock “last successful compilation” into current assignments with Back-Annotate Project command
Copyright © 1997 Altera Corporation
Example Section
(LAB 2)
Copyright © 1997 Altera Corporation
Demo 1
(1) Compile the file from previous design(2) Correct the Error(3) Demo the Functional/Timing Compilation step(4) Demo some Assign Option
- turn on Cascade/Carry Chain- Synthesis Style Option on different module
(5) Step through the RPT file(6) Step through the FloorPlan Editor
Copyright © 1997 Altera Corporation
Project Compilation Recommendations
Use assignments after design analysis to improve fitting or performance
Use the Report File to find specific information on the design
Use the Floorplan Editor to see results of Assignments
Back Annotate your design only when necessary for board layout to give MAX+PLUS II the best chance of fitting design into device
Copyright © 1997 Altera Corporation
DesignFiles
Simulation/Timing Files
Project Compilation Summary
.gdf
.tdf
.vhd
.sch
.edf
.xnf
.snf
MAX+PLUS II CompilerCompiler Netlist
Extractor (includesall netlist readers
Functional, Timing,or Linked SNF
Extractor
EDIF, VHDL &Verilog Netlist
Writers
DatabaseBuilder
Partitioner
DesignDoctor
LogicSynthesizer
Fitter
Assembler
.edo .vo .vho 3rd PartyEDA Files
ProgrammingFiles
.pof
ReportFiles
.rpt
.sdo
Copyright © 1997 Altera Corporation
System Production
Design Specification
Design Entry
Project Compilation
Device Programming
In-System Verification
Design Modification
Simulation
Timing Analysis
Copyright © 1997 Altera Corporation
MAX+PLUS II Simulator
MAX+PLUS IIWaveform Editor
.scf
.snf
MAX+PLUS IIText Editor
MAX+PLUS IISimulator
MAX+PLUS IICompiler
.scf
.vec
MAX+PLUS IIWaveform Editor
Copyright © 1997 Altera Corporation
MAX+PLUS II Simulation
Create Simulation Stimulus– Waveform– Vector
Run Functional Simulation– Fast compilation– Logical model only, no logic synthesis– All nodes are retained and can be simulated– Outputs are updated without delay
Run Timing Simulation– Slower compilation– Timing model: logical & delay model– Nodes may be synthesized away– Outputs are updated after delay
Copyright © 1997 Altera Corporation
Simulation Waveform
Stimulus Waveform– Waveform Editor File (.scf)
– Control
• Clock: Use built-in clock generator
• Others: Hand drawn with overwrite/copy/paste/repeat
– Data
• Counting patterns: Use built-in binary or gray code generator
• Others: Enter with overwrite/copy/paste/repeat
Reference Compare waveform– Waveform Editor File (.scf)
– Draw or save previous simulation result as reference waveform
– Use with Compare after new simulation run to verify output
Copyright © 1997 Altera Corporation
Create Waveform Simulation Stimulus
Open Waveform Editor Select Enter Nodes from SNF… from Node menu Enter Nodes into Selected Nodes & Groups field
Select Node Enter Node into Selected Nodes & Groups field
Copyright © 1997 Altera Corporation
Grid Control
Snap to Grid– On: waveforms drawn increments of grid size– Off: waveforms can be drawn to any size
Set Grid size
Copyright © 1997 Altera Corporation
Draw Stimulus Waveform
Highlight portion of waveform to change Overwrite with desired value (Group value or single bit)
Hightlight waveform
Overwrite value
Overwrite shortcut
Copyright © 1997 Altera Corporation
Create Clock Waveform
Snap to Grid On: Clock Period is twice the grid size Snap to Grid Off: Clock Period can be any value
Hightlight waveform
Clock shortcut
Specify clock period
Copyright © 1997 Altera Corporation
Create Counting Pattern
Make sure your counting frequency matches your clock frequency
Highlight waveform
Pattern shortcut
Specify counting pattern
Specify counting frequency
Copyright © 1997 Altera Corporation
Grouping Signals and Set Radix
Highlight waveforms to be grouped– MSB must be the top waveform
Enter Group Name and set Radix Enter Group Name
Set radix
Copyright © 1997 Altera Corporation
Save the Waveform Stimulus File
Save the waveform stimulus file with .scf extension MAX+PLUS II will use Project name as default file name
Waveform File Name
Project Directory
Copyright © 1997 Altera Corporation
Create Vector Simulation Stimulus
Open Text Editor Type in vector stimulus
– Clock
– Pattern
– Output
% units default to ns %START 0 ;STOP 1000 ;INTERVAL 100 ;INPUTS CLOCK ;PATTERN0 1 ; % CLOCK ticks every 100 ns %
INPUTS A B ;PATTERN0> 0 0220> 1 0320> 1 1 570> 0 1720> 1 1;
OUTPUTS Y1 Y0 ;PATTERN % check output at every Clock pulse %= X X= 0 0 = 0 1= 1 0= 1 1;
Copyright © 1997 Altera Corporation
Save the Vector Stimulus File
Save the vector stimulus file with .vec extension– You must change the .vec extension since MAX+PLUS II
defaults to .tdf extension for text files
Change the extension to .vec
Copyright © 1997 Altera Corporation
Select Simulation Stimulus File
Defaults to .scf file For vector input stimulus, set Vector Files Input
to .vec fileSet to .vec file
Copyright © 1997 Altera Corporation
Specify Length of Simulation
Specify maximum length of simulation time with End Time
Copyright © 1997 Altera Corporation
Run Functional Simulation
Click on Start then Open SCF to see result
Output change on clock edge
Open .scf file
Click on Start Button
Copyright © 1997 Altera Corporation
MAX+PLUS II Functional Simulation
Use to verify operation of design Advantage over Timing Simulation
– Fast compilation– All nodes are retained and can be simulated– Outputs are updated without delay
• Most of the time, this makes figuring out cause and effect much easier
Disadvantges– Logical model only, no logic synthesis– No delays in simulation
• Oscillations, glitches and other timing related errors do not show up
Copyright © 1997 Altera Corporation
Run Timing Simulation
Click on Start then Open SCF to see result
Output change after timing delay
Copyright © 1997 Altera Corporation
MAX+PLUS II Timing Simulation
Used to debug timing related errors Advantages over Functional Simulation
– Simulation of full synthesis result– Outputs change after timing delay
• Detection of oscillations, glitches and other timing related errors are possible
Disadvantages– Longer compilation time– Combinatorial logic nodes cannot be simulated
• Node may be transformed or removed– Only “Hard” nodes can be simulated– Timing delays make debugging more difficult because cause
and effect relationships are harder to locate
Copyright © 1997 Altera Corporation
Open first channel file Choose Compare under File menu Select the name of the second channel file with the
Compare dialog box Deviations of second channel file from the first are
highlighted
Compare Two Simulation Files
Comparing Different Simulations
Copyright © 1997 Altera Corporation
Example Section
(LAB 3)
Copyright © 1997 Altera Corporation
Demo 1
Demo the Waveform Editor
Copyright © 1997 Altera Corporation
Project Simulation Recommendations
Use built-in clock generator to create clock Use built-in count generator to create test pattern Use Functional Simulation to verify proper operation Use Timing Simulation to examine signal delay effects Use Compare function to verify output Use the dynamic link ( Find Node in Design File ) to
go to source file to make any necessary corrections
Copyright © 1997 Altera Corporation
Project Simulation Summary
Two types of simulation– Functional simulation
• No logic synthesis• No delay model• All nodes can be simulated
– Timing simulation• Logic synthesis• Delay model• Only hard nodes can be simulated
Two types of stimulus file– Waveform– Vector
Simulation result is stored in .scf file
Copyright © 1997 Altera Corporation
System Production
Design Specification
Design Entry
Project Compilation
Device Programming
In-System Verification
Design Modification
Timing Analysis
Project Simulation
Copyright © 1997 Altera Corporation
MAX+PLUS II Timing Analyzer
.snf
MAX+PLUS IITiming Analyzer
MAX+PLUS IICompiler
MAX+PLUS IIFloorplan Editor
MAX+PLUS IIGraphic Editor
MAX+PLUS IIText Editor
Delay Matrix
Setup/HoldMatrix
RegisteredPerformance
Copyright © 1997 Altera Corporation
Project Timing Analysis
Timing Analyzer is a static timing analyzer Three forms of timing analysis
– Registered Performance calculates fastest possible internal clock frequency
– Delay Matrix calculates combinatorial delays– Setup/Hold Matrix calculates setup & hold times for device
flipflops
Source of delay path can be located in– Design file– Floorplan Editor
Copyright © 1997 Altera Corporation
D Q Comb D Q
Tskew
Delay
Tco
Tsetup
DclkSclk
Registered Performance Analysis
Calculates maximum internal register frequency Used to determine if design meets clock specification
Clock period = delay + tco + tsuNote: tskew is added to the clock period if destination clock
edge is earlier than source clock edge
Clock inversion– Clock inversion between source clock and destination clock
results in Clock period = ( delay + tco + tsu ) * 2
Copyright © 1997 Altera Corporation
Run Registered Performance Analysis
Click on Start Source/Destination, Clock period and Frequency of
the longest path are displayed Click on List Paths to trace delay path
Copyright © 1997 Altera Corporation
Tracing Delay Path In Floorplan Editor
Highlight Path of interest Check Locate in Floorplan Editor Click on Locate All Click on show path to display path
Copyright © 1997 Altera Corporation
Application of Registered Performance
Use Registered Performance Analysis to see if design meets clock frequency requirement
What to do if frequency is less than desired– Use List Path to display the worst case delays– Use Floorplan Editor to view the entire path
• Are Logic Cells and pins scattered among different rows?• Can the Logic Cells benefit from carry/cascade chains
(FLEX) or parallel expanders (MAX)?– Use Assignments ( Clique, Logic Options, etc… ) on the
critical path to improve performance– If still less than desired, consider pipelining technique or
different design implementations where appropriate
Copyright © 1997 Altera Corporation
Delay Matrix Analysis
Calculates combinatorial logic delays Typically used to evaluate input pin to output pin delay Internal point to point delay analysis is possible by
setting node source and destination for analysis
D QComb D QComb
Combinatorial Logic
Copyright © 1997 Altera Corporation
Delay Matrix Source and Destination
Set Source and Destination to be analyzed
Copyright © 1997 Altera Corporation
Useful Analysis Options
Time Restrictions– Show All Path– Show Only Longest Paths– Show Only Shortest Paths
Cell Width– Control matrix display
Cut Off I/O Pin Feedback– See next page
Cut Off Clear & Preset Paths– No clear or preset delay analysis
List Only Longest Path– List Path lists only longest path between two points
Copyright © 1997 Altera Corporation
Cut Off I/O Pin Feedback
D Q D Q
AB
C
Used to break bi-directional pin from the analysis When on, paths A and B true C false When off, path A, B and C are true
I/O Pin
Copyright © 1997 Altera Corporation
Run Delay Matrix Analysis
Select Delay Matrix Analysis and click on Start button Matrix shows all paths, longest path, or shortest path
depending on Time Restrictions option selected Use List Path to analyze the path of delays
Copyright © 1997 Altera Corporation
Comb D Q
Tsetup , Thold
Setup/Hold Matrix Analysis
Setup/Hold Matrix calculates setup & hold times for device flipflops
Setup – clock_path - data_path - Tsetup = setup margin
Hold– data_path - clock_path - Thold = hold margin
Copyright © 1997 Altera Corporation
Run Setup/Hold Matrix Analysis
Click on Start button Setup/Hold times are displayed with respect to the
clocks
Copyright © 1997 Altera Corporation
Example Section
(LAB 4)
Copyright © 1997 Altera Corporation
Demo 1
(1) Compile the previous design by Timing Compilation(2) Run the Timing Analysis
- Delay Matrix- Setup/Hold time Matrix- Clock Performance
(3) Play around with some Timing Analysis Option
Copyright © 1997 Altera Corporation
Timing Analysis Recommendations
Use Timing Analyzer to locate performance bottleneck Use Registered Performance Analysis to determine
internal clock frequency performance of the design Use Show Only Longest Path Time Restrictions in Delay
Matrix to get the longest delay time from input pin to output pin
Use List Path and Locate in Floorplan Editor to view worst case paths
Use List Path and Locate to trace through path in design file
Use assignments and recompile to fine-tune performance
Copyright © 1997 Altera Corporation
Project Timing Analysis Summary
Timing Analyzer is a static timing analyzer Three modes of Timing Analysis
– Registered Performance– Delay Matrix– Setup/Hold Matrix
Provides ability to trace path through Floorplan Editor or design file
Copyright © 1997 Altera Corporation System Production
Design Specification
Design Entry
Project Compilation
Timing Analysis
In-System Verification
Design Modification
Device Programming
Project Simulation
Copyright © 1997 Altera Corporation
Altera Programmer– LP4, LP5, LP6(Current Version)– BitBlaster– ByteBlaster– System Supported
• PC’s (MS Windows)• Sun SPARCstations• HP 9000 Series 700• IBM RS6000
Third-party Programmer
Device Programmers Available
Copyright © 1997 Altera Corporation
Device Adapters
The On-line help provides information on adapters
Copyright © 1997 Altera Corporation
Programming a Device
Initiate programming with the Programmer module in MAX+PLUS II
Programmer defaults to programming file for specified project
Use Select Programming File (File menu) to select another programming file
Perform programming operation with buttons in Programmer
Master Programming Unit (MPU) stores last command (use Start button to repeat)
Using the Programmer & the MPU
Copyright © 1997 Altera Corporation
Altera Design MethodologyThe Big Picture
Copyright © 1997 Altera Corporation
Hierarchical Design
Break design into modules Enter and debug each module separately Create Default Symbols or Include Files for each
module Use these modules in the top-level design file Assign each module with individual logic options, if
necessary
Copyright © 1997 Altera Corporation
Compile
Select the targeted device Remember the 80/80 rule. Reserve 20% logic and
20% I/O pin resources to accommodate potential design modifications
Compile top-level design without any pin assignments first to determine if the design actually fits in the targeted device
If absolutely necessary, pin and logic locations can be assigned through design editor or Floorplan Editor or directly to the assignment & configuration file (.acf)
Copyright © 1997 Altera Corporation
Verify
Simulate.– Functionally correct?– Any glitches?
Perform Timing Analysis– Resolve performance bottlenecks
Satisfied with design: Back annotate Project to lock down pin and logic option assignments
Copyright © 1997 Altera Corporation
Program
Program the device Run system verification tests If necessary, modify the design, recompile with the
back annotated assignments and reprogram the device