8/3/2019 Ee247 Project 3 2
http://slidepdf.com/reader/full/ee247-project-3-2 1/12
UNIVERSITY OF CALIFORNIA
College of Engineering
Department of Electrical EngineeringAnd Computer Sciences
MULTIFREQUENCY CELL IMPEDENCE
MEASUREMENT
EE247 Term Project
Eddie Ng
Mounir Bohsali
Professor Bernhard Boser
8/3/2019 Ee247 Project 3 2
http://slidepdf.com/reader/full/ee247-project-3-2 2/12
Introduction:
The main objective of this project is to build a system capable of measuring cell impedance
which can be modeled as a parallel RC equivalent network.In order to alleviate the required precision, the channel/cell block is configured in a feedback
network whose output signal is compared to the calibrated reference signal.
The resulting cell impedance value is passed through ten pairs of I/Q mixers in parallel. After the signal is low pass filtered, it is digitized and fed into a DSP to calculate the end result.Since calibration is done in an early stage in the system, only the first amplifier with the
channel/cell feedback configuration requires high precision (0.01%).
The simulated system shows that the final results are accurate within 0.01% after modeling the
critical non-idealities of all different blocks such as equivalent input referred and quantization
noise, finite open loop gain, finite amplifier bandwidth, DC offset, INL, and DNL.
Hierarchical Design Description:
Fig. 1 shows a block level simulation diagram of the entire system.
To first order, the system was initially simulated with ideal components. As a second step,critical non-idealities of each building block based on actual commercial products were added,
and the system was re-simulated and the results were verified to meet the specs.
Feedback amplifier:
The channel/cell is placed in a negative feedback configuration around the amplifier. The
resulting transfer function is
Cchannel)(CcellRf sRchannelRcell
Rf
Zcell
Rf H(s)_ideal +⋅⋅−
+
−=
−=
where
Cchannel)(CcellRchannel)(Rcells1
RchannelRcellZcell
+⋅+⋅+
+=
Refer to Figures 4 and 5 for Simulink block level implementations for the above two transfer
functions.
In order to measure the cell impedance, ten input sine waves at logarithmically spaced
frequencies (f1, f2, … f10) with amplitudes as shown in table 1 are applied to the channelcontaining both the cell and the solution (See Fig. 3). The input amplitudes are chosen as such
to prevent output saturation. In that order, the table below (Table 1) showing minimum and
maximum gains at each frequency was generated. The supply voltage (+/-15V) of the chosencommercial op-amp sets a upper limit on the input voltage given by
Vcc],gain_max
Vsupply[minVin_max ≤
The integrated output noise sets a lower limit on the input voltage.
Since ten sine waves are applied simultaneously to the amplifier, each signal amplitude could
add up in phase. In order to prevent saturation, an “n factor” is used to scale each input.
Simulation showed that an n factor of 8 is sufficient to limit the output swing to +/- 12.5V(maximum output voltage swing of commercial amplifier used in the design).
8/3/2019 Ee247 Project 3 2
http://slidepdf.com/reader/full/ee247-project-3-2 3/12
Frequency Minimum Gain
(Cch=50pF, Rch=250Ω)
Maximum Gain
(Cch=1nF, Rch=500Ω)
Maximum Input
Amplitude Vo-p
100KHz 0.200025 0.4049 12.5 / n
2.15KHz 0.200114 0.422173 12.5 / n
4.64KHz 0.20053 0.494883 12.5 / n
1MHz 0.20245 0.74457 12.5 / n
2.15MHz 0.211087 1.408205 8.9 / n4.64MHz 0.247442 2.941246 4.2 / n
10MHz 0.372285 6.292726 2.0 / n
21.5MHz 0.704102 13.50792 0.93 / n
46.4MHz 1.470623 29.14195 0.43 / n
100MHz 3.146363 62.80127 0.2 / n
Table 1. Summary of maximum input amplitudes allowed before output clipping.
Simulation suggest usage of n=8,
To further refine the model, non-idealities such as finite open-loop gain, offset, finite
bandwidth, input-referred noise are added to the Simulink models.
Finite open loop gain:
The finite open loop gain results in a gain error in the above ideal transfer function as follows:
)Z
Rf (1
a
11
1H(s)_idealH(s)
++
⋅= , where a = finite amplifier gain
Refer to Figure 5 for a Simulink implementation of the above transfer function.
Finite amplifier bandwidth:The finite amplifier bandwidth is modeled as follows:
dBw
jwo
aoa
3 _ 1+
= where ao = low frequency gain
DC offset and input referred noise:
DC offset is modeled in Simulink as a constant block, and input referred noise is modeled using
a random signal generator.
The THS4021 op-amp from TI, inc. with specifications that meet the above constraints is used
in the designThe following are the key specs of the above op-amp:
Vsupply: +/-15VOutput voltage range: +/- 12.5V
Input voltage range: +/- 15V
Open loop gain: 60V/mVVos: 0.5mV
Gain Bandwidth: 350MHz
Input referred noise: 1.5nV/sqrt(Hz)
8/3/2019 Ee247 Project 3 2
http://slidepdf.com/reader/full/ee247-project-3-2 4/12
Calibration:
Calibration is performed in an early stage of the system.A dedicated path for calibration containing a channel without cells is placed in parallel with the
path containing channel with cells.
A differential topology is used to subtract the measured analog voltage signal from thecalibrated channel only analog voltage signal. This is done directly after the first stage analog
amplifier.
The transfer function of the resulting network is:
Zcell)channelZchannel(Z
ZcellRf -H(s)
+
⋅=
Since calibration is being done in an early stage of the system, all the analog componentsfollowing the fist stage amplifier only need to carry approximately a 1% accuracy.
Refer to Figures 7 and 8 for measurement calibrated values of Rchannel and Cchannel.
Mixers:
In order to separate the outputs at the different frequencies of interest, the signal is fed into
twenty analog mixers separated into ten pairs. Each pair is tuned to one input frequency (i.e. f1,
f2, … ,f10). Within each pair of mixers, the two local oscillator frequencies are 90o
out of phase
producing the real and the imaginary parts of the output signal.The commercial AD831 mixer from Analog Devices is used in this system. The mixer
specifications as summarized as follows:Vsupply = +/-5V
1dB compression point = 10dBm
IP3 = 24dBmLO drive = -10dBm
Bandwidth = 500MHz for both RF and LO
SSB NF = 10.3dB
The mixers are implemented in Simulink. Since the NF of the mixer is critical in this
application, it is modeled in Simulink as a random signal generator added with the input of themixer.
Low Pass Filters:
Following the mixers, low pass filters are used to attenuate the high frequency unwanted signalsthat result from the mixing operation and keeping only the DC signal of interest.
In Simulink, the low pass filters are implemented as a sixth order Bessel low pass filters withfpass=1/10 of input frequency. We chose a sixth order filter because it can give a good
attenuation at the frequency of interest and is easily implemented with biquads with acceptable
sensitivity of component variations at the same time. A Bessel filter is used to provide goodstep response and further reduce the settling time. As shown later, these filters also provide an
anti-aliasing function for the ADC.A gain stage is added after the low pass filters in order to present a high level signal for the
ADC to take advantage of its full scale range.
8/3/2019 Ee247 Project 3 2
http://slidepdf.com/reader/full/ee247-project-3-2 5/12
ADC:
The down-conversion of the amplifier output signal from a high frequency to DC relaxesconsiderably the speed specification of the ADC. However, note that this translation to DC is
accompanied by several potential problems as DC offset generated by the amplifiers, noise, and
harmonic distortion.A differential topology is used to fix the DC offset problem. Moreover, noise is modeled by a
random signal generator whose output is added to the ADC input. The noise variance is
calculated using the SNR of the actual ADC used.An ENOB of 14-bit resolution ADC is chosen with a sampling frequency of 40kHz.The commercial ADS7807 16-bit ADC from TI, inc. is used in this system. The following are
the critical specifications of the used ADC:
Vsupply: +/-5VDNL_max: 16-bits, no missing code
INL_max: +/- 1.5LSB
SINAD with 1kHz input: 86dBSINAD=SNDR
ENOB = 14.66.02
1.76SINAD=
+> 14 required resolution
INL and DNL distortion is modeled in Simulink by representing the input as a 3rd
order power series. Vin’ = Vin + a2*Vin
2+ a3*Vin
3
Thermal noise is modeled by a random signal generator whose output is added to the ADCinput. The noise variance is calculated using the SNR of the actual ADC used.
Refer to Figure 6 for the ADC Simulink model.
DSP:
Following the analog to digital conversion, the signal is processed by a Digital Signal Processor
(DSP) for back-end calculation of Zcell using the following two equations:
gain
voutRchannel2Rf Vin
vout
gain
2Rchannel
Rcell
2
⋅⋅−⋅
⋅⋅
=
gainviRf f π2
vout2Ccell
⋅⋅⋅⋅⋅
⋅=
where vout is the output voltage of the entire system
gain is the overall cascaded gain of the entire systemTo cancel the factor of ½ produced from mixing two sinusoidal waveforms, a factor of 2 is
multiplied to vout.
The commercial SMJ320F240 DPS from TI, inc. is used in this system.
8/3/2019 Ee247 Project 3 2
http://slidepdf.com/reader/full/ee247-project-3-2 6/12
See Fig. 3
See Fig. 5
See Fig. 2
(dashedcircle only)
Figure 1. Simulink block level simulation diagram of complete system
See Fig. 3
See Fig. 5
See Fig. 6Figure 2. Simulink block level simulation diagram of the impedance measurement system
Mixer LPFZOHQuantizer GainDisplay
10 Input SinewavesTransfer functionImpedance measurement SystemDisplay
8/3/2019 Ee247 Project 3 2
http://slidepdf.com/reader/full/ee247-project-3-2 7/12
Figure 3. Simulink block level simulationdiagram of input block
s− Rf ⋅ Ccell⋅
Figure 4. Simulink block level simulation
diagram of “ideal” feedback amplifier transfer function
H s( )Rf −
Zcell
Rf −
Rcells Rf ⋅ Ccell⋅−
Figure 5. Simulink block level simulation diagram of feedback amplifier transfer function
(including finite open loop gain and bandwidth)
)Z
Rf (1
a
11
1H(s)_idealH(s)
++
⋅=
Figure 6. Simulink block level simulation digram of ADC (non-idealities modeling includethermal noise, INL, DNL, ENOB)
f1=100k
f2=215k
f3=464k
f4=1M
f5=2.15M
f6=4.64M
f7=10M
f8=21.5M
f9=46.4M
f10=100M
Rf −
Rcell
8/3/2019 Ee247 Project 3 2
http://slidepdf.com/reader/full/ee247-project-3-2 8/12
Simulation Results and Verification:
Since calibration is used, the resistance R and the capacitance C of the cell model need to be
measured to 1% accuracy in less than 1ms.
The following tables summarize the above measurement values and show that all accuracy
specifications are met:
Measured Values
Frequency Ccell (max) Ccell (min) Rcell (max) Rcell (min)
1.000000E+05 1.004458E-11 5.030458E-13 4.971222E+00 2.499606E+00
1.00000E+08 1.00911E-11 4.96136E-13 4.95762E+00 2.47567E+00
Ccell (max) =1% of 1nF =.01nF, Rcell (max) =1% of 500 =5Ccell (min) =1% of 50pF =.5pF, Rcell (min) =1% of 250 =2.5
Table 2. Measured values of maximum and minimum Rcell and Ccell over extreme frequency
range.
error (%)=abs(measured-actual)/(actual)*100 (<1%)
Frequency Ccell (max) Ccell (min) Rcell (max) Rcell (min)
1.000000E+05 4.458366E-01* 6.091612E-01 -5.755533E-01 -1.575827E-02
1.00000E+08 9.11141E-01 -7.72849E-01 -8.47633E-01 -9.73285E-01
* example calculation: (1.004458e-11-1e-11)/1e-11*100=.4458%
Table 3. Calculated error of maximum and minimum Rcell and Ccell over extreme frequency
range.
overall error (%)=(measured/(channel+cell))*100-1 (<.01%)
Frequency Ccell (max) Ccell (min) Rcell (max) Rcell (min)
1.000000E+05 4.458366E-03* 6.091612E-03 -5.755533E-03 -1.575827E-04
1.00000E+08 9.11141E-03 -7.72849E-03 -8.47633E-03 -9.73285E-03
* example calculation: 1.004458e-11/(1e-9)*100-1=.004458%
Table 4. Calculated overall error of maximum and minimum Rcell and Ccell over extremefrequency range.
8/3/2019 Ee247 Project 3 2
http://slidepdf.com/reader/full/ee247-project-3-2 9/12
The simulation results below show that these specifications are met.
For better illustration purposes, the resistor transconductance “g” is ploted instead of its
resistance “R”.The graphs in Figures 7 and 8 show the output results of the calibration procedure for the
conductance and capacitance where the exact values of R and C are 250 and 50pF
respectively.
Figure 7. Measured conductance of calibration solution (exact R = 250Ω = ¼ mS)
Figure 8. Measured capacitance of calibration solution (exact C = 50 pF)
Conductance (S) v/s time (sec)
4.0001 mS
Capacitance (F) v/s time (sec)
50.096 pF
8/3/2019 Ee247 Project 3 2
http://slidepdf.com/reader/full/ee247-project-3-2 10/12
Figure 9. Results of the measured Rcell of 2.5
Figure 10. Results of the measured Ccell of 0.01nF
Figures 11 and 12 below show the output results of the error in Rcell and Ccell . The graphsshow an accuracy greater than 1%. These graphs are generated for resistance and capacitance of
2.5 and .01nF respectively.
Resistance () v/s time (sec)
Rcell= 2.49
Capacitance (F) v/s time (sec)
Ccell=9.975pF
8/3/2019 Ee247 Project 3 2
http://slidepdf.com/reader/full/ee247-project-3-2 11/12
Figure 11. Error for Rcell = 2.5
Figure 12. Error for Ccell = 0.01nF
The above simulations show that all specifications requirements (accuracy, settling time) are
met at the extreme cases of the cell impedances and frequencies.
Error in R in % vs time in
0.2 % < 1% required accuracy
Error in C in % v/s time
0.18% < 1% required accuracy
8/3/2019 Ee247 Project 3 2
http://slidepdf.com/reader/full/ee247-project-3-2 12/12
Conclusion:
In this project, the hierarchical design of a cell impedance measurement system is demonstrated
through the use of ideal simulation building blocks as a first step, then through the refinementof the simulations by adding relevant non-idealities to each block based on actual commercial
components.
Simulations performed on extreme cases of cell impedance values and frequencies are shown tomeet the project specifications.
The main features of the design are the implementation of the calibration at a very early stage in
the system to alleviate the accuracy requirements on all subsequent stage, especially the ADC,as well as the calculation of impedance at different frequencies in parallel.
Simulations with non-idealities added to the blocks show that the system is robust and is
insensitivity to second order effects.
A main improvement that could be done in this design is the calculation of the impedance at theten different frequencies in a serial instead of the parallel implemented fashion which will
considerably reduce the hardware complexity. However, this will make the speed requirementsof the circuit much more constrained.
Moreover, the choice of the intermediate frequency could be more carefully chosen in such away to reduce the complexity of the DSP.
We have learned how to design an impedance measurement system and select the appropriatecomponents necessary to build such a system. We also gained knowledge of modeling second
order effects in Simulink. In addition, we learned how to scale voltage swing at each stage,
making use of the full-scale voltage to achieve highest accuracy.