EE141
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Tu-Th 11am-12:30pm203 McLaughlin
EE141- Spring 2004Introduction to Digital
Integrated Circuits
EE1412
What is this class about?
Introduction to digital integrated circuits.» CMOS devices and manufacturing technology.
CMOS inverters and gates. Propagation delay, noise margins, and power dissipation. Sequential circuits. Arithmetic, interconnect, and memories. Programmable logic arrays. Design methodologies.
What will you learn?» Understanding, designing, and optimizing digital
circuits with respect to different quality metrics: cost, speed, power dissipation, and reliability
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Digital Integrated Circuits
Introduction: Issues in digital designThe CMOS inverterCombinational logic structuresSequential logic gates; timingArithmetic building blocksInterconnect: R, L and CMemories and array structuresDesign methods
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Interludium: Administrativia
Instructor
Jan M. [email protected] hours: 511 Cory
Tu 1-3pm
Brian LeibowitzDiscussion + [email protected] Hours: TBD
Gang ZhouDiscussion + [email protected] Hours: TBD
The TAs
Reader: TBA
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The Web-Site
Class and lecture notesAssignments and solutionsLab and project informationExamsMany other goodies …
The sole source of informationhttp://bwrc.eecs.berkeley.edu/Classes/ee141
Save a tree!
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Class Admission
No enrollment issues. Everyone will be accommodated! » Class is videotaped» Also webcasted
(http://webcast.berkeley.edu)Make sure your name is on the class roll!
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Discussions and Labs
Discussion sessions» Mo 4-5pm, 433 Latimer» We 2-3pm, 203 McLaughlin » Pick any of the two (the are covering the same
material)
Labs (353 Cory)» Mo 9-12am» We 11am-2pm» Th 12:30-3:30pm» Pick the one that fits you the best (pending
availability) and STICK TO IT!
EE141 8
TAmtng
M
T
W
R
F
8 9 10 11 12 1 2 3 4 5 6
Lab(Brian)353 Cory
Lab(Brian/Gang)
353 Cory
Lab(Gang)353 Cory
OH(Jan)
511 Cory
DISC*(Gang)
203 McLaughlin
DISC*(Brian)
433 Latimer
Lec(Jan)
203 McLaughlin
ProblemSets Due
Lec(Jan)
203 McLaughlin
* Discussion sections will cover identical material
Your EE141 Week At a Glance
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Class Organization
10 AssignmentsA couple of design projects (1 term project)Labs: 6 software, 1 hardware2 midterms, 1 final» Midterm 1: Th February 26, 6:30-8:00pm » Midterm 2: Th April 8, 6:30-8:00pm» Final: We May 19, 8-11am
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Grading Policy
Homeworks: 10%Labs: 10%Projects: 20%Midterms: 30%Final: 30%
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Class Material
Textbook: “Digital Integrated Circuits – A Design Perspective,” 2nd Edition, by J. Rabaey, A. Chandrakasan, and B. NikolicLab Reader:Available on the web page!Selected material will be made available from Copy
Central
Check web page for the availability of tools
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Software
Cadence software only!» Phased out the Micromagic software.» Online documentation and tutorials
HSPICE and IRSIM for simulation
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Getting Started
Make-up for lecture 1: Mo Jan 26, 4pm (usual room)Assignment 1: Getting SPICE to work –see web-pageNO discussion sessions or labs this week.First discussion sessions in Week 2First Software Lab in Week 3
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Introduction
Why is designing digital ICs different today than it was before?Will it change in future?
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The First Computer
The BabbageDifference Engine(1832)
25,000 partscost: £17,470
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ENIAC - The first electronic computer (1946)
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The Transistor Revolution
First transistorBell Labs, 1948
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The First Integrated Circuits
Bipolar logic1960’s
ECL 3-input GateMotorola 1966
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Intel 4004 Micro-Processor
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Evolution in Transistor Count
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Intel Pentium (II) microprocessor
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Moore’s Law
In 1965, Gordon Moore noted that the number of transistors on a chip doubled every 18 to 24 months.
He made a prediction that semiconductor technology will double its effectiveness every 18 months
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Moore’s Law
16151413121110
9876543210
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
LO
G2
OF
TH
E N
UM
BE
R O
FC
OM
PO
NE
NT
S P
ER
INT
EG
RA
TE
D F
UN
CT
ION
Electronics, April 19, 1965.
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Evolution in Complexity
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Moore’s law in Microprocessors
40048008
80808085 8086
286386
486Pentium® proc
P6
0.001
0.01
0.1
1
10
100
1000
1970 1980 1990 2000 2010Year
Tra
nsi
sto
rs (
MT
)
2X growth in 1.96 years!
Transistors on Lead Microprocessors double every 2 yearsTransistors on Lead Microprocessors double every 2 yearsS. Borkar
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Moore’s Law - Logic Density
Shrinks and compactions meet density goalsNew micro-architectures drop density
Shrinks and compactions meet density goalsNew micro-architectures drop density
So
urc
e: In
telPentium (R)
Pentium Pro (R) 486
386
i860
1
10
100
1000
1.5µ
1.0µ
0.8µ
0.6µ
0.35
µ
0.25
µ
0.18
µ
0.13
µ
Lo
gic
Den
sity
2x trend
Lo
gic
Tra
nsi
sto
rs/m
m2
Pentium II (R)
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Die Size Growth
40048008
80808085
8086286
386486Pentium ® proc
P6
1
10
100
1970 1980 1990 2000 2010Year
Die
siz
e (m
m)
~7% growth per year~2X growth in 10 years
Die size grows by 14% to satisfy Moore’s LawDie size grows by 14% to satisfy Moore’s Law
S. Borkar
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Frequency
P6Pentium ® proc
48638628680868085
8080800840040.1
1
10
100
1000
10000
1970 1980 1990 2000 2010Year
Fre
qu
ency
(M
hz)
Lead Microprocessors frequency doubles every 2 yearsLead Microprocessors frequency doubles every 2 years
Doubles every2 years
S. Borkar
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Processor Frequency Trend
386486
Pentium(R)
Pentium Pro(R)
Pentium(R) II
MPC750604+604
601, 603
21264S
2126421164A
2116421064A
21066
10
100
1,000
10,000
1987
1989
1991
1993
1995
1997
1999
2001
2003
2005
Mh
z
1
10
100
Gat
e D
elay
s/ C
lock
Intel
IBM Power PC
DEC
Gate delays/clock
Processor freq scales by 2X per
generation
Frequency doubles each generationNumber of gates/clock reduce by 25%
V.De, S. BorkarISLPED’99
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Power
P6Pentium ® proc
486
3862868086
80858080
80084004
0.1
1
10
100
1971 1974 1978 1985 1992 2000Year
Po
wer
(W
atts
)
Lead Microprocessors power continues to increaseLead Microprocessors power continues to increase
S. Borkar
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Processor Power
386386
486 486
Pentium(R)Pentium(R)
MMX
Pentium Pro (R)
Pentium II (R)
1
10
100
1.5µ 1µ 0.8µ 0.6µ 0.35µ 0.25µ 0.18µ 0.13µ
Max
Po
wer
(W
atts
) ?
Lead processor power increases every generation
Compactions provide higher performance at lower power
So
urc
e: In
tel
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Power will be a problem
5KW 18KW
1.5KW 500W
40048008
80808085
8086286
386486
Pentium® proc
0.1
1
10
100
1000
10000
100000
1971 1974 1978 1985 1992 2000 2004 2008Year
Po
wer
(W
atts
)
Power delivery and dissipation will be prohibitivePower delivery and dissipation will be prohibitive
S. Borkar
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Power density will increase
400480088080
8085
8086
286 386486
Pentium® procP6
1
10
100
1000
10000
1970 1980 1990 2000 2010Year
Po
wer
Den
sity
(W
/cm
2)
Hot Plate
NuclearReactor
RocketNozzle
Power density too high to keep junctions at low tempPower density too high to keep junctions at low temp
S. Borkar
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Power delivery challenges
P6Pentium® proc
486386286
8086
80858080
800840040.01
0.10
1.00
10.00
100.00
1,000.00
1970 1980 1990 2000 2010Year
Icc
(am
p)
P6Pentium® proc
486386
286
8086
80858080
80084004
1.E-041.E-031.E-021.E-011.E+001.E+011.E+021.E+031.E+041.E+051.E+061.E+07
1970 1980 1990 2000 2010Year
L(d
i/dt)
/Vd
d
High supply currents at low voltage:Challenges: IR drop and L(di/dt) noiseHigh supply currents at low voltage:
Challenges: IR drop and L(di/dt) noise
S. Borkar
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Not Only Microprocessors
Digital Cellular Market(Phones Shipped)
1996 1997 1998 1999 2000
Units 48M 86M 162M 260M 435M Analog Baseband
Digital Baseband
(DSP + MCU)
PowerManagement
Small Signal RF
PowerRF
(data from Texas Instruments)(data from Texas Instruments)
CellPhone
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Productivity Trends
1
10
100
1,000
10,000
100,000
1,000,000
10,000,000
2003
1981
1983
1985
1987
1989
1991
1993
1995
1997
1999
2001
2005
2007
2009
10
100
1,000
10,000
100,000
1,000,000
10,000,000
100,000,000
Logic Tr./ChipTr./Staff Month.
xxx
xxx
x
21%/Yr. compoundProductivity growth rate
x
58%/Yr. compoundedComplexity growth rate
10,000
1,000
100
10
1
0.1
0.01
0.001
Lo
gic
Tra
nsi
sto
r p
er C
hip
(M)
0.01
0.1
1
10
100
1,000
10,000
100,000
Pro
du
ctiv
ity
(K)
Tra
ns.
/Sta
ff -
Mo
.
Source: Sematech
Complexity outpaces design productivity
Co
mp
lexi
ty
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Challenges in Digital Design
“Microscopic Problems”• Ultra-high speed design• Interconnect• Noise, Crosstalk• Reliability, Manufacturability• Power Dissipation• Clock distribution.
Everything Looks a Little Different
“Macroscopic Issues”• Time-to-Market• Millions of Gates• High-Level Abstractions• Reuse & IP: Portability• Predictability• etc.
…and There’s a Lot of Them!
∝ DSM ∝ 1/DSM
?
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Design Abstraction Levels
n+n+S
GD
+
DEVICE
CIRCUIT
GATE
MODULE
SYSTEM
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Why Scaling?
Technology shrinks by 0.7/generationWith every generation can integrate 2x more functions per chip; chip cost does not increase significantlyCost of a function decreases by 2xHow to design chips with more and more functions?Design engineering population does not double every two years…Need to understand different levels of abstraction
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Next Class
Introduces basic metrics for design of integrated circuits – how to measure delay, power, etc.Brief intro to IC manufacturing and design