4/11/08
Introduction to Partial Reconfiguration
Adam Flynn
EEL 4930/59344/11/08
Agenda Introduction Definitions and Acronyms Potential Implementations Example Applications Demo
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Introduction Full Reconfiguration
Bitfile for entire FPGA is loaded onto FPGA Partial Reconfiguration (PR)?
Only certain portion(s) of FPGA are reprogrammed Advantages
Shorter reconfiguration time Less power Smaller bitfiles Rest of FPGA can remain operational
Few applications outlined later
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Definitions and Acronyms Partial Reconfiguration Module (PRM)
Design module that is swapped in and out on the fly
Partial Reconfiguration Region (PRR) Section of FPGA fabric set aside for a
PRM. A single PRR can have multiple PRMs
defined for it Base Design
Static portion of the design – everything that’s not a PRM and remains operational during PR
Bus Macro Pre-placed, pre-routed macro that locks
routing between PRMs and the base design
How PRM communicates with rest of FPGA
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Potential Application
ModuleA
ModuleC
PRR
ModuleB
FPGABase (Static)
RegionPR Region
Bus Macros
Apply to what we’ve done so far in class … Modules A, B, C are memory map, register file, controller, etc … PRR is Fibonacci Calculator or Accumulator
Can reconfigure FPGA to implement any function Provided function is amenable to standard interface
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PR Implementation #1
Static section controls PRR, provides interface to system
Access to I/O must go through bus macro
Single Reconfigurable Module
Static Configuration\Communication Controller
I/O Bus macros
Pad BM3
=
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PR Implementation #2Smallest
Reconfigurable Wiring
Biggest
Configuration\
Communication
Controller
Module
#1 Module
#3
Module
#4
Module
#2
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PR Implementation #3
Module
#2
Module
#1
Configuration\
Communication
Controller
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Application A Embedded system where FPGA must constantly
communicate with system Mission critical modules can maintain real-time links while the
functionality of other portions of the FPGA are reconfigured Not possible with full reconfiguration
Reconfiguring PRRs can allow FPGA to … Implement alternate video coding standard Use different radio link protocol/frequency Provide hardware acceleration for several kernels too
large to fit onto FPGA simultaneously
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Application B Fault Tolerance
Useful for FPGAs in harsh environments (i.e. space) Configuration bits can become corrupted
Adaptable Component-level Protection Level of Fault Tolerance/Protection can be reconfigured See figure for visualization
Protection Module “Frame”
A BB
2× parallel, SCP
A
no parallel, TMR
BA DC
4× parallel, single
BLANK
BLANK
no parallel, SCP“sockets” for modulesFPGA arch. diagram
Component-level
Adaptation
SIFT – Software-Implemented Fault ToleranceSSCP – Spatial Self-Checking PairTSCP – Temporal Self-Checking PairSNMR – Spatial N-Mod RedundancyTNMR – Temporal N-Mod RedundancyABFT – Algorithm-Based Fault Tolerance
Configuration Scrubbing “Configuration Manager” monitors
configuration bits, corrects corrupted bits
Application C Multipurpose System Design
Idea: Create high level design with several PPRs
PRRs can be [re]populated as application requirements are defined/change
Provides flexibility Does not require designer to
anticipate future upgrades
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Acknowledgements Chris Conger, Ross Hymel
Borrowed heavily from previous presentations
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Demo
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