Adapted from Computer Organization and Design, Patterson & Hennessy, UCB
ECE232: Hardware Organization and Design
Part 9: MIPS Lite
4th edition: Chapter 4; 3rd edition: Chapter 5
http://www.ecs.umass.edu/ece/ece232/
ECE232: MIPS-Lite 2 Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMass Koren
MIPS-lite processor
� Want to build a processor for a subset of MIPS instruction set (“MIPS-lite”)
• just enough to illustrate key ideas
• instruction set subset (3 groups):
• arithmetic-logical:add, sub, and, or, slt
• memory reference: lw, sw
• control flow: j, beq
• can we write real programs with just these?
� Need up to 5 steps to execute any instruction in our subset
Processor (CPU)
Computer
Control
Datapath
IMemory
MIPS Instructions
DMemory
ECE232: MIPS-Lite 3 Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMass Koren
Instruction Execution Steps
Instruction
Fetch
Decode, Inc PC and Read Registers
ALU Operation, Branch address
Data Memory operation
Write Back
1. Read IM[PC]
2. Instruction Decode, PC = PC + 4, Register read
3. ALU operation, Branch address computation
4. LW/STORE in Data memory
5. Register Write
ECE232: MIPS-Lite 4 Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMass Koren
Building a Datapath for MIPS (step 1)
PCInstructionMemory
Step 1
••••
••••
••••
add $t0,$t0,$t0
add $t0,$s1,$t0lw $t1,20($s0)
sw $t1,4($t0)
••••
••••
.
.
.PC-4
PCPC+4
PC+8
.
.
Flow of execution
Step 1: instruction fetch
ECE232: MIPS-Lite 5 Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMass Koren
Datapath Step 1: Any Instruction
PC
Instruction Memory(IMem)
Address
Instruction
Add
“4”
32-bit adder or ALU
wired only for add
ClockOnce program is loaded, IMem is read-only
ECE232: MIPS-Lite 6 Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMass Koren
Building a Datapath for MIPS (step 2)
PC Registers
Step 1 Step 2: Decode andRead Registers
add $t0,$s1,$t0
InstructionMemory
op rs rt rd shamt funct
0 17 8 8 0 32R
ECE232: MIPS-Lite 7 Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMass Koren
Datapath Step 2: Any Instruction
RegisterFile
ReadRegister 1 Read
data 1
Readdata 2
ReadRegister 2
WriteRegister
WriteData
Instruction
ControlDatapath Control Points
6
op rs rt rd shamt funct R add $t0,$t1,$t2
ECE232: MIPS-Lite 8 Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMass Koren
Remaining Steps in Executing Instructions
� 3rd step onwards depends on instruction class
� EX: for ALU instructions: add $t0, $t1, $t2outputs from registers t1 and t2 will be sent to the ALU input
� For Memory-reference instruction:
lw $t0,20($s0)
Address ⇐ Base + offset
ALU
ECE232: MIPS-Lite 9 Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMass Koren
Building a Datapath for MIPS (lw step 3)
PC Registers
ALU
InstructionMemory
Step 1 Step 2 Step 3
op rs rt address lw $t0, 20($s0)I
ECE232: MIPS-Lite 10 Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMass Koren
Datapath Step 3-4: R-format Instructions
Registers
ReadRegister 1 Read
data 1ALU
Readdata 2
ReadRegister 2
WriteRegister
WriteData
Instruction
Result
Zero
ALU control
3
32
RegWrite
add, sub, and, or
[$t1]
[$t2]
[$t1] ⊗⊗⊗⊗ [$t2]
{ +, -, AND, OR, etc.}
[$t3] ←←←←[$t1] ⊗⊗⊗⊗ [$t2]
ECE232: MIPS-Lite 11 Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMass Koren
Datapath Step 3: Branch
Registers
ReadRegister 1 Read
data 1ALU
Readdata 2
ReadRegister 2
WriteRegister
WriteData
Instruc-tion
Zero
RegWrite
SignExtend
3216
Add Branch
target
To branch controllogic
PC + 4 from step 1 datapath
Mult by 4
beq $t0,$t1,loop
ALU control
3
Result
[$t0]
[$t1]
ECE232: MIPS-Lite 12 Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMass Koren
Steps 4,5 in Executing lw,sw
� 4th step depends on instruction class
� Ex: for lw: Fetch Data from Memory
Data ⇐ Mem[Address]
� For sw: Put the contents of a register in Memory
From Register for SW
To register for LW
lw $t1,20($s0)
sw $t1,4($t0)
PC Registers
ALU
Step 1 Step 2 Step 3
DataMemory
Step 4
InstructionMemory
� 5th step only for lw; rest are done
� for lw: Write Result Reg[rt] ⇐⇐⇐⇐ Data
ECE232: MIPS-Lite 13 Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMass Koren
Datapath Step 3-5: Load/Store
Registers
ReadRegister 1 Read
data 1ALU
Readdata 2
ReadRegister 2
WriteRegister
WriteData
Instruc-tion
Zero
ALU control
RegWrite
Address
Readdata
WriteData
SignExtend
3216
DMem
MemRead
MemWrite
lw $t0,24($s3)
op rs rt address
Result
[$s3]
“24”
[$s3]+24
ECE232: MIPS-Lite 14 Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMass Koren
Compose Datapath: R-form + Load/Store
Registers
ReadRegister 1 Read
data 1ALURead
data 2
ReadRegister 2
WriteRegister
WriteData
Instr
ucti
on
Zero
ALU control
3
RegWrite
Address
Readdata
WriteData
SignExtend 32
16
DMem
MemRead
MemWrite
1
Mux0
MemTo-
Reg0=R-form1=L/S
Mux
ALUSrc0 = R-format
1 = Load/Store
Add muxes
ECE232: MIPS-Lite 15 Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMass Koren
Compose Datapath: + IMem + PC
Registers
ReadReg1
Readdata1 A
LURead
data2
ReadReg2
WriteReg
WriteData
Zero
ALU control
4
RegWrite
Address
Readdata
WriteData
SignExtend 32
16
DMem
MemRead
MemWrite
Mux
MemTo-Reg
Mux
ALUSrc
Read Addr
Instruc-tion
IMem
“4”
PC
add
ECE232: MIPS-Lite 16 Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMass Koren
Compose Datapath: + Branch
Registers
ReadReg1
Readdata1
ALURead
data2
ReadReg2
WriteReg
WriteData
Zero
ALUcon
RegWrite
Address
Readdata
WriteData
SignExtend 32
16
DMem
MemRead
MemWrite
Mux
MemTo-Reg
Mux
ALUSrc
Read Addr
Instruc-tion
IMem
“4”
PC
add
add<<
2
Mux
PCSrc
“Left Shift 2”module
Supports all
MIPS-lite
instructions?
(slt and ?)
ECE232: MIPS-Lite 17 Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMass Koren
Datapath: Register fields
� Destination registers may differ across instruction formats:
• R-format: [rd] � [rs] op [rt]
add $t0,$s0,$s1
For this instruction, bits 11-15 are the destination (t0),
which should be connected to the write reg. inputs
• I-format: [rt] � mem[[rs] + imm16]lw $t0,24($s3)
For this instruction, bits 16-20 should go to the write reg.
port. Bits 0-15 go to the ALU as address
• Connection to the write reg. port changes!
� Solution? mux to the rescue!
op rs rt rd functshamt
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
op rs rt offset
6 bits 5 bits 5 bits 16 bits
ECE232: MIPS-Lite 18 Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMass Koren
Datapath (add RegDst Mux)
Regs
ReadReg1
Readdata1
ALURead
data2
ReadReg2
WriteReg
WriteData
Zero
ALU-con
RegWrite
Address
Readdata
WriteData
SignExtend
DMem
MemRead
MemWrite
Mux
MemTo-Reg
Mux
Read Addr
Instruc-tion
IMem
4
PC
add
add<<
2
Mux
PCSrc
ALU-src
Mux
25:21
20:16
15:11
RegDst
15:0
31:0
ECE232: MIPS-Lite 19 Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMass Koren
Datapath: Determine next PC
� What if instruction is a conditional branch (beq)?
• if operands equal, take branch (PC gets PC+4+offset)
• else PC gets PC+4
� Therefore, set control point PCSrc = 1 if and only if beq and Zero asserted
ECE232: MIPS-Lite 20 Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMass Koren
Datapath (add Branch control point)
Regs
ReadReg1
Readdata1
ALURead
data2
ReadReg2
WriteReg
WriteData
Zero
ALU-con
RegWrite
Address
Readdata
WriteData
SignExtend
DMem
MemRead
MemWrite
Mux
MemTo-Reg
Mux
Read Addr
Instruc-tion
IMem
4
PC
add
add<<
2
Mux
ALU-src
Mux
25:21
20:16
15:11
RegDst
15:0
31:0
Branch
PCSrc
ECE232: MIPS-Lite 21 Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMass Koren
Adding Control
� CPU = Datapath + Control
� Single-Cycle Design:
• Instruction takes exactly one clock cycle
• Datapath units used only once per cycle
• Writable state updated at end of cycle
� What must be “controlled”?
• Multiplexors (Muxes)
• Writable components: Register File, Data Memory (DMem)
• what about PC? IMem?
• ALU (which operation?)
ECE232: MIPS-Lite 22 Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMass Koren
Processor = Datapath + Control
ControlLogic
op rs rt rd shamt funct
R-formatinstruction
To datapath
6 6
� Single-Cycle Design: everything happens in one clock cycle until next falling edge of clock, processor is just one big combinational circuit!!!
� Control is a combinational circuit where the output is a function of the inputs
• outputs? control points in datapath
• inputs? the current instruction! (opcode, funct control everything)
ECE232: MIPS-Lite 23 Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMass Koren
Defining Control
� Note that funct field only present in R-format instruction -funct controls ALU only
� To simplify control, define Main control, ALU control separately – using multiple levels will also increase speed –important optimization technique
� ALUop inputs will be defined
ControlLogic
MainControl
ALUcontrol
op
funct
op
funct
ALU-con
ALUop
ECE232: MIPS-Lite 24 Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMass Koren
Defining ALU Control
ALUcon
ALU
Zero
Result
ALUcon ALU function Instruction(s) supported
0000 AND R-format (and)0001 OR R-format (or)0010 add R-format (add), lw, sw0110 subtract R-format (sub), beq0111 set on less than R-format (slt)1100 NOR R-format (nor)
A
B
ECE232: MIPS-Lite 25 Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMass Koren
Defining ALU Control
Instruction Desiredopcode ALU Action ALUOp funct ALUcon
lw add 00 xxxxxx 0010sw add 00 xxxxxx 0010beq subtract 01 xxxxxx 0110R-type add 10 100000 (add) 0010R-type subtract 10 100010 (sub) 0110R-type logical AND 10 100100 (and) 0000R-type logical OR 10 100101 (or) 0001R-type set on less 10 101010 (slt) 0111
ALUOp Funct Fielda1 a0 f5 f4 f3 f2 f1 f0 ALUcon
0 0 x x x x x x 0010x 1 x x x x x x 01101 x x x 0 0 0 0 00101 x x x 0 0 1 0 01101 x x x 0 1 0 0 00001 x x x 0 1 0 1 00011 x x x 1 0 1 0 0111
Don’t Cares
c3 c2 c1 c0
ECE232: MIPS-Lite 26 Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMass Koren
OpCode field 262728,, ooo
262728,, ooo
293031,, ooo
111
110
swshsb101
lhulbulwlhlb100
traplhillo011
010
xorioriandisltiusltiaddiuaddi001
bgtz blezbnebeqjaljR-format000
111 110101100011010001000
293031,, ooo
ECE232: MIPS-Lite 27 Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMass Koren
Function field 0145,..., ffff
012,, fff
345,, fff
111
110
sltuslt101
nor xororandsubusubadduadd100
divudivmultumult011
mtlomflomthimfhi010
jalrjr001
srav srlvsllvsrasrlsll000
111 110101100011010001000
ECE232: MIPS-Lite 28 Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMass Koren
Fully Minimized ALU Control
F3
F2
F1
F0
ALUOp
ALUcon4th bit=0
funct
c2
c1
c0
a0a1
� From the truth table, output signals can be easily derived because of don’t cares
� c2 = a0 OR (a1 AND f1)
� c1 = (Not a1) OR (Not f2)
� c0 (lsb) =
a1 AND (f3 OR f0)
� ALUOp is supplied by the main control unit (to be designed)
a1,0 f5,4,3,2,1,0 ALUcon
0 0 x x x x x x 0010X 1 x x x x x x 01101 x x x 0 0 0 0 00101 x x x 0 0 1 0 01101 x x x 0 1 0 0 00001 x x x 0 1 0 1 00011 x x x 1 0 1 0 0111
ECE232: MIPS-Lite 29 Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMass Koren
Datapath + ALU Control
Registers
ReadReg1
Readdata1
ALU
Readdata2
ReadReg2
WriteReg
WriteData
Zero
ALU-
con
RegWrite
Address
Readdata
WriteData
SignExtend
DMem
MemRead
MemWrite
Mux
MemTo-
RegMux
Read Addr
Instruc-tion
IMem
“4”
PC
add
add<<
2
Mux
PCSrc
ALU Control
Instr[5:0]ALUOp
ALU-src
ECE232: MIPS-Lite 30 Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMass Koren
DatapathWith Control
ECE232: MIPS-Lite 31 Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMass Koren
Adding Jumps
� Update PC with concatenation of
• Top 4 bits of old PC
• 26-bit jump address
• 00
� Need an extra control signal decoded from opcode
2 address
31:26 25:0
Jump
ECE232: MIPS-Lite 32 Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMass Koren
DatapathWith Jumps Added